An optical path switching chip, an optical interconnection system, and an optical interconnection reconstruction control method

Abstract

The application relates to an optical path switching chip, an optical interconnection system and an optical interconnection reconstruction control method, the chip comprising an input port array, an output port array, a multi-stage on-chip optical switch subarray, an intermediate stage rearrangement network, an edge coupling array and an on-chip monitoring calibration structure, the multi-stage on-chip optical switch subarray being formed on a planar optical waveguide platform, different input and output optical paths being kept at low insertion loss, low wavelength correlation loss and low loss fluctuation in the hyperspectral range by utilizing weak light field binding, low refractive index difference and large mode field transmission characteristics. Each physical port of the application can be used as a computing node port group, and more wavelength can be used to carry wavelength division multiplexing optical channels with the same rate or different rates, so that the single-port transmission rate is improved, and heterogeneous devices, cross-generation transceivers and multi-rate link access are supported; the optical path insertion loss is low, the optical power budget of the all-optical switching link can be kept without additional optical amplifiers or gain compensation devices, and the availability of multi-wavelength interconnection is improved.

Description

Technical Field

[0001] This invention relates to the fields of optical interconnect, planar optical waveguide, optical path switching and computing system interconnect technology, and specifically to an optical path switching chip, an optical interconnect system, and an optical interconnect reconfiguration control method. Background Technology

[0002] With the development of artificial intelligence models, high-performance computing, and data center services, the amount of intermediate features, gradients, parameters, cached data, and stored data that need to be transmitted between computing nodes is rapidly increasing. Traditional electrical interconnects typically rely on multi-level switching chips, SerDes, and complex protocol stacks, which face pressure in terms of bandwidth, latency, power consumption, and scalability. Optical interconnects, on the other hand, offer advantages such as high bandwidth, low transmission loss, immunity to electromagnetic interference, and the ability to increase single-port capacity through wavelength division multiplexing, making them suitable for high-speed interconnects between processors, FPGAs, GPUs, AI accelerators, and storage nodes.

[0003] Existing research on on-chip optical interconnects typically showcases optical switch chips with a medium port count, such as 16×16 level non-blocking optical switches, and verifies their low-latency optical interconnect capabilities between multiple computing nodes. This type of approach can demonstrate the feasibility of on-chip all-optical interconnects, but when the port count increases to 32×32, 64×64 or higher, the difficulty of controlling the number of optical switch stages, the number of cross waveguides, driving channels, thermal drift, differences in optical path loss, and crosstalk increases significantly, and cannot be solved by simply replicating medium port count structures.

[0004] For optical switching chips, spectral range is a key factor determining port utilization and long-term evolution capability. The OCS itself should be as wavelength-transparent as possible and support a sufficiently wide spectral window, enabling the same physical port to carry more WDM wavelengths and be compatible with transceivers of different rates, modulation formats, and generations. If the optical switching chip can only maintain low loss within a narrow spectrum, the number of wavelengths that can be reused per port is reduced, limiting heterogeneous device interconnection and cross-generational technology evolution capabilities.

[0005] High-refractive-index-difference strongly bound waveguide platforms, including silicon photonics, are advantageous for small-size bending and high-density integration. However, their strong bound mode fields also amplify the impact of sidewall roughness, waveguide crossings, bending, mode mismatch, and polarization or wavelength-dependent losses on the system. In large-port-count OCSs, optical signals need to pass through multiple stages of switching units, long waveguide optical paths, and numerous crossing structures. The aforementioned wavelength-dependent losses are amplified in a cascaded manner, making it more difficult to simultaneously maintain low insertion loss and low loss ripple in the hyperspectral range.

[0006] Planar waveguide platforms (PLCs) possess characteristics such as low refractive index difference, weak optical field confinement, and a large mode field. Their mode field is closer to that of standard single-mode fiber, naturally reducing end-face coupling loss, wavelength-dependent loss introduced by bending or crossing, and spectral fluctuations in multi-stage optical paths. Therefore, for OCSs requiring hyperspectral, low-loss, rate-transparent, and WDM-friendly characteristics, PLC weakly confined waveguides are not merely a technological choice, but a crucial physical foundation for unlocking the broadband capabilities of OCSs, increasing single-port WDM capacity, and supporting heterogeneous device interconnections.

[0007] It's also important to note that optical amplifiers cannot fundamentally replace the low-loss and wide-spectral-flatness capabilities of the OCS chip itself. First, optical amplifiers introduce additional noise, power consumption, size, and control complexity, which is detrimental to low-latency, low-power all-optical interconnects. Second, the gain bandwidth and gain flatness of optical amplifiers are limited, making it difficult to accurately compensate for wavelength-dependent losses in the OCS caused by different wavelengths, optical paths, and crossover frequencies on a channel-by-channel and optical path-by-path basis. If the spectral response of the OCS itself is not flat, the amplifier may only increase the overall power but cannot eliminate the power imbalance between different WDM channels, still leading to bit errors or loss of lock-up in some wavelength channels. Therefore, directly reducing insertion loss and expanding the flat spectral window at the OCS chip level is a more fundamental solution to support multi-wavelength, high single-port rates, and gain-compensated all-optical interconnects.

[0008] On the other hand, there are already solutions in data center networks that use optical switches and software-defined network control to achieve dynamic topology reconfiguration. These solutions typically employ rack-level or data center-level MEMS free-space optical switching equipment and reduce network costs and power consumption through traffic engineering and topology engineering. However, these solutions focus on external network equipment and data center operations and maintenance, and cannot directly solve the problems of scalable multi-port low-loss broadband switching, port group wavelength division multiplexing, on-chip calibration, high-speed transmission without gain compensation, and reconfiguration under chip physical constraints in on-chip planar optical waveguides.

[0009] Existing optical interconnect reconfiguration solutions for GPU or AI training mainly focus on task scheduling, switching between working and reserve channels, or optical switching matrix control. They still lack optical path loss tables, wavelength-dependent loss tables, port group mapping, on-chip monitoring, fault domain control, and single-port uncompensated transmission capabilities exceeding 800 Gbps, which are tied to on-chip scalable switching chip structures.

[0010] Therefore, existing technologies lack a complete solution that integrates chip hardware structure, heterogeneous interconnection system, and computing power traffic-driven reconfiguration control, and cannot simultaneously achieve multiple core requirements such as 32-port or more scalable on-chip optical switching, ultra-spectral low-loss transmission, single-port WDM aggregation rate of over 800Gbps, stable operation without optical amplifiers, heterogeneous computing power node compatibility, and low-interruption dynamic topology reconfiguration. Summary of the Invention

[0011] To address the technical challenges in existing technologies, such as the inability of optical path switching chips to simultaneously achieve multiple core requirements including 32-port or higher expandable on-chip optical switching, ultra-spectral low-loss transmission, single-port WDM aggregation rate exceeding 800Gbps, stable operation without optical amplifiers, compatibility with heterogeneous computing nodes, and low-interruption dynamic topology reconfiguration, this invention provides an optical path switching chip, an optical interconnect system, and an optical interconnect reconfiguration control method.

[0012] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: An optical path switching chip, comprising: An input port array, comprising N input ports; An output port array comprising N output ports, where N is a positive integer not less than 32; A multi-level on-chip optical switch network is connected between the input port array and the output port array to establish a reconfigurable optical path between any input port and any output port. The multi-level on-chip optical switch network is integrated into a planar optical waveguide platform, i.e., a PLC platform. An intermediate-level rearrangement network is set between the input and output stages of the multi-stage on-chip optical switch network to rearrange the optical paths between different port groups. An on-chip monitoring and calibration structure is used to collect at least one parameter of optical power, insertion loss, crosstalk, switch bias drift, and port health status of part or all optical paths. Among them, at least some of the N input ports and N output ports are configured as computing node port groups, and each computing node port group carries multiple wavelength division multiplexing optical channels through a single physical port; The planar optical waveguide platform is equipped with a weakly bound waveguide, which is configured to reduce optical path insertion loss and wavelength correlation loss within a preset hyperspectral wavelength range, enabling the optical path switching chip to achieve a single-port transmission rate of over 800Gbps under the condition that the link has no optical amplification and no gain compensation.

[0013] Fabricated on a PLC-based planar optical waveguide platform, the N input ports of the input port array and the N output ports of the output port array are connected to an external fiber optic array via edge couplers and grating couplers, where N is a positive integer not less than 32. A multi-stage on-chip optical switch network is integrated on the PLC platform, leveraging the inherent characteristics of the weakly bound waveguide—low refractive index difference, weak optical field confinement, and large mode field—to establish a broadband, low-loss reconfigurable optical path between any input and output ports. The intermediate-stage rearrangement network performs optical path rearrangement layer by layer according to port groups, strictly controlling the path length, number of crossovers, and number of switching stages between commonly used port groups. An on-chip monitoring and calibration structure deploys optical taps at key nodes in the optical path to collect optical power, insertion loss, crosstalk, switch bias drift, and port health status parameters throughout the entire link. Some ports are configured as computing node port groups, with multiple wavelength division multiplexing optical channels carried within a single physical port, eliminating the need for independent optical switch physical ports for each wavelength. The weakly bound waveguide of the PLC platform significantly reduces path insertion loss and wavelength-dependent loss over a preset ultrawide spectral range. The all-optical switching link can support a transmission rate of over 800Gbps per port without the need for external optical amplifiers or gain compensation modules.

[0014] In some embodiments, the optical switching chip uses a 6-inch silicon dioxide wafer as the substrate. The N input ports of the input port array and the N output ports of the output port array all use standard LC fiber coupling interfaces. Microlens arrays are integrated on the port end faces to achieve low-loss connection with the on-chip waveguide. The multi-level on-chip optical switch network is integrated on a planar optical waveguide platform using an 8-layer photolithography process, with the overall chip size controlled within 12cm × 12cm. The intermediate-stage rearrangement network adopts a distributed waveguide cross-array design, rearranging the port group signals from the input stage output according to two dimensions: parity numbering and flow priority, avoiding congestion caused by high flow concentration in local areas. The on-chip monitoring and calibration structure sets a 1% splitting ratio optical tap at the output of each optical switch unit, guiding the collected optical signal to an array photodetector integrated at the chip corner, achieving millisecond-level sampling of all optical path parameters. The computing node port group is divided into subgroups of 4 ports each, and each subgroup is equipped with an on-chip miniature wavelength division multiplexing (WDM) demultiplexer. The spacing between multiple WDM optical channels within a single physical port is set to 100 GHz, enabling aggregation and transmission of multi-channel signals without the need for external large WDM devices. The weakly bound waveguide achieves a wide range of optical field distribution by adjusting the refractive index difference between the silicon dioxide core layer and the cladding to below 0.3%. Within the hyperspectral wavelength range covering the O, E, S, and C bands, the transmission loss of a single waveguide is controlled to within 0.03 dB / cm. Without the need for any internal optical amplifier chips, it can support error-free transmission of a single-port 800 Gbps PAM4 signal over a 2 km standard single-mode fiber link.

[0015] Furthermore, when N is 32, the chip is divided into a three-stage structure: input stage, intermediate stage, and output stage. Ports are grouped into groups of 4 or 8. High-frequency communication within a port group is prioritized through the shortest path, while communication between port groups is interconnected through a rearranged network in the intermediate stage. The total link path length and the number of switching stages are controlled within the optimal range. When N is 64, ports are grouped into groups of 8 or 16. Through port group arrangement, folded waveguides, low-loss crossovers, and local thermal isolation structures, path length differences and local thermal crosstalk are reduced. The two preferred port sizes can directly adapt to heterogeneous computing clusters with different computing power scales. The 32-port version is suitable for interconnecting computing nodes within small to medium-sized racks, while the 64-port version is suitable for larger-scale cross-node optical interconnect scenarios.

[0016] In some embodiments, when N is 32, the chip adopts a three-stage Benes switching network topology. The input stage has eight 4×4 optical switch subarrays, the intermediate stage has eight 4×4 optical switch subarrays, and the output stage has eight 4×4 optical switch subarrays. The intermediate stage rearrangement network is set as a 32-channel waveguide cross matrix. The entire chip integrates 1024 thermo-optical switching units, and the maximum insertion loss is controlled within 12dB. When N is 64, a five-stage Kloss switching network topology is adopted. The input stage, intermediate stage, and output stage each have 16 4×4 optical switch subarrays. The intermediate stage rearrangement network is expanded into a 64-channel two-stage cascaded waveguide cross matrix. The entire chip integrates 4096 thermo-optical switching units. By utilizing the low-loss characteristics of weakly bound waveguides, the maximum insertion loss of the entire link is controlled within 16dB, meeting the -12dBm optical sensitivity requirement of the receiver. Both types of chips use a unified peripheral electrical control interface, which can be directly adapted to AI cluster racks with different computing power scales. The 32-port version is adapted to the interconnection scenario of 32 GPU nodes in a single rack, while the 64-port version is adapted to the centralized switching scenario of 64 computing nodes across racks.

[0017] Furthermore, the planar optical waveguide platform is a silicon dioxide planar optical waveguide platform, or a planar optical waveguide platform with low refractive index contrast and weak light field confinement.

[0018] The planar optical waveguide platform for the chip can be a silicon dioxide planar optical waveguide platform, or other equivalent planar optical waveguide platforms with low refractive index difference and weak confinement transmission characteristics. Leveraging the platform's inherent weak optical field confinement characteristics, it reduces end-face coupling loss, scattering loss caused by waveguide sidewall disturbances, loss fluctuations caused by waveguide intersections, and wavelength-dependent losses introduced by curved structures. Compared to strongly confined high refractive index difference waveguide platforms, it is more suitable for long-path, multi-stage switching, and wide-spectrum optical path switching applications.

[0019] refer to Figure 3In some embodiments, a silicon dioxide planar optical waveguide platform is selected, using a silicon wafer as the substrate. A lower cladding layer, core layer, and upper cladding layer are sequentially deposited using plasma-enhanced chemical vapor deposition (PECVD). The core layer is doped with trace amounts of germanium to adjust the refractive index, and the cladding layer uses pure silicon dioxide. The overall process is fully compatible with existing semiconductor wafer production lines, achieving a stable yield of over 95%. For planar optical waveguide platforms with low refractive index contrast and weak light field confinement, a polymer-silicon dioxide hybrid integration scheme is adopted. This further reduces the refractive index contrast of the core layer to 0.15%, increases the evanescent field ratio outside the waveguide to 30%, and further reduces the waveguide's bending loss. At a bending radius of 5mm, the bending loss can be controlled within 0.001dB / 90°, while significantly reducing the transmission loss difference at different wavelengths. The wavelength-dependent loss is less than 1dB within a 100nm bandwidth. Both platforms are compatible with existing optical switch unit fabrication processes, allowing for wafer fabrication without additional adjustments to the photolithography pattern.

[0020] Furthermore, the mode field diameter of the weakly bound waveguide is matched with that of a standard single-mode fiber to reduce end-face coupling loss, optical path bending loss, and wavelength-dependent loss.

[0021] The mode field size of the weakly bound waveguide, i.e., the aforementioned mode field diameter, is configured to directly match the mode field of a standard single-mode fiber. This eliminates the need for an additional mode field converter, enabling low-loss end-face coupling while significantly reducing path bending loss and wavelength-dependent coupling loss. This matching characteristic avoids additional spectral fluctuations caused by mode mismatch, further ensuring the flatness of optical path loss over a wide spectral range.

[0022] In some embodiments, the mode field diameter of the weakly confined waveguide is controlled within the range of 9μm ± 0.5μm by adjusting the lateral dimensions and longitudinal thickness of the core layer, perfectly matching the mode field diameter of the G.652 standard single-mode fiber. At the coupling end face between the chip and the fiber, no mode field converter is needed; the standard single-mode fiber is directly connected to the on-chip waveguide using UV adhesive. The end face coupling loss can be reduced to 0.15dB / end face, far lower than the 0.5dB / end face coupling loss of traditional high-refractive-index contrast waveguides. Simultaneously, the matched mode field characteristics significantly reduce optical field leakage during waveguide bending. Even when the waveguide makes a 90° turn, with the bending radius reduced to 3mm, no significant additional loss occurs. The waveguide wiring density inside the chip can be increased by 40%, allowing for the integration of more optical switching units within the same chip area.

[0023] Furthermore, the preset hyperspectral wavelength range is at least 40 nm, preferably at least 80 nm, and even more preferably at least 100 nm.

[0024] The chip's preset ultrawide spectral range covers at least 40nm, preferably at least 80nm, and more preferably at least 100nm. Within this continuous wide spectral window, all selected optical paths meet preset insertion loss and wavelength-dependent loss thresholds, preventing situations where edge wavelengths suffer excessive loss and become unusable. The wide spectral capability allows for the configuration of more WDM channels on the same physical port. The controller can use all available wavelengths within this wide spectral range as part of the port resource pool, flexibly allocating wavelengths and rates based on the transceiver capabilities of different computing nodes.

[0025] In some embodiments, the hyperspectral wavelength range covers a 40nm wavelength range, encompassing the conventional C-band (1530nm-1570nm), adapting to the operating band of existing commercial dense wavelength division multiplexing (DWDM) optical modules. It can directly use commercially available 100GPAM4 optical transceivers without requiring customized optical devices for specific wavelengths. The 80nm wavelength range version covers the C and L bands (1525nm-1605nm), extending the number of available wavelengths to 80 channels spaced at 100GHz intervals, effectively doubling the number of WDM channels per port. The 100nm wavelength range version covers the O, E, and S bands (1460nm-1560nm). By optimizing the material doping ratio of the weakly bound waveguide, hydroxyl absorption peaks are eliminated, achieving flat, low-loss transmission across the entire band. The number of available wavelength channels exceeds 100, and the aggregated bandwidth per port can be further increased to over 1.6Tbps. All three versions of the chip use the same layout design; different bandwidth coverages can be achieved simply by adjusting the waveguide material composition, allowing for flexible selection based on customer bandwidth requirements.

[0026] Furthermore, multiple wavelength division multiplexing optical channels within a single physical port can carry optical signals with different line rates, different modulation formats, and different transceivers.

[0027] Multiple wavelength division multiplexing (WDM) optical channels within the same physical port can simultaneously carry optical signals from transceivers of different line rates, modulation formats, or generations. Some wavelength channels can be configured for 100Gbps, while others can be configured for 200Gbps, without requiring electrical domain processing of the optical signals. This feature supports direct access for heterogeneous devices and transceivers of different generations. As computing nodes gradually upgrade their hardware, older and newer rate devices can share the same chip platform without needing to redesign switching chips due to narrow spectral windows.

[0028] refer to Figure 4In some embodiments, the multiplexed optical channels within a single physical port can simultaneously carry optical signals of different line rates, such as 100G NRZ, 200G NRZ, and 400G PAM4, and are also compatible with signals of different modulation formats, such as OOK, QPSK, and 16QAM. Before entering the chip, the optical signals from different channels are combined by an external wavelength division multiplexer and transmitted through the same optical fiber to the input port of the optical path switching chip. The weakly bound waveguide inside the chip is non-selective for optical signals of different rates and modulation formats, preventing signal distortion. This feature enables hybrid networking of optical transceivers from different generations. In computing clusters where older 100G storage nodes and newer 200G GPU nodes coexist, the upgrade of the optical interconnect network can be completed without replacing all the hardware, significantly reducing the cost of cluster transformation.

[0029] Furthermore, the weakly bound waveguide of the planar optical waveguide platform is configured to enable the multi-wavelength division multiplexing optical channels to simultaneously meet the preset optical power budget within the preset hyperspectral wavelength range, thereby increasing the single-port aggregated transmission bandwidth by expanding the number of available wavelengths. The PLC platform's weakly bound waveguides ensure that multiple wavelength division multiplexing (WDM) optical channels simultaneously meet the preset optical power budget within a preset ultrawide spectral range, and the loss difference of all channels across the entire band is controlled within the allowable threshold. By fully utilizing the expanded number of available wavelengths, more WDM channels can be deployed directly within the same physical port, increasing the aggregated transmission rate of a single port without adding additional physical ports, ultimately achieving a single-port transmission capability exceeding 800Gbps.

[0030] In some embodiments, by optimizing the waveguide structure of the weakly bound waveguide, the insertion loss difference of all wavelength channels is controlled within 1 dB within a preset hyperspectral wavelength range of 100 nm, and the optical power budget across the entire band is greater than 18 dB. Under these conditions, a single physical port can simultaneously deploy 80 wavelength division multiplexing channels spaced at 100 GHz intervals, each channel carrying a 100 Gbps PAM4 signal. The total aggregated transmission bandwidth of a single port can reach 8 Tbps, far exceeding the 800 Gbps level of conventional solutions. Simultaneously, the flat spectral response avoids the problem of some wavelength channels being unusable due to excessive loss, improving wavelength utilization. Without increasing the number of ports, the transmission capacity of a single port can be significantly improved by expanding wavelength resources.

[0031] Furthermore, no optical amplifier is provided between the input port and the output port of the optical switching chip, and the low insertion loss of the weakly bound waveguide enables the all-optical switching link to meet the optical sensitivity requirements of the receiver without gain compensation.

[0032] The optical switching chip does not incorporate any optical amplifiers or active gain compensation modules between its input and output ports. Relying on the ultra-low insertion loss of the weakly bound waveguide, the total loss of the entire link remains within the acceptable range of the receiver's sensitivity even after passing through multiple stages of optical switching units and long-path transmission. The all-optical switching link can directly meet the receiver's decision margin requirements without gain compensation. This solution avoids the additional noise, power consumption, size, and control complexity introduced by optical amplifiers.

[0033] In some embodiments, no semiconductor optical amplifiers, Raman amplifiers, or any other optical amplification devices are installed on any optical signal transmission path between the input and output ports of the optical switching chip, nor are any gain compensation modules configured. Relying on the ultra-low transmission loss of the weakly bound waveguide, the total insertion loss of the all-optical switching link is controlled to within 15dB. Combined with a low-loss fiber coupling structure, the total link loss from the input fiber endface to the output fiber endface does not exceed 18dB, fully meeting the -12dBm sensitivity requirement of the 100G PAM4 optical signal receiver. Error-free transmission can be achieved without additional optical signal amplification. This solution eliminates the problems of noise introduction, limited gain bandwidth, and excessive power consumption caused by optical amplifiers. The overall power consumption of the chip can be controlled to within 15W, reducing the power consumption of the optical switching chip.

[0034] Furthermore, the optical path selection operation is completed based on the collected wavelength-dependent loss. The path status table generated by the on-chip monitoring and calibration structure records the wavelength-dependent loss parameters of all candidate optical paths. During the optical path configuration stage, the controller directly selects physical optical paths with low wavelength-dependent loss and good spectral flatness, avoiding high-loss wavelengths and high-loss paths that are difficult for optical amplifiers to compensate for at the path level. This mechanism can reduce the risk of power imbalance between channels from the source and avoid subsequent reliance on optical amplifiers for wavelength-dependent loss compensation.

[0035] In some embodiments, the on-chip monitoring and calibration structure periodically collects wavelength-dependent loss data for all candidate optical paths across the entire available wavelength range, generating a loss-wavelength curve for each physical optical path. During optical path configuration, paths with wavelength-dependent loss less than 0.5 dB are prioritized as the preferred paths, avoiding paths where loss fluctuates drastically with wavelength. Paths with high wavelength-dependent loss are marked as backup paths and only activated when all preferred paths are occupied. Simultaneously, low-rate channels that are less sensitive to loss are preferentially allocated within these paths. This selection mechanism ensures that the power difference among all working optical channels is controlled within 2 dB, avoiding bit error problems caused by excessively low power in some channels, and significantly improving the transmission stability of the all-optical switching network.

[0036] Furthermore, the multi-level on-chip optical switch network includes multiple optical switch sub-arrays of 4×4, 8×8, and 16×16 specifications. The optical switch sub-arrays are combined through the intermediate-level rearrangement network to form an N×N port-level switching function.

[0037] Multi-level on-chip optical switch networks consist of multiple 4×4, 8×8, 16×16, or other sizes of optical switch subarrays. These subarrays are interconnected through an intermediate-level rearrangement network, ultimately forming an N×N port-level full-switching function. The modular design of the subarrays significantly reduces the design difficulty of large-port-count optical networks and can flexibly adapt to port expansion requirements with different N values.

[0038] In some embodiments, the optical switch subarrays in the multi-level on-chip optical switch network are implemented as follows: a 4×4 subarray is implemented by cascading four 2×2 optical switch units; an 8×8 subarray is implemented by cascading two levels of 4×4 subarrays; and a 16×16 subarray is implemented by cascading three levels of 4×4 subarrays. For a 32-port chip, eight 4×4 input subarrays, eight 4×4 intermediate subarrays, and eight 4×4 output subarrays are interconnected through an intermediate-level rearrangement network to form a 32×32 full-port non-blocking switching function. For a 64-port chip, sixteen 4×4 input subarrays, sixteen 8×8 intermediate subarrays, and sixteen 4×4 output subarrays are interconnected through an intermediate-level rearrangement network to form a 64×64 full-port switching function. This modular combination scheme can significantly reduce the design difficulty of optical switch networks, allowing chips with different port sizes to reuse the same optical switch subarray layout, thus shortening the development cycle.

[0039] Furthermore, the multi-level on-chip optical switch network adopts any one or more combinations of the following topologies: Benesian switching network, Kloss switching network, tree-cascaded switching network, and folded switching network.

[0040] Multi-level on-chip optical switch networks can adopt any one of the following topologies: Benes type, Clos type, tree cascade type, and folded type, or a combination of multiple topologies. They can be flexibly selected according to the needs of different scenarios: Benes topology is suitable for low-latency medium-port scenarios, Clos topology is suitable for large-scale port expansion scenarios, tree cascade topology is suitable for multicast and broadcast service scenarios, and folded topology is suitable for small-size and compact design requirements.

[0041] Multi-level on-chip optical switching networks can select corresponding topologies according to different application scenarios: Benesian switching networks are used for low-latency, medium-port-scale scenarios, enabling non-blocking optical path switching with a reconfiguration latency of less than 1ms; Kloss switching networks are used for large-scale port scenarios with 64 or more ports, reducing the total insertion loss of the entire link through a three-level switching structure; tree-cascaded switching networks are used for trunking scenarios mainly for broadcast and multicast services, enabling efficient one-to-many optical signal distribution; folded switching networks are used for rack interconnection scenarios with fewer ports, significantly reducing the overall chip size. In practical designs, Benesian and Kloss topologies can be combined, with the first two stages using a Benesian structure for fast optical path switching and the last two stages using a Kloss structure for large-scale port expansion, balancing the advantages of low latency and large port scale.

[0042] Furthermore, the optical switching units in the multi-level on-chip optical switch network are selected from any one or more combinations of thermo-optical Mach-Zehnder interferometer switches, carrier-modulated Mach-Zehnder interferometer switches, phase change material switches, micro-ring switches, and on-chip microelectromechanical systems (MEMS) switches. Different types of switching units can be deployed at different switching levels, taking into account multiple performance indicators such as chip stability, switching speed, power consumption, and extinction ratio.

[0043] The thermo-optical Mach-Zehnder interferometer switch employs a silicon dioxide thermo-optical modulation structure, achieving optical path switching by changing the refractive index of the waveguide through heated electrodes. It boasts an extinction ratio greater than 25dB, making it suitable for scenarios where high stability is more important than high switching speed. The carrier-modulated Mach-Zehnder interferometer switch utilizes silicon-based optoelectronic technology, changing the waveguide refractive index by injecting carriers. Its switching speed reaches the microsecond level, making it suitable for scenarios requiring rapid optical path reconstruction. The phase-change material switch uses a Ge2Sb2Te5 phase-change film as the modulation layer, achieving optical path switching through changes in the phase-change state. After switching, no continuous power supply is required, significantly reducing the chip's static power consumption. The micro-ring switch employs a silicon-based micro-ring resonant cavity structure, achieving optical path switching by tuning the resonant wavelength of the micro-ring. Its extremely small device size enables ultra-high-density integration. The on-chip microelectromechanical system (MEMS) switch uses a micro-mirror structure, changing the optical path direction through mechanical movement. It boasts an extinction ratio greater than 30dB and crosstalk less than -40dB. In the same chip, different types of switching units can be used at different switching levels. The input and output stages use thermo-optical switches to ensure stability, while the intermediate stage uses carrier modulation switches to improve switching speed, achieving the optimal combination of performance.

[0044] Furthermore, the on-chip monitoring and calibration structure includes at least one of the following: an optical tap, a reference optical channel, and a photodetector disposed in the port region, inside the switch subarray, at the port group boundary, or at the intermediate stage output.

[0045] The on-chip monitoring and calibration structure deploys modules such as optical taps, reference optical channels, and monitoring photodetectors near ports, inside switch subarrays, at port group boundaries, or at intermediate stage outputs. This covers key monitoring nodes throughout the entire optical path, collecting operational status parameters. By importing a preset reference optical signal, the absolute insertion loss value of the entire path can be accurately calibrated, ensuring the accuracy of the monitoring data.

[0046] In some embodiments, the optical taps employ a weakly reflective waveguide branch structure with a splitting ratio of 1%, deployed at the rear end of each input port, the internal output of each optical switch subarray, the boundary of each computing node port group, and each output port of the intermediate-level rearrangement network. The reference optical channel features an integrated narrow-linewidth reference laser at the chip's corner, outputting a stable 1550nm reference light signal. This signal is guided through the waveguide branches to each optical path under test for calibrating the absolute insertion loss of the optical path. The photodetector is a germanium-silicon integrated array detector, corresponding one-to-one with the optical taps, integrated into the chip's edge region. It converts the acquired optical power signal into an electrical signal, which is transmitted to the controller via an external ADC circuit, enabling real-time acquisition of all optical path parameters across the entire chip. The sampling interval can be set to 10ms, fully meeting the real-time monitoring requirements of the optical network.

[0047] Furthermore, the on-chip monitoring and calibration structure is configured to generate an optical path status table. This table includes at least one or more of the following: input port number, output port number, candidate intermediate optical path, operating wavelength, insertion loss, wavelength-dependent loss, crosstalk value, switch bias value, chip temperature, real-time monitoring power, and fault flag. The path status table supports real-time updates, providing complete physical layer data support for subsequent optical path configuration decisions by the controller.

[0048] In some embodiments, all parameters collected by the on-chip monitoring and calibration structure are aggregated and processed by the FPGA control unit on the periphery of the chip to generate a structured optical path status table, which is stored in the DDR4 memory attached to the FPGA. Each record in the optical path status table corresponds to a port pair of an input port and an output port, recording the three candidate intermediate optical paths for that port pair, as well as the supported operating wavelength range, measured insertion loss value, full-band wavelength-dependent loss curve, crosstalk value of each switching unit, current switch bias voltage value, chip real-time temperature, currently monitored optical power value, and fault flag bit for each optical path. When the insertion loss of an optical path suddenly increases by more than 3dB, or the crosstalk value exceeds -20dB, the optical path is marked as faulty, and subsequent services are prohibited from using that optical path. The optical path status table is automatically updated every 100ms to ensure the real-time performance of all data.

[0049] Furthermore, each physical port, through at least eight 100 Gbps wavelength division multiplexing (WDM) optical channels, at least five 200 Gbps WDM optical channels, and at least three 400 Gbps WDM optical channels, or equivalent wavelength or rate combinations, forms a single-port transmission capacity exceeding 800 Gbps, and no bit errors were observed within the preset bit error rate test window. No bit errors were observed in any of the high-speed optical signals transmitted through the all-optical switching link, fully meeting the requirements for long-term stable operation of the cluster.

[0050] In some embodiments, the transmission capacity of a single physical port can be achieved through various equivalent combinations: 8 channels of 100Gbps PAM4 wavelength division multiplexing (WDM) channels, achieving a total rate of 800Gbps; 5 channels of 200Gbps PAM4 WDM channels, achieving a total rate of 1Tbps; and 3 channels of 400Gbps PAM4 WDM channels, achieving a total rate of 1.2Tbps. In the testing and verification phase, a standard bit error rate analyzer was used to generate a PRBS31 pseudo-random sequence, which was modulated by an optical module and input into the optical path switching chip. After transmission through an all-optical switching link, bit error rate statistics were performed at the receiving end. Within a preset 72-hour bit error rate test window, the bit error rate of all channels was less than 1× No errors were observed, fully meeting the requirements for long-term stable operation of the AI ​​cluster.

[0051] Furthermore, the hardware corresponding to the computing node port group can be any one or more combinations of field-programmable gate arrays, graphics processors, application-specific integrated circuits (ASICs), CPUs, storage controllers, accelerator cards, and computing units within the rack. Different heterogeneous computing nodes can be directly connected to the optical path switching chip through standardized port interfaces, achieving all-optical high-speed interconnection across heterogeneous nodes without the need for additional adapter hardware.

[0052] In some embodiments, each physical port of the compute node port group is equipped with a standardized QSFP-DD optical module interface, which can directly connect to different types of computing hardware via optical fiber: connecting to field-programmable gate arrays (FPGAs) to achieve low-latency real-time signal processing node interconnection; connecting to graphics processors (GPUs) to achieve high-bandwidth data interaction in AI training clusters; connecting to application-specific integrated circuits (ASICs) to achieve high-speed interconnection of specific computing power acceleration nodes; connecting to CPUs to achieve communication between general-purpose compute nodes; connecting to storage controllers to achieve low-latency data access to distributed storage nodes; connecting to accelerator cards to achieve high-speed data transmission between heterogeneous computing resources; and connecting to compute units within a rack to achieve all-optical interconnection of all computing resources within a single rack. All hardware can be directly connected to the optical path switching chip without additional adapter boards, adapting to the cluster networking requirements of different computing power architectures.

[0053] refer to Figure 1 The present invention also provides an optical interconnect system, comprising: The aforementioned optical path switching chip; Multiple computing nodes, each computing node being connected to at least one physical port of the optical path switching chip; Wavelength division multiplexing transceiver module is used for multi-optical channel wavelength division multiplexing and demultiplexing transmission within a single physical port, so as to carry optical signals with different line rates and different modulation formats on the same optical fiber link, thereby adapting to different types of optical transceivers; The controller is used to configure the optical path based on the computational task traffic matrix and the optical path status of the optical path switching chip.

[0054] This system is centered around an N×N on-chip optical path switching chip, coupled with multiple heterogeneous computing nodes, wavelength division multiplexing (WDM) transceiver modules, and a controller. Each computing node is directly connected to at least one physical port of the chip. The WDM transceiver modules carry multiple high-speed optical channels with different line rates, modulation formats, and transceivers of different generations within a single physical port. The controller automatically generates an optical path configuration adapted to the service requirements based on the computing task traffic matrix and the chip's path status table. The entire system supports high-performance all-optical interconnection of heterogeneous computing nodes without requiring optical amplifiers within the chip's internal links.

[0055] In some embodiments, the system uses an optical path switching chip as the core switching node. The optical interfaces of all computing nodes are directly connected to the physical ports of the optical path switching chip via single-mode fiber, without the need for a traditional electrical switch. The wavelength division multiplexing transceiver module adopts a pluggable QSFP-DD package and integrates an 8-channel 100G PAM4 optical transmitter and receiver unit. It has a built-in arrayed waveguide grating wavelength division multiplexer, which can perform multiplexing and demultiplexing of multi-channel optical signals on the same fiber, supporting the simultaneous transmission of optical signals with different rates and modulation formats. The controller adopts a heterogeneous control architecture of high-performance ARM and FPGA. The ARM core is responsible for running traffic analysis and topology generation algorithms, while the FPGA core is responsible for generating drive control signals for the optical switches. Based on the real-time traffic matrix of the computing task and combined with the optical path status table of the optical path switching chip, the system dynamically completes the configuration and adjustment of the optical path. The end-to-end transmission delay of the entire system can be controlled within 100ns, which is far lower than the microsecond-level delay of traditional electrical switching networks.

[0056] Furthermore, no optical amplifier or gain compensation device is configured between the input and output ports of the optical path switching chip, and it supports single-port transmission of over 800Gbps with zero bit error rate within a preset test window. This solution completely avoids the problems of noise accumulation, high power consumption, and complex control introduced by optical amplifiers.

[0057] In some embodiments, no optical amplifiers or gain compensation devices are configured on any optical path between the input and output ports of the optical switching chip in the entire optical interconnect system. All optical signal transmission is completed entirely within the passive optical chip. In system testing, a single port carries eight 100Gbps PAM4 signals. Optical path switching between any two ports is achieved through the optical switching chip. Within a preset test window of 72 consecutive hours, the bit error rate of all channels remains consistently at 1× The following achieves zero-error transmission. This solution eliminates the signal noise accumulation problem caused by optical amplifiers, significantly improving the long-term operational stability of the system, while also reducing overall power consumption compared to traditional optical switching systems with optical amplification.

[0058] Furthermore, if an optical amplifier or gain compensation device is added to the external link of the system, the controller will still prioritize physical optical paths with lower wavelength-dependent loss and better spectral flatness to alleviate the power imbalance between channels caused by the limited gain bandwidth of the optical amplifier.

[0059] When an optical amplifier or external gain compensation module exists in the external long-distance link, the controller still prioritizes referring to the path state table to select a physical optical path with lower wavelength-dependent loss and better spectral flatness. It utilizes the chip's own ultra-wideband flat response to offset the inter-channel power imbalance caused by the limited gain bandwidth of the optical amplifier. In this case, the optical amplifier only serves as a supplement to the external link budget and is no longer a necessary module for compensating for OCS wavelength-dependent loss.

[0060] In some embodiments, when an optical amplifier or gain compensation device is added to the external long-distance interconnect link of the system, the controller first reads the wavelength-dependent loss data of all candidate optical paths in the optical path status table, and preferentially selects physical optical paths with wavelength-dependent loss less than 0.5dB and spectral flatness better than 1dB for service configuration. These optical paths have very flat full-band loss curves. After amplification by the limited gain bandwidth of the optical amplifier, the power difference between different wavelength channels can be controlled within 2dB, effectively alleviating the power imbalance problem between channels caused by the uneven gain bandwidth of the optical amplifier, avoiding nonlinear effects caused by excessively high power in some channels, or bit errors at the receiver caused by excessively low power in some channels, and significantly improving the transmission stability of long-distance optical interconnect links.

[0061] Furthermore, the controller converts the computation task graph into an inter-node flow matrix, and determines a logical topology of any one or more combinations of point-to-point direct connection, ring, pipeline, group full interconnect, tree reduction, and single-hop relay interconnect based on the inter-node flow matrix.

[0062] The controller parses the computing task graph sent down from the upper layer into a flow matrix between nodes. Based on the communication characteristics of different computing tasks, it automatically generates an appropriate logical topology, which can support various topology forms such as point-to-point direct connection, ring, pipeline, group full interconnection, tree reduction, direct interconnection plus single-hop relay, etc., and flexibly match the communication mode of different computing tasks.

[0063] In some embodiments, the controller has a built-in task graph parsing module that receives the computing task graph from the upper-layer cluster scheduling system. It converts the communication relationships between different computing nodes in the task graph into an N×N inter-node traffic matrix, where each element corresponds to the communication bandwidth requirement between two nodes. Based on the distribution characteristics of the traffic matrix, it automatically generates corresponding logical topologies: for services primarily involving point-to-point data transmission, it generates a point-to-point direct connection topology; for services involving circular data flow, it generates a ring topology; for pipelined inference services of AI models, it generates a pipelined topology; for services requiring high-bandwidth interaction between all nodes, it generates a packet-based fully interconnected topology; for data aggregation services, it generates a tree-structured reduction topology; and for scenarios where some nodes cannot directly establish optical paths, it generates a single-hop relay interconnected topology. Multiple logical topologies can be flexibly combined according to business needs to maximize adaptability to different computing task communication modes.

[0064] Furthermore, when configuring the optical path, the controller uses at least two of the following constraints: link bandwidth requirement, optical path insertion loss, wavelength-dependent loss, optical path crosstalk, port health status, fault domain, reconfiguration difference, and service interruption threshold.

[0065] When generating optical path configurations, the controller uses at least two of the following as joint constraints: link bandwidth requirements, path insertion loss, wavelength-dependent loss, crosstalk, port health status, fault domain, reconfiguration differences, and service interruption threshold. This ensures that the final generated optical path configurations simultaneously meet the upper-layer service requirements and the on-chip physical layer's optical transmission constraints, avoiding invalid configurations that only satisfy logical connectivity but do not meet the optical power budget.

[0066] In some embodiments, when configuring optical paths, the controller simultaneously considers link bandwidth requirements, optical path insertion loss, wavelength-dependent loss, optical path crosstalk, port health status, fault domain, reconfiguration differences, and service interruption thresholds as constraints: First, it ensures that the available bandwidth of the optical path meets the link bandwidth requirements; second, it prioritizes optical paths with low insertion loss and low wavelength-dependent loss; and it avoids optical paths with crosstalk higher than -20dB and ports marked as faulty in their health status. During optical path reconfiguration, it ensures that the physical path difference between the new and original optical paths is minimized, and controls the service interruption time during optical path reconfiguration within a preset service interruption threshold to avoid significant impact on upper-layer services. Through joint optimization of multiple constraints, optimal allocation of optical network resources can be achieved while meeting service requirements.

[0067] Furthermore, the controller is configured to select different physical optical paths for the same logical topology in order to reduce optical path loss or avoid faulty ports while keeping the logical connection relationship unchanged.

[0068] The controller pre-stores multiple different physical candidate paths for the same logical connection relationship. While maintaining the logical topology between all nodes, it can flexibly switch to different physical paths. This operation reduces path loss and proactively avoids faulty ports without modifying the upper-layer service configuration, thus improving the system's fault self-healing capability and operational stability.

[0069] In some embodiments, the controller incorporates an optical path redundancy management module that pre-calculates three different physical optical paths as candidate paths for the same logical connection. When the currently used physical optical path experiences performance degradation such as increased insertion loss or crosstalk during system operation, the controller selects another candidate physical optical path with lower loss, ensuring a smooth optical path switchover while maintaining the logical connections between all nodes. This operation achieves dynamic optical path optimization without modifying the communication configuration of upper-layer services. Furthermore, when a port fails, switching physical optical paths avoids the faulty port, ensuring uninterrupted service and significantly improving the system's fault self-healing capability.

[0070] Furthermore, the controller is configured to switch between different logical topologies according to the business operation phase; at different stages of neural network inference or training tasks, pipeline topology, adjacency topology, reduction topology or fully interconnected topology are formed respectively.

[0071] The controller can automatically switch between different logical topologies based on the different stages of computing operations. For example, at different stages of neural network inference or training tasks, it can generate pipeline topologies, adjacency topologies, reduction topologies, or fully interconnected topologies, respectively. The most efficient communication topology is matched to each stage, which greatly improves the overall communication efficiency of the cluster.

[0072] In some embodiments, the controller can automatically switch the corresponding optimal logical topology according to different operational stages of the AI ​​task: during the neural network inference stage, data transmission between computing nodes in different layers is completed sequentially, automatically generating a pipeline topology and maximizing the optical path bandwidth between adjacent nodes in the pipeline, significantly improving inference throughput; during the forward propagation stage of neural network training, an adjacency topology is generated to ensure low-latency data interaction between adjacent GPU nodes; during the backpropagation gradient aggregation stage of training, a reduction topology is generated to quickly summarize the gradient data of all nodes; during the parameter synchronization stage of training, a fully interconnected topology is generated to achieve rapid parameter synchronization between all nodes. Through phased dynamic topology switching, the overall communication efficiency of the AI ​​cluster can be improved.

[0073] refer to Figure 2 The present invention also provides an optical interconnect reconfiguration control method, comprising the following steps: Collect the computation task graph and the list of computation nodes; Construct an inter-node flow matrix based on the computation task graph; Read the optical path status table of the optical path switching chip; wherein, the optical path status table stores the loss or crosstalk status of at least some port pairs under different wavelengths or different candidate optical paths; Generate the target logical topology based on the inter-node traffic matrix and the optical path status table; Solve for the physical optical path that satisfies the preset optical power budget and crosstalk constraints within the target logical topology; The physical optical path generation switching unit is configured accordingly; Control the optical path switching chip to perform optical path reconstruction; The physical optical path is configured to utilize the ultra-wideband, low-loss transmission characteristics of the weakly bound waveguide of the planar optical waveguide platform, supporting single-port transmission speeds exceeding 800 Gbps without optical amplifiers and / or gain compensation devices, and is compatible with wavelength division multiplexing (WDM) optical channels of different rates within the same physical port. The entire process supports single-port transmission speeds exceeding 800 Gbps without relying on optical amplifiers or gain compensation modules, while simultaneously being compatible with WDM optical channels of different rates within the same physical port.

[0074] In some embodiments, the execution steps of this reconfiguration control method are all completed on the heterogeneous FPGA and ARM platforms of the controller: First, the currently running computing task graph is collected from the cluster scheduling system, and the list of all online computing nodes in the system is read simultaneously; through the task graph parsing module, the communication bandwidth requirements between different nodes are quantified to construct and generate an inter-node traffic matrix; the optical path status table updated in real time by the optical path switching chip is read from the DDR4 memory attached to the controller; combining the bandwidth requirements of the traffic matrix and the optical path performance parameters in the optical path status table, the target logical topology adapted to the current service is solved; under the constraints of the target logical topology, the optimal set of physical optical paths that meets the preset optical power budget and crosstalk constraints is further solved; according to the path of each physical optical path, the corresponding switching state configuration sequence of all optical switching units is generated; the configuration sequence is sent to the driving circuit of the optical path switching chip to control the optical path switching chip to complete the optical path reconfiguration. The entire process makes full use of the ultra-wideband low-loss characteristics of weakly bound waveguides, stably supporting high-speed transmission of over 800Gbps per port without optical amplifiers, while being compatible with wavelength division multiplexing optical channels of different rates within the same physical port.

[0075] Furthermore, before controlling the optical path switching chip to perform optical path reconstruction, the method further includes: Pre-build a backup optical path between optical transmission nodes that is physically independent and topologically parallel to the original optical path; A standard reference light with a preset optical power and a pseudo-random training sequence covering all idle wavelengths are injected into the preparatory optical path. Optical signal data are collected in real time at a preset sampling frequency through optical tap sampling units deployed at both ends of the optical path. The insertion loss value and adjacent channel crosstalk coefficient of the preparatory optical path are calculated. When the calculated insertion loss is less than or equal to a preset loss threshold, and the crosstalk coefficient is less than or equal to a preset crosstalk threshold, the service data stream is smoothly switched from the original optical path to the backup optical path with zero packet loss.

[0076] Before the optical path switching chip is officially controlled to perform the reconstruction operation, a backup optical path independent of the current original optical path is built in advance. The parameters such as loss and crosstalk of the backup optical path are detected through reference light, idle wavelength, training sequence or service optical tap. When the detection results fully meet the preset threshold, the service flow is smoothly switched from the original optical path to the backup optical path with zero packet loss to avoid service errors during the reconstruction process.

[0077] In some embodiments, before optical path reconstruction, the controller pre-builds a backup optical path between the two optical transmission nodes that need adjustment. This backup optical path is physically independent and topologically parallel to the original optical path currently in use. After the backup optical path is built, the controller controls the optical modules at both ends of the backup optical path to inject standard reference light with a preset optical power and a pseudo-random training sequence covering all idle wavelengths into the backup optical path. Optical signal data is collected in real time at a preset sampling frequency of 1 GS / s using optical tap sampling units deployed at both ends of the optical path. The actual insertion loss value of the backup optical path and the crosstalk coefficient of adjacent channels are calculated. When the insertion loss is detected to be less than a preset 15 dB loss threshold and the crosstalk coefficient is less than a preset -20 dB crosstalk threshold, the controller smoothly switches the service data stream from the original optical path to the backup optical path with zero packet loss through a frame alignment mechanism. The packet loss rate during the entire switching process is 0, and it will not affect upper-layer services.

[0078] Furthermore, after the physical optical path is solved, the port performance pre-verification and optical layer multi-dimensional compliance verification of the physical optical path are performed simultaneously. If the verification fails, the resource configuration and / or topology weights are iteratively adjusted according to the specified priority, and the physical optical path is solved again.

[0079] When the physical optical path obtained by the solution does not meet the loss threshold, crosstalk threshold, port health status or fault domain constraints, the controller adjusts the port group mapping, wavelength allocation, candidate intermediate path or logical topology weight in sequence according to the preset priority, and re-solves the optical path until the generated optical path configuration fully meets all preset constraints.

[0080] After the physical optical path is solved, the controller first performs a pre-verification of port performance, checking the working status of the optical module and the port health status of each selected physical port to confirm that all ports are in a normal and usable state. Then, it performs a multi-dimensional compliance verification of the optical layer, checking whether the insertion loss, wavelength-dependent loss, and crosstalk values ​​of all selected physical optical paths meet the preset constraints. If the verification fails, the controller iteratively adjusts the optical network resource configuration according to the specified priority of "first adjusting wavelength allocation, then adjusting optical path, and finally optimizing topology weights," and re-solves the physical optical path until all verification items are qualified. Only then will it issue an optical path reconstruction command to avoid errors in subsequent service transmissions caused by unqualified optical path configurations.

[0081] Furthermore, the optical path reconstruction includes: Perform state modification operations on the switching units in the optical switching network in batches; After completing the status modification of each batch of switching units, at least one operating status parameter of the corresponding optical path is collected in real time. Based on the collected operational status parameters, the validity of the current batch of optical path reconstruction operations is determined.

[0082] During the refactoring process, all switch units that need to change their status are divided into multiple batches for modification. After the status modification of each batch of switch units is completed, the power, bit error rate, bias status, or port health status of the relevant links are immediately monitored in real time. Only after confirming that the refactoring of that batch is effective can the next batch of modification operations be started, thus avoiding large-scale link anomalies caused by batch switching.

[0083] In some embodiments, when performing optical path reconfiguration, the controller divides all switching units requiring state modification into multiple batches, with each batch containing no more than 10% of the total number of switching units. State modification operations are performed on the switching units in the optical switching network in batches. After completing the state modification of each batch of switching units, at least one operating status parameter, such as optical power and insertion loss, is immediately acquired in real time via an on-chip monitoring and calibration structure. The acquired parameter is compared with a preset normal threshold to determine the validity of the current batch's optical path reconfiguration operation. If the current batch's reconfiguration operation is valid, the next batch of switching state modifications continues; if an anomaly is detected, subsequent batches are immediately stopped to prevent the fault from escalating.

[0084] Furthermore, when abnormal events such as link power exceeding limits, bit error rate exceeding standards, abnormal optical module bias, or deterioration of port health status are detected during the optical path reconstruction process, an optical path rollback operation is triggered. The optical path rollback operation includes: restoring the configuration state of all or part of the associated switch units to the previous stable operating configuration recorded before the current optical path reconstruction was performed, or directly switching the service link to a pre-stored alternative optical path, so that the transmission service can be restored to normal operation within a preset time.

[0085] If an abnormal link event is detected during the reconstruction process, the controller immediately performs an optical path rollback operation to restore the state of at least some switching units to the previous stable operating configuration, or directly switches the service link to a pre-stored alternative path, so that the transmission service can be restored to normal operation in a very short time and avoid long-term service interruption.

[0086] In some embodiments, during optical path reconfiguration, the on-chip monitoring and calibration structure monitors the operating status of all optical paths in real time. When abnormal events such as link power exceeding limits, bit error rate exceeding standards, abnormal optical module bias, or deterioration of port health are detected, an optical path rollback operation is immediately triggered. The controller quickly restores the configuration status of all or part of the associated switching units to the previous stable operating configuration recorded before the current optical path reconfiguration, or directly switches the service link to a pre-stored alternative optical path. The entire rollback operation takes less than 1ms, allowing the transmission service to return to normal operation within a preset duration of 5ms, avoiding the impact of prolonged service interruption on cluster operation.

[0087] Furthermore, the inter-node traffic matrix is ​​generated by fusing at least one of the following: compiler static analysis results, runtime counter data, historical traffic window statistics, and application explicit declaration information.

[0088] The data for generating the inter-node traffic matrix can come from four independent dimensions: compiler static analysis results, runtime traffic counter statistics, historical traffic window statistics, and bandwidth requirements explicitly reported by the application. By weighted and fused data from multiple sources, the final inter-node traffic matrix is ​​obtained, which significantly improves the accuracy of traffic prediction and provides a reliable basis for subsequent topology generation.

[0089] In some embodiments, the data sources for generating the inter-node traffic matrix include four dimensions: First, static analysis results from the compiler are introduced, allowing the compiler to pre-parse the code of the computation task and predict the communication bandwidth requirements between different nodes; second, runtime counter data is collected, using the network counters built into the cluster nodes to statistically analyze the current communication traffic in real time; simultaneously, historical traffic window statistics are introduced, using a moving average of historical traffic data from the past 10 minutes to predict traffic trends; finally, explicit declaration information from applications is received, with upper-layer applications directly reporting their own communication bandwidth requirements. By merging the data from these four dimensions using a weighted fusion algorithm, the prediction accuracy of the generated inter-node traffic matrix can reach over 95%, providing an accurate basis for subsequent optical path configuration.

[0090] Compared with the prior art, the present invention has at least the following beneficial effects: First, the present invention uses an N×N expandable optical path switching chip as its core, wherein N is not less than 32 and preferably includes 32 and 64, which can support the interconnection of larger-scale computing nodes or port groups, while avoiding limiting the protection scope to a single port number.

[0091] Secondly, this invention incorporates the wide-spectrum, low-loss characteristics of PLC weakly bound waveguides into the OCS chip structure, enabling multi-stage optical paths to maintain low insertion loss and wavelength-dependent loss over a wide spectrum, thus making it more suitable for large-port-count, broadband, and WDM-friendly optical path switching than strongly bound waveguide platforms.

[0092] Third, this invention enables each physical port to carry more high-speed optical channels through port grouping wavelength division multiplexing, and allows different wavelength channels to carry signals of different rates or different transceivers, thereby improving port resource utilization, heterogeneous interconnect compatibility, and single-port aggregation rate of over 800 Gbps.

[0093] Fourth, this invention reduces the power budget pressure of the all-optical switching link by using the ultra-low insertion loss of the PLC, enabling the OCS link to still work without optical amplifiers or gain compensation devices, thus avoiding the introduction of noise, power consumption, size and control complexity by optical amplifiers.

[0094] Fifth, this invention addresses the limitations of optical amplifiers in gain bandwidth and gain flatness, making it difficult to compensate for wavelength-dependent losses caused by different wavelengths and optical paths within the OCS. Therefore, it improves multi-wavelength link consistency from the source by utilizing the chip's own ultra-wideband flat response.

[0095] Sixth, the present invention considers both the computational task flow matrix and chip physical constraints during topology reconstruction, avoiding the problem of only satisfying logical connections without satisfying preset optical power budget, wavelength compatibility, or wide-spectrum loss flatness.

[0096] Seventh, this invention controls insertion loss, crosstalk, wavelength-dependent loss, and bias drift under large port count conditions through on-chip monitoring, optical path status table, and calibration closed loop.

[0097] Eighth, the present invention can reduce the impact of the reconstruction process on computing services by using pre-optical path preparation, batch switching and rollback strategies.

[0098] Ninth, the present invention can reduce the need for multi-stage electrical switching and intermediate photoelectric conversion, and support single-port zero-error transmission of more than 800 Gbps without optical amplifiers or gain compensation devices, which helps to reduce interconnection latency, system power consumption and link complexity. Attached Figure Description

[0099] Figure 1 This is a schematic diagram of the optical path switching system reconfiguration process provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the reconfiguration control method provided in an embodiment of the present invention; Figure 3 A schematic diagram of the cross-section of the optical path switching chip and the stacked structure of the weakly bound waveguide provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the process of achieving over 800 Gbps transmission and being compatible with heterogeneous rates through multi-wavelength WDM on a single physical port, as provided in an embodiment of the present invention. Detailed Implementation

[0100] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0101] Example 1: Expandable N×N optical path switching chip In this embodiment, the optical path switching chip includes N input ports and N output ports, where N is a positive integer not less than 32. In a preferred embodiment, N is 32 or 64. The input ports and output ports are connected to external fiber arrays, silicon photonic transceiver chips, or board-level optical connectors via edge couplers, grating couplers, or other optical coupling structures.

[0102] The optical path switching chip is formed on a PLC planar waveguide platform. The PLC waveguide employs a weakly bound transmission method, resulting in a relatively large mode field distribution that is closer to that of standard single-mode fiber. This weakly bound characteristic reduces end-face coupling loss, scattering loss caused by waveguide sidewall perturbations, loss fluctuations due to waveguide crossings, and wavelength-dependent loss introduced by bending structures. Compared to strongly bound high-refractive-index-difference waveguides, PLC weakly bound waveguides, although with larger unit sizes, are more suitable for applications like OCS that require long optical paths, multi-stage switching, wide spectrum, and low loss.

[0103] In one embodiment, the PLC platform ensures that the selected optical path meets preset insertion loss and wavelength-dependent loss thresholds across a spectral range of at least 40 nm, at least 80 nm, or at least 100 nm. This wide-spectrum capability allows for the configuration of more WDM channels on the same physical port without sacrificing port capacity due to excessive edge wavelength loss. For multi-level N×N OCS, the controller can use available wavelengths across the wide spectral range as part of a port resource pool and allocate different wavelengths and rates based on the transceiver capabilities of different computing nodes.

[0104] A multi-stage on-chip optical switch network is positioned between the input port array and the output port array. The multi-stage on-chip optical switch network is divided into an input stage, an intermediate stage, and an output stage. The input stage includes multiple optical switch subarrays for receiving optical signals from different input port groups; the intermediate stage rearrangement network is used to redistribute optical paths among the port groups; the output stage includes multiple optical switch subarrays for outputting optical signals to the target output port.

[0105] In a preferred embodiment, the N ports are divided into multiple port groups of 4, 8, or 16 ports each. For a 32×32 implementation, port groups can be divided into 4 or 8 ports; for a 64×64 implementation, port groups can be divided into 8 or 16 ports each. High-frequency communication within a port group is preferentially accomplished through the shortest optical path, while communication between port groups is accomplished through an intermediate-level rearrangement network. Optical path length differences and local thermal crosstalk can be reduced through port group arrangement, folded waveguides, low-loss crossovers, local bypasses, and thermal isolation structures.

[0106] Example 2: Port-based Wavelength Division Multiplexing Access In this embodiment, each physical port carries multiple wavelength division multiplexing optical channels. Multiple wavelengths can be located in the O band, such as 1270 nm, 1290 nm, 1310 nm and 1330 nm, or other communication bands and wavelength spacings can be used.

[0107] Since the function of an OCS (Optical Channel Switch) is to establish optical paths rather than to perform electrical domain processing at specific rates, its ideal state should be wavelength and rate transparency. The ultra-wideband, low-loss response of a PLC (Polymerized Least Binary Waveguide) allows a single OCS port to simultaneously support multiple WDM wavelengths. Different wavelengths can carry data streams at the same rate or different rates, such as some wavelengths at 100 Gbps and others at 200 Gbps, or different generations of optical transceivers can be mixed and connected within the same port. This way, as computing nodes are upgraded, older and newer rate devices can share the same OCS platform without needing to redesign the switching chip due to excessively narrow spectral windows or high wavelength-dependent losses.

[0108] When each physical port carries more than eight 100 Gbps wavelength channels, at least five 200 Gbps wavelength channels, at least three 400 Gbps wavelength channels, or other equivalent wavelength / rate combinations, a single physical port can provide a transmission capacity exceeding 800 Gbps. Without optical amplifiers or active gain compensation devices, the system, through low-loss on-chip optical paths, broadband flat transmission, port group loss equalization, and receiver decision margin design, ensures that no bit errors are observed in single-port transmission exceeding 800 Gbps within a preset test window. The above values ​​are examples illustrating the relationship between the number of ports, wavelengths, and channel rates, and do not limit the scope of protection of this invention.

[0109] If conventional optical amplifiers are used to compensate for multi-wavelength links, the power differences between different wavelength channels after passing through multiple OCS optical paths are difficult to compensate uniformly due to the limited gain bandwidth, gain spectral flatness, and noise figure of the amplifiers. Especially when different input and output optical paths have different crossover times and different wavelength-dependent losses, the gain curve of a single amplifier cannot simultaneously match all optical paths. Therefore, this embodiment prioritizes relying on the low insertion loss and wide spectral flatness of the PLC's weakly bound waveguide itself to achieve gain-free transmission, rather than relying on subsequent amplifiers to compensate for chip losses.

[0110] When configuring optical paths, the controller not only determines whether the input and output ports are connected, but also whether the target physical optical path simultaneously meets the loss, crosstalk, and rate margin thresholds at multiple target wavelengths. If a candidate optical path has low loss at the center wavelength but excessive loss at the edge wavelengths, the controller can select another candidate optical path, adjust the wavelength allocation, or modify the port group mapping.

[0111] Example 3: Optical Path Status Table and On-Chip Calibration In this embodiment, the on-chip monitoring and calibration structure includes one or more of the following: a low-ratio optical tap, a reference optical channel, a monitoring photodetector, and a temperature sensor. The system generates an optical path status table during factory testing, power-on initialization, or operation.

[0112] The optical path status table may include the following information: input port number, output port number, candidate intermediate optical path number, wavelength number, insertion loss, wavelength-dependent loss, crosstalk level, switching unit bias value, monitoring power, temperature status, fault port marker, and fault switching unit marker. The controller selects the physical optical path according to the optical path status table and applies the corresponding bias to the switching unit.

[0113] When a decrease in power, increase in crosstalk, or bias drift is detected in a certain optical path, the controller can select another physical optical path while keeping the logical topology unchanged, or it can trigger a logical topology adjustment.

[0114] Example 4: Topology Reconstruction for Computational Tasks In this embodiment, the controller first acquires a computation task graph. This graph can originate from neural network model partitioning, distributed training frameworks, compilers, runtime systems, or applications. The controller determines the inter-node traffic matrix based on the task graph and corrects this matrix using historical traffic data or runtime counters.

[0115] For inference pipeline tasks, the controller configures the computation nodes corresponding to adjacent pipeline stages as low-loss direct-connect optical paths and reserves backup optical paths for residual connections or cross-layer connections. For distributed training tasks, the controller can configure adjacency or pipeline topology in the forward and backward computation stages, and configure grouped full interconnect, tree reduction, or ring topology in the gradient synchronization stage.

[0116] After generating the target topology, the controller solves for the physical optical paths within the target topology. During the solution process, the controller can minimize the maximum link utilization, minimize the average optical path hops, minimize the reconfiguration difference, minimize optical path loss, or maximize the remaining capacity after a failure.

[0117] Example 5: Low-interruption reconfiguration In this embodiment, the controller establishes a backup optical path before switching to a new topology. The backup optical path can use idle ports, idle wavelengths, low-priority channels, or reserved channels. The system detects whether the backup optical path meets the loss, crosstalk, and bit error thresholds by using reference light, training sequences, or service light taps.

[0118] If the preliminary optical path detection meets the standards, the controller adjusts the electrical layer routing weights, task scheduling queues, or service transmission optical paths to gradually migrate services to the new optical path. Subsequently, the controller modifies the on-chip optical switch unit states in batches. After each batch of modifications, the system checks the relevant link status. If the detection fails, the controller performs a rollback, restoring the relevant switch units to the previous stable state, or switching to an alternative physical optical path.

[0119] Example 6: Differences from Existing Solutions The difference between this invention and medium-port-count on-chip optical switches is that this invention focuses on a scalable multi-port scale with N not less than 32, preferably covering 32×32 and 64×64, and proposes port group division, intermediate-level rearrangement, optical path status table, on-chip monitoring and calibration, single-port uncompensated transmission exceeding 800 Gbps, and calculation-driven reconfiguration for this scale.

[0120] The difference between this invention and the data center MEMS optical path switching solution is that this invention is aimed at on-chip planar optical waveguide chips and computing node port groups, emphasizing on-chip optical path loss, wavelength-dependent loss, crosstalk and bias calibration constraints, rather than performing free space optical path switching only at the rack level or data center level.

[0121] This invention also defines an expandable optical path switching chip body, port-configured wavelength division multiplexing, optical path status table, chip physical constraint closed loop, and a single-port zero-error transmission capability exceeding 800 Gbps without gain compensation.

[0122] This invention does not prioritize minimizing unit size. Instead, it addresses the requirements of OCS for hyperspectral, low-loss, wavelength transparency, and rate transparency by utilizing PLC weakly bound waveguides to reduce wavelength-dependent losses and coupling losses in multi-stage optical paths, thereby improving the number of WDM wavelengths, port rate compatibility, and heterogeneous device interconnection capabilities.

[0123] Example 7: Alternative Implementation Methods The number of ports in this invention can be configured as needed to be 32×32, 64×64, 64×128, 128×128, or other scales. The number of wavelength division multiplexing channels can be 4, 8, 16, or other quantities. The rate of each wavelength channel can be 25 Gbps, 50 Gbps, 100 Gbps, 200 Gbps, 400 Gbps, or higher. Single-port transmission exceeding 800 Gbps can be achieved through more than 8×100 Gbps, at least 5×200 Gbps, at least 3×400 Gbps, or other equivalent wavelength / rate combinations.

[0124] The controller of this invention can be deployed in a host, FPGA, baseboard management controller, rack controller, network controller, or data center software-defined network controller. The topology solving algorithm can employ integer programming, minimum cost flow, graph matching, heuristic search, simulated annealing, reinforcement learning, or a combination thereof.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the concept and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An optical circuit switching chip, characterized by, include: An input port array, comprising N input ports; An output port array comprising N output ports, where N is a positive integer not less than 32; A multi-level on-chip optical switch network is connected between the input port array and the output port array to establish a reconfigurable optical path between any input port and any output port. The multi-level on-chip optical switch network is integrated into a planar optical waveguide platform. An intermediate-level rearrangement network is set between the input and output stages of the multi-stage on-chip optical switch network to rearrange the optical paths between different port groups. An on-chip monitoring and calibration structure is used to collect at least one parameter of optical power, insertion loss, crosstalk, switch bias drift, and port health status of part or all optical paths. Among them, at least some of the N input ports and N output ports are configured as computing node port groups, and each computing node port group carries multiple wavelength division multiplexing optical channels through a single physical port; The planar optical waveguide platform is equipped with a weakly bound waveguide, which is configured to reduce optical path insertion loss and wavelength correlation loss within a preset hyperspectral wavelength range, enabling the optical path switching chip to achieve a single-port transmission rate of over 800Gbps under the condition that the link has no optical amplification and no gain compensation.

2. The optical path switch chip according to claim 1, wherein, The planar optical waveguide platform is a silicon dioxide planar optical waveguide platform, or a planar optical waveguide platform with low refractive index contrast and weak light field confinement.

3. The optical path switch chip of claim 1, wherein, Multiple wavelength division multiplexing optical channels within a single physical port can carry optical signals with different line rates, different modulation formats, and different transceivers.

4. The optical path switch chip of claim 1, wherein, No optical amplifier is installed between the input and output ports of the optical switching chip, and the low insertion loss of the weakly bound waveguide enables the all-optical switching link to meet the optical sensitivity requirements of the receiver without gain compensation.

5. The optical path switch chip of claim 1, wherein, The multi-level on-chip optical switch network adopts any one or more combinations of the following topologies: Benesian switching network, Kloss switching network, tree-cascaded switching network, and folded switching network.

6. The optical path switch chip of claim 1, wherein, The optical switch units in the multi-level on-chip optical switch network are selected from any one or more combinations of thermo-optical Mach-Zehnder interferometer switches, carrier modulation Mach-Zehnder interferometer switches, phase change material switches, micro-ring switches, and on-chip microelectromechanical systems switches.

7. The optical path switch chip of claim 1, wherein, The on-chip monitoring and calibration structure is configured to generate an optical path status table, which includes at least one or more of the following: input port number, output port number, candidate intermediate optical path, operating wavelength, insertion loss, wavelength-dependent loss, crosstalk value, switch bias value, chip temperature, real-time monitoring power, and fault flag.

8. The optical path switching chip according to claim 1, characterized in that, Each physical port, through at least 8 100Gbps wavelength division multiplexing optical channels, at least 5 200Gbps wavelength division multiplexing optical channels, at least 3 400Gbps wavelength division multiplexing optical channels, or equivalent wavelength or rate combinations, forms a single-port transmission capacity of over 800Gbps, and no bit errors are observed within the preset bit error test window.

9. An optical interconnect system, characterized in that, include: The optical path switching chip as described in any one of claims 1 to 8; Multiple computing nodes, each computing node being connected to at least one physical port of the optical path switching chip; Wavelength division multiplexing transceiver module is used for multi-optical channel wavelength division multiplexing and demultiplexing transmission within a single physical port, so as to carry optical signals with different line rates and different modulation formats on the same optical fiber link, thereby adapting to different types of optical transceivers; The controller is used to configure the optical path based on the computational task traffic matrix and the optical path status of the optical path switching chip.

10. A method for controlling optical interconnect reconfiguration, characterized in that, The application to the optical path switching chip as described in any one of claims 1-8 includes the following steps: Collect the computation task graph and the list of computation nodes; Construct an inter-node flow matrix based on the computation task graph; Read the optical path status table of the optical path switching chip; wherein, the optical path status table stores the loss or crosstalk status of at least some port pairs under different wavelengths or different candidate optical paths; Generate the target logical topology based on the inter-node traffic matrix and the optical path status table; Solve for the physical optical path that satisfies the preset optical power budget and crosstalk constraints within the target logical topology; The physical optical path generation switching unit is configured accordingly; Control the optical path switching chip to perform optical path reconstruction; The physical optical path is configured to utilize the ultra-wideband, low-loss transmission characteristics of the weakly bound waveguide of the planar optical waveguide platform to support single-port transmission of more than 800 Gbps without optical amplifiers and / or gain compensation devices, and to be compatible with wavelength division multiplexing optical channels of different rates within the same physical port.

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