Control circuit for a semiconductor device and semiconductor system

Abstract

Embodiments provide a control circuit of a semiconductor device capable of reducing loss and a semiconductor system. According to an embodiment, a control circuit of a semiconductor device includes a control section configured to control the semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor element disposed between the first electrode and the second electrode, a first control electrode, and a second control electrode. At least a portion of the semiconductor element is located between the first electrode and the first control electrode. At least a portion of the semiconductor element is located between the second control electrode and the second electrode. The control section is configured to perform a second control-on operation of changing a second control potential of the second control electrode from a first potential to a second potential a plurality of times during a first control-on period in which a first control potential of the first control electrode is equal to or higher than a first threshold voltage. The first potential is lower than a second threshold voltage in the second control electrode. The second potential is equal to or higher than the second threshold voltage.

Description

[0001] This application is based on Japanese Patent Application 2025-041034 (filed on March 14, 2025), and enjoys priority benefits from this application. This application incorporates the entire contents of that application by reference. Technical Field

[0002] Embodiments of the present invention relate to control circuits for semiconductor devices and semiconductor systems. Background Technology

[0003] For example, semiconductor devices are controlled by control circuits. In semiconductor devices, it is desirable to reduce losses. Summary of the Invention

[0004] Embodiments of the present invention provide control circuits and semiconductor systems for semiconductor devices capable of reducing losses.

[0005] Technical solutions for solving technical problems According to an embodiment of the present invention, a control circuit for a semiconductor device includes a control unit configured to control the semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor component disposed between the first electrode and the second electrode, a first control electrode, and a second control electrode. At least a portion of the semiconductor component is located between the first electrode and the first control electrode. At least a portion of the semiconductor component is located between the second control electrode and the second electrode. The control unit is configured to perform a second control activation operation multiple times during a first control activation period, causing a second control potential of the second control electrode to change from a first potential to a second potential. A first condition or a second condition is satisfied. Under the first condition, during the first control activation period, the first control potential of the first control electrode is above a first threshold voltage. Under the first condition, the first potential is less than a second threshold voltage in the second control electrode, and the second potential is above the second threshold voltage. Under the second condition, during the first control activation period, the first control potential of the first control electrode is below the first threshold voltage. Under the second condition, the first potential is above the second threshold voltage in the second control electrode, and the second potential is less than the second threshold voltage.

[0006] Based on the control circuit of the semiconductor device configured as described above, a control circuit for a semiconductor device and a semiconductor system capable of reducing losses can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0008] Figure 2This is a schematic diagram illustrating the control circuit of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0012] Figure 6 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0015] Figure 9 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0016] Figure 10 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0017] Figure 11 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0018] Figure 12 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0019] Figure 13 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0020] Figure 14 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0021] Figure 15 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0022] Explanation of reference numerals in the attached figures 10M: Semiconductor component; 11~18: First~eighth semiconductor regions; 11p, 11q: Parts; 41~44: First~fourth insulating components; 51: First electrode; 52: Second electrode; 53: First control electrode; 54: Second control electrode; 70: Control unit; 110~117: Semiconductor device; 150: Control circuit; 210: Semiconductor system; D1~D5: First~fifth directions; Fpx: Second control disconnection action; Opx: Second control connection action; Pr1: Period; Ps1: Pulse; Toff1_1: First control disconnection period; Ton1_1, Ton1_2: First control connection period; V1~V3: First~third potential; Vbg: Second control potential; Vmg: First control potential; Voff1_1: First control disconnection potential; Von1: First control connection potential; Vth1, Vth2: First and second threshold voltages; ts: Reference time. Detailed Implementation

[0023] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0024] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as in reality. Even when representing the same part, there may be cases where the dimensions and ratios of each other are represented differently according to the accompanying drawings.

[0025] In this application specification and the figures, the same reference numerals are used for elements that are the same as those mentioned above with respect to the figures that have appeared, and detailed descriptions are omitted where appropriate.

[0026] (First Implementation) Figure 1 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0027] Figure 2 This is a schematic diagram illustrating the control circuit of the semiconductor device according to the first embodiment.

[0028] like Figure 2 As shown, the control circuit 150 in this embodiment includes a control unit 70. The control unit 70 is configured to control the semiconductor device 110. The semiconductor system 210 in this embodiment includes the semiconductor device 110 and the control circuit 150.

[0029] Semiconductor device 110 includes a first electrode 51, a second electrode 52, a first control electrode 53, a second control electrode 54, and a semiconductor component 10M. The semiconductor component 10M is disposed between the first electrode 51 and the second electrode 52. At least a portion of the semiconductor component 10M is located between the first electrode 51 and the first control electrode 53. At least a portion of the semiconductor component 10M is located between the second control electrode 54 and the second electrode 52.

[0030] Semiconductor component 10M includes, for example, an upper surface and a lower surface. For example, a first electrode 51 is disposed on the lower surface. A second electrode 52 is disposed on the upper surface. A first control electrode 53 is disposed on the upper surface side, for example. A second control electrode 54 is disposed on the lower surface side.

[0031] The semiconductor component 10M includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, a third semiconductor region 13 of a first conductivity type, a fourth semiconductor region 14 of a second conductivity type, and a fifth semiconductor region 15 of a first conductivity type.

[0032] Semiconductor device 110 can be n-channel or p-channel. The control circuit 150 of the embodiment can satisfy either a first condition or a second condition. Under the first condition, semiconductor device 110 is n-channel. Under the second condition, semiconductor device 110 is p-channel. Under the first condition, the first conductivity type is n-type and the second conductivity type is p-type. Under the second condition, the first conductivity type is p-type and the second conductivity type is n-type.

[0033] The second semiconductor region 12 is disposed between the first semiconductor region 11 and the second electrode 52. The second semiconductor region 12 may be in contact with the first semiconductor region 11. The third semiconductor region 13 is disposed between at least a portion of the second semiconductor region 12 and the second electrode 52. The third semiconductor region 13 may be connected to both the second semiconductor region 12 and the second electrode 52. The third semiconductor region 13 is electrically connected to the second electrode 52. The first semiconductor region 11 is, for example, a drift layer.

[0034] A fourth semiconductor region 14 is disposed between the first electrode 51 and the first semiconductor region 11. The first semiconductor region 11 is located between the second semiconductor region 12 and the fourth semiconductor region 14. A fifth semiconductor region 15 is disposed between at least a portion of the first electrode 51 and the fourth semiconductor region 14. The fifth semiconductor region 15 is not connected to the first semiconductor region 11. The fifth semiconductor region 15 is electrically connected to the first electrode 51.

[0035] Semiconductor device 110 includes a first insulating component 41 and a second insulating component 42. At least a portion of the first insulating component 41 is disposed between the first control electrode 53 and the first semiconductor region 11, between the first control electrode 53 and the second semiconductor region 12, and between the first control electrode 53 and the third semiconductor region 13. The first insulating component 41 is connected to the first control electrode 53, the first semiconductor region 11, the second semiconductor region 12, and the third semiconductor region 13. The first insulating component 41 electrically insulates the first control electrode 53 and the semiconductor device 110 from each other.

[0036] At least a portion of the second insulating member 42 is disposed between the second control electrode 54 and the first semiconductor region 11, between the second control electrode 54 and the fourth semiconductor region 14, and between the second control electrode 54 and the fifth semiconductor region 15. The second insulating member 42 electrically insulates the second control electrode 54 and the semiconductor member 10M from each other.

[0037] The semiconductor device 110 is, for example, an IGBT (Insulated Gate Bipolar Transistor) containing two control electrodes. The control unit 70 of the control circuit 150 controls the potential of the first control electrode 53 and the potential of the second control electrode 54.

[0038] The semiconductor device 110 performs IGBT operation. For example, when the first control electrode 53 functions as the main gate electrode for switching the IGBT, the first electrode 51 functions as the collector electrode, the second electrode 52 functions as the emitter electrode, and the second control electrode 54 functions as the sub-gate electrode for controlling the current path of the IGBT.

[0039] Figure 1 The potential of the first control electrode 53 (first control potential Vmg) and the potential of the second control electrode 54 (second control potential Vbg) are illustrated. Figure 1 The horizontal axis represents time tm.

[0040] The control unit 70 switches the first control potential Vmg of the first control electrode 53 between the first control off potential Voff1 and the first control on potential Von1.

[0041] Figure 1 The first condition (n-channel type) is illustrated. Under the first condition, the first control off potential Voff1 is less than the first threshold voltage Vth1. Under the first condition, the first control on potential Von1 is greater than or equal to the first threshold voltage Vth1. The period during which the first control potential Vmg is equal to the first control on potential Von1 corresponds to the first control on period Ton1_1.

[0042] In this implementation, a first control disconnection period Toff1_1 can be set between multiple first control connection periods (the first control connection period Ton1_1, the second control connection period Ton1_2, etc.). Alternatively, the first control connection period Ton1_1 and the first control disconnection period Toff1_1 can be performed repeatedly. The length of the first control connection period Ton1_1 can also be different from the length of the second control connection period Ton1_2.

[0043] like Figure 1 As shown, the control unit 70 switches the second control potential Vbg of the second control electrode 54 between the first potential V1 and the second potential V2. Under the first condition (n-channel type), the first potential V1 is less than the second threshold voltage Vth2 in the second control electrode 54. The second potential V2 is greater than or equal to the second threshold voltage Vth2. The control unit 70 is configured to perform a second control switching operation Opx multiple times during the first control switching period Ton1 when the first control potential Vmg of the first control electrode 53 is greater than or equal to the first threshold voltage Vth1. During the second control switching operation Opx, the control unit 70 changes the second control potential Vbg of the second control electrode 54 from the first potential V1 to the second potential V2.

[0044] On the other hand, under the second condition (p-channel type), the first control off potential Voff1 exceeds the first threshold voltage Vth1, and the first control on potential Von1 is below the first threshold voltage Vth1. The period during which the first control potential Vmg is the first control on potential Von1 corresponds to the first control on period Ton1_1. Under the second condition, the first potential V1 is above the second threshold voltage Vth2 in the second control electrode 54. The second potential V2 is less than the second threshold voltage Vth2. The control unit 70 is configured to perform the second control on operation Opx multiple times during the first control on period Ton1_1 when the first control potential Vmg of the first control electrode 53 is below the first threshold voltage Vth1. During the second control on operation Opx, the control unit 70 changes the second control potential Vbg of the second control electrode 54 from the first potential V1 to the second potential V2.

[0045] The following is about Figure 1 The first condition illustrated will be further explained. The following explanation can be applied to the second condition by reversing the magnitude relationship of the potentials.

[0046] For example, in the second control turn-on operation Opx, the control unit 70 applies a pulse voltage to the second control electrode 54. During the first control turn-on period Ton1_1, multiple pulse voltages are applied. The rise (turn-on) of each of the multiple pulses exists during the first control turn-on period Ton1_1.

[0047] By using such a pulsed voltage, for example, immediately after the second control gate is turned on, conduction based on a high-injection state of electrons, without passing through the pn junction, can be achieved. For example, the turn-on voltage during the second control gate's on period is lower than the turn-on voltage during the second control gate's off period. Thus, for example, when the second control gate is repeatedly turned on and off, the time-averaged conduction loss can be reduced. According to an embodiment, a control circuit for a semiconductor device capable of reducing losses can be provided.

[0048] For example, when the first control electrode 53 is in the ON state and the second control electrode 54 is in the OFF state, a large number of charge carriers accumulate in the drift layer, generating bipolar conduction via the pn junction.

[0049] On the other hand, for example, when the first control electrode 53 is in the ON state and the second control electrode 54 switches from the OFF state to the ON state, the number of carriers in the drift layer decreases. Furthermore, conduction occurs without passing through the pn junction's electron bulk.

[0050] During the period when the first control electrode 53 is in the ON state, the second control electrode 54 is repeatedly switched on and off, and the above state is switched multiple times. This stably generates conduction switching without passing through the pn junction. The average turn-on voltage time is reduced. Conduction losses are reduced.

[0051] For example, it is assumed that the following state occurs when the first control electrode 53 is turned on. For example, the IGBT is turned on by turning on the first control electrode 53. During the period from turn-on to the first moment, bipolar conduction is generated by the accumulation of charge carriers at a high density. The turn-on voltage includes a built-in voltage through conduction via the pn junction. At the first moment, the second control electrode 54 is turned on, forming an n-channel on the side of the first electrode 51. Electrons can move from the second electrode 52 to the first electrode 51 only through the n-type semiconductor. In such conduction without passing through the pn junction, the turn-on voltage does not include a built-in voltage. During the period from the first moment to the second moment, the transition from bipolar conduction to electron conduction occurs, and the turn-on voltage gradually decreases. During the period from the second moment to the third moment, the charge carriers in the drift layer (from the first electrode 51 side) gradually decrease, but the high injection state continues. The turn-on voltage of the second control electrode 54 decreases due to electron conduction reduced by the built-in voltage. In the period later than the third moment, a portion of the drift layer becomes low-injection, and the drift layer becomes highly resistive depending on the width of the low-injection region. The time from connection to the first moment is, for example, 1000 ns. The time from connection to the second moment is, for example, 1015 ns. The time from connection to the third moment is, for example, 1120 ns.

[0052] In the above example, for instance, during the period from the second time point to the third time point, the second control electrode 54 is disconnected, returning to bipolar conduction. This suppresses the reduction of charge carriers and allows charge carriers to be stored in the drift layer at a high density again. Consequently, the high resistivity of the drift layer after the third time point can be suppressed.

[0053] like Figure 1 As shown, the configuration is designed to perform multiple second control activation actions Opx. In the second control activation action Opx, the control unit 70 causes the second control potential Vbg of the second control electrode 54 to change from the first potential V1 to the second potential V2.

[0054] like Figure 1 As shown, after each of the multiple second control on-action Opx actions, a second control off-action Fpx is performed. In the second control off-action Fpx, the control unit 70 changes the second control potential Vbg from the second potential V2 to the first potential V1.

[0055] The control unit 70 performs the aforementioned second control activation action Opx N times. "N" is an integer of 2 or more. The second control activation action Opx from the first to the Nth time is performed during the first control activation period (Ton1). The second control deactivation action Fpx from the first to the (N-1)th time is performed during the first control activation period (Ton1). The Nth second control deactivation action Fpx may also be performed after the first control activation period (Ton1).

[0056] like Figure 1 As shown, the N second control connection actions Opx include the first second control connection action O_1, the (N-1)th second control connection action O_(N-1), and the Nth second control connection action O_N. The N second control disconnection actions Fpx include the first second control disconnection action F_1, the (N-1)th second control disconnection action F_(N-1), and the Nth second control disconnection action F_N.

[0057] The second control disconnection action F_(N-1) of the (N-1)th time is performed between the second control connection action O_(N-1) of the (N-1)th time and the second control connection action O_N of the Nth time.

[0058] Thus, after the (N-1)th second control activation action O_(N-1) and before the Nth second control activation action O_N, the control unit 70 is configured to perform the (N-1)th second control deactivation action F_(N-1) that changes the second control potential Vbg from the second potential V2 to the first potential V1. In the (N-1)th second control deactivation action F_(N-1), the control unit 70 changes the second control potential Vbg from the second potential V2 to the first potential V1.

[0059] The time te_(N-1) between the reference time ts when the first control potential Vmg exceeds the first threshold voltage Vth1 and the time of the (N-1)th second control disconnection action F_(N-1) can be less than 0.99 times the length of Ton1_1 during the first control turn-on period.

[0060] The time ts_1 between the reference time ts when the first control potential Vmg exceeds the first threshold voltage Vth1 and the start time of the first second control turn-on action O_1 can be more than 0.01 times the length of Ton1_1 during the first control turn-on period.

[0061] The time Ton2_(N-1) between the (N-1)th second control activation action O_(N-1) and the (N-1)th second control deactivation action F_(N-1) can be shorter than the time Ton2_N between the Nth second control activation action O_N and the Nth second control deactivation action F_N. The time of the Nth second control deactivation action F_N can also be after the end of the first control activation period (Ton1).

[0062] When the Nth second control disconnection action F_N occurs later than the first control connection period Ton1, the time between the Nth second control disconnection action F_N and the end of the first control connection period Ton1 can, for example, exceed 0 μs and be less than 200 μs. When the Nth second control disconnection action F_N occurs before the first control connection period Ton1, the time between the Nth second control disconnection action F_N and the start of the first control connection period Ton1 can exceed 0 μs and be less than 100 μs.

[0063] In this implementation, the first, second, and Nth "first control on-times" are labeled "Ton1_1", "Ton1_2", and "Ton1_N", respectively. The lengths of these first control on-times can be fixed or different from each other. The first, second, and Nth "first control off-times" are labeled "Toff1_1", "Toff1_2", and "Toff1_N", respectively. The durations of these "first control off-times" can be fixed or different from each other. The second control electrode 54 can be in an off state during the "first control off-time", for example, for more than 80% of the length of the "first control off-time".

[0064] As described above, under the second condition, the first conductivity type is p-type and the second conductivity type is n-type. In this case, the magnitude relationship between the first control on-state potential Von1 and the first control off-state potential Voff1 is the opposite of that in the first condition. Under the second condition, the magnitude relationship between the first potential V1 and the second potential V2 is the opposite of that in the first condition.

[0065] Figure 3 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0066] like Figure 3 As shown, the control unit 70 is configured to perform the nth second control on-action Opx and the nth second control off-action Fpx. "n" is an integer of 1 or more and (N-1) or less.

[0067] After the nth second control activation action O_n and before the (n+1)th second control activation action O_(n+1), the nth second control deactivation action F_n is performed. In the nth second control deactivation action F_n, the control unit 70 changes the second control potential Vbg from the second potential V2 to the first potential V1.

[0068] The connection time Ton2_n between the moment of the second control turn-on action O_n and the moment of the second control disconnect action F_n can be greater than 5ns and less than 2μs.

[0069] “n” can be an integer greater than 1 and less than (N-2). The turn-on time Ton2_n between the time of the nth second control turn-on action O_n and the time of the nth second control turn-off action F_n corresponds to the turn-on time of the nth pulse. The turn-off time Toff2_n between the time of the nth second control turn-off action F_n and the time of the (n+1)th second control turn-on action O_(n+1) corresponds to the turn-off time after the nth pulse. For example, the turn-on time Ton2_n can be shorter than the turn-off time Toff2_n.

[0070] As already explained, the turn-on time Ton2_n can be greater than 5 ns and less than 2 μs. The turn-off time Toff2_n can, for example, be greater than 5 ns and less than 3 μs. The turn-off time Toff2_n is, for example, shorter than the time between the moment of the (N-1)th second control turn-off action F_(N-1) and the moment of the Nth second control turn-on action O_N.

[0071] For example, the time Ton2_N between the Nth second control activation action O_N and the Nth second control deactivation action F_N can be longer than the activation time Ton2_n between the nth second control activation action O_n and the nth second control deactivation action F_n. The time Ton2_N can be, for example, more than 5 μs and less than 300 μs.

[0072] Figure 4 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0073] like Figure 4 As shown, the control unit 70 is configured to perform a second control deactivation operation F_(n-1) after the (n-1)th second control activation operation O_(n-1) and before the nth second control activation operation O_n. "n" is an integer greater than or equal to 1 and less than (N-1). In the (n-1)th second control deactivation operation F_(n-1), the second control potential Vbg is changed from the second potential V2 to the first potential V1. The second control activation operation O_(n-1) from the first to the (n-1)th includes applying a pulse Ps1 to the second control electrode 54. In the second control activation operation O_(n-1) from the first to the (n-1)th, the period Pr1 of the pulse Ps1 can be 5 μs or less.

[0074] In the second control activation action O_(n-1) (and the second control deactivation action F_(n-1)) from the first to the (n-1)th time, the period Pr1 of pulse Ps1 can be constant. Pulse Ps1 is applied continuously.

[0075] Figure 5 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0076] exist Figure 5 In this configuration, the control unit 70 is also configured to perform a second control deactivation operation F_(n-1) after the (n-1)th second control activation operation O_(n-1) and before the nth second control activation operation O_n. The second control activation operation O_(n-1) from the first to the (n-1)th includes applying a pulse Ps1 to the second control electrode 54. In the second control activation operation O_(n-1) from the first to the (n-1)th, the duty cycle of the pulse Ps1 can be 0.5 or less. For example, Figure 3 The example connection time Ton2_n can be less than or equal to the disconnection time Toff2_n.

[0077] For example, in the first to the (n-1)th second control turn-on action O_(n-1) (and the second control turn-off action F_(n-1), the period Pr1 of pulse Ps1 can also be constant. Pulse Ps1 is applied continuously.

[0078] like Figure 5 As shown, the moment of the Nth second control activation action O_N can overlap with the end moment of the first control activation period Ton1.

[0079] Figure 6 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0080] like Figure 6 As shown, the control unit 70 performs N second control activation actions Opx within the first control activation period Ton1. For example, the Nth second control activation action O_N is performed starting from the first second control activation action O_1. The Nth second control deactivation action F_N can be performed before the first control activation period Ton1. Alternatively, other second control activation actions O_X can be performed after the first control activation period Ton1 ends.

[0081] Figure 7 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0082] like Figure 7 As shown, the control unit 70 can set the second control potential Vbg to multiple different values ​​above the second threshold voltage Vth2 in multiple second control activation actions Opx. For example, the second potential V2 in one of the multiple implementations of the second control activation action Opx is different from the second potential V2 in another of the multiple implementations of the second control activation action Opx. In this example, in the first to the (N-1)th second control activation action O_(N-1), the second control potential Vbg is the second potential V2. In the Nth second control activation action O_N, the second control potential Vbg is a potential different from the second potential V2 (the third potential V3). The third potential V3 is above the second threshold voltage Vth2.

[0083] The first potential V1 in one of the multiple implementations of the second control activation action Opx may also be different from the first potential V1 in another of the multiple implementations of the second control activation action Opx.

[0084] Figure 8 This is a schematic diagram illustrating the operation of the control circuit of the semiconductor device according to the first embodiment.

[0085] like Figure 8As shown, in at least a portion of the multiple second control activation actions Opx, the second control potential Vbg can be controlled by a pulse Ps1 with a value of 3 or higher.

[0086] For example, the control unit 70 performs N second control activation actions Opx. "N" is an integer greater than or equal to 2. In this example, in the first to the (N-1)th second control activation actions Opx (N-1), the second control potential Vbg is controlled by a pulse Ps1 with a value of 2.

[0087] The control unit 70 is configured to perform a second control disconnection operation F_N after the Nth second control turn-on operation O_N. In the Nth second control disconnection operation F_N, the second control potential Vbg changes from a second potential V2 to a first potential V1. In at least either the Nth second control turn-on operation O_N or the Nth second control disconnection operation F_N, the second control potential Vbg is controlled by a pulse Ps1 with a value of 3 or higher. In this example, the Nth second control disconnection operation F_N is implemented using a potential with a value of 3.

[0088] For example, the potential of the pulse Ps1 with a value of 3 or higher changes from the first potential V1 to the second potential V2, and then changes from the second potential V2 to the third potential V3. The potential of the pulse Ps1 with a value of 3 or higher becomes the first potential V1 after changing to the third potential V3. The third potential V3 is between the first potential V1 and the second potential V2. The third potential V3 is equal to or greater than the second threshold voltage Vth2.

[0089] In this example, before the end of the first control on-time (Ton1), the second control potential Vbg is the second potential V2. After the end of the first control on-time (Ton1), the second control potential Vbg becomes the third potential V3.

[0090] In this embodiment, the first control potential Vmg can be the potential of the first control electrode 53, which is based on the potential of the second electrode 52. The second control potential Vbg can be the potential of the second control electrode 54, which is based on the potential of the first electrode 51.

[0091] like Figure 2 As shown in the example, the semiconductor device 110 may also include a third insulating component 43. The third insulating component 43 is located between the first control electrode 53 and the second electrode 52. The third insulating component 43 electrically insulates the first control electrode 53 and the second electrode 52 from each other.

[0092] like Figure 2As shown, the first semiconductor region 11 may include a sixth semiconductor region 16 of a first conductivity type as a partial region. At least a portion of the sixth semiconductor region 16 is located between the second control electrode 54 and other portions of the first semiconductor region 11. At least a portion of the second insulating member 42 is located between the second control electrode 54 and the sixth semiconductor region 16. The second insulating member 42 may be connected to the sixth semiconductor region 16.

[0093] For example, the concentration of the sixth impurity of the first conductivity type in the sixth semiconductor region 16 can be higher than the concentration of the first impurity of the first conductivity type in other parts of the first semiconductor region 11. The concentration of the sixth impurity can also be higher than the concentration of the first impurity.

[0094] like Figure 2 As shown, at least a portion of the fourth semiconductor region 14 may be disposed between the fifth semiconductor region 15 and the sixth semiconductor region 16. The aforementioned at least portion of the fourth semiconductor region 14 may contact the second insulating member 42. A portion of the sixth semiconductor region 16 may also be disposed between the fourth semiconductor region 14 and the first semiconductor region 11.

[0095] like Figure 2 As shown, the first semiconductor region 11 may include a seventh semiconductor region 17 of a first conductivity type as a partial region. The seventh semiconductor region 17 is, for example, located between the fourth semiconductor region 14 and other portions of the first semiconductor region 11. The seventh semiconductor region 17 is adjacent to the sixth semiconductor region 16. The concentration of the seventh impurity of the first conductivity type in the seventh semiconductor region 17 may be higher than the concentration of the first impurity of the first conductivity type in other portions of the first semiconductor region 11.

[0096] In this example, the direction from the second control electrode 54 to the fourth semiconductor region 14 follows a first direction D1. The direction from the second control electrode 54 to the fifth semiconductor region 15 follows the first direction D1. The direction from the second control electrode 54 to the sixth semiconductor region 16 follows the first direction D1. The direction from the fourth semiconductor region 14 to the fifth semiconductor region 15 follows a second direction D2. The second direction D2 intersects the first direction D1. At least a portion of the second control electrode 54 may extend along a third direction D3. The third direction D3 intersects a plane that includes both the first direction D1 and the second direction D2. The configuration including the second control electrode 54 is, for example, equivalent to a planar transistor.

[0097] In this example, the direction from the first control electrode 53 to the second semiconductor region 12 follows a fourth direction D4. The fourth direction D4 intersects the first direction D1. The direction from the first control electrode 53 to the third semiconductor region 13 also follows the fourth direction D4. At least a portion of the first control electrode 53 may extend along a fifth direction D5. The fifth direction D5 intersects a plane that includes both the first direction D1 and the fourth direction D4.

[0098] A portion 11p of a first semiconductor region 11 exists between the first electrode 51 and the first control electrode 53. A direction from the first control electrode 53 to another portion 11q of the first semiconductor region 11 intersects a first direction D1. This direction is, for example, a fourth direction D4. The configuration including the first control electrode 53 is, for example, equivalent to a trench transistor.

[0099] Let the first direction D1 be the Z-axis direction. Let the direction perpendicular to the Z-axis direction be the X-axis direction. Let the direction perpendicular to both the Z-axis and X-axis directions be the Y-axis direction. The second direction D2 can be, for example, the X-axis direction. The third direction D3 can be, for example, the Y-axis direction.

[0100] The fourth direction, D4, can run along the second direction, D2, or intersect with the second direction, D2. The fifth direction, D5, can run along the second direction, D2, or intersect with the second direction, D2.

[0101] like Figure 1 As shown, the semiconductor component 10M may further include an eighth semiconductor region 18 of a second conductivity type. The eighth semiconductor region 18 is disposed between the first semiconductor region 11 and the third insulating component 43. For example, charge carriers are accumulated at a high density. For example, conduction losses are reduced.

[0102] Hereinafter, several examples related to the semiconductor device of the control circuit 150 in the application implementation will be described.

[0103] Figures 9-15 This is a schematic cross-sectional view illustrating a semiconductor device using the control circuit of the first embodiment.

[0104] like Figure 9 As shown, in semiconductor device 111, the directions from the second control electrode 54 to the fourth semiconductor region 14 and from the second control electrode 54 to the fifth semiconductor region 15 intersect with the first direction D1. In semiconductor device 111, the configuration including the second control electrode 54 is, for example, equivalent to a trench-type transistor. In semiconductor device 111, the configuration including the first control electrode 53 is, for example, equivalent to a trench-type transistor.

[0105] like Figure 9As shown, the semiconductor device 111 may include a fourth insulating member 44. The fourth insulating member 44 is disposed between the first electrode 51 and the second control electrode 54. The fourth insulating member 44 electrically insulates the first electrode 51 and the second control electrode 54 from each other.

[0106] like Figure 10 As shown, in the semiconductor device 112, the direction from the second semiconductor region 12 to the first control electrode 53 and the direction from the third semiconductor region 13 to the first control electrode 53 are along a first direction D1. In the semiconductor device 112, the configuration including the first control electrode 53 is, for example, equivalent to a planar transistor. The configuration including the second control electrode 54 is, for example, equivalent to a planar transistor.

[0107] like Figure 11 As shown, in the semiconductor device 113, the configuration including the first control electrode 53 is, for example, equivalent to a planar transistor. The configuration including the second control electrode 54 is, for example, equivalent to a trench transistor.

[0108] like Figure 12 As shown, in the semiconductor device 114, the configuration including the first control electrode 53 is, for example, equivalent to a trench transistor. The configuration including the second control electrode 54 is, for example, equivalent to a planar transistor.

[0109] like Figure 13 As shown, in the semiconductor device 115, the structure including the first control electrode 53 is, for example, equivalent to a trench-type transistor. The structure including the second control electrode 54 is, for example, equivalent to a trench-type transistor.

[0110] like Figure 14 As shown, in the semiconductor device 116, the configuration including the first control electrode 53 is, for example, equivalent to a planar transistor. The configuration including the second control electrode 54 is, for example, equivalent to a planar transistor.

[0111] like Figure 15 As shown, in the semiconductor device 117, the configuration including the first control electrode 53 is, for example, equivalent to a planar transistor. The configuration including the second control electrode 54 is, for example, equivalent to a trench transistor.

[0112] (Second Implementation) The second embodiment relates to a semiconductor system 210 (see reference 210) Figure 2 The semiconductor system 210 of the embodiment includes a semiconductor device 110 and a control circuit 150. In the embodiment, a semiconductor system capable of reducing losses can be provided.

[0113] In this implementation, information related to the shape of the semiconductor region is obtained, for example, through electron microscope images. Information related to composition and elemental concentration is obtained, for example, through EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry).

[0114] The implementation methods may include the following technical solutions.

[0115] (Technical Solution 1) A control circuit for a semiconductor device includes a control unit configured to control the semiconductor device. The semiconductor device includes: First electrode; Second electrode; A semiconductor component is disposed between the first electrode and the second electrode; First control electrode; and Second control electrode, At least a portion of the semiconductor component is located between the first electrode and the first control electrode. At least a portion of the semiconductor component is located between the second control electrode and the second electrode. The control unit is configured to perform multiple second control switching operations during the first control switching period, causing the second control potential of the second control electrode to change from the first potential to the second potential. If either the first or second condition is met, Under the first condition, during the first control activation period, the first control potential of the first control electrode is above the first threshold voltage. Under the first condition, the first potential is less than the second threshold voltage in the second control electrode, and the second potential is greater than or equal to the second threshold voltage. Under the second condition, during the first control activation period, the first control potential of the first control electrode is below the first threshold voltage. Under the second condition, the first potential is above the second threshold voltage in the second control electrode, and the second potential is below the second threshold voltage.

[0116] (Technical Solution 2) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit is configured to perform the second control activation action N times. N is an integer greater than or equal to 2. After the (N-1)th second control activation action and before the Nth second control activation action, the control unit performs the (N-1)th second control deactivation action, causing the second control potential to change from the second potential to the first potential. The time between the reference moment when the first control potential exceeds the first threshold voltage and the moment of the (N-1)th second control disconnection action is less than 0.99 times the length of the first control on period.

[0117] (Technical Solution 3) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The time between the reference moment when the first control potential exceeds the first threshold voltage and the start moment of the first second control activation action is more than 0.01 times the length of the first control activation period.

[0118] (Technical Solution 4) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the nth second control disconnection operation, which changes the second control potential from the second potential to the first potential, after the nth second control activation operation and before the (n+1)th second control activation operation. The n is an integer greater than 1 and less than (N-1). The time between the nth second control activation action and the nth second control deactivation action is less than 2 μs.

[0119] (Technical Solution 5) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the nth second control disconnection operation, which changes the second control potential from the second potential to the first potential, after the nth second control activation operation and before the (n+1)th second control activation operation. The n is an integer greater than or equal to 1 and less than or equal to (N-2). The connection time between the nth second control connection action and the nth second control disconnection action is shorter than the disconnection time between the nth second control disconnection action and the (n+1)th second control connection action.

[0120] (Technical Solution 6) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the (n-1)th second control deactivation operation, which changes the second control potential from the second potential to the first potential, after the (n-1)th second control activation operation and before the nth second control activation operation. The n is an integer greater than 1 and less than (N-1). The first to (n-1)th second control activation actions involve applying a pulse to the second control electrode. In the first to (N-1)th second control activation actions, the period of the pulse is less than 5 μs.

[0121] (Technical Solution 7) According to the control circuit of the semiconductor device described in technical solution 6, wherein... In the first to the (n-1)th second control activation actions, the period of the pulse is constant. The pulses are applied continuously.

[0122] (Technical Solution 8) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the (n-1)th second control deactivation operation, which changes the second control potential from the second potential to the first potential, after the (n-1)th second control activation operation and before the nth second control activation operation. The n is an integer greater than 1 and less than (N-1). The first to (n-1)th second control activation actions involve applying a pulse to the second control electrode. In the first to (n-1)th second control activation actions, the duty cycle of the pulse is less than 0.5.

[0123] (Technical Solution 9) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the nth second control disconnection operation, which changes the second control potential from the second potential to the first potential, after the nth second control activation operation and before the (n+1)th second control activation operation. The n is an integer greater than 1 and less than (N-1). The control unit is configured to, after the Nth second control activation action, perform the Nth second control deactivation action to change the second control potential from the second potential to the first potential. The time between the Nth second control activation action and the Nth second control deactivation action is longer than the time between the nth second control activation action and the nth second control deactivation action.

[0124] (Technical Solution 10) The control circuit of the semiconductor device according to any one of technical solutions 1-9, wherein, The second potential in one of the multiple implementations of the second control activation action is different from the second potential in another of the multiple implementations of the second control activation action.

[0125] (Technical Solution 11) The control circuit of the semiconductor device according to any one of technical solutions 1-9, wherein, The first potential in one of the multiple implementations of the second control activation action is different from the first potential in another of the multiple implementations of the second control activation action.

[0126] (Technical Solution 12) According to the control circuit of the semiconductor device described in technical solution 1, wherein, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. In the first to (N-1)th second control activation actions, the second control potential is controlled by a pulse with a value of 2. The control unit is configured to perform a second control disconnection action after the Nth second control activation action. In the Nth second control disconnection action, the second control potential changes from the second potential to the first potential. In at least one of the Nth second control on-action and the Nth second control off-action, the second control potential is controlled by a pulse with a value of 3 or higher.

[0127] (Technical Solution 13) According to the control circuit of the semiconductor device described in technical solution 12, wherein, The potential of the pulse with a value of 3 or higher changes from the first potential to the second potential, then changes from the second potential to the third potential, and finally becomes the first potential after changing to the third potential. The third potential is located between the first potential and the second potential. Before the end of the first control activation period, the second control potential is the second potential. After the first control activation period ends, the second control potential becomes the third potential.

[0128] (Technical Solution 14) The control circuit of the semiconductor device according to any one of technical solutions 1-12, wherein, After the first control is turned on, the control unit changes the second control potential to the first potential.

[0129] (Technical Solution 15) The control circuit of the semiconductor device according to any one of technical solutions 1-14, wherein, The semiconductor device further includes a first insulating component and a second insulating component. The semiconductor component includes: First semiconductor region of first conductivity type; A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the second electrode; The third semiconductor region of the first conductivity type is disposed between at least a portion of the second semiconductor region and the second electrode; The fourth semiconductor region of the second conductivity type is electrically connected to the first electrode and is disposed between the first electrode and the first semiconductor region; and The fifth semiconductor region of the first conductivity type is electrically connected to the first electrode. At least a portion of the first insulating component is disposed between the first control electrode and the second semiconductor region. The fifth semiconductor region is disposed between at least a portion of the first electrode and the fourth semiconductor region. At least a portion of the second insulating component is disposed between the second control electrode and the first semiconductor region, and between the second control electrode and the fourth semiconductor region.

[0130] (Technical Solution 16) According to the control circuit of the semiconductor device described in technical solution 15, wherein, The semiconductor component further includes a sixth semiconductor region of the first conductivity type. At least a portion of the sixth semiconductor region is located between the second control electrode and the first semiconductor region. The at least portion of the second insulating component is located between the second control electrode and the sixth semiconductor region.

[0131] (Technical Solution 17) According to the control circuit of the semiconductor device described in technical solution 16, wherein, At least a portion of the fourth semiconductor region is located between the fifth semiconductor region and the sixth semiconductor region.

[0132] (Technical Solution 18) According to the control circuit of the semiconductor device described in technical solution 17, wherein, The concentration of the sixth impurity of the first conductivity type in the sixth semiconductor region is greater than or equal to the concentration of the first impurity of the first conductivity type in the first semiconductor region.

[0133] (Technical Solution 19) According to the control circuit of the semiconductor device described in technical solution 18, wherein, A portion of the sixth semiconductor region is located between the fourth semiconductor region and the first semiconductor region.

[0134] (Technical Solution 20) A semiconductor system comprising a control circuit and the semiconductor device as described in any one of technical solutions 1-19.

[0135] (Technical Solution 21) A control circuit for a semiconductor device includes a control unit configured to control the semiconductor device. The semiconductor device includes: First electrode; Second electrode; A semiconductor component is disposed between the first electrode and the second electrode; First control electrode; and Second control electrode, At least a portion of the semiconductor component is located between the first electrode and the first control electrode. At least a portion of the semiconductor component is located between the second control electrode and the second electrode. The control unit is configured to perform multiple operations during a first control turn-on period when the first control potential of the first control electrode is below a first threshold voltage, causing the second control potential of the second control electrode to change from the first potential to the second potential and from the second potential back to the first potential. If either the first potential or the second potential is higher than the second threshold voltage of the second control electrode, then... The other of the first potential and the second potential is lower than the second threshold voltage of the second control electrode.

[0136] (Technical Solution 22) The control circuit of the semiconductor device according to any one of technical solutions 1 to 14, wherein, The semiconductor device is an IGBT.

[0137] According to the embodiments, a control circuit and a semiconductor system capable of reducing losses in a semiconductor device can be provided.

[0138] In this application specification, "perpendicular" and "parallel" are not only strictly perpendicular and strictly parallel, but also include deviations in manufacturing processes, as long as they are substantially perpendicular and substantially parallel.

[0139] The embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, any specific configuration of the elements included in a semiconductor device, such as electrodes, semiconductor components, semiconductor regions, and insulating components, is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known scope to similarly implement the present invention and obtain the same effects.

[0140] Any solution that combines any two or more elements of each example within the technically possible range is also included within the scope of this invention as long as it contains the spirit of this invention.

[0141] As an embodiment of the present invention, any control circuit and semiconductor system of a semiconductor device that can be appropriately designed and modified by those skilled in the art based on the above-described control circuit and semiconductor system of the semiconductor device are also within the scope of the present invention as long as they contain the spirit of the present invention.

[0142] Within the scope of the present invention, those skilled in the art will be able to conceive of various modifications and alterations, which also fall within the scope of the present invention.

[0143] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A control circuit for a semiconductor device, comprising a control unit configured to control the semiconductor device. The semiconductor device includes: First electrode; Second electrode; A semiconductor component is disposed between the first electrode and the second electrode; First control electrode; as well as Second control electrode, At least a portion of the semiconductor component is located between the first electrode and the first control electrode. At least a portion of the semiconductor component is located between the second control electrode and the second electrode. The control unit is configured to perform multiple second control switching operations during the first control switching period, causing the second control potential of the second control electrode to change from the first potential to the second potential. The control circuit satisfies either the first condition or the second condition. Under the first condition, during the first control activation period, the first control potential of the first control electrode is above the first threshold voltage. Under the first condition, the first potential is less than the second threshold voltage in the second control electrode, and the second potential is greater than or equal to the second threshold voltage. Under the second condition, during the first control activation period, the first control potential of the first control electrode is below the first threshold voltage. Under the second condition, the first potential is above the second threshold voltage in the second control electrode, and the second potential is below the second threshold voltage.

2. The control circuit of the semiconductor device according to claim 1, characterized in that, The control unit is configured to perform the second control activation action N times. N is an integer greater than or equal to 2. After the (N-1)th second control activation action and before the Nth second control activation action, the control unit performs the (N-1)th second control deactivation action, causing the second control potential to change from the second potential to the first potential. The time between the reference moment when the first control potential exceeds the first threshold voltage and the moment of the (N-1)th second control disconnection action is less than 0.99 times the length of the first control on period.

3. The control circuit of the semiconductor device according to claim 1, characterized in that, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The time between the reference moment when the first control potential exceeds the first threshold voltage and the start moment of the first second control activation action is more than 0.01 times the length of the first control activation period.

4. The control circuit of the semiconductor device according to claim 1, characterized in that, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the nth second control disconnection operation, which changes the second control potential from the second potential to the first potential, after the nth second control activation operation and before the (n+1)th second control activation operation. The n is an integer greater than or equal to 1 and less than or equal to N-2. The connection time between the nth second control connection action and the nth second control disconnection action is shorter than the disconnection time between the nth second control disconnection action and the (n+1)th second control connection action.

5. The control circuit of the semiconductor device according to claim 1, characterized in that, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. The control unit is configured to perform the nth second control disconnection operation, which changes the second control potential from the second potential to the first potential, after the nth second control activation operation and before the (n+1)th second control activation operation. The n is an integer greater than or equal to 1 and less than or equal to N-1. The control unit is configured to, after the Nth second control activation action, perform the Nth second control deactivation action to change the second control potential from the second potential to the first potential. The time between the Nth second control activation action and the Nth second control deactivation action is longer than the time between the nth second control activation action and the nth second control deactivation action.

6. The control circuit of the semiconductor device according to any one of claims 1-5, characterized in that, The second potential in one of the multiple implementations of the second control activation action is different from the second potential in another of the multiple implementations of the second control activation action.

7. The control circuit of the semiconductor device according to claim 1, characterized in that, The control unit performs the second control activation action N times. N is an integer greater than or equal to 2. In the first to the (N-1)th second control activation actions, the second control potential is controlled by a pulse with a value of 2. The control unit is configured to perform a second control disconnection action after the Nth second control activation action. In the Nth second control disconnection action, the second control potential changes from the second potential to the first potential. In at least one of the Nth second control on-action and the Nth second control off-action, the second control potential is controlled by a pulse with a value of 3 or higher.

8. The control circuit of the semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first insulating component and a second insulating component. The semiconductor component includes: First semiconductor region of first conductivity type; A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the second electrode; The third semiconductor region of the first conductivity type is disposed between at least a portion of the second semiconductor region and the second electrode; The fourth semiconductor region of the second conductivity type is electrically connected to the first electrode and is disposed between the first electrode and the first semiconductor region; and The fifth semiconductor region of the first conductivity type is electrically connected to the first electrode. At least a portion of the first insulating component is disposed between the first control electrode and the second semiconductor region. The fifth semiconductor region is disposed between at least a portion of the first electrode and the fourth semiconductor region. At least a portion of the second insulating component is disposed between the second control electrode and the first semiconductor region, and between the second control electrode and the fourth semiconductor region.

9. The control circuit of the semiconductor device according to claim 8, characterized in that, The semiconductor component further includes a sixth semiconductor region of the first conductivity type. At least a portion of the sixth semiconductor region is located between the second control electrode and the first semiconductor region. The at least portion of the second insulating component is located between the second control electrode and the sixth semiconductor region.

10. A semiconductor system comprising the control circuit and the semiconductor device of claim 1.

11. A control circuit for a semiconductor device, comprising a control unit configured to control the semiconductor device. The semiconductor device includes: First electrode; Second electrode; A semiconductor component is disposed between the first electrode and the second electrode; First control electrode; as well as Second control electrode, At least a portion of the semiconductor component is located between the first electrode and the first control electrode. At least a portion of the semiconductor component is located between the second control electrode and the second electrode. The control unit is configured to perform multiple operations during a first control turn-on period when the first control potential of the first control electrode is below a first threshold voltage, causing the second control potential of the second control electrode to change from the first potential to the second potential and from the second potential back to the first potential. If either the first potential or the second potential is higher than the second threshold voltage of the second control electrode, then... The other of the first potential and the second potential is lower than the second threshold voltage of the second control electrode.

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