Method of manufacturing a semiconductor device

Abstract

Embodiments of the present application relate to the technical field of semiconductor technology, and provide a preparation method of a semiconductor device. The preparation method of the semiconductor device comprises: forming a contact region in a semiconductor body; forming a patterned composite mask on the semiconductor body, the patterned composite mask defining a well region implantation window; performing ion implantation in the semiconductor body through the well region implantation window to form a well region adjacent to the contact region; thinning the patterned composite mask; forming a patterned shielding layer in the well region implantation window of the thinned patterned composite mask, the patterned shielding layer defining a source region implantation window; performing ion implantation into the well region through the source region implantation window to form a source region; removing the patterned composite mask and the patterned shielding layer; and forming an insulating layer, a control electrode, a first load electrode and a second load electrode on the semiconductor body.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating semiconductor devices. Background Technology

[0002] Third-generation wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have shown great application potential in high-voltage and high-frequency power semiconductor devices due to their excellent properties such as high breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. Among them, SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) have become key devices in fields such as electric vehicles and photovoltaic inverters due to their low on-resistance and fast switching capability.

[0003] In the fabrication process of planar SiC MOSFETs (taking N-channel MOSFETs as an example), the formation of the P-well and N+ source regions is a core step that determines device performance. Due to the physical properties of SiC material, such as high hardness and extremely low impurity diffusion coefficient, the high-temperature diffusion methods in traditional silicon-based processes are no longer applicable. It is necessary to use a combination of hard masking and high-energy ion implantation to achieve the controllable formation of doped regions.

[0004] Related technologies typically employ a sidewall self-alignment process: first, P-well ion implantation is performed using a relatively thick hard mask; then, a sidewall structure is formed on this hard mask through deposition and anisotropic etching; finally, this sidewall structure is used as a mask for N+ source region implantation, thereby achieving self-alignment between the source and well regions. However, in the process of realizing this application, the inventors discovered that as the device cell pitch continues to shrink, this process exposes the following technical bottlenecks: Firstly, the hard mask step is too high: P-well implantation requires a sufficiently thick hard mask (usually 500-2000nm) to effectively block high-energy ions, resulting in a steep high step at the edge of the P-well implantation window, which seriously affects the uniformity of subsequent photoresist coating.

[0005] Secondly, photoresist pattern delamination / spreading: In small-pitch MOSFETs, the photoresist pattern used to define the N+ source region is extremely small (feature size is often less than 0.5μm). The small contact area between this small photoresist pattern and the substrate is small, and the adhesion is weak. During development and spin drying, it is very easy for the photoresist pattern to collapse (delamination) or peel off (spreading), which seriously affects the manufacturing yield and reliability of the device.

[0006] Current self-alignment process solutions mainly focus on controlling channel length or the steepness of the injection window, but they have not effectively solved the problem of narrow windows and low yield in subsequent photolithography processes caused by the high steps of the hard mask of the P-well. Therefore, a new fabrication method is urgently needed to solve the stability problem of small-sized photoresist patterns while achieving self-alignment between the well and source regions. Summary of the Invention

[0007] Therefore, it is necessary to provide a method for fabricating semiconductor devices to solve the technical problem in related technologies where the hard mask step of the well region injection is too high, which causes small-sized photoresist patterns to easily deflect or drift during source region photolithography, thus affecting the device manufacturing yield.

[0008] The method for fabricating the semiconductor device includes: forming a contact region of a second conductivity type within a semiconductor body of a first conductivity type; forming a patterned composite mask on the semiconductor body, the patterned composite mask defining a well implantation window corresponding to the contact region; performing ion implantation within the semiconductor body through the well implantation window to form a well region of the second conductivity type adjacent to the contact region; thinning the patterned composite mask; forming a patterned masking layer within the well implantation window of the thinned patterned composite mask, the patterned masking layer covering the sidewalls of the well implantation window and the contact region, thereby defining a source implantation window surrounding the contact region; performing ion implantation into the well region through the source implantation window to form a source region of the first conductivity type; removing the patterned composite mask and the patterned masking layer; and forming an insulating layer, a control electrode, a first load electrode, and a second load electrode on the semiconductor body, wherein the control electrode is electrically insulated from the well region via the insulating layer, the first load electrode is electrically connected to the contact region and the source region, and the second load electrode is disposed on the side of the semiconductor body layer opposite to the control electrode.

[0009] In some embodiments, the step of forming a patterned composite mask includes: sequentially forming a first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer on a semiconductor body to form a composite mask; and patterning the composite mask with the first etch stop layer as the etch endpoint to form a well injection window.

[0010] In some embodiments, during the patterning etching step of the composite mask, the well injection window penetrates the first dielectric layer, the second etch stop layer, and the second dielectric layer, and exposes the first etch stop layer.

[0011] In some embodiments, during the step of patterning the composite mask, the well injection window penetrates the composite mask.

[0012] In some embodiments, the step of thinning the patterned composite mask includes: removing the second dielectric layer with the second etch stop layer as the etch endpoint.

[0013] In some embodiments, the step of forming a patterned masking layer includes: conformally depositing a sidewall layer on a thinned patterned composite mask and within a well injection window; forming a patterned photoresist layer on the sidewall layer, the patterned photoresist layer covering a portion of the sidewall layer corresponding to the contact area; and anisotropically etching the sidewall layer using the patterned photoresist layer as a mask to retain the sidewall layer on the sidewall of the well injection window and retain the sidewall layer covered by the patterned photoresist layer above the contact area, thereby forming a patterned masking layer.

[0014] In some embodiments, in the step of patterning the composite mask, the first etch stop layer is used as the etch endpoint, such that the well injection window penetrates the first dielectric layer, the second etch stop layer, and the second dielectric layer, and exposes the first etch stop layer; in the step of anisotropically etching the sidewall layer, the first etch stop layer is used as the etch endpoint.

[0015] In some embodiments, the etching selectivity ratio between the first dielectric layer and the first etch stop layer is greater than or equal to 10:1; and the etching selectivity ratio between the second dielectric layer and the second etch stop layer is greater than or equal to 5:1.

[0016] In some embodiments, the first etch stop layer and the second etch stop layer are selected from silicon nitride, polysilicon, or a combination thereof; the first dielectric layer and the second dielectric layer are silicon oxide.

[0017] In some embodiments, prior to the step of forming the contact region, the method further includes: forming a drift region of a first conductivity type on a substrate of a first conductivity type; and forming a junction field-effect transistor region within the drift region; wherein the semiconductor body includes the substrate, the drift region, and the junction field-effect transistor region.

[0018] In the semiconductor device fabrication method of this application embodiment, after the well region implantation is completed and before the patterned masking layer is formed, the patterned composite mask is thinned. By reducing the step height at the edge of the well region implantation window, the subsequent photoresist can uniformly cover and fill the low step, effectively avoiding the problem of photoresist delamination or drift due to insufficient adhesion during the development and spin-drying process of small-sized photoresist patterns, thereby improving the device manufacturing yield. Attached Figure Description

[0019] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0020] Figure 2 Figure (a) is a planar schematic diagram of a contact region formed within a semiconductor body in a method for fabricating a semiconductor device according to an embodiment of this application; Figure 2 Figure (b) is Figure 2Figure (a) shows a cross-sectional view along line II.

[0021] Figure 3 In order to be in Figure 2 Figure (b) shows a cross-sectional schematic diagram of a composite mask formed on a semiconductor body.

[0022] Figure 4 Figure (a) in the middle is a comparison Figure 3 After the composite mask is patterned, a planar schematic diagram of the trap region is formed; Figure 4 Figure (b) is Figure 4 Figure (a) shows a cross-sectional view along line II-II.

[0023] Figure 5 In order to be in Figure 4 The cross-sectional view of the structure in Figure (b) shows the formation of the first photoresist.

[0024] Figure 6 To Figure 5 A cross-sectional diagram of a patterned composite mask after thinning.

[0025] Figure 7 To remove Figure 6 A cross-sectional view of the first photoresist layer.

[0026] Figure 8 In order to be in Figure 7 The diagram shows a cross-sectional view of the structure after the sidewall layer has been formed.

[0027] Figure 9 In order to be in Figure 8 The diagram shows a cross-sectional view of the structure after the second photoresist layer has been formed.

[0028] Figure 10 Figure (a) in the middle is a comparison Figure 8 A planar schematic diagram of the patterned second photoresist layer; Figure 10 Figure (b) is Figure 10 Figure (a) shows a cross-sectional view along line III-III.

[0029] Figure 11 Figure (a) is a schematic diagram of anisotropic etching of the sidewall layer to form a patterned masking layer using a patterned second photoresist layer as a mask. Figure 11 Figure (b) is Figure 11 Figure (a) shows a cross-sectional view along line IV-IV.

[0030] Figure 12 Figure (a) shows the removal. Figure 11 (b) is a planar schematic diagram of the patterned second photoresist layer behind the image. Figure 12 Figure (b) is Figure 12 Figure (a) shows a cross-sectional view along line VV.

[0031] Figure 13 Figure (a) in the middle is based on Figure 12 The patterned masking layer in Figure (b) is a planar schematic diagram after the source region is formed; Figure 13 Figure (b) is Figure 13 Figure (a) shows a cross-sectional view along line VI-VI.

[0032] Figure 14 In order to be in Figure 13 The subsequent processes are completed on the structure shown in Figure (b) to obtain a cross-sectional schematic diagram of the semiconductor device.

[0033] Explanation of key component symbols: Semiconductor device - 100; Semiconductor body - 10; First surface - 101; Second surface - 102; Substrate - 11; Drift region - 12; Junction field-effect transistor region - 13; Contact region - 14; Well region - 15; Source region - 16; Insulating layer - 20; Control electrode - 30; First load electrode - 40; First ohmic contact layer - 41; Metal filling layer - 42; First metal layer - 43; Second load electrode - 50; Second ohmic contact layer - 51; Second metal layer - 52; Interlayer dielectric layer - 60; Composite mask - M; Patterned composite mask - M1; First etch stop layer - A1; First dielectric layer - B1; Second etch stop layer - A2; Second dielectric layer - B2; Trap injection window - O1; Source injection window - O2; First photoresist layer - P1; Second photoresist layer - P2; Patterned masking layer - M2; Sidewall layer - C; Transistor cell - TC; First direction - X; Second direction - Y.

[0034] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0035] The embodiments of this application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0036] It should be noted that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. The terms "exemplarily" or "for example," etc., are used to indicate examples, illustrations, or explanations, and should not be interpreted as indicating a preference or advantage over other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] Unless otherwise specified, all numerical range values recited in the embodiments of the present application shall include the endpoint values.

[0038] Unless otherwise defined, the term "connected" shall be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integrated connection; it may be directly connected, or indirectly connected through an intermediate medium.

[0039] Referring Figure 1 , the method for manufacturing a semiconductor device according to an embodiment of the present application includes the following steps S10 to S60. According to different requirements, the order of each step may be changed, and some steps may be omitted or combined.

[0040] The following combines Figures 2 to 14 , a MOSFET manufactured semiconductor device is taken as an example for detailed description. However, the method for manufacturing a semiconductor device according to the embodiments of the present application is also applicable to the manufacturing of other semiconductor devices such as other Metal Insulator Semiconductor Field Effect Transistors (Metal Insulator Semiconductor FET, MISFET), Insulated Gate Bipolar Transistors (Insulated Gate Bipolar Transistor, IGBT) and MOS controlled diodes.

[0041] S10: forming a contact region.

[0042] In some embodiments, S10 includes the following steps S11 and S12.

[0043] S11: forming a drift region of a first conductivity type on a substrate of the first conductivity type; and forming a junction field effect transistor region within the drift region. Wherein, the semiconductor body includes the substrate, the drift region and the junction field effect transistor region.

[0044] With reference to Figure 2 figure (a) in Figure 2 and figure (b) in, the semiconductor body 10 includes a substrate 11, a drift region 12 and a junction field effect transistor region 13.

[0045] In some embodiments, the substrate 11 can be, but is not limited to, silicon carbide.

[0046] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0047] In some embodiments, a chemical vapor deposition method is used to grow an epitaxial layer of the first conductivity type on the substrate 11 as the drift region 12. The thickness and doping concentration of the epitaxial layer are determined according to the device withstand voltage level design.

[0048] In some embodiments, the thickness of the epitaxial layer is, but not limited to, 5 μm to 20 μm, and the doping concentration of the epitaxial layer is, but not limited to, 1 × 10⁻⁶. 15 cm -3 ~1×10 17 cm -3 .

[0049] In some embodiments, forming a junction field-effect transistor region 13 within the drift region 12 includes: depositing a first hard mask layer (not shown) on the surface of the epitaxial layer; forming a junction field-effect transistor region implantation window in the first hard mask layer by photolithography and dry etching; performing junction field-effect transistor region ion implantation with the patterned first hard mask layer as a masking layer to form a junction field-effect transistor region of a first conductivity type in the epitaxial layer; and removing the patterned first hard mask layer according to standard processes after implantation.

[0050] In some embodiments, the material of the first hard mask layer is silicon oxide, silicon nitride, polysilicon, or a combination thereof.

[0051] In some embodiments, the thickness of the first hard mask layer is determined based on the energy and dose injected into the junction field-effect transistor region 13, and the thickness range of the first hard mask layer may be, but is not limited to, 1000nm~2000nm.

[0052] S12: A contact region of the second conductivity type is formed within the semiconductor body.

[0053] In some embodiments, S12 includes: depositing a second hard mask layer (not shown) on the surface of the epitaxial layer; forming a contact region implantation window in the second hard mask layer by photolithography and dry etching; performing contact region ion implantation with the patterned second hard mask layer as a masking layer; forming a heavily doped contact region 14 of a second conductivity type in the epitaxial layer; and removing the patterned second hard mask layer according to standard processes after implantation.

[0054] In some embodiments, the material of the second hard mask layer is silicon oxide, silicon nitride, polysilicon or a combination thereof, and the thickness of the second hard mask layer is determined according to the energy and dose injected into the contact region 14. The thickness range of the second hard mask layer may be, but is not limited to, 600 nm to 1600 nm.

[0055] Figure 2 Only one cell is shown in the diagram. In the semiconductor device 100, Figure 2The structure in can be expanded in a first direction X and a second direction Y. The first direction X, the second direction Y and the thickness direction of the semiconductor body 10 (hereinafter also referred to as a third direction Z) are perpendicular to each other two by two. Along the first direction X, a plurality of contact regions 10 are distributed at intervals, and a junction field effect transistor region 13 is arranged between two adjacent contact regions 14; along the second direction Y, a plurality of contact regions 14 are distributed at intervals, and a junction field effect transistor region 13 is arranged between two adjacent contact regions 14; along the third direction Z, each contact region 14 extends to contact with the drift region 12.

[0056] S20: forming a patterned composite mask.

[0057] In some embodiments, S20 includes the following steps S21 and S22.

[0058] S21: sequentially forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer on a semiconductor body to form a composite mask.

[0059] Referring to Figure 3 , the semiconductor body 10 has a first surface 101 and a second surface 102 opposite to each other. Along the third direction Z, the composite mask M includes a first etch stop layer A1, a first dielectric layer B1, a second etch stop layer A2 and a second dielectric layer B2 that are sequentially stacked from bottom to top on the first surface 101 of the semiconductor body 10.

[0060] In some embodiments, the etch selectivity between the first dielectric layer B1 and the first etch stop layer A1 is greater than or equal to 10:1.

[0061] In some embodiments, the etch selectivity between the second dielectric layer B2 and the second etch stop layer A2 is greater than or equal to 5:1.

[0062] In some embodiments, the thickness of the first etch stop layer A1 is, but not limited to, 50 nm to 200 nm.

[0063] In some embodiments, the material of the first etch stop layer A1 is selected from a film layer with high etch selectivity for the subsequent well region etching process, and is specifically selected from silicon nitride (Si3N4), polysilicon (poly) or a combination thereof. The functions of the first etch stop layer A1 include, but are not limited to, serving as an etch stop layer when an implantation window of a well region is formed by subsequent etching, and protecting the surface of the epitaxial layer in the semiconductor body 10 from excessive etching damage.

[0064] In some embodiments, the thickness of the first dielectric layer B1 may be, but is not limited to, 200 nm to 1000 nm, and the material of the first dielectric layer B1 may be, but is not limited to, silicon oxide (SiO2). The selection of the thickness of the first dielectric layer B1 is directly related to the subsequent step thinning amount and is one of the core adjustment parameters of the step controllable design. By adjusting the thickness of the first dielectric layer B1, the thickness of the hard mask to be removed and the remaining hard mask at the edge of the well injection window can be precisely set.

[0065] In some embodiments, the thickness of the second etch stop layer A2 is, but not limited to, 50 nm to 200 nm.

[0066] In some embodiments, the material of the second etch stop layer A2 may be the same as or different from that of the first etch stop layer A1, specifically selected from silicon nitride (Si3N4), polysilicon, or a combination thereof. The function of the second etch stop layer A2 includes, but is not limited to, serving as an etch stop layer during subsequent secondary etching, ensuring that etching precisely stops at the surface of the second etch stop layer A2, thereby achieving precise control over the amount of etching of the first dielectric layer B1.

[0067] In some embodiments, the thickness of the second dielectric layer B2 may be, but is not limited to, 500 nm to 2000 nm, and the material of the second dielectric layer B2 may be, but is not limited to, silicon oxide (SiO2). The second dielectric layer B2, as the outermost layer furthest from the semiconductor body 10 in the composite mask M, is mainly used to form the well injection window O1 during the initial photolithography and etching process.

[0068] In the above embodiments, in the composite mask M, through the alternating stacking of etch stop layers and dielectric layers, each pair of etch stop layer / dielectric layer interfaces can serve as a self-terminating interface in the corresponding etching step. The introduction of the second etch stop layer A2 gives the step thinning process after well region 15 implantation a clear etching endpoint, which helps to eliminate the negative impact of uneven over-etching or unstable thickness control on the photolithography of source region 16 in traditional schemes.

[0069] In one specific embodiment, forming the composite mask M includes sequentially depositing the following on the semiconductor body 10: First etch stop layer A1: A silicon nitride layer with a thickness of 100 nm is formed by low-pressure chemical vapor deposition at a deposition temperature of 600 °C and a precursor gas of SiH4 / NH3. First dielectric layer B1: Silicon oxide is formed by plasma chemical vapor deposition with a thickness of 400 nm and a deposition temperature of 350 °C. The precursor gas is TEOS / O2. The second etch stop layer A2: silicon nitride with a thickness of 100 nm is formed by low-pressure chemical vapor deposition, under the same deposition conditions as the first etch stop layer A1; and The second dielectric layer B2 is formed by plasma chemical vapor deposition of silicon oxide with a thickness of 800 nm, under the same deposition conditions as the first dielectric layer B1.

[0070] In another specific embodiment, the thickness of the first dielectric layer B1 can be set to 300nm, 500nm and 800nm, the first etch stop layer A1 is maintained at 100nm, the second etch stop layer A2 is maintained at 100nm, and the second dielectric layer B2 is maintained at 800nm.

[0071] In some embodiments, other films or combinations of films are present on the surface of the semiconductor body 10 before the formation of the first dielectric layer B1.

[0072] S22: Using the first etch stop layer A1 as the etch endpoint, the composite mask M is patterned and etched to form the well injection window O1.

[0073] In some embodiments, S22 includes the steps S221 and S222.

[0074] S221: Coat the surface of the composite mask with resist, expose and develop using a well region mask, and define a well region injection window pattern on the surface of the second dielectric layer.

[0075] S222: Using the first etch stop layer as the etch endpoint, the second dielectric layer, the second etch stop layer, and the first dielectric layer are etched sequentially using the first dry etching process to form a trap injection window in the composite mask.

[0076] In some embodiments, in S222, the first dry etching uses a fluorine-containing gas system (such as CF4 / CHF3 / Ar / O2). Because the first etch stop layer A1 has a high etch selectivity to the fluorine-containing etch gas (the etch rate is significantly lower than that of silicon oxide), the etching process automatically stops when it reaches the surface of the first etch stop layer A1, precisely exposing the first etch stop layer A1 and protecting the epitaxial layer below the first etch stop layer A1 from etch damage.

[0077] In one specific embodiment, inductively coupled plasma (ICP) multi-step dry etching is performed using a fluorine-based gas (CF4 / CHF3 / Ar = 50 / 25 / 200 sccm with a suitable amount of O2). The etching process sequentially opens three layers: a second dielectric layer B2 (SiO2, 800 nm), a second etch stop layer A2 (Si3N4, 100 nm), and a first dielectric layer B1 (SiO2, 400 nm). The etching endpoint is detected on the surface of the first etch stop layer A1. The endpoint monitoring system detects signal changes in the material composition. Upon reaching the first etch stop layer A1 (Si3N4), the intensity of the nitrogen excitation spectral line in the plasma increases, while the signal of the silicon oxide component decreases, and the equipment automatically stops the main etching. The total etching depth is approximately 1200 nm, and the remaining thickness of the bottom first etch stop layer A1 is approximately 100 nm, indicating no significant over-etching.

[0078] Combined with parameters Figure 4 Figure (a) and Figure 4 In Figure (b), the well injection window O1 penetrates the first dielectric layer B1, the second etch stop layer A2, and the second dielectric layer B2, and exposes the first etch stop layer A1. Along the third direction Z, the projection of the sidewall of the well injection window O1 on the semiconductor body 10 coincides with the boundary of the junction field-effect transistor region 13 and the well region 15.

[0079] In other embodiments, the well injection window O1 completely penetrates the composite mask M and exposes the well region 15 and the contact region 14. Along the third direction Z, the projection of the sidewall of the patterned composite mask M1 forming the well injection window O1 onto the semiconductor body 10 coincides with the boundary of the junction field-effect transistor region 13 and the well region 15.

[0080] S30: Formation of a trap zone.

[0081] In some embodiments, in S30, a patterned composite hard mask is used as the implantation masking layer to perform second conductivity type (P-type) ion implantation (such as aluminum ions, Al). 3+ The ions penetrate the first etch stop layer A1 and enter the underlying semiconductor body 10 to form a well region 15 of the second conductivity type.

[0082] Combined with parameters Figure 4 Figure (a) and Figure 4 In Figure (b), the well region 15 is adjacent to the contact region 14 and the junction field-effect transistor region 13. A PN junction is formed between the well region 15 and the junction field-effect transistor region 13.

[0083] In some embodiments, the contact region 14 is surrounded by the well region 15 in both the first direction X and the second direction Y. In other words, each well region 15 comprises two longitudinal portions adjacent to the junction field effect transistor region 13 and extending along the second direction Y, and a transverse portion located between two adjacent contact regions 14 in the second direction Y and connecting the two longitudinal portions.

[0084] S40: thinning the patterned composite mask.

[0085] S40 comprises: performing dry etching again to thin the step at the edge of the patterned composite mask M1 corresponding to the well region implantation window O1.

[0086] In some embodiments, S40 comprises the following steps S41 to S44.

[0087] S41: forming a first photoresist layer.

[0088] Refer to Figure 5 , the first photoresist layer P1 is coated on the semiconductor body 10 provided with the patterned composite mask M1, the first photoresist layer P1 fills the well region implantation window O1 and covers the patterned composite mask M1. The surface of the first photoresist layer P1 away from the semiconductor body 10 is substantially flush at positions corresponding to the well region implantation window O1 and the patterned composite mask M1.

[0089] In some embodiments, the thickness of the first photoresist layer P1 in S41 is set according to the thickness of the second dielectric layer B2 and etching requirements, and the thickness range of the first photoresist layer P1 can be, but is not limited to, 200nm~600nm.

[0090] S42: patterning the first photoresist layer.

[0091] Refer to Figure 6 , through a photolithography process, the patterned first photoresist layer P1 retains the portion covering the well region implantation window O1 and exposes the patterned composite mask M1.

[0092] S43: using the patterned first photoresist layer as a mask, and taking the second etch stop layer as an etching endpoint, removing the second dielectric layer.

[0093] Refer to Figure 6 , in the patterned composite mask M1, the second dielectric layer B2 is removed. In the third direction Z, the thickness of the thinned patterned composite mask M1 is the sum of the thicknesses of the first etch stop layer A1, the first dielectric layer B1 and the second etch stop layer A2.

[0094] In some embodiments, S43 includes: using a second etch stop layer A2 as an etch stop layer, and employing dry etching to etch the second dielectric layer B2 (silicon oxide). In this step, an etching gas system (such as a CF4 / CHF3 / Ar / O2 mixture) with a high etching rate for silicon oxide and a high etching selectivity for the material of the second etch stop layer A2 is used. Since the etching rate of the second etch stop layer A2 is much lower than that of the second dielectric layer B2 (selectivity ≥ 5:1), etching stops at the surface of the second etch stop layer A2. Through this design, the second dielectric layer B2 at the edge of the well injection window O1 is completely removed, and the high step height originally formed by the superposition of the first dielectric layer B1, the second etch stop layer A2, and the second dielectric layer B2 is reduced to a low step mainly determined by the thickness of the first dielectric layer B1 and the two etch stop layers.

[0095] It should be noted that in step S20 above, the total thickness of the film to be etched is the sum of the thickness of the first dielectric layer B1 (e.g., 300nm~1000nm), the thickness of the second etching stop layer A2 (e.g., 50nm~200nm), and the thickness of the second dielectric layer B2 (e.g., 500nm~2000nm). This etching requires opening three layers of material simultaneously.

[0096] In the actual etching process, due to the difference in etching rates between the second etch stop layer A2 and the first dielectric layer B1, in some embodiments the etching will not completely stop on the surface of the first etch stop layer A1. Instead, the etching endpoint is made to fall near the first etch stop layer A1 by the endpoint detection system and over-etch control.

[0097] Therefore, the thickness of the first etch stop layer A1 will be somewhat reduced after etching, with the thickness of the remaining first etch stop layer A1 above the epitaxial layer between 20 and 150 nm. After etching in step S43, the top surface of the remaining first etch stop layer A1 above the epitaxial layer exhibits a certain degree of roughness, displaying a microscopic uneven morphology. This roughened surface is beneficial for increasing the density of nucleation sites used to form the sidewall layer and the composite mask M, thereby improving the adhesion and coverage uniformity of the sidewalls on the steps of the patterned composite mask M1.

[0098] In addition, the remaining first etch stop layer A1 can serve as an additional implantation barrier layer, providing some auxiliary masking for the implantation of the well region 15 (such as P-type) and the subsequent implantation of the source region 16 (such as N-type heavily doped).

[0099] That is, in different specific embodiments, the composite mask M may also be directly etched in step S20 without stopping at the first etch stop layer A1. In this case, the first etch stop layer A1 may disappear completely, disappear partially, or have its surface damaged. The first etch stop layer A1 may remain with a partial thickness or be completely removed. When the first etch stop layer A1 remains a certain thickness, the first etch stop layer A1 can continue to be used as a protective layer for subsequent processes; when the first etch stop layer A1 is completely removed, the first surface 101 of the semiconductor body 10 is directly exposed, which can also support the deposition of the material layer for forming the sidewall and the subsequent implantation of the source region 16.

[0100] S44: removing the patterned first photoresist layer.

[0101] Refer to Figure 7 , the patterned first photoresist layer P1 is removed, and the surface of the first etch stop layer A1 is exposed at the well region implantation window O1.

[0102] In other embodiments, if the well region implantation window O1 of the patterned composite mask M1 formed in the above step S20 further penetrates the first etch stop layer A1, then in step S44, the well region 15 and the contact region 14 are exposed at the well region implantation window O1.

[0103] After thinning the patterned composite mask M1 in the above step S40, the composite mask M at the edge of the well region implantation window O1 exhibits a digitally controllable step height (mainly contributed by the thickness of the first etch stop layer A1), the step sidewall angle is close to 90° (steep), and the original rough etched surface is eliminated due to the protection of the second etch stop layer A2, forming a smooth hard mask surface profile, which creates an ideal adhesion substrate for the subsequent deposition of the material layer of the sidewall.

[0104] In a specific embodiment, photoresist (e.g., AZ5214E) is uniformly coated on the surface of the wafer after the implantation of the well region 15 is completed, with a thickness of about 1500 nm (ensuring that the photoresist can fill the etched opening, and there is enough residual photoresist to protect the bottom before etching stops at the second etch stop layer A2). Dry etching is performed using a mixed gas of CF4 / CHF3 / O2 (the typical flow ratio is CF4:CHF3:O2=100:50:15 sccm), the etching bias power is controlled at a medium-low level (about 120 W), and the chamber pressure is set to about 50 mTorr ~ 100 mTorr.

[0105] Under the above etching conditions, the etching rate of silicon oxide is about 200nm / min, and the etching rate of silicon nitride is about 15nm / min to 40nm / min. The etching time is designed such that the second dielectric layer B2 (800nm silicon oxide) is completely removed. When the etching progresses to the second etching stop layer A2 (silicon nitride layer), the etching rate decreases significantly (due to the high etching selectivity (siloxide:silicon nitride ≥ 10:1)), and the etching automatically stops on the surface of the second etching stop layer A2 (silicon nitride layer). After the above secondary etching, the second dielectric layer B2 (silicon oxide) at the edge of the well region implantation window O1 is completely removed, and the remaining film structure is first etching stop layer A1 / first dielectric layer B1 / second etching stop layer A2, and the height of the composite mask is significantly reduced. After etching is completed, the patterned first photoresist layer P1 is removed.

[0106] S50: forming a source region.

[0107] In some embodiments, S50 includes the following steps S51 to S53.

[0108] S51: forming a patterned shielding layer in the well region implantation window of the thinned patterned composite mask, wherein the patterned shielding layer covers the sidewall and the contact region of the well region implantation window, thereby defining a source region implantation window surrounding the contact region.

[0109] In some embodiments, forming the patterned shielding layer M2 in step S51 includes the following steps S511 to S514.

[0110] S511: conformally depositing a sidewall layer on the thinned patterned composite mask and in the well region implantation window.

[0111] See Figure 8 , the sidewall layer C covers the surface of the patterned composite mask M1 away from the semiconductor body 10, the sidewall of the well region implantation window O1, and the bottom wall of the well region implantation window O1.

[0112] In some embodiments, the material of the sidewall layer C can be, but is not limited to, silicon oxide or silicon nitride.

[0113] In some embodiments, the method for depositing the sidewall layer C can be, but is not limited to, chemical vapor deposition or atomic layer deposition.

[0114] In some embodiments, the deposition thickness of the sidewall layer C determines the channel length of the device, and the thickness range of the sidewall layer C can be, but is not limited to, 50nm to 300nm.

[0115] In a specific embodiment, S511 includes forming a silicon oxide layer by low-pressure chemical vapor deposition at a deposition temperature of 780°C and a thickness of about 250nm. Anisotropic etching is performed with CF4 / CHF3 / O2 / Ar gas, and the residual width of the sidewall is about 250nm.

[0116] S512: forming a patterned photoresist layer on the sidewall spacer layer, wherein the patterned photoresist layer covers a portion of the sidewall spacer layer corresponding to the contact region.

[0117] Step S512 includes: forming a second photoresist layer on the sidewall spacer layer; and patterning the second photoresist layer.

[0118] Referring Figure 9 , the upper surface of the portion of the second photoresist layer P2 corresponding to the well implantation window O1 and the portion on the thinned patterned composite mask M1 are substantially flush.

[0119] With reference to Figure 10 Figure (a) in Figure 10 and Figure (b) in Figure 2 , the patterned photoresist layer (i.e., the patterned second photoresist layer P2) covers the contact region 14 and exposes the portion of the sidewall spacer layer C corresponding to other regions.

[0120] Each side surface of the patterned second photoresist layer P2 is spaced apart from the sidewall spacer layer C on the sidewall of the well implantation window O1. In other words, the patterned second photoresist layer P2 is in an isolated island shape.

[0121] S513: performing anisotropic etching on the sidewall spacer layer by using the patterned second photoresist layer as a mask, so as to retain the sidewall spacer layer on the sidewall of the well implantation window and retain the sidewall spacer layer covered by the patterned photoresist layer above the contact region, thereby forming a patterned shielding layer.

[0122] In some embodiments, dry etching is performed on the sidewall spacer layer C to remove the sidewall spacer layer C in the horizontal direction, and retain the self-aligned sidewall structure in the well implantation window O1 and the portion of the sidewall spacer layer C covered by the patterned second photoresist. During the etching process, the etching selectivity between the sidewall spacer layer C and the first etching stop layer A1 can be used for end point control to ensure accurate etching positioning.

[0123] With reference to Figure 10 Figure (a) in Figure 10 , Figure (b) in Figure 11 , Figure (a) in Figure 11 and Figure (b) in, the portion of the sidewall spacer layer C covered by the patterned second photoresist layer P2 is retained. Among the portions of the sidewall spacer layer C not covered by the patterned second photoresist layer P2, the horizontal portions are removed, and the portions on the sidewall of the well implantation window O1 are retained.

[0124] S514: removing the patterned second photoresist layer.

[0125] With reference to Figure 11 Figure (a) in Figure 11 in diagram b, Figure 12 in diagram a, Figure 12 in diagram b, the patterned second photoresist layer P2 is removed.

[0126] In some embodiments, in the step of patterning the composite mask M described above, the formed well region implantation window O1 penetrates through the first dielectric layer B1, the second etch stop layer A2 and the second dielectric layer B2, and exposes the first etch stop layer A1; then in the step of performing anisotropic etching on the sidewall layer C in step S513, the first etch stop layer A1 is used as the etching endpoint.

[0127] S52: performing ion implantation in the well region through the source region implantation window of the patterned masking layer to form a source region of a first conductivity type.

[0128] In some embodiments, using the thinned patterned composite mask M1 and the patterned masking layer M2 as the implantation mask, ion implantation of an N-type moderately doped source region 16 (nitrogen ions or phosphorus ions) is performed to form the source region 16 of the first conductivity type (N-type) in the P-type well region 15 in a self-aligned manner.

[0129] With reference to Figure 13 the diagram a and Figure 13 the diagram b, the source region 16 is located in the well region 15 and adjacent to the contact region 14. In the first direction X and the second direction Y, the source region 16 surrounds the contact region 14. In the third direction Z, the depth of the source region 16 is smaller than the depth of the contact region 14 and the depth of the well region 15 respectively. A PN junction is formed between the source region 16 and the contact region 14, and a PN junction is formed between the source region 16 and the well region 15.

[0130] S53: removing the patterned composite mask and the patterned masking layer.

[0131] Referring to Figure 13 , both the patterned composite mask M1 and the patterned masking layer M2 are removed.

[0132] In some embodiments, BOE wet etching or hot phosphoric acid may be used to selectively remove the patterned composite mask M1 and the patterned masking layer M2. BOE removes silicon oxide, and hot phosphoric acid removes silicon nitride.

[0133] S60: forming an insulating layer, a control electrode, a first load electrode and a second load electrode.

[0134] Referring to Figure 14After the subsequent process of S60, the insulating layer 20 is located on the semiconductor body 10, the control electrode 30 is electrically insulated from the well region 15 through the insulating layer 20, the first load electrode 40 is electrically connected to the contact region 14 and the source region 16, and the second load electrode 50 is disposed on the side of the semiconductor body 10 layer away from the control electrode 30.

[0135] In some embodiments, the semiconductor device 100 is a planar gate MOSFET including multiple transistor units TC, the control electrode 30 is the gate, and the insulating layer 20 is the gate dielectric layer. The first load electrode 40 is the source electrode, and the second load electrode 50 is the drain electrode.

[0136] The first load electrode 40 includes a first ohmic contact layer 41, a metal filler layer 42, and a first metal layer 43. The semiconductor device 100 also includes an interlayer dielectric layer 60. The interlayer dielectric layer 60 covers the control electrode 30 and a portion of the first surface 101 of the semiconductor body 10, and has contact holes corresponding to the contact region 14 and the source region 16. The first ohmic contact layer 41 contacts the contact region 14 and the source region 16, and the metal filler layer 42 is located within the contact holes and stacked on the first ohmic contact layer 41. The first metal layer 43 covers the interlayer dielectric layer 60 and is electrically connected to the metal filler layer 42. The second load electrode 50 includes a second ohmic contact layer 51 and a second metal layer 52. The second ohmic contact layer 51 contacts the second surface 102 of the semiconductor body 10, and the second metal layer 52 is stacked on the side of the second ohmic contact layer 51 opposite to the second surface 102. In this case, subsequent processes in S60 include, but are not limited to: gate oxide growth, gate polysilicon deposition and etching, source and drain metal deposition and ohmic contact annealing, backside thinning and drain metallization, passivation layer deposition, etc., to finally complete the fabrication of the MOSFET device.

[0137] Figure 14 The diagram illustrates two transistor units TC; however, a semiconductor device 100 may include more than two transistor units TC, such as tens, hundreds, thousands, tens of thousands, hundreds of thousands, or even millions of transistor units TC. Each of the two transistor units TC includes a drift region 12, a junction field-effect transistor region 13, a contact region 14, a well region 15, and a source region 16. The well region 15 is located between the drift region 12 and the source region 16, and between the junction field-effect transistor region 13 and the source region 16. Each transistor unit TC includes a gate, a source, and a drain. The gate of each transistor unit TC is electrically connected to a gate terminal, the source of each transistor unit TC is electrically connected to a source terminal, and the drain of each transistor unit TC is electrically connected to a drain terminal. All transistor units TC share the drift region 12, the second load electrode 50, and the first metal layer 43 in the first load electrode 40.

[0138] The method for fabricating the semiconductor device according to the embodiments of this application has at least the following beneficial effects: Firstly, it helps solve the problem of photoresist spillage or drift, as analyzed below: The semiconductor device fabrication method of this application involves forming a composite mask composed of multiple films. Before depositing the sidewall layer, the composite mask at the edge of the well injection window undergoes precise and controllable step thinning, significantly reducing the original high step height. With the step height reduced, the photoresist can completely cover and fill the low step during spin coating, effectively eliminating the influence of the step edge on the uniformity of photoresist coverage. During subsequent development and spin drying, the bottom of the photoresist will not crack, peel, or drift due to being suspended or too thin.

[0139] The method for fabricating this semiconductor device is particularly suitable for SiC power MOSFETs with small cell spacing (≤5μm) and high cell density. The photoresist desorption rate of small-sized photoresist islands (aspect ratio) in the source region photolithography process is significantly reduced, and the final yield of the device is improved.

[0140] Secondly, the precise "digital" control of the step thinning amount during the thinning of the patterned composite mask is analyzed as follows: The semiconductor device fabrication method of this application provides a composite mask composed of four alternating film layers. It utilizes an extremely high etch selectivity ratio (≥10:1) between the first etch stop layer and the first dielectric layer, and an extremely high etch selectivity ratio (≥5:1) between the second etch stop layer and the second dielectric layer, to achieve self-stopping functionality for multiple etching processes. Specifically: during well region window etching, the first etch stop layer precisely terminates the etching, protecting the epitaxial layer in the underlying semiconductor body from over-etching damage; after well region implantation is completed, the second dielectric layer is etched, precisely stopping at the surface of the second etch stop layer.

[0141] Therefore, the step thinning amount is determined by the original deposition thickness of the second dielectric layer, and the final step height is jointly determined by the thicknesses of the first etch stop layer, the first dielectric layer, and the second etch stop layer. The thinning amount no longer depends on the etching time estimation, but is guaranteed by the thin film deposition accuracy, realizing the "hard" preset and digital control of process parameters.

[0142] Third, the process uniformity and batch-to-batch consistency are high, as analyzed below: The second etch stop layer serves as a rigid etch endpoint reference, significantly improving the uniformity of etch depth across the entire wafer surface and effectively ensuring batch-to-batch repeatability. This helps avoid significant fluctuations caused by errors in etch endpoint judgment in traditional processes. This structure inherently suppresses fluctuations in photolithography exposure energy and etch chamber state drift. Combined with the adjustability of the first dielectric layer thickness during the design phase, the differentiated step height requirements of different device structures can be achieved by selecting different deposition thicknesses without adjusting the etch process.

[0143] Fourth, it has good process compatibility and is easy to implement in production lines, as analyzed below: Each layer of the composite mask can be achieved using conventional thin-film deposition processes (low-pressure chemical vapor deposition, plasma chemical vapor deposition, etc.). The materials used are mature semiconductor materials (silicon oxide, silicon nitride, polysilicon), and the photolithography and etching equipment and gases (CF4 / CHF3 / O2, etc.) used are all industry-standard, requiring no additional mask layers or the introduction of special materials. Compared to the complex processes of traditional multiple photolithography and etching steps, this method only adds one or two layers to the film thickness during the mask deposition stage. Subsequent self-terminating etching achieves precise morphology control, greatly reducing the difficulty of process integration and facilitating rapid implementation in existing SiC MOSFET production lines.

[0144] In summary, the embodiments of this application, through a composite mask structure combined with a multi-step self-terminating etching process, transform the unreliable process that originally relied on a single etching step for control into a reliable process that can be precisely preset by the thickness of multiple thin films. This helps to fundamentally solve the problem of photoresist spillage / drift in the source region caused by hard mask steps in the well region. It is particularly suitable for the mass production of SiC MOSFETs with small pitch and high-density cells.

[0145] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Within a semiconductor body of the first conductivity type, a contact region of the second conductivity type is formed; A patterned composite mask is formed on the semiconductor body, the patterned composite mask defining a well injection window corresponding to the contact region; Ion implantation is performed within the semiconductor body through the well implantation window to form a well region of a second conductivity type adjacent to the contact region; Thinning of the patterned composite mask; Within the well injection window of the thinned patterned composite mask, a patterned masking layer is formed, which covers the sidewalls of the well injection window and the contact area, thereby defining a source injection window surrounding the contact area. Ions are implanted into the well region through the source region implantation window to form a source region of the first conductivity type; Remove the patterned composite mask and the patterned masking layer; as well as An insulating layer, a control electrode, a first load electrode, and a second load electrode are formed on the semiconductor body. The control electrode is electrically insulated from the well region via the insulating layer. The first load electrode is electrically connected to the contact region and the source region. The second load electrode is disposed on the side of the semiconductor body layer opposite to the control electrode.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Forming the patterned composite mask includes: A first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer are sequentially formed on the semiconductor body to form a composite mask; and Using the first etch stop layer as the etch endpoint, the composite mask is patterned and etched to form the well injection window.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, In the step of patterning and etching the composite mask, the well injection window penetrates the first dielectric layer, the second etch stop layer, and the second dielectric layer, and exposes the first etch stop layer.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, In the step of patterning and etching the composite mask, the well injection window penetrates the composite mask.

5. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The step of thinning the patterned composite mask includes: The second dielectric layer is removed with the second etch stop layer as the etch endpoint.

6. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The step of forming the patterned masking layer includes: Conformally deposited sidewall layers on the thinned patterned composite mask and within the well injection window; A patterned photoresist layer is formed on the sidewall layer, the patterned photoresist layer covering the portion of the sidewall layer corresponding to the contact area; and Using the patterned photoresist layer as a mask, the sidewall layer is anisotropically etched to retain the sidewall layer on the sidewall of the injection window in the trap region, and to retain the sidewall layer covered by the patterned photoresist layer above the contact area, thereby forming the patterned masking layer.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, In the step of patterning and etching the composite mask, the first etch stop layer is used as the etch endpoint, so that the well injection window penetrates the first dielectric layer, the second etch stop layer and the second dielectric layer, and exposes the first etch stop layer. In the step of anisotropic etching of the sidewall layer, the first etching stop layer is taken as the etching endpoint.

8. The method for fabricating a semiconductor device according to any one of claims 2 to 7, characterized in that, The etching selectivity ratio between the first dielectric layer and the first etch stop layer is greater than or equal to 10:1; The etching selectivity ratio between the second dielectric layer and the second etching stop layer is greater than or equal to 5:

1.

9. The method for fabricating a semiconductor device according to any one of claims 2 to 7, characterized in that, The first etch stop layer and the second etch stop layer are selected from silicon nitride, polysilicon, or a combination thereof; The first dielectric layer and the second dielectric layer are silicon oxide.

10. A method for fabricating a semiconductor device according to any one of claims 1 to 7, characterized in that, Prior to the step of forming the contact area, the method further includes: A drift region of the first conductivity type is formed on a substrate of the first conductivity type; and Within the drift region, a junction field-effect transistor region is formed; The semiconductor body includes the substrate, the drift region, and the junction field-effect transistor region.

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