A double-trench gate based LDMOS and LDMOS device

Abstract

A kind of LDMOS and LDMOS device based on double-trench gate, including preparation on substrate P-type well region, N-type drift region, preparation in the source region of P-type well region, preparation on the drain region of N-type drift region and preparation in the gate region between P-type well region and N-type drift region.Gate region includes the main trench gate and vice trench gate that is set in the source region both sides, main trench gate includes the gate main trench region of trench structure and is used for the main gate oxide region of separate isolation, vice trench gate includes the gate vice trench region of trench structure and is used for the vice gate oxide region of separate isolation.Due to the added vice trench gate can produce significant field modulation effect to its contact N-type drift region, promote the area in drift region close to vice gate to form high concentration carrier accumulation layer, to form a low impedance conductive channel in addition in LDMOS device body outside conventional surface conductive path, then greatly reduce the bulk resistance of drift region, to significantly reduce the specific on-resistance of device as a whole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to an LDMOS and LDMOS device based on a double trench gate. Background Technology

[0002] DMOS stands for Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, primarily consisting of two types: VDMOS and LDMOS (Laterally Diffused MOSFET). LDMOS, with its advantages of high voltage withstand capability, high transconductance, and high gain, is widely used as a high-voltage power device in radio frequency power integrated circuits. An LDMOS device is composed of hundreds or thousands of individual LDMOS cells. In the 90nm BCD (Bipolar-CMOS-DMOS) process platform, the LDMOS device is the core component for achieving "high-voltage / high-current power switching capability," working in conjunction with on-chip low-voltage CMOS control and logic, as well as BJTs, ESD protection devices, and isolation devices to complete power conversion and intelligent control on the same chip. A crucial parameter for LDMOS devices is their breakdown voltage. Power semiconductor devices are preferably those capable of operating at voltages close to the theoretical breakdown voltage of semiconductors. In transistors integrating high voltage, the punch-through voltage between the drain / source and the semiconductor substrate, as well as the breakdown voltage between the drain / source and the well or substrate, must be greater than the operating voltage. As IC integration density increases and device feature sizes decrease, the gate oxide layer becomes increasingly thinner, significantly reducing its gate breakdown voltage. The breakdown voltage of LDMOS is a crucial parameter and a key aspect of its reliability. Although LDMOS possesses a low-doped drift region, giving it a higher breakdown voltage compared to other MOS devices, the increasing demand for high-voltage, high-power applications necessitates measures to further enhance its breakdown voltage to meet the requirements of high-frequency, high-voltage operation. Summary of the Invention

[0003] The main technical problem this invention addresses is how to improve the voltage withstand capability of LDMOS.

[0004] According to a first aspect, one embodiment provides an LDMOS based on a double trench gate, including a substrate, a P-type well region, an N-type drift region, a gate region, a source region formed in the P-type well region, and a drain region formed in the N-type drift region;

[0005] The gate region includes a main trench gate and a sub-trench gate; the P-type well region is disposed between the main trench gate and the sub-trench gate; the main trench gate includes a trench-structured gate main trench region and a main gate oxide region for individually isolating the gate main trench region; the sub-trench gate includes a trench-structured gate sub-trench region and a sub-gate oxide region for individually isolating the gate sub-trench region.

[0006] The extension depth of the main trench gate into the substrate is not less than the extension depth of the P-type well region into the substrate, and the extension depth of the secondary trench gate into the substrate is greater than the extension depth of the main trench gate into the substrate.

[0007] The source region includes a first source region, a second source region, and a body region. The first source region, the body region, and the second source region are sequentially attached between the main trench gate and the secondary trench gate. The body region is used to isolate the first source region and the second source region. The first source region and the second source region have the same doping type, but the doping type is different from that of the body region.

[0008] The gate connection terminal of the LDMOS is electrically connected to the main gate trench region and the secondary gate trench region;

[0009] The source terminal of the LDMOS is electrically connected to the first source region and the second source region;

[0010] The drain terminal of the LDMOS is electrically connected to the drain region.

[0011] In one embodiment, the secondary trench gate is attached to the first source region, and the second source region is attached to the main trench gate; the N-type drift region is attached to the main trench gate, and the drain region is located at the distal end of the attachment point between the N-type drift region and the main trench gate;

[0012] The gate sub-trench region of the sub-trench gate extends into the substrate.

[0013] In one embodiment, the N-type drift region extends into the substrate at a greater depth than the main trench gate extends into the substrate;

[0014] The substrate also contains an N-type buried region; the N-type buried region is disposed between the area where the extension of the secondary trench gate and the N-type drift region toward the substrate exceeds the extension of the main trench gate toward the substrate.

[0015] In one embodiment, a P-type buried region is further formed in the substrate; the P-type buried region is disposed between the N-type buried region and the substrate to isolate the N-type buried region and the substrate; the extended end face of the N-type drift region extending into contact with the substrate is fitted with the P-type buried region.

[0016] In one embodiment, the gate main trench region includes an upper substrate region and an under substrate region. The under substrate region serves as a trench structure extending from the gate main trench region toward the substrate. The upper substrate region is higher than the upper surfaces of the source region and the N-type drift region. The upper substrate region extends toward the upper surfaces of the source region and the N-type drift region, and the extension is isolated from the upper surfaces of the source region and the N-type drift region by the extension of the main gate oxide region.

[0017] In one embodiment, an oxide isolation layer for insulation is provided on the side of the substrate region above the upper surface of the source region and the N-type drift region, and the gate connection terminal of the LDMOS is electrically connected to the upper surface of the substrate region.

[0018] In one embodiment, the trench structure of the gate main trench region and / or the gate sub trench region is a stepped trench with decreasing width from top to bottom, an inverted trapezoidal trench with a wider top and a narrower bottom, or a square trench.

[0019] In one embodiment, the gate sub-trench region and the gate main trench region are made of polysilicon;

[0020] The main gate oxide region and the secondary gate oxide region are made of silicon dioxide; the N-type buried region and the P-type buried region are highly doped regions; the LDMOS substrate is a P-type substrate.

[0021] According to a second aspect, one embodiment provides an LDMOS device comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described in the first aspect.

[0022] According to the above embodiment of LDMOS, since a sub-trench gate is added on the basis of the main trench gate, the sub-trench gate can generate a significant field modulation effect on the N-type drift region it contacts, causing a high-concentration carrier accumulation layer to be formed in the region near the sub-gate in the drift region. Thus, in addition to the conventional surface conductive path, a low-impedance conductive channel is additionally constructed in the LDMOS device body, thereby significantly reducing the bulk resistance of the drift region and significantly reducing the overall specific on-resistance of the device. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a cross-sectional structure of an LDMOS.

[0024] Figure 2 This is a schematic diagram of the electric field line distribution of a planar LDMOS.

[0025] Figure 3 This is a schematic cross-sectional view of an LDMOS based on a double trench gate in one embodiment;

[0026] Figure 4 This is a schematic cross-sectional view of an LDMOS structure in one embodiment;

[0027] Figure 5 This is a schematic diagram of the doped profile of an LDMOS in one embodiment;

[0028] Figure 6 This is a schematic diagram of the current density distribution of an LDMOS in one embodiment, where only the main gate exists.

[0029] Figure 7 This is a schematic diagram of the current density distribution in one embodiment of the LDMOS where both the main and secondary gates exist.

[0030] Figure 8 This is a schematic diagram comparing the breakdown voltage curves of trench gate LDMOS and planar gate LDMOS in one embodiment. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0032] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0033] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0034] In the BCD (Bipolar-CMOS-DMOS) process platform, LDMOS (Laterally Diffused MOSFET) devices are the core components for achieving "high-voltage / high-current power switching capability." They work in conjunction with on-chip low-voltage CMOS control / logic and BJT / ESD / isolation devices to complete power conversion and intelligent control on the same chip. Traditional planar LDMOS typically relies on RESURF and surface field plate technology for electric field optimization to reduce specific on-resistance, but surface electric field concentration remains a key bottleneck limiting breakdown voltage. The trench gate structure introduced in this invention effectively transfers the high electric field region from the device surface to the silicon bulk, significantly reducing the local electric field peak and thus further improving the device's breakdown voltage. Furthermore, the introduction of a sub-gate creates additional charge modulation or low-resistance channels, further significantly optimizing the specific on-resistance and thereby greatly improving the overall quality factor and comprehensive performance of the LDMOS.

[0035] Please refer to Figure 1This is a schematic diagram of a cross-sectional structure of an LDMOS. Planar LDMOS typically uses a gate-N-type drift region (N-drift) for lateral voltage withstand to achieve high-voltage turn-off support. The P-body region of the LDMOS is usually short-circuited to the source. Its core functions are to form a conductive channel, form a main withstand voltage PN junction with the N-drift, and suppress parasitic BJT effects and prevent latch-up by shorting to the source. Shallow Trench Isolation (STI) serves to provide electrical isolation (isolate adjacent devices to prevent leakage) and surface electric field modulation (located on the surface of the drift region between the gate and drain, its edges help disperse the electric field and optimize the breakdown voltage). The source, as the current input terminal of the LDMOS (for N-LDMOS), has a key structural feature where the internal N+ region (providing charge carriers) and the P+ contact region (connecting the body) are shorted in the metal layer, forming a "source-body short." Polysilicon serves as the gate electrode in LDMOS (located above the gate oxide, where a voltage is applied to control the opening and closing of the channel below) and extends as a field plate (often extending to cover part of the drift region, becoming a "gate field plate" to smooth the surface electric field). Silicon nitride (Si3N4), as a dielectric material, is used in the process for etching hard masks / stop layers (due to its higher etching selectivity compared to silicon dioxide), passivation protection layers, and stress layers (to improve CMOS performance). In LDMOS, it is usually part of the process, not the active region of the device. The drain is the current output / high voltage withstand terminal of the LDMOS, located at the end of the N-drift region, led out through a metal contact, and withstands a high voltage when the LDMOS is turned off. The P-well region and the body region are usually the same area. From a manufacturing perspective, "P-well" emphasizes that it is a P-type doped region formed by ion implantation, used to form the body region of the MOSFET and the necessary PN junction. The N-type drift region is the core area for achieving high-voltage capability in LDMOS. Its functions are voltage withstand (lightly doped, it can be fully depleted to withstand high voltage during turn-off) and conductivity (providing a path for current from the channel to the drain during turn-on). Its length and doping distribution are key considerations in the trade-off design of breakdown voltage (BV) and specific on-resistance (Ron, sp). The P-type substrate (P-sub) is the mechanical base and common electrical ground of the chip. Its functions are to support all devices, provide electrical isolation (forming a PN junction with the N-type region above), and be connected to the lowest potential (e.g., grounding, providing a path for parasitic currents).

[0036] LDMOS has two operating states: off and on. Specifically, it includes:

[0037] Off-state (withstand voltage): When the gate voltage (Vg) is 0 and a high voltage (Vd) is applied to the drain, the voltage drops mainly in two regions: the reverse-biased PN junction formed by the P-well / N-drift and the fully depleted N-drift region itself. The P-sub, through its connection with the PN junction at the bottom of the N-drift region, prevents the voltage from penetrating the entire substrate. The surface electric field is most likely to concentrate at the edges of the Poly gate and the STI, thus requiring techniques such as field plates (Poly extension) and RESURF doping for optimization.

[0038] On-state (conductivity): When the gate voltage (Vg) exceeds the threshold voltage, an N-type inversion layer channel forms on the surface of the Body region beneath the Poly gate. Electrons originate from the N+ region at the Source end, pass through the channel into the N-drift region, and finally reach the N+ region at the Drain end. The resistance of the N-drift region is the main factor determining the overall on-resistance of the device; therefore, it is necessary to minimize its resistance as much as possible while ensuring the withstand voltage.

[0039] Please refer to Figure 2 The diagram shows the electric field distribution of a planar LDMOS. Due to various geometric and dielectric abrupt changes on the device surface (such as gate edge, field oxygen / isolation boundary, curvature change of P-well / N-drift junction at the surface), the potential lines are more likely to accumulate on the surface in the off state (purple area), resulting in the surface electric field peak being significantly higher than the bulk electric field, making the device prone to breakdown at the surface.

[0040] In this embodiment, the gate region includes a main trench gate and a sub-trench gate. The added sub-trench gate is used to optimize the forward conduction characteristics of the LDMOS device. The deep trench structure of the sub-trench gate extends longitudinally into the N-type drift region of the substrate. When the LDMOS device is in the forward conduction state, this sub-trench gate can generate a significant field modulation effect on its sidewalls and bottom N-type drift regions. This field modulation effect promotes the formation of a high-concentration carrier accumulation layer in the region near the sub-gate within the drift region, thereby constructing a low-impedance additional conductive channel within the LDMOS device body, in addition to the conventional surface conductive path. Furthermore, the introduction of the deep trench structure effectively guides and improves the spatial distribution of the internal current density, alleviating the current congestion effect commonly found in traditional lateral devices. Through the extension of the longitudinal conductive path and the reshaping of the current distribution, this sub-gate structure significantly reduces the bulk resistance of the drift region, thereby significantly reducing the overall specific on-resistance (R0) of the device. on,sp This effectively improves the device's conduction capability and reduces static power consumption.

[0041] Please refer to Figure 3This is a cross-sectional view of an LDMOS based on a dual trench gate in one embodiment. To improve the voltage withstand capability of the LDMOS surface, the LDMOS includes a substrate 100, a P-type well region 20, an N-type drift region 30, a gate region, a source region, and a drain region 400. The P-type well region 20, the N-type drift region 30, and the gate region are all formed on the substrate. The source region is formed on the P-type well region 20, and the drain region 400 is formed on the N-type drift region 30. The gate region includes a main trench gate and a sub-trench gate. The P-type well region 20 is disposed between the main trench gate and the sub-trench gate. The main trench gate includes a trench-shaped main trench gate region 200 and a main gate oxide region 11 that independently covers and isolates the main trench gate region 200. The sub-trench gate includes a trench-shaped sub-trench gate region 300 and a sub-gate oxide region 31 that independently covers and isolates the sub-trench gate region 300. The extension depth of the main trench gate into the substrate 100 is not less than the extension depth of the P-type well region 20 into the substrate 100, and the extension depth of the secondary trench gate into the substrate 100 is greater than the extension depth of the main trench gate into the substrate 200. The source region includes a first source region 600, a second source region 500, and a body region 10. The first source region 600, the body region 10, and the second source region 500 are sequentially attached between the main trench gate and the secondary trench gate, and the body region 10 isolates the first source region 600 and the second source region 500. Both the first source region 600 and the second source region 500 are N+ doped regions, and the body region 10 is a P+ doped region. The gate connection terminal of the LDMOS is electrically connected to both the main gate trench region 200 and the secondary gate trench region 300. The source connection terminal of the LDMOS is electrically connected to both the first source region 600 and the second source region 500. The drain connection terminal of the LDMOS is electrically connected to the drain region 400.

[0042] In one embodiment, the secondary trench gate is bonded to the first source region 600, and the second source region 500 is bonded to the main trench gate. In another embodiment, the N-type drift region 30 is bonded to the main trench gate, and the drain region 400 is located at the end of the N-type drift region 30 away from the main trench gate. In yet another embodiment, the gate secondary trench region 300 extends downward into the interior of the substrate 100.

[0043] In one embodiment, the extension depth of the N-type drift region 30 into the substrate 100 is greater than the extension depth of the main trench gate into the substrate 100. In another embodiment, an N-type buried region 40 is formed within the substrate 100, the N-type buried region 40 being located between the secondary trench gate and the extension region of the N-type drift region 30 beyond the depth of the main trench gate.

[0044] In one embodiment, a P-type buried region 50 is also formed in the substrate 100. The P-type buried region 50 is disposed between the N-type buried region 40 and the substrate 100 to achieve isolation between the N-type buried region 40 and the substrate 100. The extended end face of the N-type drift region 30 extending into contact with the substrate 100 is attached to the P-type buried region 50.

[0045] Please refer to Figure 4 This is a schematic cross-sectional view of an LDMOS in one embodiment. In one embodiment, the gate main trench region includes an upper substrate region 13 and a lower substrate region 12. The lower substrate region 12 is the main trench structure extending from the gate main trench region to the substrate. The upper surface of the upper substrate region 13 is higher than the upper surfaces of the source region and the N-type drift region 30. The upper substrate region 13 extends to the upper surfaces of the source region and the N-type drift region 30, and the extended portion is isolated from the upper surfaces of the source region and the N-type drift region by the extended portion of the main gate oxide region 11. An insulating oxide isolation layer 14 is provided on the sidewall of the upper substrate region 13 above the upper surfaces of the source region and the N-type drift region. The gate connection terminal of the LDMOS is electrically connected to the upper surface of the upper substrate region 13. In one embodiment, the oxide isolation layer is filled silicon dioxide. In one embodiment, both the gate main trench region and the gate sub-trench region are made of polysilicon. In one embodiment, the substrate 100 is a P-type substrate.

[0046] In one embodiment of this application, an LDMOS device is also disclosed, comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described above.

[0047] To achieve high breakdown voltage, traditional LDMOS devices require longer drift regions and lower drift region doping concentrations. This inevitably leads to a persistently high overall on-resistance, severely limiting the performance of silicon materials. Please refer to [reference needed]. Figure 5 , Figure 6 and Figure 7 These figures represent schematic diagrams of the LDMOS doping profile, current density distribution with only the main gate, and current density distribution with both the main and sub-gates in one embodiment of this application. In this embodiment, an innovative dual-gate structure breaks the aforementioned balance constraint. On one hand, the main gate, in conjunction with the insulating layer, optimizes the surface electric field distribution, suppressing premature avalanche breakdown and thus ensuring and improving the device's breakdown voltage. On the other hand, the introduction of a deep trench sub-gate generates a field modulation effect, extending an additional low-impedance conductive path in the drift region, thereby significantly optimizing (reducing) the device's specific on-resistance. These two elements work synergistically to achieve an excellent trade-off between high breakdown voltage and low power consumption. Because LDMOS devices exhibit various geometric and dielectric abrupt changes on their surface (such as...),... Figure 5 As shown, the gate edge, field oxygen / isolation boundary, and curvature changes of the P-well / N-drift junction at the surface, etc., indicate that potential lines tend to accumulate more easily on the surface during the off-state (e.g., Figure 6 and Figure 7 As shown in the figure, the peak value of the surface electric field is significantly higher than that of the bulk electric field, which often causes the device to break down at the surface.

[0048] The LDMOS and LDMOS devices disclosed in this application include a P-type well region, an N-type drift region, a source region fabricated on the P-type well region, a drain region fabricated on the N-type drift region, and a gate region fabricated between the P-type well region and the N-type drift region, all fabricated on a substrate. The gate region includes a main trench gate and a sub-trench gate attached to both sides of the source region. The main trench gate includes a trench-structured main trench region and a main gate oxide region for separate isolation. The sub-trench gate includes a trench-structured sub-trench region and a sub-gate oxide region for separate isolation. Because the added sub-trench gate can generate a significant field modulation effect on the N-type drift region it contacts, it promotes the formation of a high-concentration carrier accumulation layer in the region near the sub-gate within the drift region. This creates a low-impedance conductive channel within the LDMOS device, in addition to the conventional surface conductive path, thereby significantly reducing the bulk resistance of the drift region and significantly reducing the overall on-resistance of the device.

[0049] Furthermore, by extending the gate vertically into the substrate, the trench gate of the LDMOS allows for three-dimensional control of the drift region potential and depletion layer shape in the off state. This transfers equipotential lines from the device surface to the bulk, dispersing local electric field peaks on the surface and optimizing the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin. The trench gate exhibits a stepped distribution, displaying a structure that is wider at the top and narrower at the bottom. The thinner gate oxide in the upper half of the trench facilitates channel formation and reduces the device's on-resistance, while the thicker gate oxide in the lower half facilitates the redistribution of electric field lines at the trench gate corners, increasing the breakdown voltage in that area. Additionally, the thicker gate oxide helps reduce the device's Miller capacitance, improving the cutoff frequency at high frequencies.

[0050] To further reduce the specific on-resistance of the device, this application proposes a dual-gate structure. The second gate provides an additional carrier transport path, allowing the device to receive a larger current in the on-state, thereby reducing the specific on-resistance. Please refer to [reference needed]. Figure 8 This is a schematic diagram comparing the breakdown voltage curves of trench gate LDMOS and planar gate LDMOS in one embodiment. In the 90nm BCD process platform, the specific on-resistance is reduced from 13.15 mΩ·mm² to 12.57 mΩ·mm². 2 .

[0051] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. An LDMOS based on a dual trench gate, characterized in that, It includes a substrate, a P-type well region, an N-type drift region, a gate region, a source region formed on the P-type well region, and a drain region formed on the N-type drift region; The gate region includes a main trench gate and a sub-trench gate; The P-type well region is disposed between the main trench gate and the sub-trench gate; the main trench gate includes a gate main trench region with a trench structure and a main gate oxide region for separately isolating the gate main trench region; the sub-trench gate includes a gate sub-trench region with a trench structure and a sub-gate oxide region for separately isolating the gate sub-trench region. The extension depth of the secondary trench gate into the substrate is greater than the extension depth of the primary trench gate into the substrate; The source region includes a first source region, a second source region, and a body region. The first source region, the body region, and the second source region are sequentially attached between the main trench gate and the sub-trench gate. The body region is used to isolate the first source region and the second source region. The first source region and the second source region have the same doping type, but the doping type of the body region is different. The gate connection terminal of the LDMOS is electrically connected to the main gate trench region and the secondary gate trench region; The source terminal of the LDMOS is electrically connected to the first source region and the second source region; The drain terminal of the LDMOS is electrically connected to the drain region; The N-type drift region extends into the substrate to a greater depth than the main trench gate extends into the substrate. The substrate also contains an N-type buried region; the N-type buried region is disposed between the secondary trench gate and the region where the extension of the N-type drift region toward the substrate exceeds the extension of the main trench gate toward the substrate; A P-type buried region is also formed in the substrate; the P-type buried region is disposed between the N-type buried region and the substrate to isolate the N-type buried region and the substrate; the extended end face of the N-type drift region extending into contact with the substrate is fitted with the P-type buried region.

2. The LDMOS as described in claim 1, characterized in that, The secondary trench gate is attached to the first source region, and the second source region is attached to the main trench gate; the N-type drift region is attached to the main trench gate, and the drain region is located at the distal end of the attachment point between the N-type drift region and the main trench gate; The gate sub-trench region of the sub-trench gate extends into the substrate.

3. The LDMOS as described in claim 1, characterized in that, The gate main trench region includes an upper substrate region and an under substrate region. The under substrate region serves as a trench structure extending from the gate main trench region toward the substrate. The upper substrate region is higher than the upper surfaces of the source region and the N-type drift region. The upper substrate region extends toward the upper surfaces of the source region and the N-type drift region, and the extension portion is isolated from the upper surfaces of the source region and the N-type drift region by the extension portion of the main gate oxide region.

4. The LDMOS as described in claim 3, characterized in that, An oxide isolation layer for insulation is provided on the side of the substrate region above the upper surface of the gate region and the N-type drift region, and the gate connection terminal of the LDMOS is electrically connected to the upper surface of the substrate region.

5. The LDMOS as described in claim 4, characterized in that, The trench structure of the gate main trench region and / or the gate sub trench region is a stepped trench with the width decreasing from top to bottom, an inverted trapezoidal trench that is wider at the top and narrower at the bottom, or a square trench.

6. The LDMOS as described in claim 5, characterized in that, The gate sub-trench region and the gate main trench region are made of polycrystalline silicon; The main gate oxide region and the secondary gate oxide region are made of silicon dioxide; the N-type buried region and the P-type buried region are highly doped regions.

7. The LDMOS as described in claim 1, characterized in that, The substrate of LDMOS is a P-type substrate.

8. An LDMOS device, characterized in that, It includes multiple MOS units, wherein at least one MOS unit is an LDMOS as described in any one of claims 1 to 7.

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