A semiconductor device and a manufacturing method

Abstract

Embodiments of the present disclosure relate to semiconductor devices and manufacturing methods. A manufacturing method of a semiconductor device includes: forming a buried layer of a second doping type on a substrate of a first doping type; forming an epitaxial layer of the first doping type on the buried layer; forming a first trench extending from a surface of the epitaxial layer into the buried layer; forming a base layer on at least a sidewall of the first trench, the base layer being a doped polysilicon layer and the doping type of the base layer being the same as that of the buried layer; oxidizing the base layer to form an oxide layer, while dopants in the base layer diffuse into the epitaxial layer adjacent to the sidewall of the first trench to form a doped layer in the epitaxial layer in contact with the buried layer, the doped layer serving as a second conductive channel; continuing etching the first trench to deepen the first trench; and forming a first conductive channel in the first trench.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Hybrid integration processes, which integrate different types of transistors on the same semiconductor substrate or semiconductor layer, are widely used in integrated circuits. For example, integrated circuits using hybrid integration processes include: complementary metal-oxide (CMOS) integrated circuits composed of N-type MOS transistors and P-type MOS transistors; power integrated circuits composed of high-voltage transistors and low-voltage transistors; and hybrid integrated circuits composed of analog circuits and digital circuits.

[0003] In CMOS integrated circuits, complementary N-type and P-type MOS transistors are used to implement various analog circuit functions, such as amplifiers, filters, and oscillators. They can also be used to implement basic logic gates, thereby enabling various complex digital circuit functions. Because different types of transistors are used in CMOS integrated circuits, isolation structures are needed to define the active region of each transistor, ensuring that adjacent transistors are isolated and operate independently without current leakage. Furthermore, buried layers may be formed beneath the well regions in the semiconductor layer to improve the source-substrate breakdown voltage characteristics of the semiconductor device. With a well-designed isolation structure, CMOS integrated circuits offer advantages such as low power consumption, high precision, high speed, and low noise.

[0004] In the peripheral region of a semiconductor device, a first conductive channel leading out the epitaxial layer and a second conductive channel leading out the buried layer are usually provided. The first conductive channel is formed in a first trench and the second conductive channel is formed in a second trench. However, due to the difference in depth between the first trench and the second trench, the first trench and the second trench usually need to be formed through different steps, resulting in complex process steps and high manufacturing costs. Summary of the Invention

[0005] The purpose of this disclosure is to provide a deep trench isolation structure, a semiconductor device, and a method for manufacturing the isolation structure therein, which can effectively solve the problems in the prior art.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a buried layer of a second doping type on a substrate of a first doping type; forming an epitaxial layer of a first doping type on the buried layer; forming a first trench extending from the surface of the epitaxial layer into the buried layer; forming a base layer at least on the sidewalls of the first trench, the base layer being a doped polysilicon layer, and the doping type of the base layer being the same as the doping type of the buried layer; oxidizing the base layer to form an oxide layer, while a dopant in the base layer diffuses into the epitaxial layer adjacent to the sidewalls of the first trench, forming a doped layer in the epitaxial layer that contacts the buried layer, the doped layer serving as a second conductive channel; continuing to etch the first trench to deepen the depth of the first trench; and forming a first conductive channel in the first trench.

[0007] Optionally, the step of oxidizing the substrate layer includes dry oxidation, annealing, and wet oxidation.

[0008] Optionally, annealing is performed in a nitrogen atmosphere at a temperature of 900℃ to 1200℃ for a time of 0.5 hours to 1 hour.

[0009] Optionally, the temperature for wet oxidation is 925℃~1050℃.

[0010] Optionally, the junction depth of the doped layer forming the second conductive channel is 2 μm to 3 μm.

[0011] Optionally, the formed substrate layer is located on the sidewall of the first trench, and the diffused doped layer is adjacent to the sidewall of the first trench.

[0012] Optionally, the method of forming the substrate layer includes: forming a substrate layer covering the sidewalls of the first trench, the bottom of the first trench, and the surface of the epitaxial layer; etching back the substrate layer to remove the substrate layer covering the bottom of the first trench and the surface of the epitaxial layer, while retaining the substrate layer covering the sidewalls of the first trench.

[0013] Optionally, the formed base layer covers the sidewall of the first trench, the bottom of the first trench, and the surface of the epitaxial layer, and the diffused doped layer is adjacent to the sidewall of the first trench and the bottom of the first trench.

[0014] Optionally, as the first trench is further etched and deepened, the doped layer adjacent to the bottom of the first trench is removed.

[0015] Optionally, the method of forming the first conductive channel includes: forming an insulating pad in the first trench and forming an opening at the bottom of the insulating pad in the first trench; and filling the first trench with a conductive material, wherein the conductive material filled in the first trench contacts the substrate through the bottom opening of the insulating pad to form the first conductive channel.

[0016] Optionally, it further includes forming a shallow trench isolation, the shallow trench isolation being located on top of the first conductive channel and exposing the conductive core of the first conductive channel, the shallow trench isolation being used to isolate the conductive core of the first conductive channel from the second conductive channel.

[0017] Optionally, it further includes: forming a well region at the top of the second conductive channel; and forming a contact region in the well region.

[0018] Optionally, it further includes: forming an interlayer dielectric layer that covers the epitaxial layer and the first conductive channel and the second conductive channel; forming a first contact hole that penetrates the interlayer dielectric layer to reach the conductive core of the first conductive channel and a second contact hole that penetrates the interlayer dielectric layer to reach the contact area; and filling the first contact hole and the second contact hole to form a first conductive path and a second conductive path.

[0019] Optionally, a third trench is formed simultaneously with the formation of the first trench, the third trench extending from the surface of the epitaxial layer inward therefrom, and the bottom of the third trench being a certain distance from the buried layer; a base layer is formed on the sidewall of the first trench and on the sidewall of the third trench; while the base layer is oxidized, the dopant in the base layer diffuses into the epitaxial layer adjacent to the sidewalls of the first trench and the third trench, and a doped layer in the epitaxial layer that contacts the buried layer is formed. While a first conductive channel is formed in the first trench, a deep trench isolation is formed in the third trench.

[0020] Optionally, during the formation of the first trench and the third trench, the opening width of the first trench is greater than the opening width of the third trench.

[0021] Optionally, the opening size of the first trench is 1.8 micrometers to 2.2 micrometers, and the depth of the first trench is less than 18 micrometers; the opening size of the third trench is 0.9 micrometers to 1.3 micrometers, and the depth of the third trench is 12.5 micrometers to 13.5 micrometers.

[0022] Optionally, the spacing between the first trench and the third trench is 0.5 micrometers to 4 micrometers.

[0023] Optionally, the method of forming the first conductive channel and the deep trench isolation includes: forming an insulating pad in the first trench and the third trench; forming an opening at the bottom of the insulating pad in the first trench; and filling the first trench and the third trench with a conductive material, wherein the conductive material filled in the first trench contacts the substrate through the bottom opening of the insulating pad to form the first conductive channel, and the conductive material filled in the third trench forms the deep trench isolation.

[0024] Optionally, anisotropic etching is used to etch the exposed portions of the insulating pads in the first and third trenches along a direction perpendicular to the substrate surface; wherein, the first trench has a larger opening size than the third trench, the insulating pad at the bottom of the first trench is removed to form an opening, while the insulating pad at the bottom of the third trench is still retained.

[0025] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; an epitaxial layer located on the substrate; a buried layer located between the substrate and the epitaxial layer; a first conductive channel extending from the surface of the epitaxial layer into the substrate; and a second conductive channel extending from the surface of the epitaxial layer into the buried layer; wherein the first conductive channel is disposed in a first trench, the second conductive channel is a doped layer adjacent to the first trench, and the doping type of the second conductive channel is the same as the doping type of the buried layer.

[0026] Optionally, the first conductive channel includes a conductive core and an insulating pad surrounding the conductive core, the bottom of the substrate pad of the first conductive channel has an opening, and the conductive core of the first conductive channel contacts the substrate through the opening of the insulating pad.

[0027] Optionally, it further includes shallow trench isolation, which is located on top of the first conductive channel and exposes the conductive core of the first conductive channel, the shallow trench isolation being used to isolate the conductive core of the first conductive channel from the second conductive channel.

[0028] Optionally, it further includes deep trench isolation extending from the surface of the epitaxial layer into the substrate; the deep trench isolation is located in a third trench.

[0029] Optionally, the deep trench isolation includes a core and an insulating pad surrounding the core.

[0030] According to the semiconductor device of the present disclosure, the second conductive channel is a doped layer adjacent to the first trench and / or the third trench, thereby omitting the trench used to form the second conductive channel in the prior art, saving device size in terms of device structure, and omitting the etching process of a trench in terms of process, making the process simpler and easier to implement.

[0031] In this embodiment, the opening widths of the first trench of the first conductive channel and the third trench isolated by the deep trench are different. By controlling the opening sizes of the first trench and the third trench, different etching depths can be achieved in the same etching step. That is, the first conductive channel and the trench isolated by the deep trench can be formed simultaneously using a shared etching step. In this embodiment, the trench for forming the second conductive channel is omitted. During the formation of the first trench and the third trench via the same etching step, the predetermined depth of the first trench and the third trench can be controlled more precisely.

[0032] In this embodiment, a deep trench isolation is formed simultaneously with the formation of the first conductive channel, and the filling process of the first conductive channel is exactly the same as the filling process of the deep trench isolation. This avoids the need for multiple filling steps to form the first conductive channel and the deep trench isolation in the prior art, and further avoids the need for multiple fillings and removal of filler residue or over-etching due to differences in filler materials.

[0033] In this embodiment, the first trench and the third trench are formed through two etching steps. During the process of deepening the first trench and the third trench, the doped layer adjacent to the bottom of the first trench and the bottom of the third trench is removed to prevent the formation of excess doped layer. Attached Figure Description

[0034] The above and other objects, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated in the drawings by way of example and not limitation, in which: Figure 1a A schematic cross-sectional view of a semiconductor device according to an embodiment of the prior art is shown; Figure 1b A schematic cross-sectional view of a semiconductor device according to another embodiment of the prior art is shown; Figure 2 A schematic cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure is shown; Figure 3 A cross-sectional schematic diagram of the second embodiment of this application is shown; Figures 4a to 4m Schematic cross-sectional views are shown at different stages of a method for manufacturing an isolation structure of a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0035] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0036] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0037] Furthermore, the terms “top,” “bottom,” “above,” “below,” “over,” “under,” etc., used herein are for descriptive purposes and are not necessarily used to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of this disclosure are operable in directions other than those described or illustrated herein.

[0038] Furthermore, the terms "shallow trench," "medium trench," and "deep trench," as used herein, are for descriptive purposes and not necessarily to define the absolute value of trench depth. When describing "shallow trench," "medium trench," and "deep trench" within the same semiconductor device, they are used only to indicate the relative depth relationship between multiple trenches, and not necessarily to describe the relative depth relationship between multiple trenches and other device structures within the semiconductor device. For example, when describing a "deep trench" in a semiconductor device, the trench may extend below the well region of the semiconductor device, or further into the buried layer of the semiconductor device, or even further below the buried layer of the semiconductor device.

[0039] Embodiments of this disclosure generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to semiconductor devices or CMOS integrated circuits in which complementary N-type MOS transistors and P-type MOS transistors are integrated on the same substrate. CMOS integrated circuits can be used for analog integrated circuits such as amplifiers, or digital integrated circuits such as logic circuits. Embodiments in this disclosure form multiple trench structures of different depths while sharing existing trench process steps, effectively isolating different device cells in the same integrated circuit from each other together with buried layers (e.g., N+ buried layers (NBLs)).

[0040] In the field of semiconductor manufacturing technology, deep trench isolation (DTI) structures are widely used in integrated circuits to achieve effective electrical isolation between different devices, especially in power devices that require high breakdown voltage.

[0041] Figure 1a A schematic cross-sectional view of a semiconductor device according to an embodiment of the prior art is shown. Figure 1a As shown, the semiconductor device 100 includes a substrate 101, an epitaxial layer 102 disposed on the substrate 101, and a buried layer 103 disposed between the substrate 101 and the epitaxial layer 102. The substrate 101 and the epitaxial layer 102 each have a first doping type, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type.

[0042] Semiconductor device 100 includes multiple device regions. For illustrative purposes, the semiconductor device 100 shown in FIG. 1 includes a core region 110 and a peripheral region 120. In the core region 110, a first transistor 111 and a second transistor 112 are respectively disposed in the epitaxial layer 102. In the peripheral region 120, a first conductive via 10 and a second conductive via 20 are disposed. The first conductive via 10 extends from the surface of the epitaxial layer 102 to below the buried layer 103, reaching the interior of the substrate 101, and provides an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102. The second conductive via 20 extends from the surface of the epitaxial layer 102 to the interior of the buried layer 103, and provides an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102.

[0043] The first conductive channel 10 is formed in the first trench, and the second conductive channel 20 is formed in the second trench. The first trench has a first depth D1, and the second trench has a second depth D2. The first trench and the second trench have different depths, and the depth of the first trench is greater than the depth of the second trench.

[0044] Figure 1b A schematic cross-sectional view of a semiconductor device according to another embodiment of the prior art is shown, such as... Figure 1b As shown, with Figure 1a Unlike the illustrated embodiment, in this embodiment, a deep trench isolation 30 is also provided in the peripheral region 120 surrounding the core region 110. To isolate the first conductive channel 10 and the second conductive channel 20 from each other, the deep trench isolation 30 is disposed between the first conductive channel 10 and the second conductive channel 20. The deep trench isolation 30 extends from the surface of the epitaxial layer 102 to below the buried layer 103, reaching the interior of the substrate 101.

[0045] The first conductive channel 10 is formed in the first trench, the second conductive channel 20 is formed in the second trench, and the deep trench isolation 30 is formed in the third trench. The first trench has a first depth D1, the second trench has a second depth D2, and the third trench has a third depth D3. The first trench, the second trench, and the third trench have different depths.

[0046] Typically, a mask process is needed to form the first trench, and another mask is used to form the second and third trenches, resulting in complex process steps and high manufacturing costs. To reduce the number of mask layers and process costs, the industry has proposed using a single mask scheme to simultaneously form the first, second, and third trenches. However, when etching three trenches of different depths under the same mask, the etching depth of the second trench is difficult to control precisely. In actual processes, the depths of the first and third trenches are relatively easy to achieve the target values, while the depth of the second trench fluctuates significantly more than expected. This inconsistency in etching depth directly affects the uniformity of the electrical performance of the isolation structure and product yield.

[0047] Furthermore, since the depths of the first, second, and third trenches differ, and the filling materials in the first, second, and third trenches are different, it is usually necessary to fill the second trench with the smallest depth first. When filling the second trench, unwanted filling materials are inevitably introduced into the first and third trenches. Since the structure of the first and third trenches themselves has a large depth-to-width ratio, it is extremely difficult to completely remove the filling material inside such deep and narrow trenches. The process controllability is poor, which can easily lead to residues or over-etching, affecting the reliability of the device.

[0048] Figure 2 A schematic cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure is shown.

[0049] In this disclosure, the semiconductor device 100 can be any combination of different types of active devices. For example, in a CMOS integrated circuit, it is a combination of N-type MOS transistors and P-type MOS transistors, and in a power integrated circuit, it is a combination of high-voltage transistors and low-voltage transistors. High-voltage transistors are, for example, laterally diffused metal-oxide-semiconductor (LDMOS) transistors, and low-voltage transistors are, for example, conventional planar MOS transistors. The disclosure will be described in detail below using only CMOS integrated circuits as an example.

[0050] Semiconductor device 100 includes a substrate 101, an epitaxial layer 102, and a buried layer 103. The epitaxial layer 102 is, for example, a semiconductor layer disposed above the substrate 101. The buried layer 103 is, for example, a semiconductor layer disposed between the substrate 101 and the epitaxial layer 102.

[0051] Substrate 101 and epitaxial layer 102 each have a first doping type, and buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or combinations thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. In one embodiment, buried layer 103 may have a blanket structure having a substantially the same horizontal extension as substrate 101, laid flat on substrate 101. In another embodiment, buried layer 103 may have a patterned structure. The embodiments disclosed herein are not strictly limited in this respect.

[0052] Semiconductor device 100 includes multiple device regions. For illustrative purposes, in Figure 2 The semiconductor device 100 shown includes a core region 110 and a peripheral region 120.

[0053] In the core region 110 of the semiconductor device 100, a well region 104 of a first transistor 111 and a well region 105 of a second transistor 112 are disposed, which are respectively doped regions in the epitaxial layer 102. The well region 104 of the first transistor 111 has a first doping type, and a source region 106 and a drain region 107 of a second doping type are disposed in the well region 104. A gate stack is disposed above the well region 104, and the gate stack includes a gate dielectric 108 and a gate conductor 109 stacked sequentially, wherein the gate dielectric 108 is sandwiched between the gate conductor 109 and the epitaxial layer 102. For example, the gate dielectric 108 is composed of silicon oxide, and the gate conductor 109 is composed of doped polysilicon. For an N-type MOS transistor, the well region 104 of the first transistor 111 is doped with P-type, and the source region 106 and the drain region 107 are doped with N-type. For a P-type MOS transistor, the well region 104 of the first transistor 111 is doped with N-type, while the source region 106 and drain region 107 are doped with P-type. The well region 104 of the first transistor 111 serves as the body region of the transistor. When a gate voltage is applied to the gate conductor 109, a channel is formed in the well region 104 of the first transistor 111 to control the conductive path between the source region 106 and the drain region 107, thereby controlling the conduction state of the first transistor 111.

[0054] The first transistor 111 and the second transistor 112 are complementary N-type MOS transistors and P-type MOS transistors, respectively. The well region 105 of the second transistor 112 has a second doping type, and a source region and a drain region of the first doping type are disposed in the well region 105, with a gate stack disposed above the well region. Since the device structure of the second transistor 112 is similar to that of the first transistor 111, the internal structure of the second transistor 112 will not be described in detail.

[0055] Furthermore, a shallow trench isolation 121 is provided in the core region 110 to separate the first transistor 111 and the second transistor 112. In order to isolate the first transistor 111 and the second transistor 112 from each other, the shallow trench isolation 121 extends from the surface of the epitaxial layer 102 to a predetermined depth.

[0056] A first conductive via 10 and a second conductive via 20 are provided in the peripheral region 120 of the semiconductor device 100. The first conductive via 10 extends from the surface of the epitaxial layer 102 to below the buried layer 103 and into the interior of the substrate 101, reaching a depth D1, and provides an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102. The second conductive via 20 extends from the surface of the epitaxial layer 102 to the interior of the buried layer 103, reaching a depth D2, and provides an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. Depth D1 is greater than depth D2.

[0057] A first conductive channel 10 is disposed in a first trench for electrically connecting the substrate 101 to the surface of the epitaxial layer 102. In one embodiment, the first conductive channel 10 includes an insulating pad 11 and a conductive core 12. The insulating pad 11 is composed of an oxide, such as silicon oxide, and the conductive core 12 is composed of a conductive material, such as doped polysilicon. Other types of insulating pads 11 and conductive cores 12 are also feasible. The insulating pad 11 is formed on a portion of the sidewalls and bottom of the trench and includes an opening formed at the bottom of the trench. The conductive core 12 fills the trench and the opening, i.e., extends from the surface of the epitaxial layer 102 to the bottom of the trench and contacts the substrate 101. The insulating pad 11 of the first conductive channel 10 isolates the conductive core 12 from the epitaxial layer 102 and the buried layer 103.

[0058] In this embodiment, the conductive core 12 of the first conductive channel 10 is composed of doped polysilicon. The conductive core 12 of the first conductive channel 10 has the same doping type and a higher doping concentration as the substrate 101 it contacts, thus forming a low-resistance path for the substrate 101. In other embodiments, it is also feasible to use other types of conductive cores for the first conductive channel 10, as long as the semiconductor layer it contacts can be electrically connected to the surface of the epitaxial layer 102.

[0059] The insulating pad 11 of the first conductive channel 10 is a stack of multiple insulating layers. The outermost insulating layer is located on the trench sidewall, and at least one intermediate insulating layer is located between the outermost insulating layer and the conductive core 12. The multiple insulating layers in the insulating pad 11 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In one embodiment, at the upper part of the first conductive channel 10, the insulating pad 11 includes, from the outside to the inside, a first insulating layer 1601, an oxide layer S11a, and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall and constitutes the outermost insulating layer; the oxide layer S11a and the second insulating layer 1602 constitute the intermediate insulating layer. The oxide layer S11a is located between the first insulating layer 1601 and the second insulating layer 1602, and the second insulating layer 1602 is located between the oxide layer S11a and the conductive core 12. At the lower part of the first conductive channel 10, the insulating pad 11 includes a first insulating layer 1601 and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall and forms the outermost insulating layer; the second insulating layer 1602 is located between the first insulating layer 1601 and the conductive core 12 and forms an intermediate insulating layer. The outermost insulating layer and the intermediate insulating layer (including the oxide layer S11a and the second insulating layer 1602) are, for example, oxide layers. The outermost insulating layer in the insulating pad 11 can repair the damage to the trench sidewall caused when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer thereon. The intermediate insulating layer covers the surface of the existing insulating layer in the trench to enhance the isolation performance between the conductive core 12 and the epitaxial layer 102 and the buried layer 103. The bottom of the insulating pad 11 has an opening, and the conductive core 12 fills the internal space of the trench and the bottom opening of the insulating pad 11.

[0060] In other embodiments, the insulating pads 11 at the upper and lower parts of the first conductive channel 10 have the same structure, both including a first insulating layer 1601 and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall, and the second insulating layer 1602 is located between the first insulating layer 1601 and the conductive core 12. This embodiment does not limit this.

[0061] In this arrangement, the first conductive channel 10 extends through the epitaxial layer 102 and the buried layer 103, with the conductive core 12 connecting the substrate 101 to the surface of the epitaxial layer 102. Therefore, in the operating state of the semiconductor device 100, the substrate 101 can be biased to any desired potential via the first conductive channel 10. This allows the substrate 101 to be connected to any desired potential, thereby suppressing noise and interference, and also avoids latch-up problems. In this embodiment, the substrate 101 is grounded via the first conductive channel 10 to achieve the desired interference immunity.

[0062] The second conductive channel 20 is disposed in the epitaxial layer 102 and adjacent to the first trench. The second conductive channel 20 is used to electrically connect the buried layer 103 to the surface of the epitaxial layer 102. In this embodiment, the second conductive channel 20 is a doped layer formed in the epitaxial layer 102, and the doping type of the doped layer forming the second conductive channel 20 is the same as the doping type of the buried layer 103. The doped layer penetrates the epitaxial layer 102 and extends into the interior of the buried layer 103.

[0063] The top of the second conductive channel 20 is also provided with a well region 201 and a contact region 22 disposed in the well region 21. The doping type of the well region 21 and the contact region 22 is the same as that of the second conductive channel 20, thereby realizing the conductive connection of the second conductive channel 20.

[0064] In this arrangement, the second conductive channel 20 penetrates the epitaxial layer 102, connecting the buried layer 103 to the surface of the epitaxial layer 102. Therefore, during the operation of the semiconductor device 100, the buried layer 103 is biased to any desired potential via the second conductive channel 20. This allows for the improvement of the source-substrate breakdown voltage characteristics of the semiconductor device using the bias voltage of the buried layer 103, and also suppresses crosstalk between adjacent semiconductor devices using the shielding effect of the buried layer 103. In this embodiment, the power supply voltage VDD is applied to the buried layer 103 via the second conductive channel 20 to obtain the desired bias voltage and shielding effect.

[0065] In the peripheral area 120, a shallow trench isolation structure 122 is also provided. The shallow trench isolation structure 122 is located on top of the first conductive channel 10 and exposes the conductive core 12 of the first conductive channel 10. The shallow trench isolation structure 122 extends from the surface of the insulating pad 11 of the first conductive channel 10 toward its interior, and is located around the conductive core 12 to isolate the core 12 of the first conductive channel 10 and the second conductive channel 20.

[0066] Figure 3 A cross-sectional schematic diagram of the second embodiment of this application is shown, as follows: Figure 3 As shown, a deep trench isolation 30 is also provided in the peripheral region 120, surrounding the core region 110. The deep trench isolation 30 is disposed on the side of the first conductive channel 10 near the core region 110. The deep trench isolation 30 extends from the surface of the epitaxial layer 102 to below the buried layer 103, reaching the interior of the substrate 101. The opening width and depth of the first conductive channel 10 are both greater than those of the deep trench isolation 30.

[0067] A deep trench isolation 30 is disposed in a third trench. The deep trench isolation 30 includes an insulating pad 31 and a core 32. The insulating pad 31 is composed of an oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating pads 31 are also feasible. The core 32 is composed of doped polysilicon. In this embodiment, the conductive core 12 of the first conductive channel 10 has the same doping type as the core 32 of the deep trench isolation 30.

[0068] The insulating pad 31 of the deep trench isolation 30 is a stack of multiple insulating layers. The outermost insulating layer is located on the trench sidewall, and at least one intermediate insulating layer is located between the outermost insulating layer and the core 32. The multiple insulating layers in the insulating pad 31 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In one embodiment, at the upper part of the deep trench isolation 30, the insulating pad 31 includes, from the outside to the inside, a first insulating layer 1601, an oxide layer S11a, and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall and constitutes the outermost insulating layer; the oxide layer S11a and the second insulating layer 1602 constitute the intermediate insulating layer. The oxide layer S11a is located between the first insulating layer 1601 and the second insulating layer 1602, and the second insulating layer 1602 is located between the oxide layer S11a and the core 32. In the lower part of the deep trench isolation 30, the insulating pad 31 includes a first insulating layer 1601 and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall and forms the outermost insulating layer; the second insulating layer 1602 is located between the first insulating layer 1601 and the core 32 and forms an intermediate insulating layer. The outermost insulating layer and the intermediate insulating layer (including the oxide layer S11a and the second insulating layer 1602) are, for example, oxide layers. The outermost insulating layer in the insulating pad 31 can repair the damage to the trench sidewall caused when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer thereon. The intermediate insulating layer covers the surface of the existing insulating layer in the trench to enhance the isolation performance between the core 32 and the epitaxial layer 102 and the buried layer 103. The core 32 fills the internal space of the trench and is isolated from the epitaxial layer 102 and the buried layer 103 via the insulating pad 31.

[0069] In other embodiments, the insulating pads 31 at the upper and lower parts of the deep trench separator 30 have the same structure, both including a first insulating layer 1601 and a second insulating layer 1602. The first insulating layer 1601 is located on the trench sidewall, and the second insulating layer 1602 is located between the first insulating layer 1601 and the core 32. This embodiment does not limit this.

[0070] In the etching steps used to form the first and third trenches described above, if the opening widths of the multiple trenches are different, the etching depths reached by the multiple trenches will differ even after the same etching time. The larger the opening width of the trench, the greater the etching depth of the trench. Conversely, the smaller the opening width of the trench, the smaller the etching depth of the trench.

[0071] In this embodiment, the opening widths of the first trench of the first conductive channel 10 and the third trench of the deep trench isolation 30 are different. By controlling the opening sizes of the first and third trenches, different etching depths can be achieved in the same etching step. That is, the trenches of the first conductive channel 10 and the deep trench isolation 30 can be formed simultaneously using a shared etching step. Relative to Figure 1b In the embodiment shown, the second trench is omitted. During the process of forming the first trench and the third trench through the same etching step, the first trench and the third trench can be more precisely controlled to reach the predetermined depth.

[0072] In the peripheral region 120 of the semiconductor device 100, the deep trench isolation 30 is an insulating isolation ring formed inside the first conductive channel 10 (the side of the first conductive channel 10 near the core region 110). The depth of the insulating isolation ring is greater than the depth of the shallow trench isolation 122 and at least greater than the depth of the second conductive channel 20, thus improving its isolation performance.

[0073] In this embodiment, both the core 32 of the deep trench isolation 30 and the conductive core 12 of the first conductive channel 10 are made of doped polycrystalline silicon, and the shallow trench isolation 122 also covers the core 32 of the deep trench isolation 30.

[0074] In this embodiment, doped regions extending from the surface of the epitaxial layer 102 to the interior of the buried layer 103 are formed around both the first trench and the third trench, and one of them is selected to form the second conductive channel 20.

[0075] Furthermore, it should be understood that although the isolation structure described above is used to isolate CMOS N-type MOS transistors and P-type MOS transistors in integrated circuits. However, it should be understood that the above isolation structure can also be used to isolate device regions of other types of integrated circuits, and the embodiments of this disclosure are not strictly limited in this regard.

[0076] Figures 4a to 4m Schematic cross-sectional views are shown at different stages of a method for manufacturing an isolation structure of a semiconductor device according to embodiments of the present disclosure. Figures 4a to 4m The manufacturing method shown can be used to manufacture the drawing. Figure 3 The semiconductor device 100 shown is illustrated above. Figure 3 The description of semiconductor device 100 may be incorporated herein.

[0077] like Figure 4a As shown, a buried layer 103 is formed in a substrate 101, and an epitaxial layer 102 is formed on the buried layer 103. The substrate 101 and the epitaxial layer 102 each have a first doping type, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type.

[0078] In this step, a pad oxide layer is formed on the surface of substrate 101, which blankets the surface of substrate 101. The thickness of the pad oxide layer is typically 100 angstroms to 200 angstroms. In one embodiment, the thickness of the pad oxide layer is, for example, 200 angstroms.

[0079] Next, an ion implantation process is used to implant a second type of dopant into the substrate 101. By selecting a high dose of dopant, a portion of the substrate 101 is inverted to form a second type of doped region, thereby forming a second type of buried layer 103 in the substrate 101. In one embodiment, by selecting the ion implantation energy, the buried layer 103 extends downward from the surface of the substrate 101 by a predetermined distance.

[0080] Next, a wet process is used, for example, to remove the pad oxide layer. In one embodiment, a DHF (Dilute Hydrofluoric Acid) solution is used, for example, to selectively remove the pad oxide layer.

[0081] Next, an annealing process is performed to extend the buried layer 103 downwards to a predetermined depth. It is worth noting that an oxide layer forms on the surface of the buried layer 103 during annealing. Therefore, after the annealing step, a wet process is used to remove the oxide layer on the surface of the buried layer 103. In this step, for example, a combination of BOE (Buffered Oxide Etch) solution and DHF (Dilute Hydrofluoric Acid) solution is used to remove the oxide layer on the surface of the buried layer 103.

[0082] Next, an epitaxial layer 102 is formed on the surface of each layer 103. In one embodiment, the thickness of the epitaxial layer 102 is, for example, 13 micrometers.

[0083] In one embodiment, the buried layer 103 may have a blanket structure having a horizontal extension substantially the same as that of the substrate 101, laid flat on the substrate 101. In another embodiment, the buried layer 103 may have a patterned structure. The embodiments disclosed herein are not strictly limited in this regard. The epitaxial layer 102 may be used to form different device regions.

[0084] like Figure 4bAs shown, a hard mask layer HM is formed on the surface of the epitaxial layer 102.

[0085] In this step, for example, a deposition process is used to form a first hard mask layer HM11, a second hard mask layer HM12, and a third hard mask layer HM13 sequentially on the surface of the epitaxial layer 102. In one embodiment, the first hard mask layer HM11 is, for example, an oxide layer with a thickness of, for example, 200 angstroms; the second hard mask layer HM12 is, for example, a nitride layer with a thickness of 2100 angstroms; and the third hard mask layer HM13 is, for example, an oxide layer with a thickness of 2500 angstroms. It is worth noting that the number of hard mask layers HM, their material, and their thickness depend on the selectivity of the trench etching, and this embodiment does not impose any limitations on these aspects.

[0086] like Figure 4c As shown, the first trench TR1 and the third trench TR3 are formed.

[0087] In this step, a trench etching process is used to form a first trench TR1 and a third trench TR3. The first trench TR1 extends downward from the surface of the epitaxial layer 102, passing through the epitaxial layer 102 and the buried layer 103 and then into the interior of the substrate 101. The third trench TR3 extends downward from the surface of the epitaxial layer 102, and there is a certain gap between the bottom of the third trench TR3 and the top of the buried layer 103.

[0088] The aforementioned trench etching process includes forming openings in the hard mask HM using a patterning step, and etching the epitaxial layer 102, buried layer 103, and substrate 101 through the openings in the hard mask HM. In one embodiment, patterning the hard mask HM includes: forming a resist mask PR on the hard mask HM, performing a first patterning of the resist mask PR using photolithography, etching away exposed portions of the hard mask HM through the patterned resist mask PR to perform a second patterning, and then removing the resist mask PR by solvent dissolution or ashing. In other embodiments, the patterning of the hard mask HM may employ other processes, and the embodiments disclosed herein are not strictly limited in this regard.

[0089] Next, anisotropic etching, such as plasma etching, is used to etch the epitaxial layer 102, the buried layer 103, and the substrate 101 along the direction perpendicular to the substrate surface. The pattern of the hard mask HM is transferred to the epitaxial layer 102, the buried layer 103, and the substrate 101 by etching the epitaxial layer 102, the buried layer 103, and the substrate 101 via a patterned hard mask HM.

[0090] In one embodiment, the opening width of the first trench TR1 is greater than the opening width of the third trench TR3. In the same etching step, the etching depth reached by the first trench TR1 is also greater than the etching depth reached by the third trench TR3. Therefore, a common trench etching process is used to simultaneously form the first trench TR1 and the third trench TR3. In one embodiment, the opening size CD1 of the first trench TR1 is 1.8 μm to 2.2 μm, preferably 2.0 μm, and the depth Depth 11 of the first trench TR1 is less than 18 μm. The opening size CD3 of the third trench TR3 is 0.9 μm to 1.3 μm, preferably 1.1 μm, and the depth Depth 31 of the third trench TR3 is 12.5 μm to 13.5 μm.

[0091] Furthermore, the spacing (Space) between the first trench TR1 and the third trench TR3 is 0.5 micrometers to 4 micrometers. It is worth noting that for low-voltage devices, the spacing between the first trench TR1 and the third trench TR3 can be set to a smaller value, such as 1 micrometer; for high-voltage devices, the spacing between the first trench TR1 and the third trench TR3 is correspondingly increased, for example, set to 3 micrometers.

[0092] like Figure 4d As shown, a base layer S11 is formed.

[0093] In this step, a substrate layer S11 is formed, for example, using a deposition process. The substrate layer S11 conformally covers the surface of the hard mask layer, the inner walls of the first trench TR1 (including the bottom and sidewalls of the first trench TR1), and the inner walls of the third trench TR3 (including the bottom and sidewalls of the third trench TR3). Simultaneously, the substrate layer S11 also covers the surface of the substrate 101 away from the epitaxial layer 102. The substrate layer S11 is a doped polysilicon layer. It is worth noting that the doping type of the substrate layer S11 is the same as the doping type of the buried layer 103, and the thickness of the substrate layer S11 is 500 Å to 1500 Å. In one embodiment, the dopant in the substrate layer S11 is, for example, phosphorus (P), but is not limited thereto.

[0094] Next, a protective layer S12 is formed, for example, using a deposition process. The protective layer S12 covers the surface of the substrate layer S11 above the hard mask layer HM, the surface of the substrate layer S11 on the inner wall of the first trench TR1, and the surface of the substrate layer S11 on the inner wall of the third trench TR3. In one embodiment, the protective layer S12 is, for example, an oxide layer with a thickness of, for example, 200 angstroms.

[0095] After forming the protective layer S12, the base layer S11 on the surface of the substrate 101 is removed, for example, by a wet etching process. The wet etchant is, for example, a mixed solution of HF and HNO3. During the wet etching process, only the base layer S11 on the surface of the substrate 101 is brought into contact with the wet etching etchant to selectively remove the base layer S11 on the surface of the substrate 101. After wet etching, the base layer S11 on the surface of the hard mask layer HM, the inner wall of the first trench TR1, and the inner wall of the third trench TR3 are retained.

[0096] In one embodiment, before forming the substrate layer S11, an RCA cleaning step is further included to remove impurities such as particles, organic matter, metal ions, and natural oxide layers from the inner walls of the first trench TR1 and the third trench TR3, so as to ensure the cleanliness of the inner walls of the first trench TR1 and the third trench TR3.

[0097] In one embodiment, after forming the substrate layer S11, a back etching step is included to remove the substrate layer S11 on the surface of the hard mask layer HM, the bottom substrate layer S11 of the first trench TR1, and the bottom substrate layer S11 of the third trench TR3. Specifically, the substrate layer S11 is etched using an anisotropic etching process (e.g., plasma etching). The etchant is perpendicular to the surface of the hard mask layer HM, and the etchant etches the substrate layer S11 in a direction perpendicular to the substrate surface. The portion of the substrate layer S11 on the surface of the hard mask layer HM, as well as the portions on the sidewalls and bottom of the trenches (including the first trench TR1 and the third trench TR3), are simultaneously etched. By controlling the etching time, the substrate layer S11 on the surface of the hard mask layer HM and the substrate layer S11 at the bottom of the trenches can be completely removed. At this time, the portion of the substrate layer S11 on the sidewalls of the trenches is also etched back, but the portion on the sidewalls of the trenches is still completely preserved. After the back etching step, a protective layer S12 is formed. Then, the hard mask layer HM sidewalls, epitaxial layer 102 sidewalls, buried layer 103 sidewalls, substrate 101 sidewalls, and substrate layer S11 away from the surface of epitaxial layer 102 are selectively removed.

[0098] like Figure 4e As shown, the substrate S11 is oxidized to form an oxide layer S11a, while the dopant in the substrate S11 diffuses into the epitaxial layer 102 adjacent to the trench sidewall to form an inverted doped layer S11b. The top of the doped layer S11b is flush with the surface of the epitaxial layer 102 away from the buried layer 103, and the bottom is in contact with the buried layer 103, forming a second conductive channel 20 that leads the buried layer 103 to the surface of the epitaxial layer 102.

[0099] The oxidation of the substrate S11 includes a first oxidation step, an annealing step, and a second oxidation step. The first oxidation process employs dry oxygen oxidation, using high-purity dry oxygen to react with silicon to form a high-quality, dense oxide layer (SiO2) on the surface of the substrate S11. In one embodiment, the thickness of the oxide layer formed by the first oxidation is 150 angstroms.

[0100] It is worth noting that oxygen (O2) and silicon (Si) form an oxide layer (SiO2) on the surface of the substrate S11. In subsequent processes, oxygen (O2) and silicon (Si) continue to react at the interface between the substrate S11 and the oxide layer (SiO2) (Si-SiO2 interface) to form another oxide layer (SiO2). The newly formed oxide layer (SiO2) will hinder the continued diffusion of oxygen (O2), and the oxidation rate slows down as the oxide layer (SiO2) increases. Therefore, a second oxidation is required to ensure that the substrate S11 is completely oxidized to form an oxide layer.

[0101] Annealing is carried out in a nitrogen atmosphere at a temperature of 900℃ to 1200℃ (e.g., 1050℃) for 0.5 to 1 hour. During annealing, the dopant in the substrate layer S11 diffuses into the epitaxial layer 102 adjacent to the substrate layer S11, forming an inversion doped layer S11b in the epitaxial layer 102.

[0102] The second oxidation step employs a wet oxidation process, which is faster than a dry oxidation process. The wet oxidation process completely oxidizes the remaining substrate layer S11 to form oxide layer S11a. In one embodiment, the temperature for the second oxidation is, for example, 925°C to 1050°C.

[0103] This embodiment employs a combination of dry oxygen oxidation, high-temperature annealing, and wet oxygen oxidation to form an oxide layer S11a from the entire oxide layer of the substrate S11, while simultaneously diffusing most of the dopant in the substrate S11 into the epitaxial layer 102 to form an inversion doped layer S11b. Since the substrate S11 is formed on the inner walls of both the first trench TR1 and the third trench TR3, the resulting doped layers surround the first trench TR1 and the third trench TR3, respectively, and are adjacent to the bottom and sidewalls of the first trench TR1 and the third trench TR3. The doped layer S11b adjacent to the sidewalls of the first trench TR1 and the third trench TR3 are in contact with the buried layer 103, bringing the buried layer 103 to the surface of the epitaxial layer 102.

[0104] It is worth noting that during the oxidation of the substrate layer S11, due to the obstruction of the protective layer S12, most of the dopant in the substrate layer S11 diffuses into the epitaxial layer 102, but does not diffuse into the air. This prevents dopant loss and also prevents dopant diffused into the air from affecting other devices or parts. After the substrate layer S11 is completely oxidized, the protective layer 12 and the oxide layer S11a formed by the substrate layer S11 together form the final intermediate insulating layer. In one embodiment, the diffusion depth of the dopant in the substrate layer S11 is, for example, 2 μm to 3 μm, that is, the junction depth of the doped layer S11b is, for example, 2 μm to 3 μm.

[0105] like Figure 4f As shown, the first trench TR1 and the third trench TR3 are etched continuously, so that the first trench TR1 reaches a predetermined depth Depth12 and the third trench TR3 reaches a predetermined depth Depth32.

[0106] In this step, a hard mask layer HM is used as the etching mask layer to etch the first trench TR1 and the third trench TR3. First, the oxide layer S11a at the bottom of the first trench TR1 and the oxide layer S11a at the bottom of the third trench TR3 are etched. Next, the epitaxial layer 102 exposed at the bottom of the first trench TR1 and the epitaxial layer 102 exposed at the bottom of the third trench TR3 are etched, so that the first trench TR1 reaches a predetermined depth Depth 12 and the third trench TR3 reaches a predetermined depth Depth 32. In one embodiment, the predetermined depth Depth 12 of the first trench TR1 is 30 μm, and the predetermined depth Depth 32 of the third trench TR3 is 24 μm.

[0107] During the etching process described above, the oxide layer S11a at the bottom of the first trench TR1 is removed, and a portion of the oxide layer S11a on the sidewalls of the first trench TR1 is also removed simultaneously. However, a portion of the oxide layer S11a remains. After the etching process is completed, the upper sidewall of the first trench TR1 is covered with the oxide layer S11a, and the lower sidewall of the first trench TR1 is exposed. Similarly, at least a portion of the oxide layer S11a on the sidewalls of the third trench TR3 is retained. After the etching process is completed, the upper sidewall of the third trench TR3 is covered with the oxide layer S11a, and the lower sidewall of the third trench TR3 is exposed.

[0108] During the etching process described above, a portion of the hard mask layer HM is removed. Optionally, at least a portion of the second hard mask layer HM12 and the first hard mask layer HM11 are retained in the hard mask layer HM.

[0109] During the etching process described above, the doped layer S11b adjacent to the bottom of the first trench TR1 and the doped layer S11b adjacent to the bottom of the third trench TR3 are removed. Therefore, only the doped layer S11b adjacent to the sidewall of the first trench TR1 and the doped layer S11b adjacent to the sidewall of the third trench TR3 are retained.

[0110] Optionally, after completing the above etching process, a step of removing the oxide layer S11a can be added to remove the remaining oxide layer S11a on the sidewall of the first trench TR1 and the remaining oxide layer S11a on the sidewall of the third trench TR3.

[0111] like Figure 4g As shown, a first insulating layer 1061 is formed in the first trench TR1 and the third trench TR3.

[0112] A first insulating layer 1061 covers the bottom and sidewalls of the first trench TR1, and also covers the bottom and sidewalls of the third trench TR3. The first insulating layer 1061 is composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In this embodiment, the first insulating layer 1061 is composed of oxides, for example, formed on the bottom and sidewalls of the first trench TR1 and the third trench TR3 using a thermal oxidation process. The oxides can further repair damage to the trench sidewalls caused during deep etching of the epitaxial layer 102 and the buried layer 103 to form the trenches. In one embodiment, the thickness of the first insulating layer 1061 is, for example, 4000 angstroms.

[0113] It is worth noting that, in the above steps, although the upper sidewall of the first trench TR1 is covered with an oxide layer S11a, a first insulating layer 1061 is also formed thereon. In the upper part of the first trench TR1, the first insulating layer 1061 covers the upper sidewall of the first trench TR1, and the oxide layer S11a covers the first insulating layer 1061. Compared to the lower sidewall of the first trench TR1, which is not covered with the oxide layer S11a, the first insulating layer 1061 on the upper sidewall of the first trench TR1 has a thinner thickness. Similarly, a first insulating layer 1061 is formed on the upper sidewall of the third trench TR3. In the upper part of the third trench TR3, the first insulating layer 1061 covers the upper sidewall of the third trench TR3, and the oxide layer S11a covers the first insulating layer 1061. Compared to the lower sidewall of the third trench TR3, which is not covered with the oxide layer S11a, the first insulating layer 1061 on the upper sidewall of the third trench TR3 has a thinner thickness.

[0114] like Figure 4h As shown, a second insulating layer 1062 is formed in the first trench TR1 and the third trench TR3.

[0115] The second insulating layer 1062 conformally covers the surface of the hard mask layer HM, the surface of the oxide layer S11a and the surface of the first insulating layer 1061 in the first trench TR1, and the surface of the oxide layer S11a and the surface of the first insulating layer 1061 in the third trench TR3. The second insulating layer 1062 is composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In this embodiment, the first insulating layer 1061 is composed of oxides, for example, the second insulating layer 1062 is formed by a deposition process. It is worth noting that during the deposition process, the growth rate of the thin film on a flat surface is usually faster, so that the thickness of the second insulating layer 1062 on the surface of the hard mask layer HM in this embodiment is greater than the thickness of the second insulating layer 1062 at the bottom of the first trench TR1.

[0116] After the second insulating layer 1062 is formed, the first trench TR1 still has a gap of a certain width. In one embodiment, the thickness of the second insulating layer 1062 is, for example, 6000 angstroms, and after the second insulating layer 1062 is formed, the width of the gap in the first trench TR1 is 0.7 μm to 0.9 μm. Similarly, after the second insulating layer 1062 is formed, the third trench TR3 still has a gap of a certain width. In one embodiment, after the second insulating layer 1062 is formed, the width of the gap in the third trench TR3 is less than 0.2 μm.

[0117] In the first trench TR1, the first insulating layer 1061 and the second insulating layer 1062 form an insulating pad 11 for the first conductive channel. When an oxide layer S11a is formed on the upper part of the first trench TR1, the first insulating layer 1061, the oxide layer S11a, and the second insulating layer 1062 form the insulating pad 11 for the first conductive channel. In the third trench TR3, the first insulating layer 1061 and the second insulating layer 1062 form an insulating pad 31 for the deep trench isolation 30. When an oxide layer S11a is formed on the upper part of the third trench TR3, the first insulating layer 1061, the oxide layer S11a, and the second insulating layer 1062 form the insulating pad 31 for the deep trench isolation 30.

[0118] like Figure 4i As shown, an opening is formed at the bottom of the insulating pad 11.

[0119] In this step, anisotropic etching, such as plasma etching, is used to remove the exposed portions of the insulating pad 11 and the insulating substrate 31 along a direction perpendicular to the substrate surface. Since the first trench TR1 and the third trench TR3 have different morphologies, after the etching step is completed, the insulating pad 11 in the first trench TR1 and the insulating substrate 31 in the third trench TR3 will ultimately exhibit different states.

[0120] The first trench TR1 has a large opening size, and the portions of the insulating pad 11 located on the sidewalls and bottom of the first trench TR1 are etched simultaneously. The portion of the insulating pad 11 located on the sidewalls of the first trench TR1 acts as an additional hard mask, used to define the pattern of the portion of the insulating pad 11 located on the bottom of the first trench TR1. By controlling the etching time, the exposed portion of the insulating pad 11 located on the bottom of the first trench TR1 can be completely removed to form an opening. At this time, the portion of the insulating pad 11 located on the sidewalls of the first trench TR1 is also etched back, but the portion located on the sidewalls of the first trench TR1 is still completely preserved.

[0121] Compared to the first trench TR1, the third trench TR3 has a smaller opening size. The portions of the insulating pad 31 located on the sidewalls and bottom of the first trench TR1 are simultaneously etched. However, in the same etching step, the etching rate of the etchant on the insulating pad 31 in the third trench TR3 is less than the etching rate on the insulating pad 11 in the first trench TR1. When the insulating pad 11 at the bottom of the first trench TR1 is removed to form an opening, although a portion of the insulating substrate 31 on the sidewalls and bottom of the third trench TR3 is removed, it still completely covers the sidewalls and bottom of the third trench TR3.

[0122] During the etching process described above, the second insulating layer 1062 on the surface of the hard mask layer HM is also etched. However, due to its relatively thick thickness, when an opening is formed at the bottom of the insulating pad 11, the second insulating layer 1062 on the surface of the hard mask layer HM will lose some thickness, but a certain thickness will still be retained. In one embodiment, the remaining thickness of the second insulating layer 1062 on the surface of the hard mask layer HM is 1400 angstroms.

[0123] like Figure 4j As shown, a conductive layer 1001 is deposited, which fills the internal space of the first trench TR1 and the third trench TR3, as well as the bottom opening of the first trench TR1.

[0124] The conductive layer 1001 contacts the substrate 101 via an opening at the bottom of the first trench TR1. The conductive layer 1001 has the same doping type as the substrate 101 but a higher doping concentration, forming a low-resistance path for the substrate 101 within the first trench TR1. Inside the first trench TR1, the conductive layer 1001 is separated from the epitaxial layer 102 and the buried layer 103 by an insulating pad 11. Inside the second trench TR2, the conductive layer 1001 is separated from the epitaxial layer 102 and the buried layer 103 by an insulating pad 31. Outside the first trench TR1 and the third trench TR3, the conductive layer 1001 covers the surface of the second insulating layer 1062. In one embodiment, the conductive layer 1001 comprises polysilicon having a first doping type. Other types of conductive layers 1001 are also feasible.

[0125] See Figure 4k Remove the conductive layer 1001 located on the surface of the second insulating layer 1062.

[0126] In one embodiment, using the hard mask HM and one or more protective layers in the second insulating layer 1062 as stop layers, chemical mechanical polishing (CMP) is used to remove the portion of the conductive layer 1001 located on the surface of the second insulating layer 1062 to expose the surface of the second insulating layer 1062. In other embodiments, the second insulating layer 1062 is also removed simultaneously, exposing the surface of the hard mask HM. The conductive layer 1001 in the first trench TR1 is retained, forming the core 12 of the first conductive channel 10, and the conductive layer 1001 in the third trench TR3 is retained, forming the core 32 of the deep trench isolation 30.

[0127] See Figure 4l After the aforementioned chemical mechanical planarization, the core 12 of the first conductive channel 10 and the core 32 of the deep trench isolation 30 are etched back using one or more protective layers in the hard mask HM as stop layers to remove at least a portion of the top of the core 12 and at least a portion of the top of the core 32, such that the top surface of the core 12 is lower than the surface of the hard mask HM, while the top surface of the core 32 is lower than the surface of the hard mask HM.

[0128] After the above steps, the top surfaces of core 12 and core 32 are approximately flush with the upper surface of epitaxial layer 102.

[0129] See Figure 4m By removing the hard mask HM, the top of the remaining hard mask HM is made flush with the top of the conductive core 11 of the first trench TR1 and the core 32 of the third trench TR3. The surface of the remaining hard mask HM is the first hard mask layer HM11.

[0130] In the above steps, for example, a wet etching process is used to remove the second hard mask layer HM12 in the hard mask HM. In one embodiment, the second hard mask layer HM12 is first treated with diluted hydrofluoric acid (DHF), and then removed with an H3PO4 solution. Next, the first hard mask layer HM11 is removed with diluted hydrofluoric acid (DHF).

[0131] Next, shallow trench isolation (STI) is formed 122.

[0132] Shallow trench isolation 122 is located on both sides of the core 11 of the first trench TR1 and on the surface of the core 32 of the third trench TR3.

[0133] Next, a well region 21 is formed in the second conductive channel 20, and a contact region 22 is formed in the well region 21. The well region 21 and the contact region 22 have the same doping type as the doped region forming the second conductive channel 20.

[0134] Next, an interlayer dielectric layer is formed, and a first contact hole is formed that penetrates the interlayer dielectric layer to reach the core 12 of the first conductive channel 10, and a second contact hole is formed to reach the second conductive conduction 20.

[0135] Following the aforementioned method for manufacturing the isolation structure of a semiconductor device, the active region structure of a transistor is formed in the core region of the semiconductor device according to known processes and steps, thereby obtaining the final complete structure of the semiconductor device.

[0136] According to the semiconductor device of the present disclosure, the second conductive channel is a doped layer adjacent to the first trench and / or the third trench, thereby omitting the trench used to form the second conductive channel in the prior art, saving device size in terms of device structure, and omitting the etching process of a trench in terms of process, making the process simpler and easier to implement.

[0137] In this embodiment, the opening widths of the first trench of the first conductive channel and the third trench isolated by the deep trench are different. By controlling the opening sizes of the first trench and the third trench, different etching depths can be achieved in the same etching step. That is, the first conductive channel and the trench isolated by the deep trench can be formed simultaneously using a shared etching step. In this embodiment, the trench for forming the second conductive channel is omitted. During the formation of the first trench and the third trench via the same etching step, the predetermined depth of the first trench and the third trench can be controlled more precisely.

[0138] In this embodiment, a deep trench isolation is formed simultaneously with the formation of the first conductive channel, and the filling process of the first conductive channel is exactly the same as the filling process of the deep trench isolation. This avoids the need for multiple filling steps to form the first conductive channel and the deep trench isolation in the prior art, and further avoids the need for multiple fillings and removal of filler residue or over-etching due to differences in filler materials.

[0139] In this embodiment, the first trench and the third trench are formed through two etching steps. During the process of deepening the first trench and the third trench, the doped layer adjacent to the bottom of the first trench and the bottom of the third trench is removed to prevent the formation of excess doped layer.

[0140] As described above, these embodiments of the present disclosure do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description, including but not limited to changes in the local structure of the circuit and replacement of the type or model of components. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A second-doped buried layer is formed on a substrate of the first doping type; An epitaxial layer of a first doped type is formed on the buried layer; A first trench is formed, the first trench extending from the surface of the epitaxial layer into the buried layer; A substrate layer is formed at least on the sidewall of the first trench, the substrate layer being a doped polysilicon layer, and the doping type of the substrate layer being the same as the doping type of the buried layer; The substrate layer is oxidized to form an oxide layer, and at the same time, the dopant in the substrate layer diffuses into the epitaxial layer adjacent to the sidewall of the first trench to form a doped layer in the epitaxial layer that contacts the buried layer. The doped layer serves as a second conductive channel. Continue etching the first trench to deepen its depth; A first conductive channel is formed in the first trench.

2. The method of claim 1, wherein, The steps of oxidizing the substrate layer include dry oxidation, annealing, and wet oxidation.

3. The method of claim 2, wherein, Annealing is performed in a nitrogen atmosphere at a temperature of 900℃ to 1200℃ for 0.5 to 1 hour.

4. The method of claim 2, wherein, The temperature for wet oxygen oxidation is 925℃~1050℃.

5. The method of claim 1, wherein, The junction depth of the doped layer forming the second conductive channel is 2μm~3μm.

6. The method of claim 1, wherein, The formed substrate layer is located on the sidewall of the first trench, and the diffused doped layer is adjacent to the sidewall of the first trench.

7. The method of claim 6, wherein, The method of forming the base layer includes: A base layer is formed that covers the sidewalls of the first trench, the bottom of the first trench, and the surface of the epitaxial layer; The substrate layer is etched back to remove the substrate layer covering the bottom of the first trench and the surface of the epitaxial layer, while retaining the substrate layer covering the sidewalls of the first trench.

8. The method of claim 1, wherein, The formed substrate layer covers the sidewalls of the first trench, the bottom of the first trench, and the surface of the epitaxial layer. The diffused doped layer is adjacent to the sidewalls of the first trench and the bottom of the first trench.

9. The method according to claim 8, wherein, As the first trench is etched and deepened, the doped layer adjacent to the bottom of the first trench is removed.

10. The method according to claim 1, wherein, The method for forming the first conductive channel includes: An insulating pad is formed in the first trench, and an opening is formed at the bottom of the insulating pad in the first trench; and The first trench is filled with a conductive material, wherein the conductive material filling the first trench contacts the substrate through a bottom opening of an insulating pad to form a first conductive channel.

11. The method according to claim 1, wherein, It also includes forming a shallow trench isolation, which is located on top of the first conductive channel and exposes the conductive core of the first conductive channel. The shallow trench isolation is used to isolate the conductive core of the first conductive channel from the second conductive channel.

12. The method according to claim 1, wherein, Also includes: A well region is formed at the top of the second conductive channel; as well as A contact area is formed in the well region.

13. The method according to claim 12, wherein, Also includes: An interlayer dielectric layer is formed that covers the epitaxial layer and the first conductive channel and the second conductive channel; A first contact hole is formed that penetrates the interlayer dielectric layer to reach the conductive core of the first conductive channel, and a second contact hole is formed that penetrates the interlayer dielectric layer to reach the contact area; as well as The first contact hole and the second contact hole are filled to form a first conductive path and a second conductive path.

14. The method according to claim 1, wherein, A third trench is formed simultaneously with the formation of the first trench. The third trench extends from the surface of the epitaxial layer into its interior, and there is a certain distance between the bottom of the third trench and the buried layer. While forming a base layer on the sidewall of the first trench, a base layer is also formed on the sidewall of the third trench; While the substrate layer is oxidized, the dopant in the substrate layer diffuses into the epitaxial layer adjacent to the sidewalls of the first trench and the third trench, forming a doped layer in the epitaxial layer that contacts the buried layer. While forming a first conductive channel in the first trench, a deep trench isolation is formed in the third trench.

15. The method according to claim 14, wherein, During the formation of the first trench and the third trench, the opening width of the first trench is greater than the opening width of the third trench.

16. The method according to claim 15, wherein, The opening size of the first trench is 1.8 micrometers to 2.2 micrometers, and the depth of the first trench is less than 18 micrometers; the opening size of the third trench is 0.9 micrometers to 1.3 micrometers, and the depth of the third trench is 12.5 micrometers to 13.5 micrometers.

17. The method according to claim 15, wherein, The distance between the first trench and the third trench is 0.5 micrometers to 4 micrometers.

18. The method according to claim 14, wherein, The method for forming the first conductive channel and the deep trench isolation includes: An insulating pad is formed in the first trench and the third trench; An opening is formed at the bottom of the insulating pad of the first trench; and The first and third trenches are filled with conductive material, wherein the conductive material filled in the first trench contacts the substrate through the bottom opening of the insulating liner to form a first conductive channel, and the conductive material filled in the third trench forms a deep trench isolation.

19. The method of claim 18, wherein anisotropic etching is used to etch exposed portions of the insulating pads in the first and third trenches along a direction perpendicular to the substrate surface; wherein, Compared to the third trench, the first trench has a larger opening size. The insulating pad at the bottom of the first trench is removed to form the opening, while the insulating pad at the bottom of the third trench is retained.

20. A semiconductor device, comprising: Substrate; Epitaxial layer located on the substrate; The buried layer located between the substrate and the epitaxial layer; as well as A first conductive channel extends from the surface of the epitaxial layer into the substrate; as well as A second conductive channel extends from the surface of the epitaxial layer into the buried layer; The first conductive channel is disposed in the first trench, and the second conductive channel is a doped layer adjacent to the first trench. The doping type of the second conductive channel is the same as the doping type of the buried layer.

21. The semiconductor device according to claim 20, wherein, The first conductive channel includes a conductive core and an insulating pad surrounding the conductive core. The bottom of the substrate pad of the first conductive channel has an opening, and the conductive core of the first conductive channel contacts the substrate through the opening of the insulating pad.

22. The semiconductor device according to claim 20, wherein, It also includes shallow trench isolation, which is located on top of the first conductive channel and exposes the conductive core of the first conductive channel. The shallow trench isolation is used to isolate the conductive core of the first conductive channel from the second conductive channel.

23. The semiconductor device according to claim 20, wherein, It also includes deep trench isolation, which extends from the surface of the epitaxial layer into the substrate; the deep trench isolation is located in a third trench.

24. The semiconductor device according to claim 23, wherein, The deep trench isolation includes a core and an insulating pad surrounding the core.

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