Semiconductor device
Patent Information
- Application Number
- CN202610860765.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-09-15
Smart Images
Figure CN122766038A_ABST
Abstract
Description
[0001] This application is a divisional application. The original application has the application number 202411171392.8 and the original application date is August 26, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0003] With the continuous development and advancement of semiconductor manufacturing technology, electronic products are trending towards miniaturization and high integration, and the feature sizes of various semiconductor devices are also constantly shrinking. Semiconductor devices typically include active regions and isolation regions that define the active regions. As the feature sizes of semiconductor devices shrink, the uniformity of the critical dimensions of the active regions becomes poor. Summary of the Invention
[0004] This application provides a semiconductor device and its fabrication method, which improves the uniformity of the critical dimensions of the active region.
[0005] According to some embodiments, a first aspect of this application provides a semiconductor device, wherein the substrate is provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure; the plurality of first active structures all extend along a first direction, the plurality of first active structures including a first active segment and a second active segment; the second active structure is in direct contact with the second active segment, the side of the second active structure away from the second active segment is an active boundary, a plurality of first trenches are formed in the second active structure at intervals, each of the first trenches is located in the extending direction of the first active structure, and the first trenches do not intersect with the first isolation structure, the second active segment, or the active boundary; the second isolation structure fills the first trenches.
[0006] According to some embodiments, a second aspect of this application provides a semiconductor device including a substrate. The substrate is provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure. The plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment. The second active structure is in direct contact with the second active segment, and the side of the second active structure opposite to the second active segment is an active boundary. A plurality of first trenches are formed in the second active structure at intervals, and each first trench is located in the extending direction of the first active structure. In a top view, the second active structure surrounds the entire perimeter of each first trench. The second isolation structure fills the first trench.
[0007] According to some embodiments, a third aspect of this application provides a semiconductor device including a substrate. The substrate is provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure. The plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment. The second active structure is in direct contact with the second active segment, and the side of the second active structure away from the second active segment is an active boundary. A plurality of first trenches are formed in the second active structure at intervals, and each first trench is located in the extending direction of the first active structure. The second isolation structure fills the first trenches. In a top view, the outer periphery of the second isolation structure is completely surrounded by the second active structure, and each of the first trenches does not intersect with the active boundary.
[0008] In the semiconductor device provided in this application embodiment, the second active segment is in contact with the second active structure, and a first trench is provided in the second active structure. The first trench is located in the extension direction of the first active structure to improve the uniformity of the critical size of the first active structure. Attached Figure Description
[0009] Figure 1 This is a schematic diagram of a semiconductor device in an embodiment of this application;
[0010] Figure 2 This is another schematic diagram of the semiconductor device in the embodiments of this application;
[0011] Figure 3 This is yet another schematic diagram of the semiconductor device in the embodiments of this application;
[0012] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0013] Figure 5 This is a schematic diagram of the mask layer after its formation in an embodiment of this application;
[0014] Figure 6 This is a cross-sectional view of the mask layer after its formation in an embodiment of this application;
[0015] Figure 7 This is a schematic diagram of the trimming layer after its formation in an embodiment of this application;
[0016] Figure 8 This is a cross-sectional view of the trimming layer after its formation in an embodiment of this application;
[0017] Figure 9 This is a cross-sectional view of the mask layer after etching with the trimming layer as a mask in an embodiment of this application;
[0018] Figure 10 This is a cross-sectional view of the substrate formed in an embodiment of this application;
[0019] Figure 11 This is a cross-sectional view of the embodiment of this application after the filling material has been formed;
[0020] Figure 12 This is a schematic diagram of the first pattern layer after its formation in an embodiment of this application;
[0021] Figure 13 This is a cross-sectional view of the first pattern layer after its formation in an embodiment of this application;
[0022] Figure 14 This is a schematic diagram showing the formation of the second pattern layer in an embodiment of this application;
[0023] Figure 15 This is a cross-sectional view of the second pattern layer after its formation in an embodiment of this application;
[0024] Figure 16 This is a schematic diagram of the first pattern layer after etching with the second pattern layer as a mask in an embodiment of this application;
[0025] Figure 17 This is a cross-sectional view of the first pattern layer after etching with the second pattern layer as a mask in an embodiment of this application;
[0026] Figure 18 This is a schematic diagram showing the formation of the third pattern layer in an embodiment of this application;
[0027] Figure 19 This is a cross-sectional view of the third pattern layer after its formation in an embodiment of this application;
[0028] Figure 20 This is a schematic diagram of the first pattern layer after etching with the third pattern layer as a mask in an embodiment of this application.
[0029] Explanation of reference numerals in the attached figures:
[0030] 10 - First active structure;
[0031] 11-First active segment;
[0032] 12-Second active segment;
[0033] 13-Extension line;
[0034] 20 - Second active structure;
[0035] 21-First trench;
[0036] 22-Second trench;
[0037] 23-Third trench;
[0038] 24 - Fourth trench;
[0039] 30 - Third active structure;
[0040] 31-Third active segment;
[0041] 32-Fourth active segment;
[0042] 41-First isolation structure;
[0043] 42-Second isolation structure;
[0044] 43 - Third isolation structure;
[0045] 44 - Fourth isolation structure;
[0046] 50-substrate;
[0047] 60 - Mask layer;
[0048] 70 - Trimming layer;
[0049] 71 - First pattern layer;
[0050] 72 - Second pattern layer;
[0051] 73 - Third pattern layer;
[0052] 74 - First mask strip;
[0053] 75-hole;
[0054] 81-Mask trench;
[0055] 82 - Second mask strip. Detailed Implementation
[0056] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0057] Please see Figure 1 , Figure 1This is a schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device includes a substrate, which may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials.
[0058] like Figure 1 As shown, the substrate has a first active structure 10, a first isolation structure 41, a second active structure 20, and a second isolation structure 42. Multiple first active structures 10 are provided, each extending along a first direction. The multiple first active structures 10 are also spaced apart along a second direction, which intersects the first direction. The first direction is as follows: Figure 1 The L direction is shown, and the second direction is as follows: Figure 1 D direction shown.
[0059] Specifically, multiple first active structures 10 form multiple rows, with each row having at least two first active structures 10. The at least two first active structures 10 in the same row are arranged at intervals along a first direction. In two adjacent rows of first active structures 10 along a second direction, the gap between two adjacent first active structures 10 in one row is opposite to one first active structure 10 in the other row, thereby increasing the arrangement density of the first active structures 10 and enabling one active structure to be connected to at least one word line, thus increasing the storage density.
[0060] Continue reading Figure 1 The plurality of first active structures 10 include a first active segment 11 and a second active segment 12, wherein the first active segment 11 extends along a first direction and the second active segment 12 extends along the first direction. There are typically multiple first active segments 11 and second active segments 12, and they are spaced apart from each other, from each second active segment 12, and from each other, for example, by providing a first isolation structure 41 to ensure that the plurality of first active structures 10 do not contact each other.
[0061] The second active segment 12 is located outside the first active segment 11, for example, the second active segment 12 surrounds the first active segment 11, and the first active segment 11 and the second active segment 12 are spaced apart and arranged in an array. Along the first direction, at least one end of the plurality of first active segments 11 is provided with a second active structure 20.
[0062] The first active segment 11 is a complete segment, and the second active segment 12 is an incomplete segment. The complete segment can be in the shape of an elongated hole, etc. It can be understood that, along the first direction, the length of the first active segment 11 is greater than the length of the second active segment 12, the widths of multiple first active segments 11 and multiple second active segments 12 are equal, and the outline of the second active segment 12 is basically consistent with the outline of the first active segment 11 after one end is cut off, for example, they overlap.
[0063] The first active segments 11 are of equal length, and some of the second active segments 12 are of equal length, while others are of different length. Among the first active segments 11 and second active segments 12 located in the same row, the spacing between adjacent first active segments 11 and the spacing between adjacent first active segments 11 and second active segments 12 are equal along the first direction.
[0064] Specifically, along the first direction, two adjacent first active segments 11 have a first spacing between their same ends. Here, "same end" means that the ends are located at the same position in the corresponding first active segments 11. For example, with... Figure 1 Taking the orientation shown as an example, in two adjacent first active segments 11, there is a first gap between the upper end of one first active segment 11 and the upper end of the other first active segment 11, such as... Figure 1 As shown in L1.
[0065] Continue reading Figure 1 A first isolation structure 41 isolates each of the first active structures 10. The first isolation structure 41 is, for example, shallow trench isolation (STI). Insulation and isolation between the multiple first active structures 10 are achieved by filling the spaces between them with insulating materials such as silicon oxide or silicon nitride. Silicon oxide can be formed using a chemical vapor deposition (CVD) process, with precursors including tetraethyl orthosilicate (TEOS).
[0066] The second active structure 20 is in direct contact with the second active segment 12, and the two can be integrated. The second active structure 20 is not in contact with the first active segment 11. The second active structure 20 is located outside the first active segment 11 and the second active segment 12. For example, the second active structure 20 is elongated and located on one side of the first active segment 11 and the second active segment 12. Alternatively, the second active structure 20 is annular, such as a square ring or a rectangular ring, and is fitted over the first active segment 11 and the second active segment 12. By setting the second active structure 20, the uniformity of the critical dimensions of the first active structure 10 can be improved.
[0067] The side of the second active structure 20 that faces away from the second active segment 12 is the active boundary, such as... Figure 1 As shown in M. In some examples, the active boundary is a closed pattern, and the first active structure 10, the first active segment 11, and the second active segment 12 are all located within the region enclosed by the active boundary. The dimension of the second active structure 20 along the direction away from the first active segment 11 (e.g., Figure 1 W2 shown is greater than the width of the second active segment 12 (as shown in the figure). Figure 1 As shown in the diagram, W1), that is, W2 > W1, the second active structure 20 is wider.
[0068] A plurality of first grooves 21 are formed in the second active structure 20 extending in the direction of the first active structure 10. That is, a plurality of first grooves 21 are provided in the second active structure 20 at intervals. Each first groove 21 is located on the extension line 13 of the first active structure 10, and one of the extension lines 13 is as follows: Figure 1 As shown by the midpoint line, the extension direction of line 13 is parallel to the first direction.
[0069] Furthermore, the multiple first trenches 21 are all located between the first active segment 11 and the active boundary, so that the multiple first trenches 21 do not intersect with the active boundary. The first trenches 21 can be circular, elliptical, etc., and the depth of the first trenches 21 is the same as the depth of the first isolation structure 41. For example, the first trenches 21 and the first isolation structure 41 are formed simultaneously.
[0070] Continue reading Figure 1 The second isolation structure 42 fills the first trench 21, for example, the second isolation structure 42 fills the first trench 21 completely. The second isolation structure 42 includes insulating materials such as silicon oxide and silicon nitride. The second isolation structure 42 is made of the same material as the first isolation structure 41, so the second isolation structure 42 and the first isolation structure 41 can be formed simultaneously, for example, by simultaneous deposition.
[0071] In one embodiment, the second isolation structure 42 includes a silicon oxide layer and a silicon nitride layer stacked sequentially, wherein the stacking direction is away from the wall of the first trench 21. Specifically, a first silicon oxide layer covers the sidewalls and bottom wall of the first trench 21, a silicon nitride layer covers the first silicon oxide layer, and a second silicon oxide layer fills the area enclosed by the silicon nitride layer. These two silicon oxide layers and the silicon nitride layer fill the first trench 21.
[0072] Continue reading Figure 1 A first active segment 11 adjacent to the second active structure 20, and a second isolation structure 42 adjacent to the first active segment 11 along a first direction, have a second spacing, such as Figure 1As shown in L2. The second spacing is equal to the first spacing, or the difference is less than a preset value. The first spacing is the distance between the same end of two adjacent first active segments 11 in the first direction, and the preset value is equal to 3% of the length of the first isolation structure 41 between two adjacent first active segments 11 along the first direction. In this way, the second isolation structure 42 and the first isolation structure 41 between two adjacent first active segments 11 are basically arranged in an array, which is convenient for manufacturing.
[0073] See Figure 2 , Figure 2 This is another schematic diagram of the semiconductor device in an embodiment of this application. A plurality of second trenches 22 are further formed within the second active structure 20 extending in the direction of the first active structure 10. The second trenches 22 are located on the active boundary. The plurality of second trenches 22 are spaced apart, each second trench 22 is located on the extension line 13 of the first active structure 10, and different second trenches 22 correspond to different first active structures 10.
[0074] Each second trench 22 has an opening, and the opening of the second trench 22 is away from the first active segment 11. Each second trench 22 is semi-circular, semi-elliptical, or the sidewall of the second trench 22 is inferior arc-shaped, superior arc-shaped, etc. The depth of the second trench 22 can be the same as the depth of the first trench 21, so that the second trench 22 and the first trench 21 can be manufactured simultaneously.
[0075] In one embodiment, the area of the second trench 22 is 0.3-0.8 times the area of the first trench 21. In some examples, the areas of all the second trenches 22 are equal, for example, all are 0.5 times the area of the first trench 21. In some examples, some of the second trenches 22 have the same area and are different from the areas of other portions of the second trenches 22. Specifically, the areas of the plurality of second trenches 22 located on one side (e.g., the lower side) of the first active segment 11 are the same, for example, 0.4 times the area of the first trench 21. The areas of the plurality of second trenches 22 located on the other side (e.g., the left side) of the first active segment 11 are the same, for example, 0.6 times the area of the first trench 21.
[0076] See Figure 3 , Figure 3 This is another schematic diagram of the semiconductor device in an embodiment of this application. A plurality of third trenches 23 are further formed within the second active structure 20 extending in the direction of the first active structure 10. The third trenches 23 are filled with third isolation structures 43, which are in contact with the second active segment 12. The plurality of third trenches 23 are spaced apart, each third trench 23 is located on the extension line 13 of the first active structure 10, and different third trenches 23 correspond to different first active structures 10. Each third trench 23 is circular.
[0077] The third trench 23 partially contacts the first isolation structure 41 and partially contacts the second active segment 12. The third trench 23 forms a closed shape, which can be circular, elliptical, or similar. The shape of the third trench 23 can be the same as that of the first trench 21, and the area of the third trench 23 can be equal to that of the first trench 21. The depth of the third trench 23 can be the same as the depth of the first trench 21, so that the third trench 23 and the first trench 21 can be formed synchronously.
[0078] The third isolation structure 43 includes insulating materials such as silicon oxide and silicon nitride. The third isolation structure 43 is made of the same material as the second isolation structure 42, so that the third isolation structure 43 and the second isolation structure 42 can be formed simultaneously.
[0079] See Figure 2 Multiple fourth grooves 24 are formed within the second active structure 20 extending in the direction of the first active structure 10, and the first isolation structure 41 extends to the fourth grooves 24. The multiple fourth grooves 24 are spaced apart, each located on the extension line 13 of the first active structure 10, and different fourth grooves 24 correspond to different first active structures 10. Each fourth groove 24 is semi-circular, semi-elliptical, or its sidewall is of a lesser arc shape, a greater arc shape, etc. The depth of the fourth groove 24 can be the same as the depth of the first groove 21, so that the fourth groove 24 and the first groove 21 can be manufactured simultaneously.
[0080] Each fourth trench 24 has an opening facing the first active segment 11. The first isolation structure 41 extends through the opening of the fourth trench 24 and directly contacts the fourth trench 24, filling the fourth trench 24. In one embodiment, the fourth trench 24 also contacts the second active segment 12, that is, a portion of the fourth trench 24 is located within the second active segment 12.
[0081] Continue reading Figure 1 The substrate also includes a third active structure 30 and a fourth isolation structure 44. The third active structure 30 is spaced apart on the side of the second active structure 20 away from the first active structure 10. The third active structure 30 includes a plurality of third active segments 31, which are spaced apart from each other and from the second active structure 20. Each third active segment 31 is elongated, for example, rectangular, and arranged side by side on one side of the second active structure 20, for example... Figure 1 The lower side is shown.
[0082] The third active structure 30 also includes a plurality of fourth active segments 32, which are spaced apart from and spaced apart from the second active structure 20. Each fourth active segment 32 is elongated, for example rectangular, and arranged side by side on the other side of the second active structure 20, for example... Figure 1 The left side is shown.
[0083] A fourth isolation structure 44 is disposed between the third active structure 30 and the second active structure 20 to isolate the third active structure 30 and the second active structure 20. The fourth isolation structure 44 comprises an insulating material such as silicon oxide or silicon nitride. In some possible examples, the fourth isolation structure 44 may be the same as or different from the first isolation structure 41. When the substrate has a second trench 22, the fourth isolation structure 44 also contacts and fills the second trench 22.
[0084] The semiconductor device provided in this application embodiment includes a substrate. The substrate has a plurality of first active structures 10, a first isolation structure 41, a second active structure 20, and a second isolation structure 42. The first isolation structure 41 isolates each of the first active structures 10. The plurality of first active structures 10 extend along a first direction and include a first active segment 11 and a second active segment 12. The second active segment 12 is in direct contact with the second active structure 20, so that the second active structure 20 is adjacent to the first active structure 10. The side of the second active structure 20 away from the second active segment 12 is an active boundary. A plurality of first trenches 21 are formed in the second active structure 20 along the extension direction of the first active structures 10. The first trenches 21 are located between the second active segment 12 and the active boundary, and the second isolation structure 42 is filled in the first trenches 21. The first trenches 21 correspond to the gaps between adjacent first active segments 11 and second active segments 12 along the first direction, which can improve the uniformity of the critical dimensions of the first active structures 10.
[0085] Please see Figure 4 , Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. This application also provides a method for fabricating a semiconductor device, such as... Figure 1 As shown, the manufacturing method includes the following steps:
[0086] Step S100: Provide a substrate.
[0087] The substrate includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials.
[0088] Step S200: A plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure are formed on a substrate; wherein, the plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment; the second active structure is in direct contact with the second active segment, and the side of the second active structure away from the second active segment is an active boundary; a plurality of first trenches are formed in the second active structure in the extension direction of the first active structures, and the first trenches are located between the second active segment and the active boundary; the second isolation structure fills the first trenches.
[0089] like Figure 1 As shown, the substrate 50 is provided with a first active structure 10, a first isolation structure 41, a second active structure 20, and a second isolation structure 42. Multiple first active structures 10 are provided, each extending along a first direction. These multiple first active structures 10 are also spaced apart along a second direction, which intersects the first direction, for example, perpendicularly. The first direction is as follows: Figure 1 The L direction is shown, and the second direction is as follows: Figure 1 D direction shown.
[0090] Specifically, multiple first active structures 10 form multiple rows, with each row having at least two first active structures 10. The at least two first active structures 10 in the same row are arranged at intervals along a first direction. In two adjacent rows of first active structures 10 along a second direction, the gap between two adjacent first active structures 10 in one row is opposite to one first active structure 10 in the other row, thereby increasing the arrangement density of the first active structures 10 and enabling one active structure to be connected to at least one word line, thus increasing the storage density.
[0091] Continue reading Figure 1 The plurality of first active structures 10 include a first active segment 11 and a second active segment 12, wherein the first active segment 11 extends along a first direction and the second active segment 12 extends along the first direction. There are usually multiple first active segments 11 and second active segments 12, and they are spaced apart from each other, between each second active segment 12, and between the first active segments 11 and the second active segments 12, for example, by providing a first isolation structure 41 to ensure that the plurality of first active structures 10 do not come into contact with each other.
[0092] The second active segment 12 is located outside the first active segment 11, for example, the second active segment 12 surrounds the first active segment 11, and the first active segment 11 and the second active segment 12 are spaced apart and arranged in an array. Along the first direction, at least one of the two ends of the first active segment 11 is provided with a second active structure 20.
[0093] The first active segment 11 is a complete segment, and the second active segment 12 is an incomplete segment. The complete segment can be elongated in shape. It can be understood that, along the first direction, the length of the first active segment 11 is greater than the length of the second active segment 12. The widths of multiple first active segments 11 and multiple second active segments 12 are equal, and the outline of the second active segment 12 is basically consistent with the outline of the first active segment 11 after one end is cut off, for example, they overlap.
[0094] The first active segments 11 are of equal length, and some of the second active segments 12 are of equal length, while others are of different length. Among the first active segments 11 and second active segments 12 located in the same row, the spacing between adjacent first active segments 11 and the spacing between adjacent first active segments 11 and second active segments 12 are equal along the first direction.
[0095] Continue reading Figure 1 A first isolation structure 41 isolates each of the first active structures 10. The first isolation structure 41 is, for example, a shallow trench isolation. Insulation and isolation between the multiple first active structures 10 are achieved by filling the spaces between them with insulating materials such as silicon oxide or silicon nitride. Silicon oxide can be formed by a chemical vapor deposition process, and the precursor includes tetraethyl orthosilicate.
[0096] The second active structure 20 is in direct contact with the second active segment 12, and the two can be integrated. The second active structure 20 is not in contact with the first active segment 11. The second active structure 20 is located outside the first active segment 11 and the second active segment 12. For example, the second active structure 20 is elongated and located on one side of the first active segment 11 and the second active segment 12. Alternatively, the second active structure 20 is annular, such as a square ring or a rectangular ring, and is fitted over the first active segment 11 and the second active segment 12. By setting the second active structure 20, the uniformity of the critical dimensions of the first active structure 10 can be improved.
[0097] The side of the second active structure 20 away from the second active segment 12 is the active boundary, which can be, for example, a closed pattern. The first active structure 10, the first active segment 11, and the second active segment 12 are all located within the area enclosed by the active boundary. The dimension of the second active structure 20 in the direction away from the first active segment 11 is greater than the width of the second active segment 12, that is, the second active structure 20 is wider.
[0098] Multiple first trenches 21 are formed within the second active structure 20 extending along the first active structure 10. Specifically, multiple first trenches 21 are spaced apart within the second active structure 20, and each first trench 21 is located on the extension line of the first active structure 10. The multiple first trenches 21 are all located between the first active segment 11 and the active boundary, thus preventing them from intersecting with the active boundary. The first trenches 21 can be circular, elliptical, etc., and their depth is the same as the height of the first isolation structure 41. For example, the first trenches 21 and shallow trenches can be formed simultaneously.
[0099] Continue reading Figure 1 The second isolation structure 42 fills the first trench 21, for example, the second isolation structure 42 fills the first trench 21 completely. The second isolation structure 42 includes insulating materials such as silicon oxide and silicon nitride. The second isolation structure 42 is made of the same material as the first isolation structure 41, so the second isolation structure 42 and the first isolation structure 41 can be formed simultaneously, for example, by simultaneous deposition.
[0100] In one embodiment, please refer to Figures 5 to 11 , Figure 5 This is a schematic diagram of the mask layer after its formation in an embodiment of this application; Figure 6 This is a cross-sectional view of the mask layer after its formation in an embodiment of this application; Figure 7 This is a schematic diagram of the trimming layer after its formation in an embodiment of this application; Figure 8 This is a cross-sectional view of the trimming layer after its formation in an embodiment of this application; Figure 9 This is a cross-sectional view of the mask layer after etching with the trimming layer as a mask in an embodiment of this application; Figure 10 This is a cross-sectional view of the substrate formed in an embodiment of this application; Figure 11 This is a cross-sectional view of the filling material formed in an embodiment of this application.
[0101] A plurality of first active structures 10, a first isolation structure 41 isolating each of the first active structures 10, a second active structure 20, and a second isolation structure 42 are formed on the substrate 50, including:
[0102] A mask layer 60 is formed on a substrate 50, the substrate including a first region, a second region, and a third region that are sequentially adjacent to each other, and a second active structure 20 is formed in the second region B. Figure 5 As shown, the first, second, and third regions are divided by dashed lines. The first region is... Figure 5 As shown in A, the second region is Figure 5 As shown in B, the third region is Figure 5As shown in Figure C, the second region B is located between the first region A and the third region C, and is adjacent to both regions. For example, the second region B is annular, with the first region A inside and the third region C outside. The mask layer 60 can be a single layer or a stack of layers. The mask layer 60 can be a hard mask, such as silicon nitride, silicon carbide nitride, silicon oxynitride, silicon carbide, metal, or organic materials.
[0103] A trimming layer 70 is formed on the mask layer 60. The trimming layer 70 opposite to the first region A includes a plurality of first patterns extending along a first direction. The mask layer 60 is exposed between adjacent first patterns. A plurality of mask trenches 81 are provided in the trimming layer 70 opposite to the second region B.
[0104] Using the trimming layer 70 as a mask, the mask layer 60 and the substrate 50 are etched. A plurality of first active structures 10 are formed in the first region A of the substrate 50, and a second active structure 20 is formed in the second region B of the substrate 50. The second active structure 20 has a first trench 21.
[0105] The deposited isolation material forms a first isolation structure 41 between the first active structures 10, and the isolation material in the first trench 21 forms a second isolation structure 42.
[0106] like Figure 7 and Figure 8 As shown, the trimming layer 70 is located on the side of the mask layer 60 opposite to the substrate 50. The trimming layer 70 opposite to the first region includes a plurality of first patterns, such as... Figure 7 As shown in P1, multiple first patterns are spaced apart and extend along a first direction, exposing a mask layer 60 between the multiple first patterns. A plurality of mask trenches 81 are provided within a trimming layer 70 opposite the second region, spaced apart and exposing the mask layer 60. The mask trenches 81 can be closed shapes, such as circles or ellipses.
[0107] like Figure 9 and Figure 10 As shown, the mask layer 60 and the substrate 50 are etched using the trimming layer 70 as a mask to remove the exposed mask layer 60 and the corresponding substrate 50. A plurality of spaced first active structures 10 are formed in the first region A of the substrate 50, and a second active structure 20 is formed in the second region B of the substrate 50. Part of the first active structure 10 is in direct contact with the second active structure 20, and the second active structure 20 also has a first trench 21.
[0108] like Figure 10 and Figure 11As shown, isolation material is deposited between the first active structures 10 and within the first trench 21. The isolation material between the first active structures 10 forms a first isolation structure 41, and the isolation material within the first trench 21 forms a second isolation structure 42. The second isolation structure 42 fills the first trench 21; for example, the first isolation structure 41, the second isolation structure 42, the first active structure 10, and the second active structure 20 can be flush with each other.
[0109] In one example, the trimming layer 70 opposite the third region includes a plurality of third patterns P2, which are spaced apart and expose a mask layer 60 between them. The plurality of third patterns P2 are located on different sides of the trimming layer 70 opposite the second region. When the trimming layer 70 is used as a mask to etch the mask layer 60 and the substrate 50, a plurality of third active structures 30 are formed in the third region of the substrate 50, which are spaced apart. When an isolation material is deposited, the isolation material also fills the spaces between the third active structures 30 and the second active structure 20, as well as between the third active structures 30, to form a third isolation structure 43.
[0110] See also some possible implementations. Figures 12 to 20 , Figure 12 This is a schematic diagram of the first pattern layer after its formation in an embodiment of this application; Figure 13 This is a cross-sectional view of the first pattern layer after its formation in an embodiment of this application; Figure 14 This is a schematic diagram showing the formation of the second pattern layer in an embodiment of this application; Figure 15 This is a cross-sectional view of the second pattern layer after its formation in an embodiment of this application; Figure 16 This is a schematic diagram of the first pattern layer after etching with the second pattern layer as a mask in an embodiment of this application; Figure 17 This is a cross-sectional view of the first pattern layer after etching with the second pattern layer as a mask in an embodiment of this application; Figure 18 This is a schematic diagram showing the formation of the third pattern layer in an embodiment of this application; Figure 19 This is a cross-sectional view of the third pattern layer after its formation in an embodiment of this application; Figure 20 This is a schematic diagram of the first pattern layer after etching with the third pattern layer as a mask in an embodiment of this application.
[0111] A trimming layer 70 is formed on the mask layer 60, comprising:
[0112] A first pattern layer 71 is formed on the mask layer 60. The first pattern layer 71 with a first region opposite includes a plurality of spaced first mask strips 74. The mask layer 60 is exposed between adjacent first mask strips 74, and the first pattern layer 71 with a second region opposite covers the mask layer 60. Figure 12 and Figure 13As shown, the first pattern layer 71 may include spin-coated carbon, amorphous carbon, silicon nitride, silicon carbide, silicon oxynitride, polycrystalline silicon, or a combination thereof, and the material of the first pattern layer 71 is different from the material of the mask layer 60. The first mask strip 74 extends along the first direction and also contacts the first pattern layer 71 opposite the second region.
[0113] A second pattern layer 72 is formed on the first pattern layer 71. The second pattern layer 72, which is opposite to the first region and the second region, has a plurality of spaced holes 75. The holes 75 are opposite to the first mask strip 74 or located on the extension line 13 of the first mask strip 74. The second pattern layer 72, which is opposite to the third region, covers the first pattern layer 71.
[0114] like Figure 14 and Figure 15 As shown, the second pattern layer 72 fills the spaces between adjacent first mask strips 74, also covers the first mask strips 74, and is opposite to the second region. The second pattern layer 72 may include spin-coated carbon, amorphous carbon, silicon nitride, silicon carbide, silicon oxynitride, polysilicon, or combinations thereof, and the material of the second pattern layer 72 is different from that of the first mask layer 60. The holes 75 opposite to the first region expose the first mask strips 74, and the holes 75 located on the extension line 13 of the first mask strips 74 expose the first pattern layer 71.
[0115] Using the second pattern layer 72 as a mask, the first pattern layer 71 is etched to divide the first mask strip 74 into a first pattern P1, and a mask trench 81 is formed in the first pattern layer 71 opposite to the second region. Figure 16 and Figure 17 As shown, using the second pattern layer 72 as a mask, the exposed first pattern layer 71 is etched away, and the first mask strip 74 divides to form a plurality of first patterns P1. A mask trench 81 is formed in the first pattern layer 71 opposite to the second region, and the mask trench 81 exposes the mask layer 60.
[0116] In other implementations, a first pattern layer 71 is formed on the mask layer 60, such as... Figure 12 and Figure 13 As shown, the third region is further covered by a mask layer 60 over the first patterned layer 71. A second patterned layer 72 is formed on the first patterned layer 71, as shown... Figure 14 and Figure 15 As shown, the second pattern layer 72, opposite to the third region, covers the first pattern layer 71. Using the second pattern layer 72 as a mask, the first pattern layer 71 is etched, as follows. Figure 16 and Figure 17 As shown, the first pattern layer 71 opposite the third region covers the mask layer 60. In the above implementation, the mask layer 60 opposite the third region is not etched.
[0117] In other embodiments, such as Figures 17 to 20As shown, after etching the first pattern layer 71 using the second pattern layer 72 as a mask, the process further includes: Figure 17 As shown, the second pattern layer 72 is removed to expose the first pattern layer 71. Figure 18 and Figure 19 As shown, a third pattern layer 73 is formed. The third pattern layer 73, with the first and second regions opposite each other, covers the first pattern layer 71. The third pattern layer 73 includes a plurality of spaced-apart second mask strips 82, which are staggered from the mask trenches 81. The third pattern layer 73 can be a single layer or a stack of layers. Figure 20 As shown, using the third pattern layer 73 as a mask, the mask layer 60 is etched, and the mask layer 60 opposite the third region forms a third mask strip. The third pattern layer 73 is removed to expose the first pattern layer 71, and the remaining first pattern layer 71 forms a trimming layer 70.
[0118] Thus, when the mask layer 60 and the substrate 50 are etched using the trimming layer 70 as a mask, a first active structure 10 is formed in a first region of the substrate 50, a second active structure 20 and a first trench 21 are formed in a second region of the substrate 50, and a third active structure 30 is formed in a third region of the substrate 50.
[0119] The semiconductor device provided in this application embodiment includes: a substrate 50, on which a plurality of first active structures 10, a first isolation structure 41 isolating each of the first active structures 10, a second active structure 20, and a second isolation structure 42 are formed. The plurality of first active structures 10 extend along a first direction, and each of the first active structures 10 includes a first active segment 11 and a second active segment 12. The second active structure 20 is in direct contact with the second active segment 12, and the side of the second active structure 20 facing away from the second active segment 12 is an active boundary. A plurality of first trenches 21 are formed within the second active structure 20 in the direction of extension of the first active structures 10, and the first trenches 21 are located between the second active segment 12 and the active boundary. The second isolation structure 42 fills the first trenches 21. The substrate 50 has a plurality of first active structures 10, a first isolation structure 41, a second active structure 20, and a second isolation structure 42, and the first isolation structure 41 isolates each of the first active structures 10. Multiple first active structures 10 extend along a first direction. Each first active structure 10 includes a first active segment 11 and a second active segment 12. The second active segment 12 is in direct contact with a second active structure 20, such that the second active structure 20 is adjacent to the first active structure 10. The side of the second active structure 20 facing away from the second active segment 12 forms an active boundary. Multiple first trenches 21 are formed within the second active structure 20 along the extension direction of the first active structure 10. The first trenches 21 are located between the second active segment 12 and the active boundary, and are filled with a second isolation structure 42. The first trenches 21 correspond to the gaps between adjacent first active segments 11 and second active segments 12 along the first direction, which can improve the uniformity of the critical dimensions of the first active structure 10.
[0120] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.
[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor device, characterized in that, The device includes a substrate, the substrate being provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure; The plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment; The second active structure is in direct contact with the second active segment. The side of the second active structure away from the second active segment is the active boundary. Multiple first grooves are spaced apart in the second active structure. Each first groove is located in the extension direction of the first active structure, and the first groove does not intersect with the first isolation structure, the second active segment, or the active boundary. The second isolation structure is filled in the first groove.
2. The semiconductor device according to claim 1, characterized in that, Along the first direction, two adjacent first active segments have a first spacing between the same end; A first active segment adjacent to the second active structure has a second spacing with a second isolation structure adjacent along the first direction, the second spacing being equal to the first spacing or the difference being less than a preset value.
3. The semiconductor device according to claim 2, characterized in that, The preset value is equal to 3% of the length of the first isolation structure between two adjacent first active segments along the first direction.
4. The semiconductor device according to any one of claims 1-3, characterized in that, Multiple second grooves are also formed in the second active structure in the extension direction of the first active structure. The second grooves intersect with the active boundary but do not intersect with the first isolation structure or the second active segment.
5. The semiconductor device according to claim 4, characterized in that, The area of the second trench is 0.3-0.8 times the area of the first trench.
6. The semiconductor device according to any one of claims 1-3, characterized in that, Multiple third grooves are also formed in the second active structure in the extension direction of the first active structure. The third grooves are filled with third isolation structures. The third isolation structures are in contact with the second active segment and do not intersect with the first isolation structure or the active boundary.
7. The semiconductor device according to any one of claims 1-3, characterized in that, A plurality of fourth grooves are also formed in the second active structure in the extension direction of the first active structure. The fourth grooves do not intersect with the active boundary, and the first isolation structure extends into the fourth grooves.
8. The semiconductor device according to claim 7, characterized in that, The fourth trench does not intersect with the second active segment; or... The fourth trench is in contact with the second active segment.
9. The semiconductor device according to any one of claims 1-3, characterized in that, The second active structure surrounds the first active structure and is spaced apart from the first active segment.
10. The semiconductor device according to any one of claims 1-3, characterized in that, The first active segment and the second active segment are spaced apart and arranged in an array.
11. The semiconductor device according to any one of claims 1-3, characterized in that, The substrate is further provided with: The third active structure is spaced apart and disposed on the side of the second active structure away from the first active structure; A fourth isolation structure is disposed between the third active structure and the second active structure.
12. A semiconductor device, characterized in that, The device includes a substrate, the substrate being provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure; The plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment; The second active structure is in direct contact with the second active segment. The side of the second active structure away from the second active segment is the active boundary. The second active structure has a plurality of first grooves spaced apart. Each first groove is located in the extension direction of the first active structure. In the top view, the second active structure surrounds the entire perimeter of each first groove. The second isolation structure is filled in the first trench.
13. A semiconductor device, characterized in that, The device includes a substrate, the substrate being provided with: a plurality of first active structures, a first isolation structure isolating each of the first active structures, a second active structure, and a second isolation structure; The plurality of first active structures extend along a first direction, and the plurality of first active structures include a first active segment and a second active segment; The second active structure is in direct contact with the second active segment. The side of the second active structure away from the second active segment is the active boundary. Multiple first grooves are spaced apart in the second active structure, and each first groove is located in the extension direction of the first active structure. The second isolation structure is filled in the first groove. In the top view, the outer periphery of the second isolation structure is completely surrounded by the second active structure, and each first groove does not intersect with the active boundary.