image sensor

Abstract

An image sensor is disclosed. The image sensor includes a semiconductor substrate; a PD isolation pattern disposed in the semiconductor substrate and defining a first PD region and a second PD region; a first floating diffusion region provided in the semiconductor substrate of the first PD region; an interconnect conductive pattern disposed on a first surface of the semiconductor substrate and in contact with the first floating diffusion region; a source follower gate electrode provided in the second PD region, the source follower gate electrode including a first portion disposed on the semiconductor substrate of the second PD region and a second portion extending from the first portion and disposed on the PD isolation pattern, the second portion adjacent to the interconnect conductive pattern; and a common contact plug commonly connected to the source follower gate electrode and the interconnect conductive pattern.

Description

Technical Field

[0001] This disclosure relates to image sensors, and more particularly to image sensors having improved electrical and optical properties. Background Technology

[0002] An image sensor is a device that converts light signals into electrical signals. With the development of the computer and communications industries in recent years, the demand for high-performance image sensors has been growing in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, miniature cameras for medical applications, and / or robots.

[0003] Image sensors are generally classified into charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS) image sensors. Because CMOS image sensors integrate signal processing chips onto a single chip, their product size can be reduced. CMOS image sensors also exhibit very low power consumption, making them suitable for products with limited battery capacity. Furthermore, because CMOS image sensors are compatible with CMOS process technology, their manufacturing costs can be reduced. Therefore, as technological advancements enable high-resolution CMOS image sensors, their use is rapidly increasing. Summary of the Invention

[0004] Embodiments of the disclosed concept provide an image sensor with improved electrical and optical properties.

[0005] According to some example embodiments of the disclosed concept, an image sensor may include: a semiconductor substrate; a photodiode (PD) isolation pattern disposed in the semiconductor substrate and defining a first PD region and a second PD region; a first floating diffusion region provided in the semiconductor substrate of the first PD region; an interconnect conductive pattern disposed on a first surface of the semiconductor substrate and in contact with the first floating diffusion region; a source follower gate electrode provided in the second PD region and including a first portion disposed on the semiconductor substrate of the second PD region and a second portion extending from the first portion and disposed on the PD isolation pattern, the second portion being adjacent to the interconnect conductive pattern; and a common contact plug commonly connected to the source follower gate electrode and the interconnect conductive pattern.

[0006] According to some example embodiments of the disclosed concept, an image sensor may include: a semiconductor substrate; a PD isolation pattern disposed within the semiconductor substrate to define a first PD region and a second PD region; a first floating diffusion region provided in the semiconductor substrate within the first PD region; a second floating diffusion region provided in the semiconductor substrate within the second PD region; an interconnect conductive pattern disposed on a first surface of the semiconductor substrate and in contact with the first floating diffusion region; a pixel transistor provided in the second PD region and including a pixel gate electrode and a source / drain region located on the opposite side of the pixel gate electrode; and a common contact plug connecting the interconnect conductive pattern to the pixel gate electrode or the source / drain region.

[0007] According to some example embodiments of the disclosed concept, an image sensor may include: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a PD isolation pattern disposed in the semiconductor substrate to define a first PD region to a fourth PD region; a photoelectric conversion region provided in the semiconductor substrate in the first PD region to the fourth PD region; a device isolation layer adjacent to the first surface of the semiconductor substrate and defining a first active portion and a second active portion in each of the first PD region to the fourth PD region; a transfer gate electrode provided in the first active portion of the first PD region to the fourth PD region; a floating diffusion region provided in the first active portion of the first PD region to the fourth PD region; and a pixel transistor provided in the first PD region to the fourth PD region. In the second active portion of the fourth PD region, a pixel transistor includes a pixel gate electrode, the pixel gate electrode including a first portion disposed on the second active portion in the third PD region and the fourth PD region, and a second portion extending from the first portion and disposed on the PD isolation pattern and adjacent to the floating diffusion regions in the first PD region and the second PD region; an interconnect conductive pattern, the interconnect conductive pattern contacting the floating diffusion regions of the first PD region to the fourth PD region respectively; a common contact plug, the common contact plug connecting the pixel gate electrode to the interconnect conductive pattern of the first PD region to the fourth PD region; a color filter, the color filter being disposed on the second surface of the semiconductor substrate corresponding to the first PD region to the fourth PD region; a grid, the grid being disposed between the color filters and overlapping the PD isolation pattern; and a microlens, the microlens being located on the color filter.

[0008] According to some example embodiments of the disclosed concept, a method of manufacturing an image sensor may include: forming a PD isolation pattern defining a first PD region and a second PD region in a semiconductor substrate; forming a device isolation layer adjacent to a first surface of the semiconductor substrate, the device isolation layer defining a first active portion and a second active portion in each of the first PD region and the second PD region; forming a floating diffusion region in the first active portion of the first PD region and the second PD region; forming a pixel gate electrode on the second active portion of the first PD region and the second PD region; forming an interconnect conductive pattern on the floating diffusion region of the first PD region and the second PD region and on the first surface of the semiconductor substrate; forming an interlayer insulating layer covering the first surface of the semiconductor substrate; patterning the interlayer insulating layer to form a common contact hole exposing one of the interconnect conductive patterns and one of the pixel gate electrodes; and forming a common contact plug in the common contact hole.

[0009] In some example embodiments, forming the interconnect conductive pattern may include: forming a spacer insulating layer with a substantially uniform thickness covering the first surface of the pixel gate electrode and the semiconductor substrate; patterning the spacer insulating layer to form a spacer insulating pattern exposing the floating diffusion region; depositing a conductive layer in contact with the floating diffusion region on the spacer insulating pattern; and patterning the conductive layer.

[0010] In some example embodiments, a pixel gate electrode may include a first portion disposed on the semiconductor substrate of the second PD region and a second portion extending from the first portion and disposed on the PD isolation pattern and adjacent to the floating diffusion region.

[0011] In some example embodiments, the common contact plug may have a length in a first direction and a width less than the length in a second direction perpendicular to the first direction.

[0012] In some example embodiments, the common contact hole may expose a portion of the PD isolation pattern between one of the interconnect conductive patterns and one of the pixel gate electrodes. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating an image sensor according to an embodiment of the disclosed concept.

[0014] Figure 2A and Figure 2B This is a circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the disclosed concept.

[0015] Figure 3This is a plan view illustrating a portion of an image sensor according to an embodiment of the disclosed concept.

[0016] Figure 4A , Figure 4B and Figure 4C They are along Figure 3 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0017] Figure 5A and Figure 5B This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0018] Figure 6 This is a plan view illustrating an image sensor according to an embodiment of the disclosed concept.

[0019] Figure 7A , Figure 7B and Figure 7C They are along Figure 6 The cross-sectional views taken from lines D-D', E-E', and F-F'.

[0020] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0021] Figure 9A , Figure 9B and Figure 9C This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0022] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0023] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0024] Figure 12A , Figure 12C , Figure 12D , Figure 12E , Figure 12F and Figure 12G This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0025] Figure 12B It is along Figure 12A A cross-sectional view taken from line G-G'.

[0026] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0027] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0028] Figure 15A , Figure 15B , Figure 15C and Figure 15D This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0029] Figure 16 This is a circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the disclosed concept.

[0030] Figure 17A and Figure 18A This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0031] Figure 17B and Figure 18B They are along Figure 17A and Figure 18A A cross-sectional view taken from line H-H'.

[0032] Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0033] Figures 23 to 27 It is along Figure 3 A cross-sectional view taken along line A-A' to illustrate a method for manufacturing an image sensor according to an embodiment of the disclosed concept.

[0034] Figure 28 This is a schematic plan view illustrating an image sensor according to an embodiment of the disclosed concept.

[0035] Figure 29 and Figure 30 It is along Figure 28 A cross-sectional view taken by line I-I' to illustrate an image sensor according to some example embodiments. Detailed Implementation

[0036] Example embodiments of the disclosed concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0037] Figure 1 This is a block diagram illustrating an image sensor according to an embodiment of the disclosed concept.

[0038] refer to Figure 1 The image sensor may include an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer 8.

[0039] The active pixel sensor array 1 may include multiple unit pixels arranged in a two-dimensional manner, each unit pixel being configured to convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by multiple drive signals from the row driver 3, such as pixel selection signals, reset signals, and charge transfer signals. The converted electrical signals may be provided to the associated dual sampler 6.

[0040] The row decoder 2 can provide a drive signal to each unit pixel in each row. In addition, in response to the drive signal, the electrical signal converted in the active pixel sensor array 1 can be provided to the associated dual sampler 6.

[0041] The row driver 3 can provide several driving signals to the active pixel sensor array 1 to drive several unit pixels based on the decoding results obtained from the row decoder 2. When the unit pixels are arranged in a matrix shape, driving signals can be provided to each row.

[0042] The timing generator 5 can control the row decoder 2, column decoder 4, correlated double sampler 6, analog-to-digital converter 7, and input / output buffer 8, and can provide control signals (e.g., clock signals, timing control signals, etc.) during their operation. The timing generator 5 may include logic control circuitry, phase-locked loop (PLL) circuitry, timing control circuitry, and communication interface circuitry.

[0043] The Correlation Dual Sampler (CDS) 6 can receive electrical signals generated in the active pixel sensor array 1, and can hold and sample the received electrical signals. The Correlation Dual Sampler 6 can perform a dual sampling operation to sample specific noise levels and signal levels of the electrical signals, and then output a difference level corresponding to the difference between the noise level and the signal level.

[0044] The analog-to-digital converter (ADC) 7 can convert the analog signal corresponding to the difference level received from the correlated dual sampler 6 into a digital signal, and then output the converted digital signal.

[0045] The input / output buffer 8 can latch digital signals and then, in response to the decoding result obtained from the column decoder 4, sequentially output the latched digital signals to the image signal processing unit (not shown).

[0046] Figure 2A and Figure 2B This is a circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the disclosed concept.

[0047] refer to Figure 2A Each unit pixel PX can include a photoelectric conversion circuit 10P and a pixel circuit 20P.

[0048] The photoelectric conversion circuit 10P may include multiple photoelectric conversion groups 10a and 10b. The photoelectric conversion circuit 10P may include at least 2, 4, 8, or 16 photoelectric conversion groups 10a and 10b. Each of the photoelectric conversion groups 10a and 10b may include at least 2, 4, 8, or 16 photoelectric conversion elements (e.g., photodiodes), multiple transfer transistors, and a floating diffusion region.

[0049] In some embodiments, the photoelectric conversion circuit 10P may include a first photoelectric conversion group 10a and a second photoelectric conversion group 10b.

[0050] The first photoelectric conversion group 10a may include a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a first transfer transistor TX1, and a second transfer transistor TX2. The first transfer transistor TX1 and the second transfer transistor TX2 transfer the charge accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the floating diffusion region FD.

[0051] The second photoelectric conversion group 10b may include a third photoelectric conversion element PD3, a fourth photoelectric conversion element PD4, a third transfer transistor TX3, and a fourth transfer transistor TX4. The third transfer transistor TX3 and the fourth transfer transistor TX4 transfer the charge accumulated in the third photoelectric conversion element PD3 and the fourth photoelectric conversion element PD4 to the floating diffusion region FD.

[0052] The first to fourth transfer transistors TX1, TX2, TX3 and TX4 can share the floating diffusion region FD. The transfer gate electrodes of the first to fourth transfer transistors TX1, TX2, TX3 and TX4 can be controlled by the first to fourth transfer signals TS1, TS2, TS3 and TS4.

[0053] Specifically, the first to fourth photoelectric conversion elements PD1 to PD4 can generate and accumulate charges corresponding to the incident light. The first to fourth photoelectric conversion elements PD1 to PD4 can be, for example, photodiodes, phototransistors, photogates, pinned photodiodes (PPDs), or combinations thereof.

[0054] The floating diffusion region FD receives and accumulates the charge generated in at least one of the first to fourth photoelectric conversion elements PD1 to PD4. The source follower transistor SF can be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0055] The pixel circuit 20P may include a reset transistor RX, a source follower transistor SF, and a select transistor SX. In some embodiments, each unit pixel PX is disclosed to include three pixel transistors; however, the example embodiments are not limited thereto. The number of pixel transistors in each unit pixel PX may vary.

[0056] Specifically, the reset transistor RX can periodically reset the charge accumulated in the floating diffusion region FD by applying a reset signal RG to the reset gate electrode. More specifically, the reset transistor RX may include a source terminal connected to the floating diffusion region FD and a terminal connected to the power supply voltage V. PIX The drain terminal. When the reset transistor RX is turned on, the power supply voltage V... PIX It can be transferred to the floating diffusion region FD. Therefore, the charge accumulated in the floating diffusion region FD can be discharged to reset the floating diffusion region FD.

[0057] The source follower transistor SF can be a source follower buffer amplifier configured to generate a source-drain current proportional to the amount of charge input to the floating diffusion region FD of the source follower gate electrode. The source follower transistor SF can amplify the potential change of the charge sense node, and the amplified signal can be output to the output line Vout via the selection transistor SX. The source follower transistor SF may include components connected to the supply voltage V. PIX The drain terminal and the source terminal connected to the drain terminal of the select transistor SX.

[0058] The select transistor SX can be used to select a row of unit pixels P to be read. When the select transistor SX is turned on by the select signal SG applied to the select gate electrode, the electrical signal output to the source terminal of the source follower transistor SF can be transmitted to the output line Vout.

[0059] refer to Figure 2BThe photoelectric conversion circuit 10P may include a first photoelectric conversion group 10a, a second photoelectric conversion group 10b, a third photoelectric conversion group 10c, and a fourth photoelectric conversion group 10d. Each of the first photoelectric conversion group 10a, the second photoelectric conversion group 10b, the third photoelectric conversion group 10c, and the fourth photoelectric conversion group 10d may include two photoelectric conversion elements and two transfer transistors.

[0060] In detail, the photoelectric conversion circuit 10P may include first photoelectric conversion elements PD1 to eighth photoelectric conversion elements PD8, first transfer transistors TX1 to eighth transfer transistors TX8, and a floating diffusion region FD. Here, the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2, as well as the first transfer transistor TX1 and the second transfer transistor TX2, can constitute a first photoelectric conversion group 10a. The third photoelectric conversion element PD3 and the fourth photoelectric conversion element PD4, as well as the third transfer transistor TX3 and the fourth transfer transistor TX4, can constitute a second photoelectric conversion group 10b.

[0061] The fifth photoelectric conversion element PD5 and the sixth photoelectric conversion element PD6, as well as the fifth transfer transistor TX5 and the sixth transfer transistor TX6, can constitute the third photoelectric conversion group 10c. The seventh photoelectric conversion element PD7 and the eighth photoelectric conversion element PD8, as well as the seventh transfer transistor TX7 and the eighth transfer transistor TX8, can constitute the fourth photoelectric conversion group 10d.

[0062] The first to fourth photoelectric conversion groups 10a, 10b, 10c, and 10d can be collectively connected to the floating diffusion region FD. In other words, the first transfer transistor TX1 to the eighth transfer transistor TX8 can be collectively connected to the floating diffusion region FD.

[0063] Although each of the first to fourth photoelectric conversion groups 10a, 10b, 10c and 10d is shown to include two photodiodes, the disclosed concept is not limited thereto, and each photoelectric conversion group may include four or eight photodiodes.

[0064] The transfer gate electrodes of the first transfer transistor TX1 to the eighth transfer transistor TX8 can be controlled by the first charge transfer signal TS1 to the eighth charge transfer signal TS8. Each transfer transistor in this document can have a dual vertical gate structure. A dual vertical gate structure can mean that there are two vertical transfer gates corresponding to a photodiode. The same transfer control signal can be applied to each of the two vertical transfer gates included in the dual vertical gate structure.

[0065] The floating diffusion region FD can receive and accumulate the charge generated in at least one of the first photoelectric conversion elements PD1 to the eighth photoelectric conversion elements PD8. The source follower transistor SF can be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0066] The pixel circuit 20P may include the reference above. Figure 2A The described reset transistor RX, source follower transistor SF, and select transistor SX may also include a dual-conversion gain transistor DCX.

[0067] The dual-conversion-gain transistor DCX can be connected between the floating diffuse region FD and the reset transistor RX. When the reset transistor RX and the dual-conversion-gain transistor DCX are turned on, the supply voltage V... PIX It can be transferred to the floating diffusion region FD. Therefore, the charge accumulated in the floating diffusion region FD can be discharged to reset the floating diffusion region FD.

[0068] The dual conversion gain transistor DCX can change the capacitance of the floating diffusion region FD in response to the dual conversion gain control signal DCG, thereby changing the conversion gain of the unit pixel PX.

[0069] In detail, during image capture, both low-brightness and high-brightness light can be incident on the pixel array, and the dual conversion gain transistor DCX can be turned on in high-brightness mode and turned off in low-brightness mode. Due to the dual conversion gain transistor DCX, different conversion gains can be achieved in high-brightness and low-brightness modes.

[0070] When the dual-conversion-gain transistor DCX is turned on, the capacitance of the floating diffusion region FD can increase and the conversion gain can decrease; conversely, when the dual-conversion-gain transistor DCX is turned off, the capacitance of the floating diffusion region FD can decrease and the conversion gain can increase.

[0071] Figure 3 This is a plan view illustrating a portion of an image sensor according to an embodiment of the disclosed concept. Figure 4A , Figure 4B and Figure 4C They are along Figure 3 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0072] refer to Figure 3 , Figure 4A , Figure 4B and Figure 4C An image sensor according to some example embodiments may include a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and an optical transparency layer 30.

[0073] In the cross-sectional view, the photoelectric conversion circuit layer 10 can be disposed between the pixel circuit layer 20 and the optically transparent layer 30. The photoelectric conversion circuit layer 10 may include a semiconductor substrate 100, a PD isolation pattern PIS, a device isolation layer STI, photoelectric conversion regions 110a and 110b, transfer gate electrodes TG1 and TG2, and a floating diffusion region FD.

[0074] Pixel circuit layer 20 may include pixel circuitry (e.g., MOS transistors) electrically connected to the floating diffusion region FD. That is, pixel circuit layer 20 may include a reference... Figure 2A and Figure 2B The described reset transistor RX, select transistor SX, dual-conversion gain transistor DCX, and source follower transistor SF, and connected to... Figures 2A to 2B The pixel circuit has 20P interconnects.

[0075] Specifically, the semiconductor substrate 100 may have a first surface 100a (or front surface) and a second surface 100b (or rear surface) opposite to the first surface 100a. The semiconductor substrate 100 may be or may include a substrate of a first conductivity type (e.g., p-type), comprising a bulk silicon substrate and an epitaxial layer located on the bulk silicon substrate. If the bulk silicon substrate is removed during the process of manufacturing the image sensor, the semiconductor substrate 100 may have only a p-type epitaxial layer. In some example embodiments, the semiconductor substrate 100 may be a bulk semiconductor substrate including a well of a first conductivity type.

[0076] The semiconductor substrate 100 may include a plurality of PD regions PR1, PR2, PR3 and PR4 defined by a PD isolation pattern PIS. The plurality of PD regions PR1, PR2, PR3 and PR4 may be arranged on a first direction D1 and a second direction D2 intersecting the first direction D1, or arranged in a matrix shape.

[0077] The plurality of PD regions may include a first PD region PR1, a second PD region PR2, a third PD region PR3, and a fourth PD region PR4. The first PD region PR1 and the second PD region PR2 may be arranged adjacent to each other in a first direction D1, and the first PD region PR1 and the third PD region PR3 may be arranged adjacent to each other in a second direction D2. The second PD region PR2 and the fourth PD region PR4 may be adjacent to each other in the second direction D2, and the second PD region PR2 and the third PD region PR3 may be arranged diagonally. Here, the first direction D1 and the second direction D2 are parallel to and may intersect each other with the first surface 100a of the semiconductor substrate 100. The third direction D3 may be a direction perpendicular to the first surface 100a of the semiconductor substrate 100.

[0078] The first PD regions PR1 to the fourth PD regions PR4 can constitute a single PD group GPX. In some embodiments, each PD group GPX is shown as including four PD regions PR1, PR2, PR3 and PR4, but the disclosed concept is not limited thereto. For example, the PD group GPX can consist of 6, 8, 9, 16, etc. PD regions.

[0079] In the plan view, each of the first PD regions PR1 to the fourth PD regions PR4 may be surrounded by a PD isolation pattern PIS. Each of the first PD regions PR1 to the fourth PD regions PR4 may be defined by a pair of first portions Pa extending in the first direction D1 and a pair of second portions Pb extending in the second direction D2. Furthermore, the PD isolation pattern PIS may include at least one third portion Pc in each of the first PD regions PR1 to the fourth PD regions PR4. The third portion Pc may extend from the first portion Pa in the second direction D2.

[0080] In some embodiments, the PD isolation pattern PIS can penetrate the semiconductor substrate 100. Specifically, the PD isolation pattern PIS can have a length in a direction perpendicular to the surface of the semiconductor substrate 100 (i.e., third direction D3), and the length of the PD isolation pattern PIS can be substantially the same as the vertical thickness of the semiconductor substrate 100. As another example, the PD isolation pattern PIS can extend perpendicularly from a first surface 100a of the semiconductor substrate 100 to a second surface 100b, and can be spaced apart from the second surface 100b of the semiconductor substrate.

[0081] In some embodiments, the PD isolation pattern PIS may include a pad insulating pattern 111, a buried pattern 113, and a cover insulating pattern 115. The buried pattern 113 may penetrate vertically through a portion of the semiconductor substrate 100, and the pad insulating pattern 111 may be provided between the buried pattern 113 and the semiconductor substrate 100. The cover insulating pattern 115 may be disposed on the buried pattern 113. Each of the pad insulating pattern 111 and the cover insulating pattern 115 may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The buried pattern 113 may include an undoped polysilicon layer and / or a doped polysilicon layer. The buried pattern 113 may include an air gap or may define a void. The cover insulating pattern 115 of the PD isolation pattern PIS may be formed of or comprise the same insulating material as the device isolation layer STI, and in this case, there may be no visible or observable boundary or interface between the cover insulating pattern 115 and the device isolation layer STI.

[0082] According to some example embodiments, in each of the first PD regions PR1 to the fourth PD regions PR4, a first photoelectric conversion region 110a and a second photoelectric conversion region 110b can be provided in the semiconductor substrate 100. Light incident from the outside can be converted into electrical signals in the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0083] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be impurity regions doped with impurities of a second conductivity type (e.g., n-type) opposite to the first conductivity type of the semiconductor substrate 100. The semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can constitute a pair of photodiodes. For example, a junction serving as a photodiode can be formed from the semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion region 110a or the second photoelectric conversion region 110b of the second conductivity type. When light is incident on the first photoelectric conversion region 110a and the second photoelectric conversion region 110b constituting the photodiode, photocharge proportional to the intensity of the incident light can be generated and accumulated.

[0084] In each of the first PD regions PR1 to the fourth PD regions PR4, the electrical signals output from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may have a phase difference. The image sensor can be configured to measure the distance to a target object based on the phase difference between the electrical signals output from the paired first photoelectric conversion regions 110a and second photoelectric conversion regions 110b, to check whether the target object is in focus or to what extent it is out of focus, and to correct, for example, automatically correct the focus of the image sensor based on the check result.

[0085] Each of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may have a first width in the first direction D1 and a first length greater than the first width in the second direction D2. In some embodiments, the first length may be approximately twice the first width.

[0086] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be spaced apart from each other in the first direction D1, with the third portion Pc of the PD isolation pattern PIS located between them. The third portion Pc of the PD isolation pattern PIS can be configured to physically reflect incident light at the edge of each of the first PD regions PR1 to the fourth PD regions PR4, thereby reducing crosstalk between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0087] In each of the first PD regions PR1 to the fourth PD regions PR4, the device isolation layer STI may be configured to be adjacent to the first surface 100a of the semiconductor substrate 100. The lower surface of the device isolation layer STI may be spaced apart from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0088] A device isolation layer (STI) can be provided in a trench formed by recessing a portion of a first surface 100a of a semiconductor substrate 100. The device isolation layer STI can be formed of an insulating material. In some embodiments, the device isolation layer STI may include a pad oxide layer and a pad nitride layer formed to conformally cover the inner surface of the trench, and a buried oxide layer filling the trench in which the pad oxide layer and the pad nitride layer are formed. The buried oxide layer may include at least one of, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

[0089] According to some embodiments, the device isolation layer STI may define a first active portion ACT1 and a second active portion ACT2 in each of the first PD regions PR1 to the fourth PD regions PR4. In some example embodiments, a first active portion ACT1 and two second active portions ACT2 may be provided in each of the PD regions PR1 to PR4, but the example embodiments are not limited thereto.

[0090] The first active portion ACT1 and the second active portion ACT2 can be part of the semiconductor substrate 100. The first active portion ACT1 and the second active portion ACT2 can have various polygonal shapes, such as rhombuses.

[0091] In some example embodiments, the first active portion ACT1 may include a first portion overlapping with the first photoelectric conversion region 110a, a second portion overlapping with the second photoelectric conversion region 110b, and a connecting portion connecting the first portion and the second portion. The connecting portion of the first active portion ACT1 may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0092] In the plan view, the second active portion ACT2 may overlap with the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. The second active portion ACT2 may be separated from the first active portion ACT1 by the device isolation layer STI between them. The second active portion ACT2 may have a long axis in the second direction D2 and a short axis in the first direction D1. Each second active portion ACT2 may have a second length in the second direction D2 that is smaller than the first length of the first photoelectric conversion region 110a or the second photoelectric conversion region 110b.

[0093] The first active portion ACT1 and the second active portion ACT2 of the third PD region PR3 and the fourth PD region PR4 can be set in a mirror-symmetric manner with the first active portion ACT1 and the second active portion ACT2 of the first PD region PR1 and the second PD region PR2.

[0094] In each of the first PD regions PR1 to the fourth PD regions PR4, a first transfer gate electrode TG1 and a second transfer gate electrode TG2 may be disposed on a first surface 100a of the semiconductor substrate 100. The first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be disposed on a first active portion ACT1. A portion of the first transfer gate electrode TG1 and a portion of the second transfer gate electrode TG2 may be disposed in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. A gate insulating layer may be disposed between the first transfer gate electrode TG1 and the second transfer gate electrode TG2 and the semiconductor substrate 100. An insulating spacer SP may be disposed on the opposite sidewalls of each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0095] In some embodiments, each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may have a dual vertical gate electrode structure in which two vertical portions extend into the semiconductor substrate 100. In some embodiments, the shape and position of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be modified differently.

[0096] In each of the first PD regions PR1 to the fourth PD regions PR4, the floating diffusion region FD can be provided in the portion of the first active portion ACT1 between the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0097] The floating diffusion region FD can be formed by doping with a dopant of a second conductivity type opposite to the first conductivity type of the semiconductor substrate 100. For example, the floating diffusion region FD can be an n-type doped region.

[0098] In each of the first PD regions PR1 to the fourth PD regions PR4, a pixel transistor may be provided on the second active portion ACT2. The pixel transistor may include... Figure 2A and Figure 2B Source follower transistor SF, Figure 2A and Figure 2B The reset transistor RX, Figure 2B The dual-conversion gain transistor DCX and Figure 2A and Figure 2B The selection of transistor SX.

[0099] In each of the first PD region PR1 and the second PD region PR2, a first pixel gate electrode PG1 and a second pixel gate electrode PG2 may be respectively disposed on a second active portion ACT2. In the third PD region PR3, the first pixel gate electrode PG1 may be disposed on a second active portion ACT2. In the fourth PD region PR4, the second pixel gate electrode PG2 may be disposed on a second active portion ACT2.

[0100] The source / drain region SDR can be provided in the second active portion ACT2 on the opposite sides of the first pixel gate electrode PG1 and the second pixel gate electrode PG2. The insulating spacer SP can be disposed on the opposite sidewalls of the first pixel gate electrode PG1 and the second pixel gate electrode PG2.

[0101] In each of the first PD regions PR1 to the fourth PD regions PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can constitute the previous reference. Figure 2A and Figure 2B At least one of the described pixel transistors (e.g., reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and select transistor SX). The functions of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first PD region PR1 to the fourth PD region PR4 can vary.

[0102] According to some embodiments, a third pixel gate electrode can be commonly disposed on adjacent second active portions ACT2 in the third PD region PR3 and the fourth PD region PR4. The third pixel gate electrode can correspond to a reference. Figure 2A and Figure 2B The source follower transistor SF is described as having a source follower gate electrode SFG.

[0103] The source / drain region SDR can be provided on the opposite side of the source follower gate electrode SFG in the second active portion ACT2. Insulating spacers SP can be disposed on the opposite sidewalls of the source follower gate electrode SFG.

[0104] The source follower gate electrode SFG may be longer than the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first direction D1. In some embodiments, the source follower gate electrode SFG may span (or cross) the second active portions ACT2 of each other in the third PD region PR3 and the fourth PD region PR4.

[0105] According to some embodiments, the source follower gate electrode SFG may include a first portion G1 spanning a second active portion ACT2 in a third PD region PR3 and a fourth PD region PR4, and a second portion G2 extending from the first portion G1 in a second direction D2 and configured to be adjacent to the floating diffusion region FD of the first PD region PR1 and the second PD region PR2. The second portion G2 of the source follower gate electrode SFG may be disposed on a PD isolation pattern PIS or a device isolation layer STI.

[0106] A second portion G2 of the source follower gate electrode SFG may be adjacent to the floating diffusion region FD in the first PD region PR1, and another second portion G2 may be adjacent to the floating diffusion region FD in the second PD region PR2. The width of the second portion G2 may be smaller than the width of the first portion G1.

[0107] Furthermore, a ground impurity region GR may be provided in each of the first PD regions PR1 to the fourth PD regions PR4. The ground impurity region GR may be adjacent to the first surface 100a of the semiconductor substrate 100 and may overlap with the first photoelectric conversion region 110a and the second photoelectric conversion region 110b in a planar view. The ground impurity region GR may be formed by doping with a dopant of the same first conductivity type as the semiconductor substrate 100.

[0108] According to some embodiments, an interconnect conductive pattern ICP may be formed on a first surface 100a of a semiconductor substrate 100, and the interconnect conductive pattern ICP may be in contact with a floating diffusion region FD provided in a first active portion ACT1 of each of the first PD regions PR1 to the fourth PD regions PR4.

[0109] In a planar view, the interconnect conductive pattern ICP can have various polygonal shapes, such as squares, rectangles, circles, and rhombuses. The interconnect conductive pattern ICP can be formed of or include conductive materials. The interconnect conductive pattern ICP can be formed of single-crystal silicon or polycrystalline silicon doped with a dopant of a second conductivity type. Additionally, the interconnect conductive pattern ICP can include at least one metallic material, such as tungsten, titanium, tantalum, cobalt, etc. The concentration of the dopant of the second conductivity type in the interconnect conductive pattern ICP can be higher than the doping concentration in the floating diffusion region (FD).

[0110] The interconnect conductive pattern ICP may have a first thickness on the first surface 100a of the semiconductor substrate 100, and each of the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the source follower gate electrode SFG may have a second thickness on the first surface 100a of the semiconductor substrate 100. Here, the second thickness may be greater than the first thickness.

[0111] The interconnect conductive pattern ICP of the first PD region PR1 and the second PD region PR2 can be adjacent to the second portion G2 of the source follower gate electrode SFG. The interconnect conductive pattern ICP of the third PD region PR3 and the fourth PD region PR4 can be adjacent to the first portion G1 of the source follower gate electrode SFG.

[0112] Additionally, the interconnect conductive pattern ICP may include an edge portion adjacent to its outer sidewall and a pad portion contacting the floating diffusion region FD. The interconnect conductive pattern ICP may have a first top surface at its edge portion and a second top surface at its pad portion, and the first top surface may be located at a higher horizontal level than the second top surface relative to the first surface 100a of the semiconductor substrate 100. The interconnect conductive pattern ICP may have a first lower surface contacting the device isolation layer STI and a second lower surface contacting the floating diffusion region FD, and the first and second lower surfaces may be located at different horizontal levels.

[0113] According to some embodiments, a barrier pattern BLK may be provided between the edge portion of the interconnect conductive pattern ICP and the semiconductor substrate 100, the device isolation layer STI, or the PD isolation pattern PIS. The barrier pattern BLK may be provided along the outer sidewall of the interconnect conductive pattern ICP.

[0114] The blocking pattern BLK may include the same insulating material as the insulating spacer SP disposed on the opposite sidewalls of the first transfer gate electrode TG1 and the second transfer gate electrode TG2, and on the opposite sidewalls of the first pixel gate electrode PG1 and the second pixel gate electrode PG2. The blocking pattern BLK may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The blocking pattern BLK prevents the edge portions of the interconnect conductive pattern ICP from contacting the first active portion ACT1 and the second active portion ACT2.

[0115] A first etch stop layer 140 and a second etch stop layer 150 may be sequentially stacked on a first surface 100a of a semiconductor substrate 100. The first etch stop layer 140 and the second etch stop layer 150 may cover a first transfer gate electrode TG1 and a second transfer gate electrode TG2, a first pixel gate electrode PG1 and a second pixel gate electrode PG2, a pixel gate electrode PG, and an interconnect conductive pattern ICP with a substantially uniform thickness. The first etch stop layer 140 and the second etch stop layer 150 may comprise, for example, silicon oxide, silicon nitride, or silicon oxynitride. The second etch stop layer 150 may be thicker than the first etch stop layer 140. The first etch stop layer 140 may cover the outer walls of the barrier pattern BLK and the outer walls of the interconnect conductive pattern ICP with a substantially uniform thickness.

[0116] An interlayer insulating layer 210 may be disposed on a first surface 100a of a semiconductor substrate 100, and the interlayer insulating layer 210 may cover the first transfer gate electrode TG1 and the second transfer gate electrode TG2. Figure 2A and Figure 2B The pixel transistors are RX, SF, DCX, and SX. The interlayer insulating layer 210 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0117] Figure 2A and Figure 2B The pixel circuit 20P, contact plug CT, and common contact plug BCT can be disposed in the interlayer insulating layer 210.

[0118] The contact plug CT can penetrate the interlayer insulating layer 210, the first etch stop layer 140, and the second etch stop layer 150 to connect to the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the source / drain region SDR, respectively.

[0119] According to some embodiments, the common contact plug BCT can be commonly connected to the source follower gate electrode SFG and the interconnect conductive pattern ICP of the first PD region PR1 to the fourth PD region PR4.

[0120] The common contact plug BCT can connect the source follower gate electrode SFG to the interconnect conductive pattern ICP of the first PD region PR1 to the fourth PD region PR4 via a common ground connection.

[0121] Specifically, in the first PD region PR1 and the second PD region PR2, the common contact plug BCT can be disposed between the interconnect conductive pattern ICP and the second part G2 of the source follower gate electrode SFG.

[0122] In the third PD region PR3 and the fourth PD region PR4, the common contact plug BCT can be disposed between the interconnect conductive pattern ICP and the first part G1 of the source follower gate electrode SFG.

[0123] Each common contact plug (BCT) may contact a portion of the top surface of the interconnect conductive pattern (ICP) and a portion of the top surface of the source follower gate electrode (SFG). Additionally, a portion of each common contact plug (BCT) may directly contact the device isolation layer (STI) or the PD isolation pattern (PIS) between the interconnect conductive pattern (ICP) and the source follower gate electrode (SFG). Furthermore, each common contact plug (BCT) may directly contact one sidewall of the source follower gate electrode (SFG) and one sidewall of the interconnect conductive pattern (ICP).

[0124] In some example embodiments, each common contact plug BCT may have a width in a first direction D1 and a length greater than the width in a second direction D2. The length of each common contact plug BCT may be greater than the distance between the interconnect conductive pattern ICP and the second portion G2 of the source follower gate electrode SFG. In a plan view, each common contact plug BCT may have a rectangular or elliptical shape.

[0125] The bottom surface of the common contact plug BCT can extend continuously from the top surface of the interconnect conductive pattern ICP to the top surface of the source follower gate electrode SFG. The bottom surface of the common contact plug BCT can be located at a different horizontal level than the bottom surface of the contact plug CT.

[0126] The lower surface of the common contact plug BCT between the interconnect conductive pattern ICP and the source follower gate electrode SFG can be located at a lower horizontal level than the top surface of the device isolation layer STI or the PD isolation pattern PIS.

[0127] The top surface of the common contact plug BCT can be substantially coplanar with the top surface of the contact plug CT. In addition, the top surface of the common contact plug BCT can be substantially coplanar with the top surface of the interlayer insulation layer 210.

[0128] Each of the contact plug CT and the common contact plug BCT may include a blocking metal pattern 221 and a metal pattern 223. The blocking metal pattern 221 may cover the lower surface and sidewalls of the metal pattern 223 with a substantially uniform thickness. The blocking metal pattern 221 may include a conductive metal nitride layer, such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The metal pattern 223 may include a metallic material, such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or alloys thereof.

[0129] According to some embodiments, the floating diffusion region FD in the first PD region PR1 to the fourth PD region PR4 can be connected to a source follower gate electrode SFG via the interconnect conductive pattern ICP and the common contact plug BCT.

[0130] An optically transparent layer 30 may be disposed on the second surface 100b of the semiconductor substrate 100. The optically transparent layer 30 may include a planarization insulating layer 310, a grid 320, a color filter 330, and a microlens 340. The optically transparent layer 30 can perform focusing and filtering operations on light incident from the outside, and provide the light to the photoelectric conversion circuit layer 10.

[0131] The planarization insulating layer 310 may cover the second surface 100b of the semiconductor substrate 100. The planarization insulating layer 310 may be formed of a transparent insulating material and may include multiple layers. The planarization insulating layer 310 may be formed of an insulating material having a different refractive index than the semiconductor substrate 100. The planarization insulating layer 310 may include metal oxides and / or silicon oxide.

[0132] A grid 320 can be disposed on the planarized insulating layer 310. In a planar view, the grid 320 can have a grid shape similar to the PD isolation pattern PIS. In a planar view, the grid 320 can overlap with the PD isolation pattern PIS. In other words, the grid 320 can include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 and crossing the first portion. The width of the grid 320 can be substantially equal to or less than the minimum width of the PD isolation pattern PIS.

[0133] The grid 320 may include a light-blocking pattern and / or a low-refractive-index pattern. The light-blocking pattern may include, for example, a metallic material such as titanium, tantalum, or tungsten. The low-refractive-index pattern may be formed of a material having a lower refractive index than the conductive pattern. The low-refractive-index pattern may be formed of an organic material and may have a refractive index of approximately 1.1 to 1.3. For example, the grid 320 may be a polymer layer containing silica nanoparticles.

[0134] Color filter 330 may be configured to correspond to first PD regions PR1 to fourth PD regions PR4. Color filter 330 may be provided to fill the space defined by grid 320. Color filter 330 may include a red, green, or blue color filter or a magenta, cyan, or yellow color filter determined based on the position of a unit pixel. In some embodiments, at least one color filter 330 may include an infrared color filter.

[0135] Microlens 340 may be disposed on color filter 330. Microlens 340 may have a convex shape and a predetermined radius of curvature. Microlens 340 may be formed of optically transparent resin. Microlens 340 may be disposed on color filter 330 to correspond to each of PD regions PR1 to PR4. In some embodiments, at least one microlens 340 may be commonly disposed on at least two PD regions PR1 to PR4.

[0136] The following describes image sensors based on various exemplary embodiments of the disclosed concepts. For the sake of brevity, references to the above may be omitted from the following description. Figure 3 , Figure 4A , Figure 4B and Figure 4C The image sensors described share the same technical features, and different technical features will also be described.

[0137] Figure 5A and Figure 5B This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0138] refer to Figure 5A The first PD area PR1 to the fourth PD area PR4 can form a PD group GPX.

[0139] A first source follower gate electrode SFG1 can be provided on the first PD region PR1 and the third PD region PR3, and a second source follower gate electrode SFG2 can be provided on the second PD region PR2 and the fourth PD region PR4.

[0140] Each of the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 may include a first portion G1 located on the second active portion ACT2 and a second portion G2 extending from the first portion G1 and disposed on the PD isolation pattern PIS or the device isolation layer STI. The first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 may be arranged in a mirror-symmetric manner with each other.

[0141] The first source follower gate electrode SFG1 can be connected to the common ground of the interconnect conductive pattern ICP of the first PD region PR1 and the third PD region PR3 via the common contact plug BCT. The second source follower gate electrode SFG2 can be connected to the common ground of the interconnect conductive pattern ICP of the second PD region PR2 and the fourth PD region PR4 via the common contact plug BCT.

[0142] refer to Figure 5B The first PD region PR1 to the fourth PD region PR4 can constitute a PD group GPX, and the PD group GPX can include an interconnect conductive pattern ICP.

[0143] In detail, the interconnect conductive pattern ICP can be publicly connected to the floating diffusion region FD in the first PD region PR1 to the fourth PD region PR4.

[0144] In a plan view, the interconnected conductive pattern ICP may include a first connection portion CP1 that contacts the floating diffusion region FD, a second connection portion CP2 that extends from the first connection portion CP1 in a second direction D2, and a third connection portion CP3 that extends in a first direction D1 and connects the second connection portions CP2 to each other.

[0145] The source follower gate electrode SFG can be commonly disposed on adjacent second active portions ACT2 in the third PD region PR3 and the fourth PD region PR4. The source follower gate electrode SFG may include a first portion G1 and a second portion G2 extending from the first portion G1 in a second direction D2. The first portion G1 may span across adjacent second active portions ACT2 in the third PD region PR3 and the fourth PD region PR4. The second portion G2 may be disposed on the PD isolation pattern PIS or the device isolation layer STI. The second portion G2 may be adjacent to the third connection portion CP3 of the interconnect conductive pattern ICP.

[0146] In some embodiments, the common contact plug BCT may be disposed between the third connection portion CP3 of the interconnect conductive pattern ICP and the second portion G2 of the source follower gate electrode SFG. In other words, the common contact plug BCT may directly contact the third connection portion CP3 of the interconnect conductive pattern ICP and the second portion G2 of the source follower gate electrode SFG.

[0147] Figure 6 This is a plan view illustrating an image sensor according to an embodiment of the present invention. Figure 7A , Figure 7B and Figure 7C They are along Figure 6 The cross-sectional views taken from lines D-D', E-E', and F-F'.

[0148] refer to Figure 6 , Figure 7A , Figure 7B and Figure 7C The PD isolation pattern PIS defining the first PD region PR1 to the fourth PD region PR4 can be disposed in the semiconductor substrate 100.

[0149] In the plan view, each of the first PD regions PR1 to the fourth PD regions PR4 can be surrounded by a PD isolation pattern PIS. Each of the first PD regions PR1 to the fourth PD regions PR4 can be defined by a pair of first portions Pa extending in the first direction D1 and a pair of second portions Pb extending in the second direction D2. Additionally, the PD isolation pattern PIS can include a pair of third portions Pc in each of the first PD regions PR1 to the fourth PD regions PR4. The third portions Pc can extend from the first portions Pa in the second direction D2 or from the second portions Pb in the first direction D1, and can be spaced apart from each other.

[0150] In each of the first PD regions PR1 to the fourth PD regions PR4, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be provided in the semiconductor substrate 100.

[0151] In each of the first PD regions PR1 to the fourth PD regions PR4, the device isolation layer STI may be configured to be adjacent to the first surface 100a of the semiconductor substrate 100. The bottom surface of the device isolation layer STI may be spaced apart from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0152] According to some embodiments, the device isolation layer STI may define a first active portion ACT1 and a second active portion ACT2 in each of the first PD regions PR1 to the fourth PD regions PR4. The first active portion ACT1 and the second active portion ACT2 may be part of the semiconductor substrate 100. In a plan view, the first active portion ACT1 and the second active portion ACT2 may overlap with each of the first photoelectric conversion regions 110a and the second photoelectric conversion region 110b. In other words, two first active portions ACT1 and two second active portions ACT2 may be provided in each of the PD regions PR1 to PR4, but the exemplary embodiments are not limited thereto.

[0153] The first active portion ACT1 and the second active portion ACT2 can be spaced apart from each other in the second direction D2 by a device isolation layer STI, and can have different sizes and shapes. The first active portion ACT1 can have a "T" shape, but the example embodiment is not limited to this; for example, the first active portion ACT1 can have a rectangular shape or various polygonal shapes. The second active portion ACT2 can have a major axis in the second direction D2 and a minor axis in the first direction D1. The first photoelectric conversion region 110a or the second photoelectric conversion region 110b can have a first length in the second direction D2, and each second active portion ACT2 can have a second length in the second direction D2 that is less than the first length.

[0154] The first active portion ACT1 and the second active portion ACT2 of the third PD region PR3 and the fourth PD region PR4 can be set in a mirror-symmetric manner with the first active portion ACT1 and the second active portion ACT2 of the first PD region PR1 and the second PD region PR2.

[0155] In each of the first PD regions PR1 to the fourth PD regions PR4, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be respectively disposed on the first active portion ACT1. Each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may have a dual vertical gate electrode structure including two vertical portions extending into the semiconductor substrate 100.

[0156] In each of the first PD regions PR1 to the fourth PD regions PR4, a first floating diffusion region FD1 may be provided in a first active portion ACT1 on one side of the first transfer gate electrode TG1. A second floating diffusion region FD2 may be provided in a first active portion ACT1 on one side of the second transfer gate electrode TG2.

[0157] Each of the first floating diffusion region FD1 and the second floating diffusion region FD2 may include a first doped region FDa and a second doped region FDb within the first doped region FDa. The doping concentration of the second doped region FDb may be higher than the doping concentration of the first doped region FDa.

[0158] Furthermore, in each of the first PD regions PR1 to the fourth PD regions PR4, a ground impurity region GR may be provided between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The ground impurity region GR may be provided between the third portions Pc of the PD isolation pattern PIS. The ground impurity region GR may be formed by doping with a dopant of the same first conductivity type as the semiconductor substrate 100.

[0159] According to some embodiments, the interconnect conductive pattern ICP can be disposed on a first surface 100a of the semiconductor substrate 100, and can be commonly connected to a first floating diffusion region FD1 and a second floating diffusion region FD2 provided in the first PD regions PR1 to the fourth PD regions PR4. A portion of the interconnect conductive pattern ICP can contact the top surface of the device isolation layer STI and the top surface of the PD isolation pattern PIS.

[0160] Interconnected conductive patterned silicon cores (ICPs) can be formed from conductive materials. Interconnected conductive patterned ICPs can be formed from monocrystalline or polycrystalline silicon doped with dopants of a second conductivity type.

[0161] The interconnect conductive pattern ICP may include an edge portion adjacent to its outer sidewall and a pad portion contacting the first floating diffusion region FD1 and the second floating diffusion region FD2. Additionally, in a plan view, the interconnect conductive pattern ICP may have a substantially uniform width in the second direction D2 and may extend along the first direction D1.

[0162] In each of the first PD region PR1, the second PD region PR2, and the fourth PD region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be respectively disposed on the second active portion ACT2. In each of the first PD region PR1, the second PD region PR2, and the fourth PD region PR4, the first pixel gate electrode PG1 may overlap with the first photoelectric conversion region 110a, and the second pixel gate electrode PG2 may overlap with the second photoelectric conversion region 110b.

[0163] In the third PD region PR3, the source follower gate electrode SFG can be disposed on the second active portion ACT2. In the third PD region PR3, the source follower gate electrode SFG can be longer than the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first direction D1. For example, the source follower gate electrode SFG can span the second active portion ACT2 of the third PD region PR3.

[0164] As described above, the source follower gate electrode SFG may include a first portion G1 spanning the second active portion ACT2 and a second portion G2 extending from the first portion G1 in the second direction D2 and disposed on the PD isolation pattern PIS or the device isolation layer STI. The second portion G2 may be configured to be adjacent to the interconnect conductive pattern ICP. For example, the second portion G2 of the source follower gate electrode SFG may be disposed on the PD isolation pattern PIS between the third PD region PR3 and the fourth PD region PR4.

[0165] The common contact plug BCT can electrically connect the source follower gate electrode SFG and the interconnect conductive pattern ICP. The common contact plug BCT can be located between the second part G2 of the source follower gate electrode SFG and the interconnect conductive pattern ICP.

[0166] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figure 6 , Figure 7A , Figure 7B and Figure 7C The image sensors described have the same technical features, and different technical features will be described below.

[0167] refer to Figure 8A The first interconnect conductive pattern ICP1 can be disposed on the first PD region PR1 and the third PD region PR3, and the first source follower gate electrode SFG1 can be provided on a second active portion ACT2 of the third PD region PR3.

[0168] The second interconnect conductive pattern ICP2 can be disposed on the second PD region PR2 and the fourth PD region PR4, and the second source follower gate electrode SFG2 can be provided in a second active portion ACT2 of the fourth PD region PR4.

[0169] Each of the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 may include a first portion G1 spanning a second active portion ACT2 and a second portion G2 extending from the first portion G1 in a second direction D2 and disposed on the PD isolation pattern PIS or the device isolation layer STI.

[0170] The first interconnect conductive pattern ICP1 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the second PD region PR2 and the fourth PD region PR4.

[0171] The common contact plug BCT can be connected between the first interconnect conductive pattern ICP1 and the first source follower gate electrode SFG1, and between the second interconnect conductive pattern ICP2 and the second source follower gate electrode SFG2, respectively.

[0172] refer to Figure 8B As described above, the first source follower gate electrode SFG1 can be provided on a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided on a second active portion ACT2 of the second PD region PR2. In the plan view, the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 can be arranged point-symmetrically.

[0173] refer to Figure 8C ,and Figure 8A Unlike the embodiments shown, the ground impurity region GR can be provided between the first PD region PR1 and the third PD region PR3, and between the second PD region PR2 and the fourth PD region PR4.

[0174] An interconnect conductive pattern ICP can be publicly connected to the floating diffusion regions FD in the first PD region PR1 to the fourth PD region PR4, and a source follower gate electrode SFG can be provided on the second active portion ACT2 of the third PD region PR3.

[0175] The source follower gate electrode SFG may include a first portion G1 spanning the second active portion ACT2 and a second portion G2 extending from the first portion G1 in the second direction D2 and disposed on the PD isolation pattern PIS or the device isolation layer STI. In the third PD region PR3, the second portion G2 may be disposed between the first active portions ACT1 and the second active portions ACT2.

[0176] The common contact plug BCT can electrically connect the second part G2 of the source follower gate electrode SFG and the interconnect conductive pattern ICP on the third PD region PR3.

[0177] refer to Figure 8D The first source follower gate electrode SFG1 can be provided in a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided in a second active portion ACT2 of the fourth PD region PR4.

[0178] Each of the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 may include a first portion G1 spanning a second active portion ACT2 and a second portion G2 extending from the first portion G1 in a second direction D2 and disposed on a PD isolation pattern PIS or a device isolation layer STI. The second portion G2 of each of the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 may be disposed between the first active portion ACT1 and the second active portion ACT2.

[0179] refer to Figure 8E ,and Figure 8D Unlike the embodiment shown, the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the second PD region PR2. The second portion G2 of the second source follower gate electrode SFG2 can be disposed between the first active portions ACT1 and the second active portions ACT2 in the second PD region PR2.

[0180] Figure 9A , Figure 9B and Figure 9C This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figure 6 , Figure 7A , Figure 7B and Figure 7C The image sensors described have the same technical features, and different technical features will be described below.

[0181] refer to Figure 9A , Figure 9B and Figure 9C The first PD region PR1 to the fourth PD region PR4 may be defined by a PD isolation pattern PIS. In each of the first PD regions PR1 to the fourth PD regions PR4, a first active portion ACT1 and a second active portion ACT2 may be defined by a device isolation layer STI. In some embodiments, each of the first PD regions PR1 to the fourth PD regions PR4 may include two first active portions ACT1 and at least one second active portion ACT2.

[0182] Each first active portion ACT1 can be in the shape of an angle iron or the letter "L". In each of the first PD areas PR1 to the fourth PD areas PR4, the first active portion ACT1 can be arranged symmetrically to each other. The second active portion ACT2 in each of the first PD areas PR1 to the fourth PD areas PR4 can be in the shape of an L or a U.

[0183] refer to Figure 9A The pixel gate electrode PG can be disposed on the second active portion ACT2 of the first PD region PR1 and the second PD region PR2, respectively.

[0184] The source follower gate electrode SFG can be disposed on the second active portion ACT2 of the third PD region PR3 and the fourth PD region PR4. The second portion G2 of the source follower gate electrode SFG can be disposed on the PD isolation pattern PIS between the third PD region PR3 and the fourth PD region PR4.

[0185] The interconnect conductive pattern ICP can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD regions PR1 to the fourth PD regions PR4. The interconnect conductive pattern ICP can have a uniform width and extend in the first direction D1.

[0186] refer to Figure 9B The first interconnect conductive pattern ICP1 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 in the second PD region PR2 and the fourth PD region PR4.

[0187] The first source follower gate electrode SFG1 can be provided on the second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the fourth PD region PR4.

[0188] The second part G2 of the gate electrode SFG1 of the first source follower can be disposed between the first active part ACT1 of the third PD region PR3. The second part G2 of the gate electrode SFG2 of the second source follower can be disposed between the first active part ACT1 of the fourth PD region PR4.

[0189] refer to Figure 9C ,and Figure 9BUnlike other methods, the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the second PD region PR2. The second portion G2 of the second source follower gate electrode SFG2 can be disposed between the first active portions ACT1 in the second PD region PR2.

[0190] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figure 6 , Figure 7A , Figure 7B and Figure 7C The image sensors described have the same technical features, and different technical features will be described below.

[0191] refer to Figures 10A to 10F The first PD region PR1 to the fourth PD region PR4 can be defined by the PD isolation pattern PIS. In each of the first PD region PR1 to the fourth PD region PR4, the first active portion ACT1 and the second active portion ACT2 can be defined by the device isolation layer STI.

[0192] Each first active portion ACT1 may have a "T" shape and may be positioned diagonally relative to the first direction D1 and the second direction D2. In other words, the first active portion ACT1 may be tilted relative to the first direction D1 and the second direction D2.

[0193] refer to Figure 10A The interconnect conductive pattern ICP can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 in the first PD region PR1 to the fourth PD region PR4. In some embodiments, the interconnect conductive pattern ICP may include a first connecting portion that contacts the first floating diffusion region FD1 and the second floating diffusion region FD2 in the first PD region PR1 and the third PD region PR3, a second connecting portion that contacts the first floating diffusion region FD1 and the second floating diffusion region FD2 in the second PD region PR2 and the fourth PD region PR4, and a third connecting portion that connects the first connecting portion and the second connecting portion. Here, the first connecting portion and the second connecting portion may have a circular shape, and the third connecting portion may have a linear shape.

[0194] In the third PD region PR3, the source follower gate electrode SFG can be disposed on the second active portion ACT2 of the third PD region PR3. The second portion G2 of the source follower gate electrode SFG can be disposed on the PD isolation pattern PIS between the third PD region PR3 and the fourth PD region PR4, and can be electrically connected to the interconnect conductive pattern ICP through the common contact plug BCT.

[0195] refer to Figure 10B The first interconnect conductive pattern ICP1 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 in the second PD region PR2 and the fourth PD region PR4.

[0196] Each of the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2 may include a first connection portion that commonly contacts the first floating diffusion region FD1 and the second floating diffusion region FD2, and a second connection portion that extends from the first connection portion in a first direction D1 and is disposed on the PD isolation pattern PIS or the device isolation layer STI.

[0197] The first source follower gate electrode SFG1 can be provided in a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided in a second active portion ACT2 of the fourth PD region PR4.

[0198] A common contact plug BCT can connect the second connection portion of the first interconnect conductive pattern ICP1 and the second portion G2 of the first source follower gate electrode SFG1. Another common contact plug BCT can connect the second connection portion of the second interconnect conductive pattern ICP2 and the second portion G2 of the second source follower gate electrode SFG2.

[0199] refer to Figure 10C ,and Figure 10B Unlike other source follower devices, the first source follower gate electrode SFG1 can be provided in a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided in a second active portion ACT2 of the second PD region PR2. In a plan view, the first source follower gate electrode SFG1 and the second source follower gate electrode SFG2 can be arranged symmetrically at points.

[0200] refer to Figure 10D ,and Figure 10AUnlike the embodiment shown, in the third PD region PR3, the source follower gate electrode SFG can be disposed on the second active portion ACT2 of the third PD region PR3, and the second portion G2 of the source follower gate electrode SFG can be disposed between the first active portion ACT1 and the second active portion ACT2 of the third PD region PR3.

[0201] refer to Figure 10E The first interconnect conductive pattern ICP1 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the second PD region PR2 and the fourth PD region PR4.

[0202] The first source follower gate electrode SFG1 can be provided on the second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the fourth PD region PR4.

[0203] The second part G2 of the gate electrode SFG1 of the first source follower can be disposed between the first active part ACT1 of the third PD region PR3. The second part G2 of the gate electrode SFG2 of the second source follower can be disposed between the first active part ACT1 of the fourth PD region PR4.

[0204] refer to Figure 10F ,and Figure 10D Unlike the embodiment shown, the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the second PD region PR2. The second portion G2 of the second source follower gate electrode SFG2 can be disposed between the first active portions ACT1 of the second PD region PR2.

[0205] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0206] refer to Figure 11A The semiconductor substrate 100 may include a plurality of PD groups GPX1 to GPX4. Each of the PD groups GPX1 to GPX4 may include at least 4, 8, or 16 PD regions PR1 to PR4. In each of the PD groups GPX1 to GPX4, the PD regions PR1 to PR4 may be arranged in a matrix shape along a first direction D1 and a second direction D2 that intersect each other.

[0207] The first photoelectric conversion region 110a to the fourth photoelectric conversion region 110d can be provided in the first PD region PR1 to the fourth PD region PR4, respectively.

[0208] A common active portion ACT can be provided in each of the PD groups GPX1 to GPX4, and a second active portion ACT2 can be provided in each of the first PD regions PR1 to the fourth PD regions PR4. In other words, the common active portion ACT can be commonly provided to the first PD regions PR1 to the fourth PD regions PR4. The common active portion ACT and the second active portion ACT2 can be defined by a device isolation layer STI adjacent to the first surface 100a of the semiconductor substrate 100.

[0209] The first transfer gate electrode TG1 to the fourth transfer gate electrode TG4 can be provided on the common active portion ACT in each of the first PD regions PR1 to the fourth PD regions PR4. As described above, each of the first to fourth transfer gate electrodes TG1, TG2, TG3 and TG4 can have a dual vertical gate electrode structure including two vertical portions extending into the semiconductor substrate.

[0210] A common floating diffusion region CFD can be provided in the common active portion ACT at the center of each PD group GPX1 to GPX4. In some embodiments, the common floating diffusion region CFD can be commonly provided in the first PD regions PR1 to the fourth PD regions PR4. The first portions Pa of the PD isolation pattern PIS can be spaced apart from each other in the first direction D1, and the second portions Pb of the PD isolation pattern PIS can be spaced apart from each other in the second direction D2. The common floating diffusion region CFD can be disposed between the first portions Pa and between the second portions Pb.

[0211] The interconnect conductive pattern ICP can be connected to the common floating diffusion region CFD in each of the PD groups GPX1 to GPX4. As described above, the interconnect conductive pattern ICP can directly contact the common floating diffusion region CFD located on the first surface 100a of the semiconductor substrate 100.

[0212] In each of the first PD regions PR1 to the fourth PD regions PR4 of each of the PD groups GPX1 to GPX4, a pixel transistor may be provided on the second active portion ACT2. The first to fourth pixel gate electrodes PG1, PG2, PG3 and SFG may be provided on the second active portion ACT2 of the first PD regions PR1 to the fourth PD regions PR4.

[0213] The fourth pixel gate electrode can be a reference. Figure 2A and Figure 2BThe source follower transistor SX is described with a source follower gate electrode SFG. The source follower gate electrode SFG may be provided on at least one second active portion ACT2 in each of the PD groups GPX1 to GPX4. The location of the source follower gate electrode SFG may be different from each other in the PD groups GPX1 to GPX4.

[0214] In some embodiments, the source follower gate electrode SFG in the first PD group GPX1 and the second PD group GPX2 can be disposed on the second active portion ACT2 of the fourth PD region PR4, and the source follower gate electrode SFG in the third PD group GPX3 and the fourth PD group GPX4 can be disposed on the second active portion ACT2 of the third PD region PR3.

[0215] The source follower gate electrode SFG may include a first portion G1 disposed on a second active portion ACT2 and a second portion G2 extending from the first portion G1 and disposed on a device isolation layer STI or a PD isolation pattern PIS. The second portion G2 of the source follower gate electrode SFG may be disposed between adjacent second active portions ACT2 and may be adjacent to an interconnect conductive pattern ICP.

[0216] The common contact plug BCT is located between the second part G2 of the source follower gate electrode SFG and the interconnect conductive pattern ICP, and can electrically connect the source follower gate electrode SFG to the interconnect conductive pattern ICP.

[0217] refer to Figure 11B ,and Figure 11A Unlike the embodiments shown, the first interconnect conductive pattern ICP1 can be commonly connected to a common floating diffusion region CFD provided in the first PD group GPX1 and the third PD group GPX3. The second interconnect conductive pattern ICP2 can be commonly connected to a common floating diffusion region CFD provided in the second PD group GPX2 and the fourth PD group GPX4.

[0218] In some embodiments, each of the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2 may include a first connection portion CP1 in contact with the common floating diffusion region CFD of the first PD group GPX1 or the second PD group GPX2, a second connection portion CP2 in contact with the common floating diffusion region CFD of the third PD group GPX3 or the fourth PD group GPX4, and a third connection portion CP3 connecting the first connection portion CP1 and the second connection portion CP2. Here, the first connection portion CP1 and the second connection portion CP2 may have a circular shape or a quadrilateral shape, and the third connection portion CP3 may have a linear shape.

[0219] The first source follower gate electrode SFG1 can be commonly provided to the fourth PD region PR4 of the first PD group GPX1 and the second PD region PR2 of the third PD group GPX3, and the second source follower gate electrode SFG2 can be commonly provided to the fourth PD region PR4 of the second PD group GPX2 and the second PD region PR2 of the fourth PD group GPX4.

[0220] The second part G2 of the gate electrode SFG1 of the first source follower can be disposed on the PD isolation pattern PIS between the first PD group GPX1 and the third PD group GPX3. The second part G2 of the gate electrode SFG2 of the second source follower can be disposed on the PD isolation pattern PIS between the second PD group GPX2 and the fourth PD group GPX4.

[0221] refer to Figure 11C ,and Figure 11B Unlike the embodiment shown, the source follower gate electrode SFG can be commonly provided to the first PD group GPX1 through the fourth PD group GPX4. In other words, the source follower gate electrode SFG can be commonly provided on four adjacent second active portions ACT2 in the first PD group GPX1 through the fourth PD group GPX4. In other words, the source follower gate electrode SFG can be provided in the fourth PD region PR4 of the first PD group GPX1, the third PD region PR3 of the second PD group GPX2, the second PD region PR2 of the third PD group GPX3, and the first PD region PR1 of the fourth PD group GPX4.

[0222] The source follower gate electrode SFG may include a second portion G2 protruding toward the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2. A common contact plug BCT may be commonly connected to the first interconnect conductive pattern ICP1, the second interconnect conductive pattern ICP2, and the second portion G2 of the source follower gate electrode SFG.

[0223] refer to Figure 11D ,and Figure 11C Unlike the embodiments shown, the first interconnect conductive pattern ICP1 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD group GPX1 and the second PD group GPX2. The second interconnect conductive pattern ICP2 can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the third PD group GPX3 and the fourth PD group GPX4. The source follower gate electrode SFG may include a second portion G2 protruding toward the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2.

[0224] Figure 12A , Figure 12C , Figure 12D , Figure 12Eand Figure 12F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. Figure 12B It is along Figure 12A A cross-sectional view taken from line G-G'.

[0225] refer to Figure 12A and Figure 12B For reference Figure 6 As described, the first PD region PR1 to the fourth PD region PR4 can be defined by a PD isolation pattern PIS. In each of the first PD region PR1 to the fourth PD region PR4, the first active portion ACT1 and the second active portion ACT2 can be defined by a device isolation layer STI.

[0226] The first active portion ACT1 may be spaced apart from the second active portion ACT2 by a device isolation layer STI in the second direction D2. The first active portion ACT1 and the second active portion ACT2 may have different sizes and shapes. For example, each first active portion ACT1 may have a T-shape, and each second active portion ACT2 may have a strip shape.

[0227] In each of the first PD region PR1, the second PD region PR2 and the fourth PD region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can be respectively disposed on the second active portion ACT2.

[0228] In the third PD region PR3, the source follower gate electrode SFG can be disposed on the second active portion ACT2. The second portion G2 of the source follower gate electrode SFG can be disposed between the third PD region PR3 and the fourth PD region PR4, and can be electrically connected to the interconnect conductive pattern ICP through a common contact plug BCT.

[0229] The interconnect conductive pattern ICP can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 to the fourth PD region PR4.

[0230] In some embodiments, a local conductive pad (LCP) may be provided on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the second PD region PR2.

[0231] Local conductive pads (LCPs) can contact the source / drain regions (SDRs) and can extend to the top surface of the device isolation layer (STI) or the PD isolation pattern (PIS). LCPs can be formed from the same conductive material as interconnect conductive patterns (ICPs) and can have substantially the same thickness.

[0232] In some embodiments, the first common contact plug BCTB can electrically connect a portion of the source follower gate electrode SFG and the interconnect conductive pattern ICP. The second common contact plug BCTB or a connection contact plug can electrically connect a second portion G2 of the interconnect conductive pattern ICP and the local conductive pad LCP. The second common contact plug BCTB can directly contact the top surface of the interconnect conductive pattern ICP and the top surface of the local conductive pad LCP.

[0233] In some embodiments, in the second PD region PR2, the first pixel gate electrode PG1 and the source / drain region SDR on the opposite side of the first pixel gate electrode PG1 can constitute Figure 2A and Figure 2B The reset transistor RX or Figure 2A and Figure 2B The dual-conversion-gain transistor DCX.

[0234] refer to Figure 12C For reference Figure 8A As described, the first source follower gate electrode SFG1 can be provided on a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided on a second active portion ACT2 of the second PD region PR2.

[0235] The first interconnect conductive pattern ICP1 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the second PD region PR2 and the fourth PD region PR4.

[0236] Each of the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2 may include a first connection portion that commonly contacts the first floating diffusion region FD1 and the second floating diffusion region FD2, and a second connection portion that extends from the first connection portion in a second direction D2 and is disposed on the PD isolation pattern PIS or the device isolation layer STI.

[0237] The first interconnect conductive pattern ICP1 can be connected to the second portion G2 of the first source follower gate electrode SFG1 via the first common contact plug BCTa. The second interconnect conductive pattern ICP2 can be connected to the second portion G2 of the second source follower gate electrode SFG2 via the first common contact plug BCTa.

[0238] In some embodiments, a first local conductive pad LCP1 may be provided on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the first PD region PR1. The first local conductive pad LCP1 may be electrically connected to the first interconnect conductive pattern ICP1 via a second common contact plug BCTb.

[0239] A second local conductive pad LCP2 can be provided on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the second PD region PR2. The second local conductive pad LCP2 can be electrically connected to the second interconnect conductive pattern ICP2 through the second common contact plug BCTb.

[0240] refer to Figure 12D ,and Figure 12C Unlike the embodiment shown, the second source follower gate electrode SFG2, the second interconnect conductive pattern ICP2, and the second local conductive pad LCP2 can be arranged symmetrically with the first source follower gate electrode SFG1, the first interconnect conductive pattern ICP1, and the first local conductive pad LCP1.

[0241] In other words, the second source follower gate electrode SFG2 can be disposed on the second active portion ACT2 of the second PD region PR2, and the second local conductive pad LCP2 can be disposed on one side of the second pixel gate electrode PG2 of the fourth PD region PR4.

[0242] refer to Figure 12E An interconnect conductive pattern ICP can be commonly connected to the floating diffusion regions FD of the first PD regions PR1 to the fourth PD regions PR4. The interconnect conductive pattern ICP may include a connection portion protruding in the second direction D2 and disposed between the first active portion ACT1 and the second active portion ACT2 of the second PD region PR2. A first common contact plug BCTa can be connected between the second portion G2 of the source follower gate electrode SFG and the interconnect conductive pattern ICP.

[0243] A source follower gate electrode SFG can be commonly disposed on the second active portion ACT2 of the third PD region PR3.

[0244] A local conductive pad (LCP) can be provided on the source / drain region SDR on one side of the second pixel gate electrode PG2 in the second PD region PR2. The LCP can contact the source / drain region SDR and can extend to the top surface of the device isolation layer STI or PD isolation pattern PIS. The LCP and the second common contact plug BCTb can be electrically connected to the connection portion of the interconnect conductive pattern ICP.

[0245] refer to Figure 12FThe first source follower gate electrode SFG1 can be provided on the second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided on the second active portion ACT2 of the fourth PD region PR4.

[0246] The first interconnect conductive pattern ICP1 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the second PD region PR2 and the fourth PD region PR4.

[0247] Each of the first interconnect conductive pattern ICP1 and the second interconnect conductive pattern ICP2 protrudes in the second direction D2 and may include a connection portion disposed on the PD isolation pattern PIS or the device isolation layer STI.

[0248] A first local conductive pad LCP1 can be provided on the source / drain region SDR on one side of the second pixel gate electrode PG2 in the first PD region PR1. The first local conductive pad LCP1 can be electrically connected to the first interconnect conductive pattern ICP1 through a second common contact plug BCTb.

[0249] A second local conductive pad LCP2 can be provided on the source / drain region SDR on one side of the second pixel gate electrode PG2 in the second PD region PR2. The second local conductive pad LCP2 can be electrically connected to the second interconnect conductive pattern ICP2 through the second common contact plug BCTb.

[0250] refer to Figure 12G ,and Figure 12F Unlike the embodiment shown, the second source follower gate electrode SFG2, the second interconnect conductive pattern ICP2, and the second local conductive pad LCP2 can be arranged symmetrically with the first source follower gate electrode SFG1, the first interconnect conductive pattern ICP1, and the first local conductive pad LCP1.

[0251] In other words, the first local conductive pad LCP1 can be disposed on one side of the second pixel gate electrode PG2 in the first PD area PR1, and the second local conductive pad LCP2 can be disposed on one side of the first pixel gate electrode PG1 in the fourth PD area.

[0252] Figure 13A , Figure 13C , Figure 13D , Figure 13E and Figure 13F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figures 10A to 10F The image sensors described have the same technical features, and different technical features will be described below.

[0253] refer to Figures 13A to 13F As shown in the reference above Figures 10A to 10F As described, each of the first active portions ACT1 in each of the first PD regions PR1 to the fourth PD regions PR4 may have a T-shape and may be set at an angle relative to the first direction D1 and the second direction D2.

[0254] refer to Figure 13A For reference Figure 10A As described, the interconnect conductive pattern ICP can be commonly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD regions PR1 to the fourth PD regions PR4. Additionally, the interconnect conductive pattern ICP may also include connection portions protruding in the second direction D2 and disposed on the device isolation layer STI or the PD isolation pattern PIS.

[0255] Additionally, as referenced Figure 12A As described, the Locally Conductive Pad (LCP) can be provided on the source / drain region (SDR) on one side of the first pixel gate electrode (PG1) in the second PD region (PR2).

[0256] refer to Figure 13B For reference Figure 12C As described, the first source follower gate electrode SFG1 can be provided in a second active portion ACT2 of the third PD region PR3, and the second source follower gate electrode SFG2 can be provided in a second active portion ACT2 of the fourth PD region PR4.

[0257] The first interconnect conductive pattern ICP1 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the first PD region PR1 and the third PD region PR3. The second interconnect conductive pattern ICP2 can be publicly connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 provided in the second PD region PR2 and the fourth PD region PR4.

[0258] In the first PD region PR1, a first local conductive pad LCP1 can be provided on the source / drain region SDR on one side of the first pixel gate electrode PG1, and in the second PD region PR2, a second local conductive pad LCP2 can be provided on the source / drain region SDR on one side of the first pixel gate electrode PG1.

[0259] refer to Figure 13C ,and Figure 13BUnlike the embodiment shown, the second source follower gate electrode SFG2, the second interconnect conductive pattern ICP2, and the second local conductive pad LCP2 can be arranged symmetrically with the first source follower gate electrode SFG1, the first interconnect conductive pattern ICP1, and the first local conductive pad LCP1.

[0260] refer to Figure 13D An interconnect conductive pattern ICP can be commonly connected to the floating diffusion regions FD of the first PD regions PR1 to the fourth PD regions PR4. The interconnect conductive pattern ICP may include a connection portion protruding in the second direction D2 and disposed between the first active portion ACT1 and the second active portion ACT2 of the first PD region PR1. A source follower gate electrode SFG can be commonly disposed on the second active portion ACT2 of the third PD region PR3. A local conductive pad LCP can be provided on the source / drain region SDR on one side of the second pixel gate electrode PG2 in the first PD region PR1. In the local conductive pad LCP, a second common contact plug BCTb can be electrically connected to the connection portion of the interconnect conductive pattern ICP in the first PD region PR1.

[0261] refer to Figure 13E For reference Figure 12F As described, the first interconnect conductive pattern ICP1 can be electrically connected to the first source follower gate electrode SFG1 and the first local conductive pad LCP1 via the first common contact plug BCTa and the second common contact plug BCTb.

[0262] The second interconnect conductive pattern ICP2 can be electrically connected to the second source follower gate electrode SFG2 and the second local conductive pad LCP2 via the first common contact plug BCTa and the second common contact plug BCTb.

[0263] refer to Figure 13F ,and Figure 13E Unlike the embodiment shown, the second source follower gate electrode SFG2, the second interconnect conductive pattern ICP2, and the second local conductive pad LCP2 can be arranged symmetrically with the first source follower gate electrode SFG1, the first interconnect conductive pattern ICP1, and the first local conductive pad LCP1.

[0264] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figure 3 , Figure 5A and Figure 5BThe image sensors described share the same technical features, and different technical features will also be described.

[0265] refer to Figure 14A ,Apart from Figure 3 In addition to the embodiments shown, the image sensor may also include a Locally Conductive Pad (LCP) in the second PD region PR2. The LCP may be disposed on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the second PD region PR2. The LCP may contact the source / drain region SDR and may extend to the top surface of the device isolation layer STI or the PD isolation pattern PIS. The LCP may be connected to the second portion G2 of the source follower gate electrode SFG via a second common contact plug BCTb.

[0266] refer to Figure 14B ,Apart from Figure 5A In addition to the embodiments shown, the image sensor may also include a first local conductive pad LCP1 in the first PD region PR1 and a second local conductive pad LCP2 in the second PD region PR2.

[0267] The first local conductive pad LCP1 can be disposed on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the first PD region PR1. The first local conductive pad LCP1 can be connected to the second part G2 of the first source follower gate electrode SFG1 through the second common contact plug BCTb.

[0268] The second local conductive pad LCP2 can be disposed on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the second PD region PR2. The second local conductive pad LCP2 can be connected to the second part G2 of the second source follower gate electrode SFG2 through the second common contact plug BCTb.

[0269] refer to Figure 14C ,Apart from Figure 5B In addition to the embodiments shown, the image sensor may also include a Locally Conductive Pad (LCP) in the second PD region PR2. The LCP may be disposed on the source / drain region SDR on one side of the first pixel gate electrode PG1 in the second PD region PR2.

[0270] The interconnect conductive pattern ICP can be publicly connected to the floating diffusion area FD of the first PD area PR1 to the fourth PD area PR4, and the local conductive pad LCP can be connected to the interconnect conductive pattern ICP through the second common contact plug BCTb.

[0271] Figure 14D , Figure 14E and Figure 14FThis is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figure 9A , Figure 9B and Figure 9C The image sensors described share the same technical features, and different technical features will also be described.

[0272] refer to Figure 14D ,Apart from Figure 9A In addition to the embodiments shown, the image sensor may also include locally conductive pads (LCPs) in the second PD region PR2.

[0273] The Local Conductive Pad (LCP) can be disposed on the source / drain region SDR on one side of the pixel gate electrode PG in the second PD region PR2. The LCP can contact the source / drain region SDR and can extend to the top surface of the device isolation layer STI or the PD isolation pattern PIS.

[0274] The interconnect conductive pattern ICP may also include a connection portion that protrudes in the second direction D2 and is disposed on the device isolation layer STI or PD isolation pattern PIS. The local conductive pad LCP can be connected to the connection portion of the interconnect conductive pattern ICP via a second common contact plug BCTb.

[0275] refer to Figure 14E ,Apart from Figure 9B In addition to the embodiments shown, the image sensor may also include local conductive pads (LCPs) in the second PD region PR2. The second interconnect conductive pattern (ICP2) may also include a connection portion protruding in the second direction D2 and disposed between the first active portions ACT1 of the second PD region PR2. The local conductive pads (LCPs) can be connected to the connection portion of the second interconnect conductive pattern (ICP2) via a second common contact plug (BCTb).

[0276] refer to Figure 14F ,Apart from Figure 9C In addition to the embodiments shown, the image sensor may also include local conductive pads (LCPs) in the fourth PD region PR4. The second interconnect conductive pattern (ICP2) may also include a connection portion protruding in the second direction D2 and disposed between the first active portions ACT1 of the fourth PD region PR4. The local conductive pads (LCPs) can be connected to the connection portion of the second interconnect conductive pattern (ICP2) via a second common contact plug (BCTb).

[0277] Figure 15A , Figure 15B , Figure 15C and Figure 15DThis is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. For the sake of brevity, references may be omitted from the following description. Figures 11A to 11D The image sensors described share the same technical features, and different technical features will also be described.

[0278] refer to Figure 15A ,Apart from Figure 11A In addition to the embodiments shown, in the first PD group GPX1, the first local conductive pad LCP1 may be disposed on one side of the third pixel gate electrode PG3 of the third PD region PR3. In the second PD group GPX2, the second local conductive pad LCP2 may be disposed on one side of the third pixel gate electrode PG3 of the third PD region PR3.

[0279] In the third PD group GPX1, the third local conductive pad LCP3 can be disposed on one side of the first pixel gate electrode PG1 of the first PD area PR1. In the fourth PD group GPX4, the fourth local conductive pad LCP4 can be disposed on one side of the first pixel gate electrode PG1 of the first PD area PR1.

[0280] In each of the third PD group GPX3 and the fourth PD group GPX4, the interconnect conductive pattern ICP may further include a connection portion that protrudes in the first direction D1 and is disposed on the device isolation layer STI or the PD isolation pattern PIS.

[0281] The first local conductive pad LCP1 can be electrically connected to the interconnect conductive pattern ICP of the first PD group GPX1 via the second common contact plug BCTb. The second local conductive pad LCP2 can be electrically connected to the interconnect conductive pattern ICP of the second PD group GPX2 via the second common contact plug BCTb. The third local conductive pad LCP3 can be electrically connected to the connection portion of the interconnect conductive pattern ICP of the third PD group GPX3 via the second common contact plug BCTb. The fourth local conductive pad LCP4 can be electrically connected to the connection portion of the interconnect conductive pattern ICP of the fourth PD group GPX4 via the second common contact plug BCTb.

[0282] refer to Figure 15B ,Apart from Figure 11B In addition to the embodiments shown, in the first PD group GPX1, the first local conductive pad LCP1 may be disposed on one side of the third pixel gate electrode PG3 of the third PD region PR3. In the second PD group GPX2, the second local conductive pad LCP2 may be disposed on one side of the third pixel gate electrode PG3 of the third PD region PR3.

[0283] The first local conductive pad LCP1 can be electrically connected to the first interconnect conductive pattern ICP1 via the second common contact plug BCTb. The second local conductive pad LCP2 can be electrically connected to the second interconnect conductive pattern ICP2 via the second common contact plug BCTb.

[0284] refer to Figure 15C ,Apart from Figure 11C In addition to the embodiments shown, in the first PD group GPX1, the local conductive pad LCP may be disposed on one side of the third pixel gate electrode PG3 of the third PD area PR3.

[0285] The local conductive pad LCP can be electrically connected to the first interconnect conductive pattern ICP1 via the second common contact plug BCTb. That is, the local conductive pad LCP can be electrically connected to the source follower gate electrode SFG via the second common contact plug BCTb, the first interconnect conductive pattern ICP1, and the first common contact plug BCTa. In other words, the local conductive pad LCP can be electrically connected to the common floating diffusion region CFD of the first PD group GPX1 to the fourth PD group GPX4.

[0286] refer to Figure 15D ,Apart from Figure 11D In addition to the embodiments shown, in the first PD group GPX1, the local conductive pad LCP may be disposed on one side of the third pixel gate electrode PG3 of the third PD region PR3. The source follower gate electrode SFG may include a portion extending in the first direction D1 and adjacent to the local conductive pad LCP. The local conductive pad LCP may be electrically connected to a portion of the source follower gate electrode SFG via a second common contact plug BCTb.

[0287] Figure 16 This is a circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the disclosed concept.

[0288] refer to Figure 16 As shown in the reference above Figure 2A and Figure 2B As described, a unit pixel PX may include a photoelectric conversion circuit 10P and a pixel circuit 20P.

[0289] The photoelectric conversion circuit 10P may include a first photoelectric conversion element PD1 to an eighth photoelectric conversion element PD8, a first transfer transistor TX1 to an eighth transfer transistor TX8, and a floating diffusion region FD.

[0290] The pixel circuit 20P may include a first dual-conversion gain transistor DCX1, a second dual-conversion gain transistor DCX2 and a third dual-conversion gain transistor DCX3, a first source follower transistor SF1 and a second source follower transistor SF2, and a select transistor SX.

[0291] The first source follower transistor SF1 can be connected to the power supply voltage V. PIX Between the selection transistor SX and the second source follower transistor SF2, the power supply voltage V can be connected. PIX Between the selection transistor SX and the first source follower transistor SF1 and the second source follower transistor SF2, they can be connected in parallel.

[0292] The first dual-conversion gain transistor DCX1, the second dual-conversion gain transistor DCX2, and the third dual-conversion gain transistor DCX3 can be connected to the power supply voltage V. PIX Between the floating diffusion region FD and the first dual-conversion gain transistor DCX1, the second dual-conversion gain transistor DCX2, and the third dual-conversion gain transistor DCX3 can change the dual-conversion gain per unit pixel PX by changing the capacitance of the floating diffusion region FD in response to the first dual-conversion gain control signal DCG1, the second dual-conversion gain control signal DCG2, or the third dual-conversion gain control signal DCG3.

[0293] Figure 17A and Figure 18A This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept. Figure 17B and Figure 18B They are along Figure 17A and Figure 18A A cross-sectional view taken from line H-H'.

[0294] refer to Figure 17A and Figure 17B For reference Figure 3 As described, the first PD region PR1 to the fourth PD region PR4 can be defined by the PD isolation pattern PIS in the semiconductor substrate 100.

[0295] The device isolation layer STI can define a first active portion ACT1 and a second active portion ACT2 in each of the first PD regions PR1 to the fourth PD regions PR4. (See reference...) Figure 3 As described, the device isolation layer STI may have a first active portion ACT1 and two second active portions ACT2 in each of the first PD region PR1, the third PD region PR3 and the fourth PD region PR4.

[0296] According to some embodiments, in the second PD region PR2, the first active portion ACT1 can be connected to a second active portion ACT2 to define a common active portion ACT.

[0297] In the second PD region, a common floating diffusion region CFD can be provided in the common active portion ACT on one side of the first pixel gate electrode PG1 and on one side of the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0298] The interconnect conductive pattern ICP of the second PD region PR2 can directly contact the common floating diffusion region CFD. In other words, the common floating diffusion region CFD, the source / drain regions SDR of the pixel transistor (e.g., reset transistor or dual conversion gain transistor) of the second PD region PR2, and the source follower gate electrode SFG can be electrically connected to each other through the interconnect conductive pattern ICP and the common contact plug BCT.

[0299] refer to Figure 18A and Figure 18B For reference Figure 3 As described, a first active portion ACT1 and two second active portions ACT2 may be provided in each of the first PD regions PR1 to the fourth PD regions PR4.

[0300] According to some embodiments, a common contact plug BCT in the second PD region PR2 can directly contact the interconnect conductive pattern ICP of the second PD region PR2, the second part G2 of the source follower gate electrode SFG, and the source / drain region SDR on one side of the first pixel gate electrode of the second PD region PR2.

[0301] Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a plan view illustrating an image sensor according to some embodiments of the disclosed concept.

[0302] refer to Figure 19 The device isolation layer STI can define a first active portion ACT1 and a second active portion ACT2 in each of the first PD regions PR1 to the fourth PD regions PR4. (See reference...) Figure 3 As described, the device isolation layer STI may have a first active portion ACT1 and two second active portions ACT2 in each of the first PD region PR1, the third PD region PR3 and the fourth PD region PR4.

[0303] According to some embodiments, in the second PD region PR2, the first active portion ACT1 can be connected to a second active portion ACT2 to define a common active portion ACT. In the second PD region PR2, a common floating diffusion region CFD can be provided on one side of the second pixel gate electrode PG2 and in the common active portion ACT between the first transfer gate electrode TG1 and the second transfer gate electrode TG2. The interconnect conductive pattern ICP of the second PD region PR2 can directly contact the common floating diffusion region CFD.

[0304] Additionally, the source follower gate electrode SFG can be commonly disposed in the first PD regions PR1 to the fourth PD regions PR4. In other words, the source follower gate electrode SFG can include a first portion G1 spanning the second active portion ACT2 and a second portion G2 extending from the first portion in the second direction D2 and disposed on the device isolation layer STI or PD isolation pattern PIS. Here, one first portion G1 can span the second active portion ACT2 of the first PD region PR1 and the second PD region PR2, and another first portion G1 can span the second active portion ACT2 of the third PD region PR3 and the fourth PD region PR4. Furthermore, one second portion G2 can be adjacent to the interconnect conductive pattern ICP of the first PD region PR1 and the third PD region PR3, and another second portion G2 can be adjacent to the connection conductive pattern ICP of the second PD region PR2 and the fourth PD region PR4.

[0305] The interconnecting conductive pattern ICP of the first PD region PR1 to the fourth PD region PR4 can be connected to the second part G2 of the source follower gate electrode SFG via a common contact plug BCT.

[0306] refer to Figure 20 , and reference Figure 19 The described embodiments differ, and each of the first PD region PR1 to the fourth PD region PR4 may be provided with a first active portion ACT1 and two second active portions ACT2.

[0307] According to some embodiments, the common contact plug BCT in the second PD region PR2 can directly contact the interconnect conductive pattern ICP of the second PD region PR2, the second part G2 of the source follower gate electrode SFG, and the source / drain region SDR on one side of the second pixel gate electrode PG2 of the second PD region PR2.

[0308] according to Figure 21 The embodiments shown are similar to those described above. Figure 19 Unlike the embodiments shown, the device isolation layer STI may have a first active portion ACT1 and two second active portions ACT2 in each of the first PD region PR1, the third PD region PR3 and the fourth PD region PR4.

[0309] According to some embodiments, in the fourth PD region PR4, the first active portion ACT1 can be connected to a second active portion ACT2 to define a common active portion ACT. Additionally, in each of the first PD regions PR1 to the fourth PD region PR4, the second active portion ACT2 can be arranged diagonally relative to the first direction D1 and the second direction D2. The interconnect conductive pattern ICP of the fourth PD region PR4 can directly contact the common floating diffusion region CFD.

[0310] refer to Figure 22 ,and Figure 20 Unlike the embodiments shown, in each of the first PD regions PR1 to the fourth PD regions PR4, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 provided on the first active portion ACT1 can face each other diagonally. In the first PD regions PR1 to the fourth PD regions PR4, the directions in which the first transfer gate electrode TG1 and the second transfer gate electrode TG2 face each other can be different. Furthermore, in each of the first PD regions PR1 to the fourth PD regions PR4, the second active portion ACT2 can be arranged diagonally relative to each other.

[0311] In addition, the common contact plug BCT in the fourth PD region PR4 can directly contact the interconnect conductive pattern ICP of the fourth PD region PR4, the second part G2 of the source follower gate electrode SFG, and the source / drain region SDR on one side of the second pixel gate electrode PG2 of the fourth PD region PR4.

[0312] Figures 23 to 27 It is along Figure 3 A cross-sectional view taken along line A-A' to illustrate a method for manufacturing an image sensor according to an embodiment of the disclosed concept.

[0313] refer to Figure 3 and Figure 23 A semiconductor substrate 100 of a first conductivity type (e.g., p-type) may be provided. In some embodiments, the semiconductor substrate 100 may include an epitaxial layer. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a.

[0314] In some embodiments, the semiconductor substrate 100 may be a bulk semiconductor substrate including a well of a first conductivity type. Alternatively, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0315] In each of the PD regions PR1 to PR4, a device isolation layer STI may be formed on the semiconductor substrate 100, adjacent to the first surface 100a of the semiconductor substrate 100 and defining an active portion. Forming the device isolation layer STI may include patterning the first surface 100a of the semiconductor substrate 100 to form a first trench, forming a pad insulating layer conformally covering the inner surface of the first trench, and forming an insulating layer filling the first trench in which the pad insulating layer is formed. The formation of the device isolation layer STI may be performed before or after the formation of the photoelectric conversion regions 110a and 110b.

[0316] PD isolation patterns PIS defining PD regions PR1 to PR4 can be formed on the semiconductor substrate 100. Forming the PD isolation patterns PIS may include patterning a first surface 100a of the semiconductor substrate 100 to form a second trench, forming a pad insulating layer conformally covering the inner side of the second trench, depositing a semiconductor layer to fill the second trench in which the pad insulating layer is formed, and planarizing the pad insulating layer and the buried pattern 113 to expose the first surface 100a of the semiconductor substrate and forming a pad insulating pattern 111, a buried pattern 113 and a cover insulating pattern 115 in the second trench.

[0317] The padding insulation pattern 111 and the cover insulation pattern 115 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The buried pattern 113 may include a doped polysilicon layer and / or an undoped polysilicon layer.

[0318] Next, a first photoelectric conversion region 110a and a second photoelectric conversion region 110b can be formed in the semiconductor substrate 100 of each PD region PR1 to PR4.

[0319] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be formed by doping the semiconductor substrate 100 in each of the PD regions PR1 to PR4 with a dopant of a second conductivity type (e.g., n-type) different from the first conductivity type. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be spaced apart from the first surface 100a and the second surface 100b of the semiconductor substrate 100. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be formed before or after the formation of the PD isolation pattern PIS.

[0320] Subsequently, a first transfer gate electrode TG1 and a second transfer gate electrode TG2 can be formed in the first active portion ACT1 of each PD region PR1 to PR4. Forming the first transfer gate electrode TG1 and the second transfer gate electrode TG2 includes patterning the first surface 100a of the semiconductor substrate 100 to form a gate recess region in each PD region PR1 to PR4, forming a gate insulating layer conformally covering the inner surface of the gate recess region, and forming and patterning a gate conductive layer filling the gate recess region. In some embodiments, each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include two vertical portions disposed in the semiconductor substrate 100.

[0321] The gate insulating layer may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The gate insulating layer can be formed by performing a deposition process to conformally cover the inner wall of the vertical trench.

[0322] The first transfer gate electrode TG1 and the second transfer gate electrode TG2 can be formed by forming a gate conductive layer that fills a vertical trench in which a gate insulating layer is formed, and then patterning the gate conductive layer. The gate conductive layer may include a doped polysilicon layer, a metal silicide layer, a conductive metal nitride layer, or a metal layer.

[0323] When the first transfer gate electrode TG1 and the second transfer gate electrode TG2 are formed, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 of the pixel transistor and the source follower gate electrode SFG can be formed together in the second active portion ACT2 of each PD region PR1 to PR4.

[0324] After forming the first transfer gate electrode TG1 and the second transfer gate electrode TG2, a floating diffusion region FD can be formed in the semiconductor substrate 100 between the first transfer gate electrode TG1 and the second transfer gate electrode TG2. The floating diffusion region FD can be formed by implanting a dopant of a second conductivity type using an ion implantation mask. Furthermore, when forming the floating diffusion region FD, the source / drain regions of the pixel transistor can be formed together.

[0325] Subsequently, a spacer insulating layer 120 can be deposited on the first surface 100a of the semiconductor substrate 100. The spacer insulating layer 120 can cover the first transfer gate electrode TG1 and the second transfer gate electrode TG2, the pixel gate electrodes PG1 and PG2, and the source follower gate electrode SFG with a substantially uniform thickness.

[0326] The spacer insulating layer 120 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), or silicon carbonitride (SiCON). The spacer insulating layer 120 may be deposited by, for example, atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), or flowable CVD (FCVD).

[0327] A first mask pattern MP1 with an opening exposing a portion of the spacer insulating layer 120 can be formed on the spacer insulating layer 120. The opening of the first mask pattern MP1 can overlap with a portion of the floating diffusion region FD of the PD regions PR1 to PR4. For example, the first mask pattern MP1 can be formed by coating a photoresist layer on a first surface 100a of the semiconductor substrate 100 and performing an exposure and development process on the photoresist layer.

[0328] refer to Figure 3 and Figure 24 The spacer insulating layer 120 can be anisotropically etched to form the spacer insulating pattern 121 by using the first mask pattern MP1 as an etching mask.

[0329] Subsequently, a floating diffusion region FD can be formed by implanting dopant ions of the second conductivity type into the first active portion ACT1 of the semiconductor substrate 100 using spacer insulating pattern 121 as an ion implantation mask pattern.

[0330] A conductive layer 130 having a substantially uniform thickness can then be deposited over the entire surface of the semiconductor substrate 100. The conductive layer 130 can directly contact the second doped region FDb and can cover the spacer insulating pattern 121. The conductive layer 130 may include, for example, a doped polysilicon layer, a metal silicide layer, a conductive metal nitride layer, or a metal layer. For example, the conductive layer 130 can be formed by depositing a semiconductor layer, and impurities can be doped in situ during the deposition of the semiconductor layer.

[0331] refer to Figure 3 and Figure 25 A second mask pattern MP2 can be formed on the conductive layer 130, and the second mask pattern MP1 can overlap with the floating diffusion region FD.

[0332] Subsequently, the conductive layer 130 can be anisotropically etched using the second mask pattern MP2 as an etching mask to form the interconnect conductive pattern ICP. After forming the interconnect conductive pattern ICP, the second mask pattern MP2 can be removed.

[0333] refer to Figure 3 and Figure 26An etching process (e.g., etch-back) can be performed on the first surface 100a of the semiconductor substrate 100 on which the spacer insulating pattern 121 is formed. As a result, a portion of the spacer insulating pattern 121 can be retained, and insulating spacers SP can be formed on the opposite sidewalls of the first transfer gate electrode TG1 and the second transfer gate electrode TG2, on the opposite sidewalls of each of the pixel gate electrodes PG1 and PG2, and on the opposite sidewalls of the source follower gate electrode SFG. A blocking pattern BLK can be formed on the edge portions of the interconnect conductive pattern ICP.

[0334] Subsequently, refer to Figure 3 and Figure 27 A first etch stop layer 140 and a second etch stop layer 150 can be sequentially deposited on a first surface 100a of a semiconductor substrate 100 with substantially uniform thickness.

[0335] The first etch stop layer 140 and the second etch stop layer 150 can be deposited by processes such as plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), or flowable chemical vapor deposition (FCVD). The first etch stop layer 140 and the second etch stop layer 150 may comprise silicon nitride or silicon oxynitride.

[0336] An interlayer insulating layer 210 may be formed on the second etch stop layer 150. The interlayer insulating layer 210 may include at least one of, for example, a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer. The interlayer insulating layer 210 may be formed using at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques. The interlayer insulating layer 210 may have a top surface planarized by a planarization process.

[0337] After forming a mask pattern (not shown) on the interlayer insulating layer 210, a common contact hole CH is formed by sequentially etching the interlayer insulating layer 210 and the first etch stop layer 140 and the second etch stop layer 150 to expose a portion of the interconnect conductive pattern ICP and a portion of the source follower gate electrode SFG. The common contact hole CH can expose the portion of the PD isolation pattern PIS between the interconnect conductive pattern ICP and the source follower gate electrode SFG.

[0338] Subsequently, a barrier metal layer and a metal layer can be sequentially deposited on the interlayer insulating layer 210, and a planarization process can be performed on the barrier metal layer and the metal layer to expose the top surface of the interlayer insulating layer 210. Therefore, as... Figure 3 and Figures 4A to 4C As shown, a common contact plug BCT can be formed to fill the common contact hole CH.

[0339] Figure 28This is a schematic plan view illustrating an image sensor according to an embodiment of the disclosed concept. Figure 29 and Figure 30 It is along Figure 28 A cross-sectional view taken by line I-I' to illustrate an image sensor according to some example embodiments.

[0340] refer to Figure 28 and Figure 29 The image sensor may include a sensor chip C1 and a logic chip C2. The sensor chip C1 may include a pixel array area R1 and a pad area R2.

[0341] The pixel array region R1 may include a plurality of unit pixels P arranged in two dimensions along a first direction D1 and a second direction D2 that intersect each other. Each unit pixel P may include a photoelectric conversion element and a readout element. An electrical signal generated by incident light can be output from each unit pixel P of the pixel array region R1.

[0342] The pixel array region R1 may include a light-receiving region AR and a light-blocking region OB. In a planar view, the light-blocking region OB may surround the light-receiving region AR. For example, in a planar view, the light-blocking region OB may surround the light-receiving region AR in four different directions (e.g., up, down, left, and right). In an embodiment, a reference pixel on which light is not incident may be provided in the light-blocking region OB, and the amplitude of the electrical signal sensed in the unit pixel PX can be calculated by comparing the amplitude of the charge sensed in the unit pixel PX of the light-receiving region AR with a reference amount of charge generated in the reference pixel.

[0343] Multiple conductive pads CP can be set in the pad area R2 for inputting and outputting control signals, photoelectric signals, etc. In a planar view, the pad area R2 can surround the pixel array area R1 to facilitate electrical connection with external devices. The conductive pads CP can output electrical signals generated in a unit pixel P to an external device or input electrical signals from an external device to a unit pixel P.

[0344] In the light-receiving region AR, the sensor chip C1 may include the same technical features as the image sensor described above. That is, as described above, the sensor chip C1 may include a photoelectric conversion circuit layer 10 located on the third direction D3 between the pixel circuit layer 20 and the optically transparent layer 30. As described above, the photoelectric conversion circuit layer 10 of the sensor chip C1 may include a semiconductor substrate 100, a PD isolation pattern PIS defining the PD region, and a photoelectric conversion region 110 provided in the PD region. The PD isolation pattern PIS may have substantially the same structure in both the light-receiving region AR and the light-blocking region OB. The PD isolation pattern PIS may be disposed in the semiconductor substrate 100 of the light-blocking region OB. The buried pattern 113 of the PD isolation pattern PIS may be electrically connected to the back contact plug PLG in the light-blocking region OB. A predetermined bias voltage may be applied to the buried pattern 113 via the back contact plug PLG. The width of the back contact plug PLG may be greater than the width of the PD isolation pattern PIS. The back contact plug PLG may include a metal and / or a metal nitride. For example, the back contact plug PLG may include titanium and / or titanium nitride.

[0345] The contact plug CT can be embedded in a contact hole in which a back contact plug PLG is formed. The contact plug CT can be made of a different material than the back contact plug PLG. For example, the contact plug CT can be made of aluminum (Al).

[0346] The contact plug CT and the back contact plug PLG can be electrically connected to the buried pattern 113 of the PD isolation pattern PIS. A negative bias voltage can be applied to the buried pattern 113 of the PD isolation pattern PIS via the contact plug CT, and the negative bias voltage can be transmitted from the light blocking region OB to the light receiving region AR. Therefore, the dark current generated at the interface between the PD isolation pattern PIS and the semiconductor substrate 100 can be reduced.

[0347] The optically transparent layer 30 may include a light-blocking pattern OBP, a filter layer 335, and an organic layer 345 in the light-blocking region OB. In some embodiments, the PD isolation pattern PIS may extend continuously from the light-receiving region AR to the light-blocking region OB.

[0348] In the light-blocking region OB, the light-blocking pattern OBP can be disposed on the top surface of the planarized insulating layer 310. The light-blocking pattern OBP can include the same material as the conductive pattern of the grid 320 of the light-receiving region AR. In other words, the light-blocking pattern OBP can include metal patterns and metal oxide patterns. For example, the light-blocking pattern OBP can include titanium nitride and titanium oxynitride. The light-blocking pattern OBP may not extend into the light-receiving region AR.

[0349] A light-blocking pattern (OBP) can block light incident on the photoelectric conversion region (PD) within the light-blocking region (OB). In the reference PD region of the light-blocking region (OB), the photoelectric conversion region (PD) can output a noise signal instead of a photoelectric signal. The noise signal can be generated by dark current or electrons produced by heat.

[0350] The filter layer 335 can cover the light-blocking pattern OBP in the light-blocking region OB. The filter layer 335 can block light with a wavelength different from that of the color filter 330. For example, the filter layer 335 can block infrared light. The filter layer 335 can include, but is not limited to, a blue color filter.

[0351] Organic layer 345 and passivation layer can be provided on the protective layer in the light-blocking region OB and the pad region R2. Organic layer 345 may include the same material as microlens 340.

[0352] In the light-blocking region OB, the first through-conductive pattern 510 can penetrate the semiconductor substrate 100 to electrically connect to the metal wiring of the pixel circuit layer 20 and the metal wiring 1111 of the logic chip C2. The first through-conductive pattern 510 may have a first bottom surface and a second bottom surface located at different horizontal levels. A first buried pattern 511 may be provided inside the first through-conductive pattern 510. The first buried pattern 511 comprises a low refractive index material and may have insulating properties.

[0353] In the pad region R2, conductive pads CP can be provided on the second surface 100b of the semiconductor substrate 100. The conductive pads CP can be embedded in the second surface 100b of the semiconductor substrate 100. For example, in the pad region R2, the conductive pads CP can be provided in pad trenches formed in the second surface 100b of the semiconductor substrate 100. The conductive pads CP can be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, or alloys thereof). In the process of mounting an image sensor, bonding leads can be bonded to the conductive pads CP. The conductive pads CP can be electrically connected to external devices via the bonding leads.

[0354] In pad region R2, a second through-conductive pattern 520 can penetrate the semiconductor substrate 100 to electrically connect to the metal wiring 1111 of the logic chip C2. The second through-conductive pattern 520 can extend onto the second surface 100b of the semiconductor substrate 100 to electrically connect to the conductive pad CP. A portion of the second through-conductive pattern 520 can cover the bottom surface and sidewalls of the conductive pad CP. A second buried pattern 513 can be provided inside the second through-conductive pattern 520. The second buried pattern 513 comprises a low refractive index material and can have insulating properties. In pad region R2, a PD isolation pattern PIS can be provided around the second through-conductive pattern 520.

[0355] The logic chip C2 may include a logic semiconductor substrate 1000, a logic circuit TR, metal wiring 1111 connected to the logic circuit TR, and an interlayer insulating layer 1100. The uppermost layer of the interlayer insulating layer 1100 may be bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 may be electrically connected to the sensor chip C1 through a first through-conductive pattern 510 and a second through-conductive pattern 520.

[0356] In the embodiments, the sensor chip C1 and the logic chip C2 have been described as being electrically connected to each other via a first through conductive pattern 510 and a second through conductive pattern 520, but the disclosed concept is not limited thereto.

[0357] according to Figure 30 The embodiments shown may be omitted. Figure 29 The first through conductive pattern 510 and the second through conductive pattern 520 are shown in the figure, and the sensor chip C1 and the logic chip C2 can be electrically connected to each other by directly bonding bonding pads provided in the top metal layer of the sensor chip C1 and the logic chip C2.

[0358] In detail, in the sensor chip C1, the buried pattern 113 of the PD isolation pattern PIS extending from the light receiving area AR to the light blocking area OB can be connected to the back contact plug PLG in the light blocking area OB.

[0359] Additionally, the sensor chip C1 may include a first bonding pad BP1 provided in the topmost metal layer of the pixel circuit layer 20, and the logic chip C2 may include a second bonding pad BP2 provided in the topmost metal layer of the metal wiring 1111. The first bonding pad BP1 and the second bonding pad BP2 may include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0360] The first bonding pad BP1 of sensor chip C1 and the second bonding pad BP2 of logic chip C2 can be directly electrically connected to each other using a hybrid bonding method. A hybrid bonding method refers to a bonding process used to fuse two components at the interface between two components comprising homogeneous materials. For example, when the first bonding pad BP1 and the second bonding pad BP2 are formed of copper (Cu), they can be physically electrically connected via a copper (Cu)-copper (Cu) bond. Alternatively, the surfaces of the insulating layers of sensor chip C1 and logic chip C2 can be bonded via a dielectric-dielectric bond.

[0361] According to embodiments of the disclosed concept, by forming interconnected conductive patterns connecting spaced-apart floating diffusion regions, the capacitance increase and signal delay that may occur when using metal layers for interconnection can be prevented or reduced, and the conversion gain per unit pixel can be improved. Furthermore, the degree of freedom in constructing the interconnect structure of the image sensor can be increased.

[0362] Furthermore, a portion of the source follower gate electrode can extend onto the device isolation layer or PD isolation pattern to be adjacent to the interconnect conductive pattern, and a common contact plug can be publicly connected to both the interconnect conductive pattern and a portion of the source follower gate electrode. Therefore, the metal wiring connecting the floating diffusion region and the source follower gate electrode can be reduced, thereby further improving the conversion gain per pixel.

[0363] While embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the disclosed concept as defined in the appended claims. Therefore, the exemplary embodiments of the disclosed concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the disclosed concept are indicated by the appended claims.

Claims

1. An image sensor, the image sensor comprising: Semiconductor substrate; A photodiode (PD) isolation pattern is disposed in the semiconductor substrate and defines a first PD region and a second PD region; A first floating diffusion region is provided in the semiconductor substrate of the first PD region; An interconnect conductive pattern is disposed on a first surface of the semiconductor substrate and in contact with the first floating diffusion region; A source follower gate electrode is provided in the second PD region and includes a first portion disposed on the semiconductor substrate of the second PD region and a second portion extending from the first portion and disposed on the PD isolation pattern, the second portion being adjacent to the interconnect conductive pattern; as well as A common contact plug, which is publicly connected to the source follower gate electrode and the interconnect conductive pattern.

2. The image sensor of claim 1, wherein, The common contact plug contacts the top surface of the second portion of the source follower gate electrode and the top surface of the interconnect conductive pattern.

3. The image sensor of claim 1, wherein, The top surface of the interconnect conductive pattern is located at a different horizontal height than the top surface of the source follower gate electrode.

4. The image sensor according to claim 1, wherein, A portion of the common contact plug contacts the PD isolation pattern between the second portion of the source follower gate electrode and the interconnect conductive pattern.

5. The image sensor according to claim 1, wherein, The common contact plug contacts the sidewall and top surface of the second portion of the source follower gate electrode.

6. The image sensor according to claim 1, wherein, The bottom surface of the common contact plug is at a lower horizontal level than the top surface of the PD isolation pattern.

7. The image sensor of claim 1, further comprising a contact plug connected to the source follower gate electrode. in, The contact plug comprises the same conductive material as the common contact plug.

8. The image sensor according to claim 1, wherein, The interconnect conductive pattern is spaced apart from the second portion of the source follower gate electrode in a first direction, and The common contact plug has a length in the first direction and a width less than the length in a second direction perpendicular to the first direction.

9. The image sensor according to claim 1, further comprising: A first photoelectric conversion region and a second photoelectric conversion region are disposed in the semiconductor substrate in each of the first PD region and the second PD region. as well as A first transfer gate electrode and a second transfer gate electrode are provided in each of the first PD region and the second PD region. In the first PD region, the first floating diffusion region is commonly provided between the first transfer gate electrode and the second transfer gate electrode.

10. The image sensor according to claim 1, further comprising: A first photoelectric conversion region and a second photoelectric conversion region are disposed in the semiconductor substrate in each of the first PD region and the second PD region. A first transfer gate electrode and a second transfer gate electrode are provided in each of the first PD region and the second PD region; as well as A second floating diffusion region is provided in the semiconductor substrate of the second PD region. Each of the first floating diffusion region and the second floating diffusion region includes a first doped region provided on a first side of the first transfer gate electrode and a second doped region provided on a first side of the second transfer gate electrode. The interconnected conductive pattern commonly contacts the first doped region and the second doped region of the first floating diffusion region.

11. The image sensor according to claim 1, further comprising: A pixel gate electrode is provided in the first PD region; Source / drain regions are provided in the semiconductor substrate on opposite sides of the pixel gate electrode; A conductive pad, the conductive pad being in contact with one of the source / drain regions; as well as A connection contact plug is provided, which is in common contact with the conductive pad and the interconnect conductive pattern.

12. The image sensor according to claim 11, wherein, The interconnect conductive pattern includes a first connection portion that contacts the first floating diffusion region and a second connection portion that extends from the first connection portion and is adjacent to the conductive pad. The connecting contact plug contacts the second connecting portion of the interconnecting conductive pattern and the conductive pad.

13. An image sensor, the image sensor comprising: Semiconductor substrate; A photodiode (PD) isolation pattern is disposed within the semiconductor substrate to define a first PD region and a second PD region; A first floating diffusion region is provided in the first PD region within the semiconductor substrate; A second floating diffusion region is provided in the semiconductor substrate within the second PD region; An interconnect conductive pattern is disposed on a first surface of the semiconductor substrate and in contact with the first floating diffusion region; A pixel transistor is provided in the second PD region and includes a pixel gate electrode and a source / drain region located on the opposite side of the pixel gate electrode; as well as A common contact plug connects the interconnect conductive pattern to the pixel gate electrode or the source / drain region.

14. The image sensor according to claim 13, wherein, The pixel gate electrode includes a first portion disposed on the semiconductor substrate of the second PD region and a second portion adjacent to the first floating diffusion region and disposed on the PD isolation pattern. The common contact plug contacts the second portion of the pixel gate electrode and a portion of the interconnect conductive pattern.

15. The image sensor of claim 13, further comprising a conductive pad in contact with one of the source / drain regions. in, The common contact plug contacts a portion of the interconnecting conductive pattern and a portion of the conductive pad.

16. The image sensor according to claim 15, wherein, The interconnecting conductive pattern includes a first connection portion that contacts the first floating diffusion region and the second floating diffusion region, and a second connection portion that extends from the first connection portion and is disposed on the PD isolation pattern. The second connection portion is adjacent to the conductive pad.

17. The image sensor according to claim 13, wherein, The common contact plug has a length in a first direction and a width less than the length in a second direction perpendicular to the first direction.

18. An image sensor, the image sensor comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A photodiode (PD) isolation pattern is disposed in the semiconductor substrate to define a first PD region, a second PD region, a third PD region, and a fourth PD region; A photoelectric conversion region is provided in the semiconductor substrate in the first PD region, the second PD region, the third PD region, and the fourth PD region; A device isolation layer, the device isolation layer being adjacent to the first surface of the semiconductor substrate, and defining a first active portion and a second active portion in each of the first PD region, the second PD region, the third PD region and the fourth PD region; A transfer gate electrode is provided in the first active portion of the first PD region, the second PD region, the third PD region, and the fourth PD region; A floating diffusion region is provided in the first active portion of the first PD region, the second PD region, the third PD region, and the fourth PD region; A pixel transistor is provided in a second active portion of a first PD region, a second PD region, a third PD region, and a fourth PD region. One pixel transistor includes a pixel gate electrode, the pixel gate electrode including a first portion disposed on the second active portion in the third PD region and the fourth PD region, and a second portion extending from the first portion and disposed on the PD isolation pattern and adjacent to the floating diffusion region in the first PD region and the second PD region. Interconnecting conductive patterns, wherein the interconnecting conductive patterns are respectively in contact with the floating diffusion regions of the first PD region, the second PD region, the third PD region and the fourth PD region; A common contact plug connects the pixel gate electrode to the interconnect conductive patterns of the first PD region, the second PD region, the third PD region, and the fourth PD region; A color filter, the color filter being disposed on the second surface of the semiconductor substrate corresponding to the first PD region, the second PD region, the third PD region and the fourth PD region; A grid, wherein the grid is disposed between the color filters and overlaps with the PD isolation pattern; as well as A microlens, the microlens being located on the color filter.

19. The image sensor according to claim 18, wherein, A portion of each of the common contact plugs contacts the PD isolation pattern between the pixel gate electrode and the interconnect conductive pattern.

20. The image sensor according to claim 18, wherein, Each of the common contact plugs has a length in a first direction and a width less than the length in a second direction perpendicular to the first direction.

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