Elevator control system and control method

Abstract

This application relates to an elevator control system and control method. The elevator control system includes a microcontroller and an off-chip memory connected to the microcontroller. The microcontroller includes on-chip volatile memory and on-chip non-volatile memory. The on-chip non-volatile memory stores elevator control data and elevator operation monitoring conditions from the on-chip volatile memory that need to be retained even after power loss. The off-chip memory includes a first off-chip non-volatile memory and a second off-chip non-volatile memory connected to the microcontroller. The first off-chip non-volatile memory stores elevator operation data from the on-chip volatile memory that needs to be retained even after power loss, and the second off-chip non-volatile memory stores elevator operation status data from the on-chip volatile memory that needs to be retained even after power loss. By configuring the elevator control data storage, the goal of maintaining performance can be achieved using low-cost but performance-limited memory.

Description

Technical Field

[0001] This application relates to the field of elevator control technology, and in particular to an elevator control system and control method. Background Technology

[0002] Elevator operation control requires the storage of a large amount of data, some of which needs to be retained even after the main control board loses power. Currently, data is typically stored in memory with high-speed parallel transmission interfaces; however, such memory is often large in size and expensive. Summary of the Invention

[0003] Therefore, it is necessary to provide an elevator control system and control method that can reduce costs and maintain performance in response to the above-mentioned technical problems.

[0004] In a first aspect, this application provides an elevator control system, including a microcontroller and an off-chip memory connected to the microcontroller; wherein:

[0005] The microcontroller includes on-chip volatile memory and on-chip non-volatile memory; the on-chip non-volatile memory is used to store elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory during elevator operation.

[0006] The off-chip memory includes a first off-chip non-volatile memory and a second off-chip non-volatile memory connected to the microcontroller; the first off-chip non-volatile memory is used to store elevator operation data that needs to be retained when power is off from the on-chip volatile memory during elevator operation, and the second off-chip non-volatile memory is used to store elevator operation status data that needs to be retained when power is off from the on-chip volatile memory during elevator operation.

[0007] In one embodiment, the elevator control data includes elevator control programs and elevator specification parameters; the on-chip non-volatile memory includes:

[0008] On-chip program memory is used to store elevator control programs;

[0009] The on-chip data storage is used to store elevator specifications and elevator operation monitoring conditions.

[0010] The microcontroller is used to write the elevator operation monitoring conditions in the on-chip volatile memory into the on-chip data memory when the operating conditions change, and to write the elevator operation monitoring conditions in the on-chip data memory into the on-chip volatile memory when power-on initialization.

[0011] In one embodiment, the on-chip non-volatile memory is an on-chip Flash memory, the on-chip program memory is an on-chip program Flash memory, and the on-chip data memory is an on-chip data Flash memory.

[0012] In one embodiment, the elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip volatile memory is on-chip RAM, which includes:

[0013] The first RAM memory is used to store elevator operation safety data;

[0014] The second RAM memory is used to store elevator operation control data;

[0015] The third RAM memory is used to store elevator operation monitoring conditions and elevator operation status data;

[0016] The microcontroller is used to write elevator operation safety data from the first RAM memory and elevator operation control data from the second RAM memory into the first external non-volatile memory based on the write cycle; and to write elevator operation safety data from the first external non-volatile memory into the first RAM memory and elevator operation control data from the first external non-volatile memory into the second RAM memory after power failure and power-on initialization.

[0017] The microcontroller is also used to write elevator operating status data from the third RAM memory to the second external non-volatile memory when the elevator is in an abnormal operating state.

[0018] In one embodiment, the first external non-volatile memory is connected to the microcontroller via a serial communication interface.

[0019] In one embodiment, the elevator control system further includes a direct memory access controller connected to the microcontroller;

[0020] The microcontroller is used to start the direct memory access controller when the write cycle arrives, so that the direct memory access controller writes the elevator operation safety data in the first RAM memory and the elevator operation control data in the second RAM memory into the first off-chip non-volatile memory through the serial communication interface.

[0021] In one embodiment, the first off-chip non-volatile memory is an off-chip NvRAM memory, and the second off-chip non-volatile memory is an off-chip Flash memory.

[0022] Secondly, this application also provides an elevator control method, applied to a microcontroller in an elevator control system as described above, the method comprising:

[0023] Elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory, are written into the on-chip non-volatile memory.

[0024] During elevator operation, elevator operation data that needs to be retained after power failure from the on-chip volatile memory is written into the first off-chip non-volatile memory.

[0025] The elevator operating status data that needs to be retained after power failure is written from the on-chip volatile memory to a second off-chip non-volatile memory.

[0026] In one embodiment, the elevator control data includes an elevator control program and elevator specification parameters; the on-chip non-volatile memory includes on-chip program memory and on-chip data memory.

[0027] Elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory, are written into the on-chip non-volatile memory, including:

[0028] Write the elevator control program into the on-chip program memory;

[0029] The first partition and the second partition are identified in the on-chip data memory; the first partition is a partition allocated from the on-chip data memory for storing elevator specification parameters, and the second partition is a partition allocated from the on-chip data memory for storing elevator operation monitoring conditions.

[0030] Store the elevator specifications in the first partition;

[0031] When the operating conditions change, the operating conditions region is identified in the on-chip volatile memory; the operating conditions region is a partition from the on-chip volatile memory used to store elevator operation monitoring conditions; the elevator operation monitoring conditions in the operating conditions region are stored in the second partition.

[0032] Upon power-on initialization, the elevator operation monitoring conditions in the second partition are written into the operation status conditions area.

[0033] In one embodiment, the elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip non-volatile memory includes a first RAM memory, a second RAM memory, and a third RAM memory;

[0034] The process of writing elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory includes:

[0035] A first power-down retention storage area is identified in a first RAM memory, and a second power-down retention storage area is identified in a second RAM memory; the first power-down retention storage area is a partition from the first RAM memory used to store elevator operation safety data; the second power-down retention storage area is a partition from the second RAM memory used to store elevator operation control data.

[0036] Elevator operation safety data is stored in the first power failure retention storage area, and elevator operation control data is written to the second power failure retention storage area.

[0037] When the write cycle arrives, the elevator operation safety data in the first power-down retention storage area and the elevator operation control data in the second power-down retention storage area are written to the first external non-volatile memory.

[0038] In the case of power failure and power-on initialization, the elevator operation safety data in the first external non-volatile memory is written into the first power failure retention storage area, and the elevator operation control data in the first external non-volatile memory is written into the second power failure retention storage area.

[0039] The process of writing elevator operating status data that needs to be retained even after power failure from the on-chip volatile memory to a second off-chip non-volatile memory includes:

[0040] The operating status data area is identified in the third RAM memory; the operating status data area is a partition allocated from the third RAM memory for storing elevator operating status data;

[0041] Multiple storage areas were identified in the second external non-volatile memory; the storage areas are partitions allocated from the second external non-volatile memory for storing elevator operating status data;

[0042] When the elevator is in an abnormal working state, the elevator operating status data is stored in the operating status data area. The target storage area is selected from multiple storage areas, and the elevator operating status data in the operating status data area is written to the target storage area.

[0043] Specifically, when the number of erase / write cycles of the target storage area reaches the lifetime threshold, the next storage area is designated as the target storage area; the next storage area is a storage area other than the target storage area among multiple storage areas.

[0044] The aforementioned elevator control system and method include an elevator control system comprising a microcontroller and an off-chip memory connected to the microcontroller. The microcontroller includes on-chip volatile memory and on-chip non-volatile memory. The on-chip non-volatile memory stores elevator control data and elevator operation monitoring conditions from the on-chip volatile memory that need to be retained even after power loss. The off-chip memory includes a first off-chip non-volatile memory and a second off-chip non-volatile memory connected to the microcontroller. The first off-chip non-volatile memory stores elevator operation data from the on-chip volatile memory that needs to be retained even after power loss, and the second off-chip non-volatile memory stores elevator operation status data from the on-chip volatile memory that needs to be retained even after power loss. This embodiment of the application achieves performance retention using low-cost but performance-limited memory through the configuration of elevator control data storage. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 An elevator control system is one embodiment;

[0047] Figure 2 This is a schematic diagram of an on-chip non-volatile memory structure;

[0048] Figure 3 This is a schematic diagram of an on-chip volatile memory structure;

[0049] Figure 4 A schematic diagram illustrating the storage of data using the first external non-volatile memory chip;

[0050] Figure 5 An elevator control system according to a specific embodiment;

[0051] Figure 6 This is a flowchart illustrating an elevator control method in one embodiment;

[0052] Figure 7 This is a schematic diagram of the region division of the second external non-volatile memory in one embodiment. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0054] It is understood that terms such as “first” and “second” in this application are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0055] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0056] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0057] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0058] Currently, elevators are typically controlled by microcomputers. This microcomputer control requires a large amount of control data, which is usually stored in memory with a high-speed parallel transmission interface. While memory with a high-speed parallel transmission interface offers superior performance, its package size is often large, which hinders the miniaturization of the main control board.

[0059] Elevator operation control requires some data to be retained after a power outage on the main control board, so that the elevator can automatically resume operation after power is restored, preventing people from being trapped in the elevator for extended periods. Currently, the industry widely uses ferroelectric memory with high-speed parallel transmission interfaces to store power-loss retained data. Besides the disadvantage of large package size, these memories are also typically quite expensive.

[0060] Based on the aforementioned traditional technologies, the embodiments of this application can solve the problem that using a low-cost but performance-limited (including space, access speed, and erase / write cycles) memory to store a large amount of elevator operation control data in the elevator main control board achieves the same effect as a high-cost, high-performance memory. For example, the elevator control system provided in this application can be understood as an elevator control microcomputer storage system. It should be noted that the beneficial effects or technical problems solved by the embodiments of this application are not limited to this one, but may also include other implicit or related problems, as detailed in the following description of the embodiments.

[0061] like Figure 1 As shown, an elevator control system according to one embodiment includes a microcontroller 10 and an off-chip memory 20 connected to the microcontroller 10; wherein:

[0062] The microcontroller 10 includes an on-chip volatile memory 120 and an on-chip non-volatile memory 110; the on-chip non-volatile memory 110 is used to store elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory 120 during elevator operation.

[0063] The off-chip memory 20 includes a first off-chip non-volatile memory 210 and a second off-chip non-volatile memory 220 connected to the microcontroller 10; the first off-chip non-volatile memory 210 is used to store elevator operation data that needs to be retained when power is off from the on-chip volatile memory 120 during elevator operation, and the second off-chip non-volatile memory 220 is used to store elevator operation status data that needs to be retained when power is off from the on-chip volatile memory 120 during elevator operation.

[0064] Specifically, the elevator control system may include a microcontroller 10 and an off-chip memory 20 connected to the microcontroller 10. Exemplarily, the microcontroller may include, but is not limited to, a CPU (Central Processing Unit). This embodiment of the application is applicable to elevators controlled by a microcomputer. Furthermore, the off-chip memory 20 is connected to the microcontroller 10. It can be understood that in this embodiment, the reading and writing of the off-chip memory, area partitioning, etc., are controlled and executed by the microcontroller.

[0065] The microcontroller 10 may include an on-chip non-volatile memory 110 and an on-chip volatile memory 120. The on-chip non-volatile memory 110 is a non-volatile memory suitable for storing data that does not require frequent changes, has a small data volume, and needs to be retained even after power loss. The on-chip volatile memory 120 is a volatile memory, and its data cannot be retained after power loss. In this embodiment, the on-chip non-volatile memory 110 is used to store elevator control data and elevator operation monitoring conditions from the on-chip volatile memory 120 that need to be retained after power loss. The elevator control data may refer to data related to elevator control, such as elevator control programs. The elevator operation monitoring conditions may refer to conditions set for online monitoring of the elevator's operating status, such as conditions set by the user or system for online monitoring of the elevator's operating status. This data generally does not change for a relatively long period after being set, and needs to be retained even after power loss when the microcomputer controls the elevator.

[0066] This application embodiment stores elevator control data using on-chip non-volatile memory, ensuring that the elevator control data is retained even when power is lost. Furthermore, the on-chip non-volatile memory is also used to store elevator operation monitoring conditions that need to be retained even when power is lost, derived from the on-chip volatile memory, so that the elevator operation monitoring conditions remain valid even when the elevator is powered off.

[0067] It should be noted that the elevator operation monitoring conditions in this application embodiment may include elevator load, car position, speed command, speed feedback, torque command, feedback current, safety circuit status, door status, running command, brake control command, door opening command, door closing command, internal and external call login, and operating status. This application embodiment does not limit these aspects.

[0068] Further, the off-chip memory 20 may include a first off-chip non-volatile memory 210 and a second off-chip non-volatile memory 220 connected to the microcontroller 10. It is understood that both the first off-chip non-volatile memory 210 and the second off-chip non-volatile memory 220 are non-volatile memories and can be used to store data that needs to be retained even after power loss. Optionally, the first off-chip non-volatile memory 210 has a serial communication interface, meaning the microcontroller 10 can transmit relevant data to the first off-chip non-volatile memory 210 through the serial communication interface. Exemplarily, the second off-chip non-volatile memory 220 has a serial communication interface, meaning the microcontroller 10 can transmit relevant data to the second off-chip non-volatile memory 220 through the serial communication interface.

[0069] In this embodiment, the first external non-volatile memory 210 can be used to store elevator operation data that needs to be retained after power loss from the on-chip volatile memory 120 during elevator operation. This elevator operation data can refer to data related to elevator operation, such as elevator safety-related data and elevator operation control-related data. When the microcomputer controls the elevator operation, this data needs to be retained after power loss. It is understood that this data has high real-time requirements and is constantly read and written during the microcomputer-controlled elevator operation. It should be noted that not all elevator operation control-related data needs to be retained after power loss; only some data, such as the car position, needs to be retained after power loss.

[0070] The second external non-volatile memory 220 can be used to store elevator operating status data that needs to be retained even when power is off, which comes from the on-chip volatile memory 120 during elevator operation. The elevator operating status data can refer to data related to elevator operating status records, such as data that users or systems use to monitor elevator operating status online. When the microcomputer controls the elevator to run, this part of the data needs to be retained even when power is off. It can be understood that this part of the data is generally recorded when the elevator operation meets the user-set conditions, and it is required that the data can be retained even when the elevator is powered off, so that users can read and analyze the elevator operating status at any time.

[0071] This application embodiment stores elevator operation data that needs to be retained during power loss from the on-chip volatile memory through a first external non-volatile memory, and stores elevator operation status data that needs to be retained during power loss from the on-chip volatile memory through a second external non-volatile memory. This allows the data that needs to be retained during power loss during elevator operation to be stored even when the elevator is powered off, through storage configuration.

[0072] The aforementioned elevator control system, through low-cost but performance-limited on-chip volatile memory and on-chip non-volatile memory, as well as a first off-chip non-volatile memory and a second off-chip non-volatile memory, achieves the ability to retain some data in elevator operation control even after the main control board is powered off, by configuring the storage. This solves the problem of using low-cost but performance-limited (including space, access speed, and erase / write cycles) memory to store a large amount of elevator operation control data in the elevator main control board in order to achieve the same effect as high-cost, high-performance memory.

[0073] In some embodiments, elevator control data includes elevator control programs and elevator specification parameters; such as Figure 2 As shown, an embodiment of the on-chip non-volatile memory may include an on-chip program memory and an on-chip data memory, wherein the on-chip program memory is used to store elevator control programs, and the on-chip data memory is used to store elevator specification parameters and elevator operation monitoring conditions.

[0074] The microcontroller is used to write the elevator operation monitoring conditions from the on-chip volatile memory to the on-chip data memory when the operating conditions change, and to write the elevator operation monitoring conditions from the on-chip data memory to the on-chip volatile memory when power-on initialization.

[0075] Specifically, elevator control data includes elevator control programs and elevator specifications. These specifications may include, but are not limited to, elevator load capacity, speed, main unit parameters, door operator parameters, number of service floors, number of doors opened, and displayed content.

[0076] In this embodiment, the on-chip non-volatile memory can be divided into on-chip program memory and on-chip data memory. The on-chip program memory stores the elevator control program, and the on-chip data memory stores elevator specifications. Furthermore, the on-chip data memory also stores elevator operation monitoring conditions that need to be retained even after power loss, obtained from the on-chip volatile memory. It is understood that in practical applications, the on-chip data memory can be divided into regions (e.g., a first partition and a second partition) to store elevator specifications and elevator operation monitoring conditions respectively.

[0077] Optionally, the on-chip volatile memory can be divided into multiple volatile memories (e.g., RAM memory). One of the multiple volatile memories can be used to store elevator operation monitoring conditions and elevator operation status data. For example, the volatile memory can be divided into regions (e.g., an operation status condition region and an operation status data region) to store elevator operation monitoring conditions and elevator operation status data respectively. In one possible implementation, elevator operation data may include elevator operation safety data and elevator operation control data. Therefore, the other two volatile memories mentioned above can be used to store elevator operation safety data and elevator operation control data respectively.

[0078] Furthermore, the microcontroller can be used to write the elevator operation monitoring conditions from the on-chip volatile memory to the on-chip data memory when the operating state conditions change, and to write the elevator operation monitoring conditions from the on-chip data memory to the on-chip volatile memory during power-on initialization, thereby achieving power-off retention of the elevator operation monitoring conditions. Changes in operating state conditions can include normal elevator operation, maintenance, fault, entrapment, emergency operation (including power outages, fire alarms, earthquakes, etc.), and abnormal elevator stop states. This application does not limit these states.

[0079] It should be noted that the microcontroller writes the elevator operation monitoring conditions into the on-chip data memory, which can be an overwrite storage, that is, the microcontroller stores the elevator operation monitoring conditions in the on-chip data memory in an overwrite manner.

[0080] In one embodiment, the on-chip non-volatile memory is an on-chip Flash memory, the on-chip program memory is an on-chip program Flash memory, and the on-chip data memory is an on-chip data Flash memory.

[0081] Specifically, the on-chip non-volatile memory in the embodiments of this application can be an on-chip Flash memory, which can be divided into on-chip program Flash memory and on-chip data Flash memory.

[0082] It is understood that the on-chip non-volatile memory mentioned above can also be other types of memory, not limited to the forms already mentioned in the above embodiments, as long as it can achieve the function of low-cost power-down retention.

[0083] This application embodiment utilizes an on-chip non-volatile memory configuration to ensure that elevator control data and elevator operation monitoring conditions that need to be retained even after power failure can still be stored after the main control board loses power. This achieves the same effect as high-cost, high-performance memory by using a low-cost but performance-limited memory (including space, access speed, and erase / write cycles) to store a large amount of elevator operation control data.

[0084] In one embodiment, the elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip volatile memory is on-chip RAM memory, such as... Figure 3 As shown, an embodiment of the on-chip RAM memory may include:

[0085] The first RAM memory is used to store elevator operation safety data;

[0086] The second RAM memory is used to store elevator operation control data;

[0087] The third RAM memory is used to store elevator operation monitoring conditions and elevator operation status data;

[0088] The microcontroller is used to write elevator operation safety data from the first RAM memory and elevator operation control data from the second RAM memory into the first external non-volatile memory based on the write cycle; and to write elevator operation safety data from the first external non-volatile memory into the first RAM memory and elevator operation control data from the first external non-volatile memory into the second RAM memory after power failure and power-on initialization.

[0089] The microcontroller is also used to write elevator operating status data from the third RAM memory to the second external non-volatile memory when the elevator is in an abnormal operating state.

[0090] Specifically, elevator operation data may include elevator operation safety data and elevator operation control data; the on-chip non-volatile memory in this embodiment may be an on-chip RAM memory, and the on-chip RAM memory may be divided into a first RAM memory, a second RAM memory and a third RAM memory. The first RAM memory is used to store elevator operation safety data, the second RAM memory is used to store elevator operation control data, and the third RAM memory is used to store elevator operation monitoring conditions and elevator operation status data.

[0091] Elevator operation safety data can refer to elevator safety-related data, such as elevator operation mode and safety circuit status; elevator operation control data can refer to elevator operation control-related data, such as operation commands, brake commands, car position, car speed, and door opening / closing commands; elevator operation status data can refer to data related to elevator operation status records, including data related to elevator calling, display, and operation status recording, such as internal and external call logins and indicator data. This application embodiment does not limit these aspects.

[0092] For example, the first RAM memory and the second RAM memory may have ECC (Error Checking and Correcting) function, which can detect and correct single-bit errors caused by electromagnetic interference or hardware failure, and are used to store key tasks and variables of elevator control, so as to improve the stability and reliability of the elevator control system.

[0093] Furthermore, the microcontroller can be used to write elevator operation safety data from the first RAM memory and elevator operation control data from the second RAM memory into the first off-chip non-volatile memory based on the write cycle, so as to complete the backup storage; wherein, the write cycle can be set according to the data real-time requirements (such as 10ms, 40ms, etc.).

[0094] The microcontroller is used to write elevator operation safety data from the first external non-volatile memory into the first RAM memory and elevator operation control data from the first external non-volatile memory into the second RAM memory during power-on initialization after a power outage, so as to realize the data retention function after power failure; wherein, power-on initialization after power failure can refer to the situation where the microcontroller performs initialization after the elevator is powered off and then powered on again.

[0095] The microcontroller is also used to write elevator operating status data from the third RAM memory to the second external non-volatile memory when the elevator is in an abnormal operating state, thus achieving data retention even after power failure. When a user needs to read the operating record data, the microcontroller can directly read the recorded data from the second external non-volatile memory and send it to the user. It can be understood that the second external non-volatile memory can store the written elevator operating status data sequentially to ensure data integrity and meet user retrieval requirements.

[0096] It is understood that the on-chip volatile memory mentioned above can also be other types of memory, not limited to the forms already mentioned in the above embodiments, as long as they can achieve the function of low-cost data retention after power loss.

[0097] In one embodiment, the first external non-volatile memory is connected to the microcontroller via a serial communication interface.

[0098] Specifically, the microcontroller can transmit elevator operation safety data and elevator operation control data to a first external non-volatile memory for backup storage via a serial communication interface. Alternatively, it can copy the backup data from the first external non-volatile memory to a first RAM memory and a second RAM memory via the serial communication interface to achieve data retention even after power loss. For example, the serial communication interface can be an SPI (Serial Peripheral interface).

[0099] Optionally, the second external non-volatile memory can also be connected to the microcontroller via a serial communication interface and perform related data transmission backup to achieve data retention function after power failure.

[0100] In some embodiments, the elevator control system may further include a direct memory access controller connected to a microcontroller; the microcontroller is configured to start the direct memory access controller when a write cycle arrives, so that the direct memory access controller writes elevator operation safety data in a first RAM memory and elevator operation control data in a second RAM memory into a first off-chip non-volatile memory via a serial communication interface.

[0101] Specifically, the microcontroller can start the direct memory access controller when the write cycle arrives. For example, the microcomputer can periodically start the DMAC (Direct Memory Access Controller) to copy the data in the first RAM memory and the second RAM memory to the transmit buffer of the serial communication interface (such as SPI), and then transmit it to the first external non-volatile memory through the serial communication interface (such as SPI) to complete the backup storage.

[0102] like Figure 4 As shown, taking a microcontroller using a CPU and an external NvRAM as the first non-volatile memory as the first external NvRAM, a power-down retention (DPWR) storage area (i.e., the first DPWR storage area) can be partitioned in the first RAM, and a DPWR storage area (i.e., the second DPWR storage area) can be partitioned in the second RAM. The data in the DPWR storage area needs to be retained even when the power is lost. Alternatively, n areas (area 1, area 2, ..., area n) can be partitioned in the external NvRAM. Then, the microcomputer can periodically start the DMAC (Direct Memory Access Controller) to copy the data from the DPWR storage areas of the first and second RAM to the transmit buffer of the serial communication interface (such as SPI), and then transmit it to the external NvRAM for backup storage via the serial communication interface (such as SPI).

[0103] Furthermore, when the elevator is powered on again after a power outage, the microcomputer can copy the backup data from the first RAM memory and the second RAM memory in the off-chip NvRAM memory to the first RAM memory and the second RAM memory respectively through a serial communication interface (such as SPI) during initialization, thus realizing the data retention function after power failure.

[0104] In one embodiment, the first off-chip non-volatile memory is an off-chip NvRAM memory, and the second off-chip non-volatile memory is an off-chip Flash memory.

[0105] Specifically, the first off-chip non-volatile memory can be an off-chip NvRAM (Non-Volatile Random Access Memory) memory, and the second off-chip non-volatile memory can be an off-chip Flash memory.

[0106] For example, the off-chip NvRAM memory is a non-volatile memory that may have a serial communication interface for storing periodically changing data that needs to be retained even when power is off. Optionally, the off-chip Flash memory is a non-volatile memory that may have a serial communication interface for storing event-driven elevator operation data, status records, and other data that needs to be retained even when power is off.

[0107] It is understood that the above-mentioned off-chip non-volatile memory can also be other types of memory, not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of low-cost power-down retention.

[0108] Furthermore, such as Figure 5As shown, an elevator control system in one embodiment may include an on-chip program Flash memory, an on-chip data Flash memory, a first RAM memory, a second RAM memory, a third RAM memory, an off-chip NvRAM memory, and an off-chip Flash memory. The above-described elevator control system, through its storage configuration, solves the problem of achieving the same effect as high-cost, high-performance memories using low-cost but performance-limited memories (including space, access speed, and erase / write cycles).

[0109] Based on the same inventive concept, this application provides an elevator control method based on the aforementioned elevator control system. The elevator control method provided in this application can be applied to the microcontroller in the aforementioned elevator control system, that is, the microcontroller executes the elevator control method in this application. In an exemplary embodiment, such as... Figure 6 As shown, an elevator control method is provided. Taking the application of this method to a microcontroller in an elevator control system as an example, the method includes the following steps 302 to 306, wherein:

[0110] Step 302: Write the elevator control data and the elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory into the on-chip non-volatile memory.

[0111] Step 304: Write the elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory.

[0112] Step 306: Write the elevator running status data that needs to be retained after power failure from the on-chip volatile memory into the second off-chip non-volatile memory.

[0113] Specifically, based on the configuration of the elevator control system described above, the microcontroller can use the corresponding data storage control method to ensure that the data that needs to be retained during elevator operation control can still be stored after the main control board loses power.

[0114] Specifically, the microcontroller can write elevator control data and elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory into the on-chip non-volatile memory, write elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory, and write elevator operation status data that needs to be retained after power failure from the on-chip volatile memory into the second off-chip non-volatile memory.

[0115] It should be noted that the concepts and specific storage methods of the elevator control data, elevator operation monitoring conditions, elevator operation data, and elevator operation status data mentioned above can be found in the relevant descriptions of the elevator control system mentioned earlier, and will not be repeated here.

[0116] In one embodiment, the elevator control data includes an elevator control program and elevator specification parameters; the on-chip non-volatile memory includes on-chip program memory and on-chip data memory.

[0117] Elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory, are written into the on-chip non-volatile memory, including:

[0118] Write the elevator control program into the on-chip program memory;

[0119] The first partition and the second partition are identified in the on-chip data memory; the first partition is a partition allocated from the on-chip data memory for storing elevator specification parameters, and the second partition is a partition allocated from the on-chip data memory for storing elevator operation monitoring conditions.

[0120] Store the elevator specifications in the first partition;

[0121] When the operating conditions change, the operating conditions region is identified in the on-chip volatile memory; the operating conditions region is a partition from the on-chip volatile memory used to store elevator operation monitoring conditions; the elevator operation monitoring conditions in the operating conditions region are stored in the second partition.

[0122] Upon power-on initialization, the elevator operation monitoring conditions in the second partition are written into the operation status conditions area.

[0123] Specifically, the microcontroller can write the elevator control program into the on-chip program memory. For example, taking the on-chip program memory as an example, the on-chip program flash memory can be used to store the elevator control program.

[0124] Furthermore, the microcontroller can identify a first partition and a second partition in the on-chip data memory; the first partition is a partition allocated from the on-chip data memory for storing elevator specification parameters, and the second partition is a partition allocated from the on-chip data memory for storing elevator operation monitoring conditions. The microcontroller can then store the elevator specification parameters in the first partition and, when the operating conditions change, store the elevator operation monitoring conditions from the operating condition area in the second partition. In this embodiment, the on-chip data memory stores elevator specification parameters and elevator operation monitoring conditions in different areas respectively.

[0125] When the operating conditions change, the microcontroller can identify the operating condition region in the on-chip volatile memory. The operating condition region is a partition of the on-chip volatile memory used to store elevator operation monitoring conditions. The microcontroller stores the elevator operation monitoring conditions in the operating condition region in the second partition. Then, during power-on initialization, the microcontroller writes the elevator operation monitoring conditions in the second partition into the operating condition region.

[0126] It should be noted that the "operation status condition area" can refer to the area for storing the online monitoring elevator's operation status conditions, i.e., the storage area for these conditions. Taking on-chip volatile memory as on-chip RAM, and dividing the on-chip RAM into a first RAM, a second RAM, and a third RAM, as an example, the microcontroller can identify the operation status condition area and the operation status data area within the third RAM. The operation status condition area is a partition from the third RAM used to store elevator operation monitoring conditions; the operation status data area is a partition from the third RAM used to store elevator operation status data. The operation status data area can refer to the area for storing online monitoring elevator operation status data.

[0127] In some embodiments, elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip non-volatile memory includes a first RAM memory, a second RAM memory, and a third RAM memory;

[0128] The process of writing elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory includes:

[0129] A first power-down retention storage area is identified in a first RAM memory, and a second power-down retention storage area is identified in a second RAM memory; the first power-down retention storage area is a partition from the first RAM memory used to store elevator operation safety data; the second power-down retention storage area is a partition from the second RAM memory used to store elevator operation control data.

[0130] Elevator operation safety data is stored in the first power failure retention storage area, and elevator operation control data is written to the second power failure retention storage area.

[0131] When the write cycle arrives, the elevator operation safety data in the first power-down retention storage area and the elevator operation control data in the second power-down retention storage area are written to the first external non-volatile memory.

[0132] In the case of power failure and power-on initialization, the elevator operation safety data in the first external non-volatile memory is written into the first power failure retention storage area, and the elevator operation control data in the first external non-volatile memory is written into the second power failure retention storage area.

[0133] The process of writing elevator operating status data that needs to be retained even after power failure from the on-chip volatile memory to a second off-chip non-volatile memory includes:

[0134] The operating status data area is identified in the third RAM memory; the operating status data area is a partition allocated from the third RAM memory for storing elevator operating status data;

[0135] Multiple storage areas were identified in the second external non-volatile memory; the storage areas are partitions allocated from the second external non-volatile memory for storing elevator operating status data;

[0136] When the elevator is in an abnormal working state, the elevator operating status data is stored in the operating status data area. The target storage area is selected from multiple storage areas, and the elevator operating status data in the operating status data area is written to the target storage area.

[0137] Specifically, when the number of erase / write cycles of the target storage area reaches the lifetime threshold, the next storage area is designated as the target storage area; the next storage area is a storage area other than the target storage area among multiple storage areas.

[0138] Specifically, the implementation process of writing elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory can be found in the previous description, and will not be repeated here.

[0139] Regarding writing elevator operating status data that needs to be retained after power failure from the on-chip volatile memory into a second off-chip non-volatile memory, the microcontroller can identify the operating status data area in the third RAM memory for storing the elevator operating status data.

[0140] Furthermore, the microcontroller can identify multiple storage areas in the second external non-volatile memory, which are partitions allocated from the second external non-volatile memory for storing elevator operating status data. For example, such as... Figure 7 As shown, multiple storage regions can be divided in the second external non-volatile memory, namely the first region, the second region, the third region... the Nth region.

[0141] When the elevator is in an abnormal operating state, the microcontroller can store the elevator's operating status data in the operating status data area and select a target storage area from multiple storage areas to write the elevator's operating status data from the operating status data area into the target storage area. If the number of erase / write cycles in the target storage area reaches a lifespan threshold, the next storage area will be selected as the target storage area. The next storage area is any of the multiple storage areas excluding the target storage area. It can be understood that when the microcontroller detects that the elevator operation meets preset conditions, it can determine that the elevator is in an abnormal operating state. Optionally, the preset conditions may include elevator malfunction, passenger entrapment, abnormal elevator stop, etc.

[0142] Through the above storage method, the embodiments of this application can achieve the purpose of increasing the number of erase / write cycles using space. For example, when the microcomputer detects that the elevator operation meets preset conditions, it can record the elevator operation status data on the third RAM memory, that is, store the elevator operation status data in the operation status data area of ​​the third RAM memory, and at the same time copy the data recorded in the third RAM memory to the first area of ​​the external Flash memory for backup storage (that is, use the first area as the target storage area), and record the number of erase / write cycles of the first area of ​​the external Flash memory. When the microcomputer detects that the number of erase / write cycles of the first area of ​​the external Flash memory is about to reach the lifespan threshold, it copies the data recorded in the third RAM memory to the second area (that is, use the second area as the target storage area), and so on, thus achieving the design purpose of increasing the number of erase / write cycles using space.

[0143] To further illustrate the method of this application, a specific example is provided below to demonstrate its application. Figure 5 Taking the elevator control system shown as an example, the elevator control system may include an on-chip program Flash memory, an on-chip data Flash memory, a first RAM memory, a second RAM memory, a third RAM memory, an off-chip NvRAM memory, and an off-chip Flash memory. The off-chip NvRAM memory and the off-chip Flash memory are connected to the microcontroller of the elevator control system through a serial communication interface.

[0144] First, the storage content and storage method of the memory in the embodiments of this application are shown in Table 1 below:

[0145] Table 1 - List of stored contents of the memory

[0146]

[0147] Regarding the control method for storing data in the on-chip Flash memory, due to its limited storage space and limited number of erase / write cycles, the on-chip Flash memory is suitable for storing data that does not need frequent changes, has a small data volume, and needs to be retained even after power loss. When a microcomputer controls an elevator, some data needs to be retained even after power loss. This data consists of conditions set by the user or system for online monitoring of the elevator's operating status (i.e., elevator operation monitoring conditions). This data generally remains unchanged for a considerable period after being set, including during power outages. The control methods for storing this data can include:

[0148] 1) First, the online monitoring elevator operation status condition area (i.e., operation status condition area) is divided in the third RAM memory.

[0149] 2) When the microcomputer detects a change in the operating status conditions, it copies the data from the online monitoring elevator operating status condition area of ​​the third RAM memory to the on-chip data Flash memory to complete the backup storage.

[0150] 3) When the elevator is powered on, the microcomputer performs initialization and copies the power-off retained data stored in the on-chip data Flash memory to the online monitoring elevator operation status condition area of ​​the third RAM memory.

[0151] Regarding the control method for storing data in off-chip NvRAM memory, off-chip NvRAM memory has limited storage space but unlimited erase and write cycles, making it suitable for storing critical control data that needs to be frequently read and written and needs to be retained even when power is off.

[0152] When a microcomputer-controlled elevator is running, some data needs to be retained even after power loss. This data is used by the microcomputer to control the elevator (i.e., data related to elevator operation control), such as the car's position in the hoistway. This data has high real-time requirements and is constantly read and written during the operation of the microcomputer-controlled elevator. Data storage and control methods for this part can include:

[0153] 1) First, power-loss retention storage areas are divided into the first RAM memory and the second RAM memory respectively. The data in these storage areas needs to have power-loss retention function.

[0154] 2) The microcomputer reads and writes to the first RAM memory and the second RAM memory according to the needs of controlling the elevator operation. At the same time, according to the real-time requirements of the data, it periodically (such as 10ms, 40ms, etc.) transmits the data of the power-off retention storage area of ​​the first RAM memory and the second RAM memory to the off-chip NvRAM memory through the serial communication port (such as SPI) to complete the backup storage.

[0155] Furthermore, the microcomputer can also periodically start the DMAC direct memory access controller to copy the data in the power-off retention area of ​​the first RAM memory and the second RAM memory to the transmit buffer of the serial communication port (such as SPI), and then transmit it to the off-chip NvRAM memory to complete the backup storage.

[0156] 3) When the elevator is powered off and then powered on again, the microcomputer copies the backup data of the first RAM memory and the second RAM memory in the external NvRAM memory to the first RAM memory and the second RAM memory through the serial communication port (such as SPI) during initialization, so as to realize the data retention function after power failure.

[0157] Regarding the control method for storing data in off-chip Flash memory, off-chip Flash memory has a limited number of erase / write cycles but relatively abundant storage space. It is suitable for storing data that needs to be frequently changed, has a large amount of data, and needs to be retained even when power is off.

[0158] When a microcomputer-controlled elevator is running, some data needs to be retained even after power loss. This data is for users or the system to monitor the elevator's operating status online (i.e., elevator operating status data). This data is typically recorded when the elevator meets user-set conditions and must be stored even after power is interrupted, so that users can access and analyze the elevator's operating status at any time. Data storage and control methods for this portion can include:

[0159] 1) First, an area for online monitoring of elevator operation status data is allocated in the third RAM memory, and multiple storage areas (e.g., the first area, the second area... the Nth area) are allocated in the off-chip Flash memory.

[0160] 2) When the microcomputer detects that the elevator operation meets the preset conditions, it can record the operating status data in the third RAM memory. At the same time, it copies the data recorded in the third RAM memory to the first area of ​​the external Flash memory for backup storage, and records the number of erase / write cycles of the first area of ​​the external Flash memory. When the microcomputer detects that the number of erase / write cycles of the first area of ​​the external Flash memory is about to reach the lifespan threshold, it copies the data recorded in the third RAM memory to the second area, and so on, achieving the design purpose of using space to increase the number of erase / write cycles.

[0161] 3) When a user needs to read the running record data, the microcomputer directly reads the data recorded in the external Flash memory and sends it to the user.

[0162] In summary, the embodiments of this application use a low-cost but performance-limited (including space, access speed, and erase / write cycles) memory to achieve the same design purpose as a high-cost, high-performance memory.

[0163] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0164] Based on the same inventive concept, this application also provides an elevator control device for implementing the elevator control method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more elevator control device embodiments provided below can be found in the limitations of the elevator control method described above, and will not be repeated here.

[0165] In one exemplary embodiment, an elevator control device is provided, comprising:

[0166] The data writing module is used to write elevator control data and elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory into the on-chip non-volatile memory.

[0167] The first power-down write module is used to write elevator operation data that needs to be retained during power-down from the on-chip volatile memory into the first off-chip non-volatile memory.

[0168] The second power-down write module is used to write elevator operating status data that needs to be retained during power-down from the on-chip volatile memory into the second off-chip non-volatile memory.

[0169] In one embodiment, the elevator control data includes an elevator control program and elevator specification parameters; the on-chip non-volatile memory includes on-chip program memory and on-chip data memory.

[0170] The data writing module is used to write the elevator control program into the on-chip program memory; identify a first partition and a second partition in the on-chip data memory; the first partition is a partition allocated from the on-chip data memory for storing elevator specification parameters, and the second partition is a partition allocated from the on-chip data memory for storing elevator operation monitoring conditions; store the elevator specification parameters in the first partition; when the operating status conditions change, identify the operating status condition area in the on-chip volatile memory; the operating status condition area is a partition allocated from the on-chip volatile memory for storing elevator operation monitoring conditions; store the elevator operation monitoring conditions in the operating status condition area in the second partition; and when power-on initialization occurs, write the elevator operation monitoring conditions in the second partition into the operating status condition area.

[0171] In one embodiment, the elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip non-volatile memory includes a first RAM memory, a second RAM memory, and a third RAM memory; a first power-down write module is used to identify a first power-down retention storage area in the first RAM memory and a second power-down retention storage area in the second RAM memory; the first power-down retention storage area is a partition from the first RAM memory used to store elevator operation safety data; the second power-down retention storage area is a partition from the second RAM memory used to store elevator operation control data; the elevator operation safety data is stored in the first power-down retention storage area, and the elevator operation control data is written to the second power-down retention storage area; when the write cycle arrives, the elevator operation safety data in the first power-down retention storage area and the elevator operation control data in the second power-down retention storage area are written to the first off-chip non-volatile memory; and in the case of power-on initialization after power failure, the elevator operation safety data in the first off-chip non-volatile memory is written to the first power-down retention storage area, and the elevator operation control data in the first off-chip non-volatile memory is written to the second power-down retention storage area;

[0172] The second power-down write module is used to identify the operating status data area in the third RAM memory; the operating status data area is a partition allocated from the third RAM memory for storing elevator operating status data; identify multiple storage areas in the second external non-volatile memory; the storage areas are partitions allocated from the second external non-volatile memory for storing elevator operating status data; and when the elevator is in an abnormal operating state, store the elevator operating status data in the operating status data area, select a target storage area from the multiple storage areas, and write the elevator operating status data in the operating status data area into the target storage area; wherein, when the erase / write cycles of the target storage area reach the lifespan threshold, the next storage area is selected as the target storage area; the next storage area is a storage area other than the target storage area among the multiple storage areas.

[0173] The modules in the aforementioned elevator control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the computer device's memory as software, so that the processor can call and execute the corresponding operations of each module.

[0174] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0175] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0176] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0177] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0178] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0179] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An elevator control system, characterized in that, Includes a microcontroller and off-chip memory connected to the microcontroller; wherein: The microcontroller includes on-chip volatile memory and on-chip non-volatile memory; the on-chip non-volatile memory is used to store elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory during elevator operation. The off-chip memory includes a first off-chip non-volatile memory and a second off-chip non-volatile memory connected to the microcontroller; the first off-chip non-volatile memory is used to store elevator operation data that needs to be retained after power failure from the on-chip volatile memory during elevator operation, and the second off-chip non-volatile memory is used to store elevator operation status data that needs to be retained after power failure from the on-chip volatile memory during elevator operation.

2. The elevator control system according to claim 1, characterized in that, The elevator control data includes the elevator control program and elevator specification parameters; the on-chip non-volatile memory includes: An on-chip program memory is used to store the elevator control program; The on-chip data storage is used to store the elevator specifications and the elevator operation monitoring conditions; The microcontroller is configured to write the elevator operation monitoring conditions from the on-chip volatile memory into the on-chip data memory when the operating conditions change, and to write the elevator operation monitoring conditions from the on-chip data memory into the on-chip volatile memory during power-on initialization.

3. The elevator control system according to claim 2, characterized in that, The on-chip non-volatile memory is an on-chip Flash memory, the on-chip program memory is an on-chip program Flash memory, and the on-chip data memory is an on-chip data Flash memory.

4. The elevator control system according to claim 1, characterized in that, The elevator operation data includes elevator operation safety data and elevator operation control data; The on-chip volatile memory is an on-chip RAM memory, which includes: A first RAM memory is used to store the elevator's operational safety data; The second RAM memory is used to store the elevator operation control data; The third RAM memory is used to store the elevator operation monitoring conditions and the elevator operation status data; The microcontroller is configured to write the elevator operation safety data in the first RAM memory and the elevator operation control data in the second RAM memory into the first off-chip non-volatile memory based on a write cycle; and to write the elevator operation safety data in the first off-chip non-volatile memory into the first RAM memory and the elevator operation control data in the first off-chip non-volatile memory into the second RAM memory during power-on initialization after power failure. The microcontroller is also used to write the elevator operating status data from the third RAM memory into the second off-chip non-volatile memory when the elevator is in an abnormal operating state.

5. The elevator control system according to claim 4, characterized in that, The first external non-volatile memory is connected to the microcontroller via a serial communication interface.

6. The elevator control system according to claim 5, characterized in that, The elevator control system also includes a direct memory access controller connected to the microcontroller; The microcontroller is used to start the direct memory access controller when the write cycle arrives, so that the direct memory access controller writes the elevator operation safety data in the first RAM memory and the elevator operation control data in the second RAM memory into the first off-chip non-volatile memory through the serial communication interface.

7. The elevator control system according to any one of claims 1 or 4 to 6, characterized in that, The first off-chip non-volatile memory is an off-chip NvRAM memory, and the second off-chip non-volatile memory is an off-chip Flash memory.

8. An elevator control method, characterized in that, The method, applied to a microcontroller in an elevator control system as described in any one of claims 1 to 7, comprises: Elevator control data, as well as elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory, are written into the on-chip non-volatile memory. During elevator operation, elevator operation data that needs to be retained after power failure from the on-chip volatile memory is written into the first off-chip non-volatile memory. The elevator operating status data that needs to be retained after power failure, from the on-chip volatile memory, is written into the second off-chip non-volatile memory.

9. The method according to claim 8, characterized in that, The elevator control data includes the elevator control program and elevator specification parameters; the on-chip non-volatile memory includes on-chip program memory and on-chip data memory. Writing elevator control data and elevator operation monitoring conditions that need to be retained after power failure from the on-chip volatile memory into the on-chip non-volatile memory includes: Write the elevator control program into the on-chip program memory; A first partition and a second partition are identified in the on-chip data memory; the first partition is a partition allocated from the on-chip data memory for storing the elevator specification parameters, and the second partition is a partition allocated from the on-chip data memory for storing the elevator operation monitoring conditions. The elevator specifications are stored in the first partition; When the operating conditions change, the operating conditions region is identified in the on-chip volatile memory; the operating conditions region is a partition from the on-chip volatile memory used to store the elevator operation monitoring conditions; the elevator operation monitoring conditions in the operating conditions region are stored in the second partition; Upon power-on initialization, the elevator operation monitoring conditions in the second partition are written into the operation status conditions area.

10. The method according to claim 8, characterized in that, The elevator operation data includes elevator operation safety data and elevator operation control data; the on-chip non-volatile memory includes a first RAM memory, a second RAM memory, and a third RAM memory; Writing elevator operation data that needs to be retained after power failure from the on-chip volatile memory into the first off-chip non-volatile memory includes: A first power-down retention storage area is identified in the first RAM memory, and a second power-down retention storage area is identified in the second RAM memory; the first power-down retention storage area is a partition allocated from the first RAM memory for storing the elevator operation safety data; the second power-down retention storage area is a partition allocated from the second RAM memory for storing the elevator operation control data; The elevator operation safety data is stored in the first power failure retention storage area, and the elevator operation control data is written into the second power failure retention storage area; When the write cycle arrives, the elevator operation safety data in the first power-down retention storage area and the elevator operation control data in the second power-down retention storage area are written into the first off-chip non-volatile memory. In the case of power-on initialization after power failure, the elevator operation safety data in the first external non-volatile memory is written into the first power-down retention storage area, and the elevator operation control data in the first external non-volatile memory is written into the second power-down retention storage area. Writing elevator operating status data that needs to be retained after power failure from the on-chip volatile memory into the second off-chip non-volatile memory includes: An operating status data area is identified in the third RAM memory; the operating status data area is a partition allocated from the third RAM memory for storing the elevator operating status data; Multiple storage areas are identified in the second external non-volatile memory; the storage areas are partitions allocated from the second external non-volatile memory for storing the elevator operating status data; When the elevator is in an abnormal working state, the elevator operating status data is stored in the operating status data area, a target storage area is selected from the plurality of storage areas, and the elevator operating status data in the operating status data area is written into the target storage area; Wherein, if the number of erase / write cycles of the target storage area reaches the lifetime count threshold, the next storage area is designated as the target storage area; the next storage area is a storage area other than the target storage area among the plurality of storage areas.

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