High linearity dual-redundancy pressure sensor chip preparation method and chip

Abstract

The application provides a high-linearity dual-redundancy pressure sensor chip preparation method and a chip, and belongs to the technical field of pressure sensors. The method first grows SiO2 oxide layers on two opposite surfaces of a silicon substrate, performs photoetching to form a sensitive resistance area and a contact hole, forms a PN junction through ion implantation to obtain a first substrate; grows a silicon nitride film on two opposite surfaces of the first substrate, performs secondary photoetching on the contact hole to expose the silicon substrate to obtain a second substrate; uses negative glue to photoetch two pre-set shape pressure welding points on two opposite surfaces of the second substrate respectively to obtain a third substrate; deposits a metal electrode, removes the glue to form an ohmic contact to obtain a fourth substrate, and performs etching on a silicon cup and electrostatic sealing with glass to complete the preparation. Through the symmetrical structure design and process steps, the application realizes the precise preparation of the dual-redundancy sensing structure, effectively improves the linearity and reliability of the sensor chip, and is suitable for pressure detection scenes with high requirements for measurement accuracy and stability.

Description

Technical Field

[0001] This invention relates to the field of pressure sensor technology, and in particular to a method for fabricating a high linearity dual-redundancy pressure sensor chip and the chip itself. Background Technology

[0002] Piezoresistive diffused silicon pressure sensors are widely used in industrial measurement and control fields due to their large output signal, simple supporting circuit, and ability to simultaneously measure pressure and differential pressure. They are an important part of the current sensor market.

[0003] Currently, mainstream piezoresistive sensors generally use a Wheatstone bridge composed of four sensitive resistors as the sensing core. The principle is to use the characteristic that the resistance values ​​of adjacent sensitive resistors change in opposite directions when the diaphragm is deformed by force to realize pressure detection.

[0004] However, this existing technology has significant drawbacks: when the pressure-sensitive diaphragm deforms under stress, adjacent sensitive resistors at different positions on the diaphragm experience stresses that are neither strictly equal in magnitude nor completely opposite in direction. This stress asymmetry directly leads to nonlinearity in the bridge output signal, which is particularly severe when operating beyond its range. To correct this nonlinearity, complex point-by-point compensation must be performed in the back-end circuitry, significantly increasing the circuit design complexity and overall packaging cost. Furthermore, these chips are all single-redundant designs, inherently limiting their reliability. To improve system reliability, multiple independent sensors are typically deployed for redundant measurements, further increasing system cost and complexity. Summary of the Invention

[0005] This invention provides a method for fabricating a high linearity dual-redundancy pressure sensor chip and the chip itself, in order to solve the technical problems of insufficient structural reliability and high manufacturing cost of sensor chips.

[0006] In a first aspect, the present invention provides a method for fabricating a high linearity dual-redundancy pressure sensor chip, comprising: Growth is performed on two opposing surfaces of a silicon substrate. Oxide layer.

[0007] For growth The surface of the oxide layer is photolithographically processed to form a sensitive resistor region of a predetermined shape and at least one contact hole; the bottom surface of the sensitive resistor region and the contact hole is a silicon substrate, and the sensitive resistor region is used to set the sensitive resistor.

[0008] Ion implantation is performed on the sensitive resistor region and contact hole to form a PN junction, thus obtaining the first substrate.

[0009] Silicon nitride thin films are grown on the two opposite surfaces of the first substrate.

[0010] The contact holes of the silicon nitride thin film grown on the first substrate are subjected to photolithography so that the bottom surface of the contact holes on the first substrate is a silicon substrate, thus obtaining the second substrate.

[0011] Two pre-defined bonding pads are photolithographically formed on two opposite surfaces of the second substrate using negative adhesive to obtain the third substrate. The two bonding pads are located on both sides of the sensitive resistor region, and one of the bonding pads is located at the same position as the contact hole. The bottom surface of the bonding pad near the center of the third substrate is a silicon nitride film, and the bottom surface of the bonding pad corresponding to the contact hole is a silicon substrate.

[0012] Metal electrodes are deposited on the two opposing surfaces of the third substrate.

[0013] The third substrate with deposited metal electrodes is subjected to a desizing process to obtain a fourth substrate; in the fourth substrate, the metal electrodes form an ohmic contact with the third substrate through an alloy annealing process.

[0014] Silicon cups are etched on two opposing surfaces of the fourth substrate, with the bottom of the silicon cups located within the silicon substrate.

[0015] Electrostatic sealing of glass and silicon cup surface yields a high-linearity dual-redundancy pressure sensor chip.

[0016] Optionally, growth is performed on two opposing surfaces of the silicon substrate. Oxide layer, including: An N-type wafer with a first resistivity range is selected as the silicon substrate, and within a first temperature range, growth is performed on two opposing surfaces of the N-type wafer with a first thickness range. Oxide layer.

[0017] The first resistivity range is from 1 ohm·cm to 20 ohm·cm, the first temperature range is from 1000 degrees Celsius to 1150 degrees Celsius, and the first thickness range is from 0.5 micrometers to 3 micrometers.

[0018] Optionally, for growth The surface of the oxide layer is photolithographically processed to form a sensitive resistor region of a predetermined shape and at least one contact hole; the bottom surface of the sensitive resistor region and the contact hole is a silicon substrate, including: At the first rotational speed Photoresist is coated onto the oxide layer.

[0019] The photoresist is subjected to a first baking process, a first exposure process, a first development process, and a first hardening process in sequence to form a sensitive resistor region of a preset shape and at least one contact hole.

[0020] Remove the areas not protected by photoresist The oxide layer region exposes the silicon substrate.

[0021] The first rotational speed is within the first rotational speed range; the duration of the first baking process is within the first baking time range; the duration of the first exposure process is within the first exposure time range; the duration of the first developing process is within the first developing time range; and the duration of the first hardening process is within the first hardening time range.

[0022] Optionally, ion implantation is performed on the sensitive resistor region and the contact hole to form a PN junction, resulting in a first substrate, comprising: The first element is selected as the doping ion source, and ion implantation is performed on the sensitive resistor region and contact hole with the first implantation energy and the first implantation dose to form a PN junction and obtain the first substrate.

[0023] The first injection energy ranges from 10 keEV to 70 keEV, and the first injection dose ranges from... Atoms per square centimeter to The first element per square centimeter is boron.

[0024] Optionally, silicon nitride thin films are grown on two opposing surfaces of the first substrate, including: The two opposing surfaces of the first substrate are cleaned.

[0025] A silicon nitride thin film is grown simultaneously on two opposing surfaces of a first substrate using a first process.

[0026] The first process is LPCVD or PECVD.

[0027] The first process is LPCVD, and the conditions for the first process include: The temperature ranges from 500 degrees Celsius to 850 degrees Celsius. The flow rate is from 100 cubic centimeters per minute to 500 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute.

[0028] The first process is PECVD, and the conditions for the first process include: RF high-frequency power of 100 watts to 600 watts and low-frequency power of 200 watts to 500 watts. The flow rate is from 100 cubic centimeters per minute to 300 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute. The flow rate is 3,000 cubic centimeters per minute to 8,000 cubic centimeters per minute.

[0029] Optionally, the contact holes of the silicon nitride thin film grown on the first substrate are subjected to photolithography to make the bottom surface of the contact holes on the first substrate a silicon substrate, thereby obtaining a second substrate, comprising: Photoresist is coated on the surface of a silicon nitride thin film at a second rotation speed.

[0030] The photoresist is subjected to a second baking process, a second exposure process, a second development process, and a second hardening process in sequence to define the contact hole area.

[0031] Remove the photoresist in the contact hole area and the underlying silicon nitride film to expose the silicon substrate and obtain the second substrate.

[0032] The second rotation speed is within the second rotation speed range, the duration of the second baking process is within the second baking time range, the duration of the second exposure process is within the second exposure time range, the duration of the second developing process is within the second developing time range, and the duration of the second hardening process is within the second hardening time range.

[0033] Optionally, two pre-defined bonding pads are photolithographically formed on two opposite surfaces of the second substrate using negative adhesive to obtain a third substrate, and metal electrodes are deposited on two opposite surfaces of the third substrate, including: The negative adhesive was coated on the two opposite surfaces of the second substrate at a third rotation speed.

[0034] The negative adhesive is subjected to a third baking process, a third exposure process, a third development process, and a third hardening process in sequence, and two bonding points are photolithographically formed.

[0035] Metal layers are deposited on two opposing surfaces of a third substrate using a deposition process to form metal electrodes.

[0036] The third rotation speed is within the range of the third rotation speed, the duration of the third baking process is within the range of the third baking time, the duration of the third exposure process is within the range of the third exposure time, the duration of the third developing process is within the range of the third developing time, and the duration of the third hardening process is within the range of the third hardening time.

[0037] Optionally, the third substrate on which the deposited metal electrode is deposited is subjected to a photoresist removal process to obtain a fourth substrate; in the fourth substrate, the metal electrode forms an ohmic contact with the third substrate through an alloy annealing process, including: The third substrate after the metal electrode is deposited is placed in a resist remover solution to remove residual negative adhesive and metal adhering to the negative adhesive.

[0038] The substrate after desizing is subjected to alloy annealing in the second temperature range to obtain a fourth substrate in which the metal electrode forms an ohmic contact with the silicon substrate.

[0039] The second temperature range is 400 degrees Celsius to 750 degrees Celsius, and the alloy annealing time is within the third time range, which is 20 minutes to 60 minutes.

[0040] Optionally, silicon cups are etched on two opposing surfaces of the fourth substrate, with the bottom surface of the silicon cups located within the silicon substrate, including: A silicon nitride mask is applied to the non-etched area of ​​the fourth substrate to obtain a fourth substrate in which the non-etched area is protected.

[0041] The masked fourth substrate is placed in the first etchant for anisotropic etching to obtain a substrate with a groove of a preset depth.

[0042] After etching, the silicon nitride mask is removed to obtain a silicon cup with its bottom surface located within the silicon substrate.

[0043] The first corrosive agent is a potassium hydroxide solution or a tetramethylammonium hydroxide solution, and the concentration of the first corrosive agent is within a first concentration range, which is 10% to 45%.

[0044] Secondly, this application provides a high linearity dual-redundant pressure sensor chip, fabricated by the high linearity dual-redundant pressure sensor chip fabrication method provided in the first aspect, comprising: Silicon substrate, used as a chip substrate.

[0045] The oxide layer is located on two opposite surfaces of the silicon substrate.

[0046] Depend on After photolithography, the oxide layer forms a pre-shaped sensitive resistor region and at least one contact hole; the bottom surface of the sensitive resistor region and the contact hole is a silicon substrate.

[0047] A PN junction is formed by ion implantation in the sensitive resistance region and the contact hole.

[0048] Covered Silicon nitride film on the surface of oxide layer.

[0049] Two bonding pads are formed on the silicon nitride thin film by photolithography. The two bonding pads are located on both sides of the sensitive resistor region. One bonding pad is located at the same position as the contact hole, and the bottom surface of the bonding pad that is located at the same position as the contact hole is the silicon substrate; the bottom surface of the other bonding pad is the silicon nitride thin film.

[0050] Metal electrodes are deposited on the surface of the bonding pads, and the metal electrodes form ohmic contacts with the silicon substrate through alloy annealing.

[0051] A silicon cup located on two opposite surfaces of a silicon substrate and extending inward.

[0052] And glass bonded to the surface of a silicon cup via electrostatic sealing.

[0053] The sensitive resistor region is located on two opposite surfaces of the chip; multiple sensitive resistors are set in the center of the sensitive resistor region; the silicon cups are positioned complementaryly on the front and back sides, so that the corresponding sensitive resistors in the two Wheatstone bridges are in stress fields with equal stress magnitude and opposite direction.

[0054] The two sensitive resistors on the front and the two sensitive resistors on the back form the first Wheatstone bridge.

[0055] The two sensitive resistors on the front and the two sensitive resistors on the back form a second Wheatstone bridge.

[0056] When the first Wheatstone bridge and the second Wheatstone bridge are connected in parallel, they form a dual-redundant pressure sensor; when connected in series, they form a single-redundant pressure sensor with double the sensitivity.

[0057] This invention provides a method for fabricating a high-linearity dual-redundancy pressure sensor chip and the chip itself, belonging to the field of pressure sensor technology. The method involves growing chips on two opposing surfaces of a silicon substrate. An oxide layer is formed on its surface using photolithography to create a sensitive resistor region of a predetermined shape and at least one contact hole. Ion implantation is then performed on the sensitive resistor region and contact hole to form a PN junction, resulting in a first substrate. Subsequently, silicon nitride films are grown on both surfaces of the first substrate, and a second photolithography is performed on the contact hole locations to expose the underlying silicon substrate, resulting in a second substrate. Next, negative adhesive is used to photolithographically create two pre-defined bonding pads on the two opposite surfaces of the second substrate, resulting in a third substrate. Metal electrodes are then deposited on both surfaces of the third substrate, and after adhesive removal, ohmic contacts are formed between the metal electrodes and the substrate, resulting in a fourth substrate. The double surfaces of the fourth substrate are then etched to form a silicon cup with its bottom surface located inside the silicon substrate. Finally, glass is electrostatically sealed to the surface of the silicon cup to fabricate a high-linearity dual-redundancy pressure sensor chip. The chip's high linearity stems from its complementary symmetrical mechanical structure: by fabricating complementary silicon cups on the front and back sides of the substrate and symmetrically arranging sensitive resistors, corresponding pairs of sensitive resistors in the Wheatstone bridge are placed in stress fields of equal magnitude and opposite direction. The resistance changes of the two resistors are equal in magnitude and opposite in sign, thus directly canceling each other out in the bridge output, structurally eliminating nonlinear errors. Simultaneously, its high reliability is ensured by a dual-redundancy design: both the front and back sides of the chip independently integrate complete Wheatstone bridges, forming two parallel signal channels. When one channel partially fails, the other channel can still independently provide a valid signal. This invention, through the aforementioned dual-symmetric structural design and process, achieves precise fabrication of the sensing structure, effectively improving the linearity and reliability of the sensor chip, making it suitable for pressure detection scenarios with high requirements for measurement accuracy and stability. Attached Figure Description

[0058] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1This is one of the schematic diagrams of the fabrication process of a high linearity dual-redundancy pressure sensor chip provided in an embodiment of the present invention; Figure 2 This is the second schematic diagram of the fabrication method of a high linearity dual-redundancy pressure sensor chip provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the structure of a high linearity dual-redundancy pressure sensor chip provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the front structure of a high linearity dual-redundancy pressure sensor chip provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the back structure of a high linearity dual-redundancy pressure sensor chip provided in an embodiment of the present invention.

[0060] Illustration markings: Among them, 1. N-type wafer; 2. 1. Oxide layer; 2. Sensitive resistor area; 3. Contact hole; 4. Silicon nitride film; 5. Negative adhesive; 6. Bonding joint; 7. Metal electrode; 8. Silicon cup; 9. Glass; 10. Sensitive resistor. Detailed Implementation

[0061] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application.

[0062] like Figure 1 and Figure 2 As shown, the fabrication method of a high linearity dual-redundancy pressure sensor chip includes the following steps: wherein, Figure 2 Figure (a) and Figure 2 Figure (b) in the diagram corresponds to the structural schematic diagram of S101; Figure 2 Figure (c) in the diagram corresponds to the structural schematic diagram of S102; Figure 2 Figure (d) in the diagram corresponds to the structural schematic diagram of S103; Figure 2 Figure (e) in the diagram corresponds to the structural schematic diagram of S104; Figure 2 Figure (f) in the diagram corresponds to the structural schematic diagram of S105; Figure 2 Figure (g) in the diagram corresponds to the structural schematic diagram of S106; Figure 2 The (h) diagram in the diagram corresponds to the structural schematic diagram of S107; Figure 2 Figure (i) in the diagram corresponds to the structural schematic diagrams of S108, S109 and S110.

[0063] S101, Growing on two opposite surfaces of a silicon substrate respectively Oxide layer 2.

[0064] In this process, growth is performed on two opposing surfaces of the silicon substrate. Oxide layer 2 includes: An N-type wafer 1 with a first resistivity range is selected as the silicon substrate, and within a first temperature range, growth is performed on the two opposing surfaces of the N-type wafer 1 with a first thickness range. Oxide layer 2.

[0065] The first resistivity range is from 1 ohm·cm to 20 ohm·cm, the first temperature range is from 1000 degrees Celsius to 1150 degrees Celsius, and the first thickness range is from 0.5 micrometers to 3 micrometers.

[0066] S102, has growth-promoting effects The surface of the oxide layer 2 is photolithographically processed to form a sensitive resistor region 3 of a predetermined shape and at least one contact hole 4.

[0067] The bottom surface of the sensitive resistor region 3 and the contact hole 4 is a silicon substrate, and the sensitive resistor region 3 is used to set the sensitive resistor 11.

[0068] Specifically, regarding growth The surface of the oxide layer 2 is photolithographically processed to form a sensitive resistor region 3 of a predetermined shape and at least one contact hole 4; the bottom surface of the sensitive resistor region 3 and the contact hole 4 is a silicon substrate, including: At the first rotational speed Photoresist is coated on oxide layer 2.

[0069] The photoresist is subjected to a first baking process, a first exposure process, a first development process, and a first hardening process in sequence to form a sensitive resistor region 3 of a preset shape and at least one contact hole 4.

[0070] Remove the areas not protected by photoresist Oxide layer 2 region exposes the silicon substrate.

[0071] The first rotational speed is within the first rotational speed range; the duration of the first baking process is within the first baking time range; the duration of the first exposure process is within the first exposure time range; the duration of the first developing process is within the first developing time range; and the duration of the first hardening process is within the first hardening time range.

[0072] In one embodiment of this specification, the first rotation speed ranges from 1500 rpm to 4000 rpm, the first baking time ranges from 30 seconds to 120 seconds, the first exposure time ranges from 15 seconds to 60 seconds, the first developing time ranges from 10 seconds to 90 seconds, and the first hardening time ranges from 25 minutes to 60 minutes.

[0073] S103. Ion implantation is performed on the sensitive resistor region 3 and the contact hole 4 to form a PN junction, thus obtaining the first substrate.

[0074] Specifically, ion implantation is performed on the sensitive resistor region 3 and the contact hole 4 to form a PN junction, resulting in a first substrate, including: The first element is selected as the doping ion source, and the sensitive resistor region 3 and the contact hole 4 are ion implanted with the first implantation energy and the first implantation dose to form a PN junction and obtain the first substrate.

[0075] The first injection energy ranges from 10 keEV to 70 keEV, and the first injection dose ranges from... Atoms per square centimeter to The first element per square centimeter is boron.

[0076] S104. Silicon nitride thin films 5 are grown on the two opposite surfaces of the first substrate.

[0077] Specifically, silicon nitride thin films 5 are grown on two opposing surfaces of the first substrate, including: The two opposing surfaces of the first substrate are cleaned.

[0078] A silicon nitride thin film 5 is grown simultaneously on two opposing surfaces of the first substrate using the first process.

[0079] The first process is either LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition).

[0080] When the first process is LPCVD, the conditions for the first process include: a temperature of 500 degrees Celsius to 850 degrees Celsius. The flow rate is from 100 cubic centimeters per minute to 500 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute.

[0081] When the first process is PECVD, the conditions for the first process include: RF high-frequency power of 100 watts to 600 watts and low-frequency power of 200 watts to 500 watts. The flow rate is from 100 cubic centimeters per minute to 300 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute. The flow rate is 3,000 cubic centimeters per minute to 8,000 cubic centimeters per minute.

[0082] S105. Photolithography is performed on the contact hole 4 of the silicon nitride thin film 5 grown on the first substrate so that the bottom surface of the contact hole 4 on the first substrate is a silicon substrate, thus obtaining the second substrate.

[0083] Specifically, the contact holes 4 of the silicon nitride thin film 5 grown on the first substrate are photolithographically processed so that the bottom surface of the contact holes 4 on the first substrate is a silicon substrate, thus obtaining the second substrate, including: Photoresist was coated on the surface of the silicon nitride thin film 5 at a second rotation speed.

[0084] The photoresist is subjected to a second baking process, a second exposure process, a second development process, and a second hardening process in sequence to define the contact hole 4 region.

[0085] Remove the photoresist in the contact hole 4 area and the underlying silicon nitride film 5 to expose the silicon substrate and obtain the second substrate.

[0086] The second rotation speed is within the range of the second rotation speed, the duration of the second baking process is within the range of the second baking time, the duration of the second exposure process is within the range of the second exposure time, the duration of the second developing process is within the range of the second developing time, and the duration of the second hardening process is within the range of the second hardening time.

[0087] In one embodiment of this specification, the second rotation speed ranges from 1500 rpm to 4000 rpm, the second baking time ranges from 30 seconds to 120 seconds, the second exposure time ranges from 15 seconds to 60 seconds, the second developing time ranges from 10 seconds to 90 seconds, and the second hardening time ranges from 25 minutes to 60 minutes.

[0088] S106. Using negative adhesive 6, two pre-defined bonding points 7 are photolithographically formed on the two opposite surfaces of the second substrate to obtain the third substrate; Two bonding pads 7 are located on both sides of the sensitive resistor region 3, and the position of one of the bonding pads 7 is the same as that of the contact hole 4. The bottom surface of the bonding pad 7 near the center of the third substrate is a silicon nitride film 5, and the bottom surface of the bonding pad 7 corresponding to the contact hole 4 is a silicon substrate.

[0089] S107. Deposit metal electrodes 8 on the two opposite surfaces of the third substrate.

[0090] Specifically, two bonding pads 7 of a predetermined shape are photolithographically formed on two opposite surfaces of the second substrate using negative adhesive 6 to obtain a third substrate, and metal electrodes 8 are deposited on the two opposite surfaces of the third substrate, including: Negative adhesive 6 was applied to the two opposing surfaces of the second substrate at a third rotation speed; The negative adhesive 6 is subjected to a third baking process, a third exposure process, a third development process, and a third hardening process in sequence, and two bonding points 7 are photolithographically formed.

[0091] Metal layers are deposited on two opposing surfaces of a third substrate using a deposition process to form metal electrodes 8.

[0092] Among them, the third rotation speed is within the range of the third rotation speed, the duration of the third baking treatment is within the range of the third baking time, the duration of the third exposure treatment is within the range of the third exposure time, the duration of the third developing treatment is within the range of the third developing time, and the duration of the third hardening treatment is within the range of the third hardening time.

[0093] In one embodiment of this specification, the third rotation speed ranges from 1500 rpm to 4000 rpm, the duration of the third baking process ranges from 30 seconds to 120 seconds, the duration of the third exposure process ranges from 15 seconds to 60 seconds, the duration of the third developing process ranges from 10 seconds to 90 seconds, and the duration of the third hardening process ranges from 25 minutes to 60 minutes.

[0094] S108. The third substrate of the deposited metal electrode 8 is subjected to a photoresist removal process to obtain the fourth substrate.

[0095] In the fourth substrate, the metal electrode 8 forms an ohmic contact with the third substrate through alloy annealing treatment.

[0096] Specifically, the third substrate of the deposited metal electrode 8 is subjected to a resist removal process to obtain a fourth substrate, including: The third substrate after the metal electrode 8 is deposited is placed in a stripper solution for stripping to remove residual negative adhesive 6 and metal attached to the negative adhesive 6.

[0097] The substrate after desizing is subjected to alloy annealing in the second temperature range to obtain a fourth substrate in which the metal electrode 8 forms an ohmic contact with the silicon substrate.

[0098] The second temperature range is 400 degrees Celsius to 750 degrees Celsius, and the alloy annealing time is within the third time range, which is 20 minutes to 60 minutes.

[0099] S109. Silicon cups 9 are etched on the two opposite surfaces of the fourth substrate.

[0100] The bottom surface of the etched silicon cup 9 is located inside the silicon substrate.

[0101] In some embodiments, etching the silicon cup 9 on the two opposing surfaces of the fourth substrate specifically includes: A silicon nitride mask is applied to the non-etched area of ​​the fourth substrate to obtain a fourth substrate in which the non-etched area is protected.

[0102] The masked fourth substrate is placed in the first etchant for anisotropic etching to obtain a substrate with a groove of a preset depth.

[0103] After etching, the silicon nitride mask is removed to obtain a silicon cup 9 with its bottom surface located inside the silicon substrate.

[0104] The first etchant is a potassium hydroxide solution or a tetramethylammonium hydroxide solution, and the concentration of the first etchant is within a first concentration range, which is 10% to 45%. By using potassium hydroxide or tetramethylammonium hydroxide within a specific concentration range to etch silicon to form silicon cups 9, the etching process is ensured to be stable and controllable, and silicon cups 9 with complementary symmetry structures can be precisely manufactured.

[0105] S110. Electrostatically seal the glass 10 and the silicon cup 9 to obtain a high linearity dual-redundancy pressure sensor chip.

[0106] In this embodiment, by controlling the ion implantation, double-sided anisotropic etching, and complementary silicon cup 9 forming process, two Wheatstone bridges in symmetrical stress fields are simultaneously constructed on the N-type wafer 1. Combined with silicon nitride thin film 5 passivation and glass 10 electrostatic sealing, the stable manufacturing of a dual-redundant pressure sensor chip with high linearity and high reliability is achieved.

[0107] In this embodiment, the process conditions ensure efficient and uniform deposition of a silicon nitride thin film 5 with good insulation and protection properties at relatively low temperatures. These process conditions broaden the temperature selection range during manufacturing, making them particularly suitable for device integration that is thermally sensitive or contains temperature-sensitive structures.

[0108] Based on the same general inventive concept, this invention also protects a high linearity dual-redundant pressure sensor chip, which is prepared by the high linearity dual-redundant pressure sensor chip preparation method provided in the above embodiments. The high linearity dual-redundant pressure sensor chip provided by this invention will be described below, and the high linearity dual-redundant pressure sensor chip described below can be referred to in correspondence with the high linearity dual-redundant pressure sensor chip preparation method described above.

[0109] like Figures 3 to 5 As shown, (where, Figure 4 Figure A shows the front surface structure of the chip from a frontal view. Figure 4 Figure B in the diagram shows the surface structure of the back of the chip from a frontal view. Figure 5 Figure A shows the front surface structure of the chip from a rear view. Figure 5 Figure B in the image shows the back surface structure of the chip from a rear view. The high linearity dual-redundancy pressure sensor chip includes: Silicon substrate, used as a chip substrate.

[0110] Oxide layer 2 is located on two opposite surfaces of the silicon substrate.

[0111] Depend on After photolithography, the oxide layer 2 forms a pre-shaped sensitive resistor region 3 and at least one contact hole 4; the bottom surface of the sensitive resistor region 3 and the contact hole 4 is a silicon substrate.

[0112] A PN junction is formed by ion implantation in sensitive resistance region 3 and contact hole 4.

[0113] Covered Silicon nitride film 5 on the surface of oxide layer 2.

[0114] Two bonding points 7 are formed on the silicon nitride thin film 5 by photolithography. The two bonding points 7 are located on both sides of the sensitive resistor region 3. One bonding point 7 is located at the same position as the contact hole 4, and the bottom surface of the bonding point 7 that is located at the same position as the contact hole 4 is a silicon substrate; the bottom surface of the other bonding point 7 is the silicon nitride thin film 5.

[0115] The metal electrode 8 is deposited on the surface of the bonding joint 7, and the metal electrode 8 forms an ohmic contact with the silicon substrate through alloy annealing treatment.

[0116] Silicon cup 9, located on two opposite surfaces of a silicon substrate and extending inward.

[0117] And glass 10 bonded to the surface of silicon cup 9 by electrostatic sealing.

[0118] In this embodiment, the silicon substrate is an N-type wafer 1. Complementary silicon cups 9 are formed on the front and back sides of the N-type wafer 1, and multiple sensitive resistors 11 are disposed at the center of the sensitive resistor region 3 on its surface. These sensitive resistors 11 are configured as two independent Wheatstone bridges. The corresponding pairs of sensitive resistors 11 in each Wheatstone bridge are in stress fields of equal magnitude and opposite direction when subjected to pressure, suppressing the nonlinear output caused by stress asymmetry and improving the linearity and measurement accuracy of the sensor. A silicon nitride thin film 5 covers the sensitive resistor region 3 and the contact hole 4. Two bonding points 7 are formed on the silicon nitride thin film 5 by photolithography. The two bonding points 7 are set on both sides of the sensitive resistor region 3. The position of one bonding point 7 is the same as that of the contact hole 4, and the bottom surface of the bonding point 7 with the same position as the contact hole 4 is a silicon substrate. The bottom surface of the other bonding point 7 is the silicon nitride thin film 5. The metal electrode 8 deposited on the surface of the bonding point 7 is connected to the bonding point 7, which has high reliability. The silicon cup 9 and the glass 10 are electrostatically sealed to form a stable package, which ensures long-term stability and reliability under complex working conditions. This solves the technical problems of existing piezoresistive pressure sensors, such as severe nonlinearity, insufficient reliability of single redundancy structure, and high cost due to the need for multiple chip redundancy.

[0119] In one embodiment of this specification, two sets of sensitive resistors 11 are provided on both the front and back sides of the chip. The top and bottom sensitive resistors 11 on the front side and the top and bottom sensitive resistors 11 on the back side form a first Wheatstone bridge. The left and right sensitive resistors 11 on the front side and the left and right sensitive resistors 11 on the back side form a second Wheatstone bridge. The silicon cup 9 is positioned complementaryly on the front and back sides, so that the corresponding sensitive resistors 11 in the two Wheatstone bridges are in stress fields with equal magnitude and opposite direction.

[0120] In this embodiment, two sets of sensitive resistor regions 3 are provided on both the front and back sides of the N-type wafer 1, and a sensitive resistor 11 is formed at the center of each region. The two upper and lower sensitive resistors 11 on the front side and the two upper and lower sensitive resistors 11 on the back side form a first Wheatstone bridge, and the two left and right sensitive resistors 11 on the front side and the two left and right sensitive resistors 11 on the back side form a second Wheatstone bridge. Combined with the complementary silicon cup 9 structure on the front and back sides, the corresponding sensitive resistors 11 in the two Wheatstone bridges are always in a stress field of equal magnitude and opposite direction under pressure. This not only cancels nonlinear components and improves output linearity, but also realizes two fully functional, mutually redundant independent sensing channels, thereby achieving the effect of high linearity and dual redundancy detection on a single chip.

[0121] In one embodiment of this specification, the resistivity of the N-type wafer 1 is from 1 ohm·cm to 20 ohm·cm.

[0122] The thickness of oxide layer 2 is 0.5 micrometers to 3 micrometers.

[0123] In this embodiment, the resistivity of the N-type wafer 1 is from 1 ohm·cm to 20 ohm·cm. The thickness of oxide layer 2 is 0.5 micrometers to 3 micrometers. These parameters, while ensuring piezoresistive sensitivity, help control the uniformity of carrier mobility and doping distribution, giving the sensitive resistor 11 stable electrical characteristics; an appropriate thickness... The oxide layer 2 provides good insulation and surface passivation while avoiding stress transmission attenuation due to excessive thickness or leakage risk due to excessive thinness, thereby synergistically improving the linearity and long-term stability of the sensor.

[0124] In one embodiment of this specification, the material of the metal electrode 8 is aluminum, chromium-nickel-gold stack, or titanium-platinum-gold stack.

[0125] The thickness of the metal electrode 8 is 0.8 micrometers to 2 micrometers.

[0126] In this embodiment, not only can the contact resistance be reduced and the signal transmission efficiency improved, but the mechanical strength and connection reliability during wire bonding or flip-chip welding are also ensured by optimizing the electrode thickness, thereby enhancing the electrical connection stability of the sensor in long-term operation and harsh environments.

[0127] In one embodiment of this specification, when the first Wheatstone bridge and the second Wheatstone bridge are connected in parallel, they constitute a dual-redundant pressure sensor; when they are connected in series, they constitute a single-redundant pressure sensor with doubled sensitivity.

[0128] In this embodiment, parallel connection forms a dual-redundant sensor, improving system reliability; series connection forms a single-redundant sensor, enhancing signal output strength. This expands the sensor's applicable scenarios without altering the chip manufacturing process.

[0129] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. A method for fabricating a high linearity dual-redundancy pressure sensor chip, characterized in that, include: Growth is performed on two opposing surfaces of a silicon substrate. Oxide layer (2); For growth The surface of the oxide layer (2) is photolithographically processed to form a sensitive resistor region (3) of a preset shape and at least one contact hole (4); the bottom surface of the sensitive resistor region (3) and the contact hole (4) is the silicon substrate, and the sensitive resistor region (3) is used to set the sensitive resistor (11). Ion implantation is performed on the sensitive resistor region (3) and the contact hole (4) to form a PN junction, thereby obtaining the first substrate; Silicon nitride films are grown on the two opposite surfaces of the first substrate (5); Photolithography is performed on the contact hole (4) of the silicon nitride thin film (5) grown on the first substrate so that the bottom surface of the contact hole (4) on the first substrate is the silicon substrate, and a second substrate is obtained. Two pre-defined bonding pads (7) are photolithographically formed on two opposite surfaces of the second substrate using a negative adhesive (6) to obtain a third substrate; wherein, the two bonding pads (7) are disposed on both sides of the sensitive resistor region (3), and the position of one of the bonding pads (7) is the same as the position of the contact hole (4); the bottom surface of the bonding pad (7) near the center point of the third substrate is the silicon nitride film (5), and the bottom surface of the bonding pad (7) corresponding to the contact hole (4) is the silicon substrate; Metal electrodes (8) are deposited on the two opposing surfaces of the third substrate, respectively. The third substrate of the deposited metal electrode (8) is subjected to a desizing process to obtain a fourth substrate; in the fourth substrate, the metal electrode (8) forms an ohmic contact with the third substrate through an alloy annealing process. Silicon cups (9) are etched on two opposing surfaces of the fourth substrate, with the bottom surface of the silicon cups (9) located within the silicon substrate; The glass (10) is electrostatically sealed to the surface of the silicon cup (9) to obtain the high linearity dual redundancy pressure sensor chip.

2. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Growth is performed on two opposing surfaces of a silicon substrate. The oxide layer (2) includes: An N-type wafer (1) with a first resistivity range is selected as the silicon substrate, and a silicon substrate with a first thickness range is grown on two opposite surfaces of the N-type wafer (1) within a first temperature range. Oxide layer (2); The first resistivity ranges from 1 ohm·cm to 20 ohm·cm, the first temperature ranges from 1000 degrees Celsius to 1150 degrees Celsius, and the first thickness ranges from 0.5 micrometers to 3 micrometers.

3. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, growth The surface of the oxide layer (2) is photolithographically processed to form a sensitive resistor region (3) of a preset shape and at least one contact hole (4). The bottom surface of the sensitive resistor region (3) and the contact hole (4) is the silicon substrate, including: At the first rotational speed in Photoresist is coated on the oxide layer (2); The photoresist is subjected to a first baking process, a first exposure process, a first development process and a first hardening process in sequence to form a sensitive resistor region (3) of a preset shape and at least one contact hole (4). Remove the parts not protected by photoresist The oxide layer (2) region exposes the silicon substrate; The first rotational speed is within a first rotational speed range; the duration of the first baking process is within a first baking time range; the duration of the first exposure process is within a first exposure time range; the duration of the first developing process is within a first developing time range; and the duration of the first hardening process is within a first hardening time range.

4. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Ion implantation is performed on the sensitive resistor region (3) and the contact hole (4) to form a PN junction, resulting in a first substrate comprising: The first element is selected as the doping ion source, and the sensitive resistor region (3) and the contact hole (4) are ion implanted with the first implantation energy and the first implantation dose to form a PN junction and obtain the first substrate; The first injection energy ranges from 10 kiloelectron volts to 70 kiloelectron volts, and the first injection dose ranges from... Atoms per square centimeter to Atoms per square centimeter, the first element is boron.

5. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Silicon nitride thin films (5) are grown on two opposing surfaces of the first substrate, including: The two opposing surfaces of the first substrate are cleaned. A silicon nitride thin film is simultaneously grown on two opposing surfaces of the first substrate using the first process (5). The first process is LPCVD or PECVD; The first process is LPCVD, and the conditions for the first process include: The temperature ranges from 500 degrees Celsius to 850 degrees Celsius. The flow rate is from 100 cubic centimeters per minute to 500 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute; The first process is PECVD, and the conditions of the first process include: RF high-frequency power ranges from 100 watts to 600 watts, and low-frequency power ranges from 200 watts to 500 watts. The flow rate is from 100 cubic centimeters per minute to 300 cubic centimeters per minute. The flow rate is from 50 cubic centimeters per minute to 400 cubic centimeters per minute. The flow rate is 3,000 cubic centimeters per minute to 8,000 cubic centimeters per minute.

6. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Photolithography is performed on the contact holes (4) of the silicon nitride thin film (5) grown on the first substrate so that the bottom surface of the contact holes (4) on the first substrate is the silicon substrate, to obtain a second substrate, comprising: Photoresist is coated on the surface of the silicon nitride film (5) at a second rotation speed; The photoresist is subjected to a second baking process, a second exposure process, a second development process and a second hard film process in sequence to define the contact hole (4) area; Remove the photoresist in the contact hole (4) area and the underlying silicon nitride film (5) to expose the silicon substrate and obtain the second substrate; The second rotation speed is within the second rotation speed range, the duration of the second baking process is within the second baking time range, the duration of the second exposure process is within the second exposure time range, the duration of the second developing process is within the second developing time range, and the duration of the second hardening process is within the second hardening time range.

7. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Using negative adhesive (6), two pre-defined bonding points (7) are photolithographically formed on two opposite surfaces of the second substrate to obtain a third substrate. Metal electrodes (8) are then deposited on two opposite surfaces of the third substrate, including: The negative adhesive was coated on the two opposing surfaces of the second substrate at a third rotation speed (6). The negative adhesive (6) is subjected to a third baking process, a third exposure process, a third development process and a third hardening process in sequence, and two bonding points (7) are photolithographically formed. Metal layers are deposited on the two opposing surfaces of the third substrate using a deposition process to form metal electrodes (8). The third rotation speed is within the third rotation speed range, the duration of the third baking process is within the third baking time range, the duration of the third exposure process is within the third exposure time range, the duration of the third developing process is within the third developing time range, and the duration of the third hardening process is within the third hardening time range.

8. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, The third substrate of the deposited metal electrode (8) is subjected to a photoresist removal process to obtain a fourth substrate; In the fourth substrate, the metal electrode (8) forms an ohmic contact with the third substrate through alloy annealing, including: The third substrate after the metal electrode (8) is deposited is placed in a stripping solution for stripping treatment to remove residual negative adhesive (6) and metal attached to the negative adhesive (6); The substrate after desizing is subjected to alloy annealing in the second temperature range to obtain a fourth substrate in which the metal electrode (8) forms an ohmic contact with the silicon substrate; The second temperature range is 400 degrees Celsius to 750 degrees Celsius, and the duration of the alloy annealing treatment is within a third time range, which is 20 minutes to 60 minutes.

9. The method for fabricating a high linearity dual-redundancy pressure sensor chip according to claim 1, characterized in that, Silicon cups (9) are etched into two opposing surfaces of the fourth substrate, the bottom surface of which is located within the silicon substrate, comprising: A silicon nitride mask is applied to the non-etched area of ​​the fourth substrate to obtain a fourth substrate in which the non-etched area is protected. The masked fourth substrate is placed in the first etchant for anisotropic etching to obtain a substrate with a groove of a preset depth. After etching, the silicon nitride mask is removed to obtain a silicon cup (9) with its bottom surface located inside the silicon substrate. The first corrosive agent is a potassium hydroxide solution or a tetramethylammonium hydroxide solution, and the concentration of the first corrosive agent is within a first concentration range, which is 10% to 45%.

10. A high linearity dual-redundancy pressure sensor chip, fabricated by the high linearity dual-redundancy pressure sensor chip fabrication method according to any one of claims 1-9, characterized in that, include: Silicon substrate used as a chip substrate; Oxide layer (2) is located on two opposite surfaces of the silicon substrate; From the above After photolithography, the oxide layer (2) forms a sensitive resistor region (3) of a preset shape and at least one contact hole (4); the bottom surface of the sensitive resistor region (3) and the contact hole (4) is the silicon substrate; A PN junction is formed by ion implantation in the sensitive resistance region (3) and the contact hole (4); Covering the Silicon nitride film (5) on the surface of oxide layer (2); Two bonding pads (7) are formed on the silicon nitride thin film (5) by photolithography. The two bonding pads (7) are located on both sides of the sensitive resistor region (3). One of the bonding pads (7) is located at the same position as the contact hole (4), and the bottom surface of the bonding pad (7) located at the same position as the contact hole (4) is the silicon substrate. The bottom surface of the other bonding pad (7) is the silicon nitride thin film (5). A metal electrode (8) is deposited on the surface of the bonding joint (7), and the metal electrode (8) forms an ohmic contact with the silicon substrate through alloy annealing treatment; Silicon cups (9) located on two opposite surfaces of the silicon substrate and extending inward; And glass (10) bonded to the surface of the silicon cup (9) by electrostatic sealing. The sensitive resistor region (3) is located on two opposite surfaces of the chip; multiple sensitive resistors (11) are disposed at the center of the sensitive resistor region (3); the silicon cup (9) is positioned complementaryly on the front and back sides, so that the corresponding sensitive resistors (11) in the two Wheatstone bridges are in stress fields with equal stress magnitude and opposite direction. The two sensitive resistors (11) on the front and the two sensitive resistors (11) on the back form the first Wheatstone bridge; The two sensitive resistors (11) on the front and the two sensitive resistors (11) on the back form a second Wheatstone bridge; When the first Wheatstone bridge and the second Wheatstone bridge are connected in parallel, they form a dual-redundant pressure sensor; when they are connected in series, they form a single-redundant pressure sensor with double the sensitivity.

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