System and method for multi-lane parallel device testing

Abstract

Systems and methods for parametric multi-channel testing of semiconductor devices are described. A system provides multiple test channels that include pulse resources and measurement resources, the measurement resources having high current (HC) and low current (LC) switches coupled to potential nodes connected to test pins. The pulse resources include a first leg having a pulse generator, a programmable gain amplifier, a switch for providing different leg or operation for pulse current / voltage monitoring, and a high speed switch. A mode switch can be incorporated to selectively connect the potential nodes to the pulse resources for pulse testing, to the measurement resources for high potential testing with the HC switch closed, or to the measurement resources for low potential testing with the LC switch closed. The channels can further include direct digital synthesizers and processing circuitry that generate calibrated test signals, perform analog to digital conversion, and perform frequency domain transformation, with unique frequency / phase locking for coordinated low latency parallel operation.

Description

[0001] Cross-referencing related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 773,888, filed March 18, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosed techniques generally relate to systems, apparatuses, devices, and methods for multichannel testing of devices, as well as improvements in parameter testing to facilitate accurate, synchronous, and parallel electrical measurements in circuits and / or semiconductor devices. Specifically, and non-limitingly, the disclosed systems and methods relate to multichannel test architectures that incorporate configurable test channels, synchronous timing mechanisms, direct digital synthesizers (DDS), and calibration routines for accurate parameter analysis. The multichannel test systems described herein can be configured to perform various types of electrical measurements simultaneously with systems that improve measurement accuracy, throughput, and efficiency in semiconductor device testing applications. Background Technology

[0003] Semiconductor devices are core components of modern electronics, powering everything from smartphones and computers to automobiles and medical devices. As these devices become increasingly complex and miniaturized, ensuring their reliability and performance becomes paramount. Semiconductor testing is a useful step in the manufacturing process of these devices, designed to identify defects and verify that each component meets stringent quality standards before the product reaches the market.

[0004] Parametric testing is a subset of semiconductor testing that focuses on measuring the electrical parameters of semiconductor devices. These parameters include voltage, current, resistance, capacitance, impedance, leakage current, breakdown voltage, IV characteristics, or CV characteristics, which are extremely useful for evaluating the functionality and performance of devices. Parametric testing is performed at various stages of the semiconductor manufacturing process, including wafer testing, packaging testing, and final testing.

[0005] Wafer testing, performed before semiconductor wafers are diced into individual chips, is invaluable for detecting defects early in the production process. This stage includes probing the wafer to measure its electrical characteristics and ensure they are within specified limits. Packaging testing, performed after the semiconductor die has been assembled and packaged, verifies the integrity of the package and the connections between the die and external leads. Final testing, as the last stage of the production cycle, ensures that the assembled device meets all performance and reliability standards.

[0006] Wafer-level parameter testing is useful because it provides direct insight into device behavior at an early stage, before packaging or assembly can mask inherent electrical characteristics. By probing test structures and transistors distributed across the wafer, engineers can assess process uniformity, monitor variations in threshold voltage, leakage current, or capacitance, and generate statistics on device variability. These measurements not only help identify defective chips but also guide process control and yield improvement, making parameter testing a cornerstone of both device characterization and manufacturing quality assurance. Summary of the Invention

[0007] Semiconductor devices are typically parametrically tested at the wafer stage to evaluate electrical characteristics such as resistance, capacitance, inductance, current-voltage (IV), and capacitance-voltage (CV) behavior. This allows for monitoring of the wafer fabrication process, controlling manufacturing reliability, monitoring process variations, and ensuring yield. The device under test (DUT) can be a single die on a wafer, a dedicated test structure, or a packaged assembly. Test setups may include test heads, probe stations, instrumentation units, and host control software.

[0008] Some semiconductor device testing uses a single-instrument approach, where a single LCR (inductance (L), capacitance (C), and resistance (R)) instrument or measurement unit is routed via a switch matrix or multiplexer to test different test pins or DUTs sequentially. While this "single-instrument plus switching" architecture reduces upfront complexity and cost, it introduces limitations in high-throughput and high-precision scenarios. For example, throughput may be limited by the setup time of each switch and parasitic charging or discharging, and true simultaneous measurements are not possible. Furthermore, longer routing and relay paths can introduce additional parasitic effects, leakage current, crosstalk, and switching transients, reducing signal integrity and bandwidth. Additionally, repeatability can be affected by temperature variations and contact resistance drift.

[0009] The disclosed technology aims to address problems in test systems and improve the speed, accuracy, and overall workflow of semiconductor testing by leveraging systems capable of independent multi-channel parameter testing. The disclosed technology provides a parameter testing platform that delivers improved measurement performance in production environments, overcoming the limitations of other systems that rely on centralized switch matrices and shared instrumentation. For example, some aspects of the disclosed technology employ a per-pin architecture, where each test pin can be equipped with a dedicated source / measurement resource. The disclosed technology eliminates switching delays, reduces measurement parasitics, and enables truly parallel testing of multiple devices. Therefore, embodiments of the disclosed technology can provide higher throughput and improved data fidelity compared to other systems that typically require serial testing and exhibit correlation gaps between benchtop analyzers and automated test equipment.

[0010] Furthermore, the disclosed system can integrate advanced resources, such as high-frequency capacitance measurement units and pulse generators capable of delivering high voltage, three-state waveforms. For example, in embodiments of the disclosed system, these resources can be located inside the test head for direct routing to the probe card interface, shortening the analog path between the DUT and the instrument. This increases the effective bandwidth of the application and sensing paths, reduces series inductance and RC load, improves edge fidelity and settling time, and reduces crosstalk and leakage current. With these features, the disclosed system can extend measurement coverage to advanced device nodes and a variety of applications, including, for example, dielectric evaluation and memory technology evaluation. Moreover, the disclosed embodiments integrate a dedicated software platform, allowing for faster and more unified test development and execution across desktop and production environments, enabling test algorithms to be created once and deployed seamlessly for more consistent results.

[0011] Some aspects of the disclosed technology introduce a channel that integrates multiple measurement units—such as a source measurement unit (SMU), a capacitance measurement unit (CMU), a frequency measurement unit (FMU), a pulse generator unit (PGU), and a pulse IV path—and can be reconfigured within a single channel to perform different measurements as needed. This variable channel, or xMU, can integrate multiple resources and selectively route them to a common interface consisting of drive force terminals and high-impedance sensing terminals using a switching network. The switching network allows for function selection while protecting measurement integrity and preventing reverse drive. For example, the CMU can switch between its high and low paths to implement classic four-terminal technology, while the pulse engine can apply or capture fast waveforms on the same interface. This integrated, per-channel architecture enables rapid reconfiguration between DC, AC, and pulse modes without external cables or shared matrices, thereby reducing parasitic effects and increasing parallel test throughput. For example, in one mode, the CMU performs a four-terminal Kelvin CV measurement with drive protection while the SMU applies a reverse bias to the DUT; in another mode, the PGU / Pulse IV path delivers the pulses, and the FMU reciprocally counts cycles at a comparator threshold set by the DAC. Because these resources are co-located on each pin and phase-locked across channels, the xMU system can support truly parallel, low-parasitic measurements with reduced setup time and repeatable timing, thereby improving throughput and data fidelity without relying on a centralized switching matrix.

[0012] Some aspects relate to a system for multi-channel parametric testing, comprising multiple test channels. A test channel may include a pulse resource, a measurement resource having a high-current (HC) switch and a low-current (LC) switch, and / or a mode switch coupled to the pulse resource, the measurement resource, and / or a potential node that may be coupled to a test pin. In operation, when the mode switch connects the pulse resource to the potential node, the potential node can be configured for pulse testing (which may include pulse delivery, pulse measurement, or both); when the HC switch is closed and the mode switch connects the measurement resource to the potential node, the potential node can also be configured for high-potential (HP) testing; and when the LC switch is closed and the mode switch connects the measurement resource to the potential node, the potential node can be configured for low-potential (LP) testing.

[0013] Other aspects relate to a system for parallel testing, comprising one or more processors, a system clock, and multiple test channels coupled to the one or more processors. A test channel may include at least one of the following: a pulse resource, including a first branch and a second branch, and a high-speed switch coupled to the first and second branches; or a measurement resource including a first configurable switch, a second configurable switch, and a direct digital synthesizer. These components may be coupled to a mode switch, which may be coupled to a test pin. The first branch of the pulse resource may include a pulse generator, a programmable gain amplifier (PGA), and a first branch switch (e.g., a configurable switch); the second branch of the pulse resource may provide pulse current and voltage measurements and includes a second branch switch. Based on the configuration of the first configurable switch, the second configurable switch, and the mode switch, any test channel may be configured as a high channel, a low channel, a pulse generator, or a measurement channel. Furthermore, one or more processors may be configured to: configure the direct digital synthesizer in the test channel to generate a test signal with a unique frequency or phase; and simultaneously measure a set of test channels by configuring the corresponding direct digital synthesizer to generate a test signal with a phase and frequency determined based on the system clock.

[0014] Other aspects relate to a parametric multichannel test system comprising multiple test channels. A test channel includes: resources (including one or more pulse resources and measurement resources), channel processing circuitry, mode switches coupled to the pulse resources, measurement resources, and processing circuitry, and nodes coupled to the mode switches and test pins. The pulse resources may include high-speed switches and programmable gain amplifiers, and the measurement resources include a first configurable switch, a second configurable switch, and a direct digital synthesizer. Based on the arrangement of the first configurable switch, the second configurable switch, and the mode switches, the test channel can be configured via a processor to operate as any of a high channel, a low channel, a pulse generator, or a measurement channel. The direct digital synthesizer in the test channel is configured to generate a test signal with a unique frequency or phase and is calibrated relative to the system clock. The processing circuitry is configured to perform operations including converting analog measurements to digital measurements, transforming signals from the time domain to the frequency domain, or transmitting digital data to at least one of the following in the processor:

[0015] Some example implementations of the disclosed system relate to a system for multi-channel parametric testing. The system may include multiple test channels, each including a pulse resource, a measurement resource with a first configurable switch and a second configurable switch, channel processing circuitry, and nodes coupled to corresponding test pins. The mode and arrangement of the configurable switches determine whether the channel operates as a high channel, low channel, pulse generator, or measurement channel, enabling per-channel reconfiguration without an external relay matrix. Each test channel also includes a direct digital synthesizer (DDS) that generates precisely timed analog test signals. The DDS unit is synchronized and calibrated relative to the global system clock to maintain consistent phase and frequency alignment across all channels. Through processor control, the DDS unit can be programmed with a unique phase offset or frequency, allowing channels to operate coherently in a uniform time domain while stimulating or measuring different parts of the device under test.

[0016] The channel processing circuitry in each test channel performs localized signal processing operations, which may include converting analog measurements to digital form using on-channel analog-to-digital conversion, and transforming those digital signals from the time domain to the frequency domain using computational elements such as Fast Fourier Transform (FFT) circuitry. The processing circuitry can also package the processed data and transmit it to a centralized processor or controller for higher-level analysis or storage. This distributed processing approach reduces data throughput bottlenecks and minimizes timing skew that can occur when all measurements are collected externally. By embedding generation, measurement, and signal processing capabilities at the channel level, the disclosed architecture enables scalable, low-latency, and phase-coherent multi-channel parameter testing. This configuration enhances overall test fidelity, supports high-speed device characterization, and allows for complex synchronous measurement modes that are difficult to achieve using traditional centralized test systems. Attached Figure Description

[0017] Details of one or more aspects of the subject matter described in this disclosure are set forth in the accompanying drawings and the following description. However, the drawings illustrate only some typical aspects of this disclosure and should not be considered as limiting its scope. Other features, aspects, and advantages will become apparent from the specification, drawings, and claims.

[0018] Figure 1 A schematic diagram of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A top front view of the test head of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A rear bottom view of the test head of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A front view of the test head of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram of a retractable electrical contact interface device in a retracted position according to an embodiment of the present disclosure is shown.

[0023] Figure 6 A schematic diagram of the power supply of the top component according to an embodiment of the present disclosure is shown.

[0024] Figure 7 A hub block diagram of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0025] Figure 8 A hub architecture and communication according to embodiments of this disclosure are illustrated.

[0026] Figure 9 A parameter block diagram of a top component according to an embodiment of the present disclosure is shown.

[0027] Figure 10 A schematic circuit of a test channel in a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0028] Figure 11 A block diagram of an adaptability test channel according to an embodiment of the present disclosure is shown.

[0029] Figure 12 A block diagram of a resource card according to an embodiment of the present disclosure is shown.

[0030] Figure 13This is a circuit diagram of a pulse sub-board according to an embodiment of the present disclosure.

[0031] Figure 14 A block diagram of a reciprocal mode of a frequency measurement unit (FMU) according to an embodiment of the present disclosure is shown.

[0032] Figure 15 The measurement path of a capacitance measurement unit (CMU) according to an embodiment of the present disclosure is shown.

[0033] Figure 16 A block diagram of a CMU according to an embodiment of the present disclosure is shown.

[0034] Figure 17 A block diagram of a measurement unit (MU) with a transimpedance amplifier (TIA) according to an embodiment of the present disclosure is shown.

[0035] Figure 18 A schematic circuit of a test channel of a multi-channel parallel device test system according to an embodiment of the present disclosure is shown.

[0036] Figure 19 A schematic circuit of a test channel for a multi-channel parallel device test system for a high-impedance DUT is shown according to an embodiment of the present disclosure.

[0037] Figure 20 A block diagram is shown of multiple test channels in a multi-channel parallel device test system according to an embodiment of the present disclosure.

[0038] Figure 21 A block diagram of multiple test channels in a multichannel parallel device test system for a high-impedance DUT according to an embodiment of the present disclosure is shown.

[0039] Figure 22 An embodiment of a test system according to an embodiment of the present disclosure is shown.

[0040] Figure 23 Another embodiment of a test system for a high-impedance DUT according to embodiments of the present disclosure is shown.

[0041] Figure 24 A schematic circuit for measuring the CV characteristics of a MOSFET on a wafer is shown according to an embodiment of the present disclosure, wherein a multi-channel parallel device test system is mounted on the wafer.

[0042] Figure 25 A schematic circuit for measuring CV characteristics according to an embodiment of the present disclosure is shown.

[0043] Figure 26 A schematic diagram of a single high channel and other low channel tests according to an embodiment of the present disclosure is shown.

[0044] Figure 27A A schematic diagram of a first high-speed pulse IV test according to an embodiment of the present disclosure is shown.

[0045] Figure 27B A schematic diagram of a second high-speed pulse IV test according to an embodiment of the present disclosure is shown.

[0046] Figure 28 A calibration block diagram according to an embodiment of the present disclosure is shown.

[0047] Figure 29 A flowchart of a calibration method according to an embodiment of the present disclosure is shown.

[0048] Figure 30 A flowchart of a calibration method according to an embodiment of the present disclosure is shown.

[0049] Figure 31 A flowchart of a calibration method according to an embodiment of the present disclosure is shown.

[0050] Figure 32 A flowchart of a method for configuring a digital synthesizer according to an embodiment of the present disclosure is shown.

[0051] Figure 33 A flowchart of a method for configuring a processor and / or a digital synthesizer according to an embodiment of the present disclosure is shown. Detailed Implementation

[0052] Some disclosed embodiments are described with reference to the accompanying drawings. In the drawings, the leftmost numeral of the reference numeral identifies the drawing in which that numeral first appears. Where convenient, the same reference numerals are used throughout the drawings to denote the same or similar parts. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosed example systems or methods. However, those skilled in the art will understand that the principles of the example methods and systems can be practiced without every specific detail. Well-known methods, processes, and components are not described in detail to avoid obscuring the principles of some of the disclosed methods and systems. Unless explicitly stated otherwise, the example methods and processes described herein are neither limited to a particular order or sequence nor to a particular system configuration. Furthermore, some of the methods and systems described, or elements thereof, may occur or be performed simultaneously, at the same point in time, or concurrently.

[0053] It should be understood that the foregoing general description and the following detailed description are merely illustrative and not intended to limit the scope of this disclosure. Several disclosed methods and systems are illustrated in conjunction with the accompanying drawings, which form part of this specification, and together with the specification serve to outline the principles of some of the disclosed methods and systems.

[0054] In some aspects of the disclosed technology, the parametric multichannel tester includes multiple test channels, each constructed as having a pulse resource, a measurement resource providing high-current (HC) and low-current (LC) switching, and a mode switch coupled between the pulse resource, the measurement resource, and a channel potential node connected to a test pin. A system clock allocates timing to the channels to maintain precise coordination. When the mode switch couples the pulse resource to the potential node, the channel delivers a programmed pulse to the pin; when the mode switch alternatively couples the measurement resource and the HC switch is closed, the node operates under high-potential (HP) test conditions; when the LC switch is closed, the node operates under low-potential (LP) test conditions. By embedding pulse test and measurement functions in the same signal path, this architecture eliminates the delays and parasitic effects associated with an external switching matrix. This integration allows each channel to electronically change its operating mode, reducing transition times and improving the accuracy of voltage and current control directly at the device under test (DUT).

[0055] In some implementations, each channel of the test system may include a local channel clock (e.g., a per-test-channel clock) locked in frequency and phase to a shared system clock, ensuring precise synchronization across the test array. Calibration logic is programmed to compensate for the phase offset of each channel, ensuring that the effective timing of each channel is aligned at the DUT. Safety interlocks force the HC and LC switches to operate alternately, ensuring that when one branch is closed, the other remains open. This clocking and switching scheme provides deterministic synchronization and prevents overcurrent or range overlap. As a result, timing deviations between channels are minimized, allowing for simultaneous measurements with sub-nanosecond phase consistency and significantly improving test repeatability in high-speed device characterization.

[0056] In some implementations, each channel of the system may include a force line connected to the DUT from a potential node via mode and range switches, and a sensing line coupling measurement resources to the DUT for feedback. The force line can provide a programmed excitation or bias, while the sensing line monitors the actual potential at the DUT. This four-wire arrangement allows the measurement circuitry to adjust the voltage based on the sensed potential rather than the output driver voltage, thereby compensating for lead and contact resistance.

[0057] In some implementations, the measurement resources for each channel may include a capacitance measurement unit (CMU) and a source measurement unit (SMU), and the system instantiates at least four channels. Control logic drives the first, second, and third channels to a first dynamic potential, and drives the fourth channel to a second dynamic potential different from the first dynamic potential. The CMU applies a voltage scan and measures the capacitance as a function of these potentials, thereby generating a capacitance-voltage characteristic under differential bias conditions.

[0058] In some aspects, each channel of the disclosed system may include a direct digital synthesizer (DDS) configured to generate test waveforms whose phase and frequency are locked to the system clock. Because each channel derives its timing from the same reference, multiple channels can coherently excite or sample the DUT. Channels can be configured to be phase-aligned, thereby improving the accuracy of cross-channel correlation.

[0059] In some embodiments, each channel integrates local memory, a pair of analog-to-digital converters (ADCs), and two direct digital synthesizers (DDSs). The first DDS can drive the potential node with a programmable excitation waveform, while the second DDS provides a sampling clock or phase marker for the ADCs. Both ADCs can capture response data and store it in the channel memory for real-time or delay analysis.

[0060] In some implementations, each channel also includes first and second Fast Fourier Transform (FFT) circuitry coupled to the corresponding ADC and memory. The FFT circuitry directly converts the digitized samples into a frequency domain spectrum within the hardware channel. By performing these transformations locally, the tester avoids the latency of transmitting large datasets to a central processing unit and can instead calculate harmonic distortion, gain response, or impedance in near real-time. This local processing increases test throughput and enables adaptive measurement control based on frequency domain feedback. Furthermore, the DDS unit can generate measurement stimuli while the ADC and FFT chains capture and analyze the resulting DUT response. The tight coupling between signal generation and capture allows for phase-coherent operation with minimal timing uncertainty. Performing these two tasks within the same channel reduces external wiring and improves signal integrity, enabling rapid extraction of amplitude, phase, and impedance characteristics under controlled timing.

[0061] In some aspects of the disclosed technology, the tester can provide at least eight synchronous channels, each with independently programmable amplitude and phase settings that remain calibrated to a shared system clock. The pulse resources for each channel can include digital-to-analog converters (DACs) driving multiple programmable gain amplifiers (PGAs), the outputs of which can be selected via high-speed switches. This configuration supports dynamic range scaling and flexible waveform shaping without sacrificing phase alignment. As a result, the tester can simultaneously drive and measure multiple DUT pins, achieving high throughput with consistent amplitude and phase accuracy across all channels.

[0062] On the other hand, the processor, coupled to the system clock, coordinates channel calibration. Each channel includes a DDS that receives calibration data from the processor. During the calibration routine, the processor can output a reference, measure the relative phase delay of each channel, and write the corresponding correction to the phase shift register of each DDS. Once stored, these offsets can automatically adjust subsequent waveform generation so that all channels remain in phase alignment.

[0063] In some embodiments, each DDS in a channel can generate its waveform using a numerically controlled oscillator (NCO) operating on the system clock. A programmable phase offset applied within the NCO compensates for deviations measured in each channel during calibration. Because the correction can be implemented directly in the digital phase accumulator, synchronization accuracy is maintained even during frequency changes or waveform modulation. This method particularly improves inter-channel phase coherence and timing accuracy in high-frequency or pulse testing.

[0064] In coordinated operation, DDS units across test channels can generate test signals with phase aligned to the same system clock reference. This synchronization enables coherent pulses, step bias sequences, and other time-sensitive measurements that rely on simultaneous excitation of multiple pins. Alignment of waveform phase and timing across channels results in cleaner multi-pin correlation and reduced uncertainty in transient and frequency domain data.

[0065] In some embodiments, each channel can be configured to include separate high-potential (HP) and low-potential (LP) circuits, and the control logic uses HC and LC switches to alternate between these circuits. This configuration allows the tester to apply large signal pulses or measure high-voltage behavior in HP mode, and then seamlessly switch to low-noise, high-sensitivity LP mode without physically disconnecting the DUT. The dual-path architecture can support wide dynamic range characterization while maintaining signal integrity and minimizing mechanical wear caused by repeated switching.

[0066] In some calibration routines, the processor can multiplex a reference signal into the HP and LP circuits of each channel and align the signal to a global trigger to maintain uniform phase across the tester. The processor then measures the amplitude and phase response of each circuit, generates a second reference signal for comparison, and calculates correction coefficients for each path. These coefficients update the channel's gain and phase characteristics, ensuring a precise match between the HP and LP modes. This type of automated calibration improves consistency across ranges and ensures accurate cross-mode data correlation.

[0067] In an exemplary implementation, the first reference signal can be set to a sine wave, and the second reference can be an internally generated calibration signal. After calibrating the HP circuit, the processor determines any residual phase offset between the HP circuit and the LP circuit and writes a compensating phase correction for the LP path.

[0068] In some implementations, the processor can store the calculated gain and phase correction values ​​in per-channel non-volatile memory. For example, each channel retrieves its calibration data at startup and automatically applies the stored coefficients during test operations. By embedding calibration at the hardware level, the tester maintains consistent measurement accuracy across varying environments and reduces setup time between test sessions, thereby improving system stability and repeatability.

[0069] In another aspect of the disclosed technology, a system includes one or more processors, a system clock, and multiple configurable test channels. Each channel includes pulse resources, measurement resources with first and second configurable switches and a DDS, a mode switch, and a potential node coupled to a test pin. Under processor control, any channel can be used as a high, low, pulse, or measurement channel depending on the programmed switch states. The processor synchronizes all DDS units to the system clock, allowing each channel to operate at a unique frequency or phase while maintaining time alignment. This reconfigurable architecture enables per-pin assignment without hardware modifications, thereby significantly improving throughput and utilization in multi-site wafer or device testing.

[0070] In some embodiments, each channel may include a local processor performing FFT analysis on the captured waveform, while the main system allocates excitation frequencies aligned with different FFT bins to isolate the responses on the channels. Pulse resources may reside on a pulse board comprising programmable gain amplifiers, slew-rate limiters, and high-speed switches, which together form clean, high-speed pulses with controlled edge rates. By distributing FFT processing across channels, the system minimizes data transfer overhead and achieves faster, parallel spectral characterization with high signal isolation.

[0071] In some arrangements, each DDS may include a programmable phase shift register that stores correction values ​​for that channel. During waveform synthesis, the DDS applies the stored offset to its internal phase accumulator, thus keeping the channel output aligned with the system clock. This self-compensation capability allows phase alignment to be maintained during long-duration or high-frequency testing without recalibration, ensuring consistent cross-channel timing and repeatable measurement accuracy during extended operation.

[0072] Other aspects of the disclosed technology relate to a system that integrates pulse resources, a measurement source with configurable switches and a DDS, channel processing circuitry, and mode switches coupled to nodes connected to test pins within each channel. The processor can configure each channel as a high, low, pulse, or measurement path by setting switch states and DDS parameters, all calibrated to the system clock. The processing circuitry can digitize analog signals, perform frequency domain transformations, or transmit data to a host controller. By embedding generation, acquisition, and processing at the channel level, the system achieves reduced latency, higher data fidelity, and scalable, phase-coherent testing across many DUT pins in parallel.

[0073] Some aspects of the disclosed technology relate to a system for multi-channel parametric testing employing per-channel pulse control and measurement circuitry synchronized via a global system clock. In such a system, multiple test channels are provided, each including a pulse resource, a measurement resource with a high-current (HC) switch and a low-current (LC) switch, and a mode switch coupled to a potential node connected to a corresponding test pin. The pulse resource in each test channel generates a controlled drive waveform that can be shaped or timed according to calibration or test parameters received from a controller. The mode switch selectively connects the potential node to either the pulse resource or the measurement resource, thereby determining whether the channel delivers a test pulse or performs a measurement operation. When the mode switch connects the pulse resource to the potential node, the channel applies a pulse waveform to the device under test (DUT) through its test pin. When the mode switch connects the measurement resource to the potential node and the HC switch is closed, the channel operates in a high-potential (HP) measurement mode suitable for sourcing or measuring high voltage or large signal conditions. When the LC switch is closed, the channel operates in a low-potential (LP) mode supporting precise low-current or high-sensitivity measurements. Each test channel operates on a timing signal derived from a common system clock, which maintains frequency and phase alignment across all channels. This synchronization enables simultaneous pulse testing (e.g., both delivery and measurement, or both independently) and parameter testing across multiple pins of the DUT with deterministic timing and minimal deviation. Per-channel configuration and timing control allow the system to dynamically reassign roles—e.g., pulse generation / measurement, high-level measurement, or low-level measurement—without relying on external switching matrices or mechanical relays. By combining independent pulse control, synchronous measurement capabilities, and integrated high-current and low-current switching within each channel, the disclosed architecture supports high-speed, flexible, and parallel parameter testing with improved accuracy, reduced switching latency, and enhanced timing consistency across test channels.

[0074] Another aspect of this disclosure relates to a system for parallel testing that enables flexible per-channel configuration and coordinated signal generation under centralized processor control. In such a system, one or more processors manage multiple test channels synchronized by a system clock. Each test channel may include a pulse resource, a measurement resource including a first configurable switch, a second configurable switch, and a direct digital synthesizer (DDS), a mode switch coupled to the pulse and measurement resources, and a potential node connected to a corresponding test pin. This potential node forms an interface to the device under test (DUT) and serves as the point where pulse, source, or measurement operations occur. The mode switch determines whether the potential node is coupled to a pulse resource for waveform delivery or to a measurement resource for measurement functions. The configurable switch within the measurement resource allows each channel to be dynamically assigned as a high channel, low channel, pulse generator, or measurement channel. For example, closing one switch configures the channel for high-potential operation, while closing another switch configures it for low-potential or sensitive measurement conditions. The DDS in each channel generates a programmable analog waveform whose frequency and phase are derived from the global system clock, ensuring that all test channels operate with precise timing alignment. Through coordinated control, the processor configures each DDS to generate a test signal with a unique frequency or phase, allowing simultaneous excitation of multiple DUT pins without crosstalk. The processor can also command channels to perform simultaneous measurements using timing derived from the same system clock, maintaining coherence across the entire test array. By integrating per-channel DDS generation, configurable switching, and mode selection under processor control, the disclosed parallel test system supports true simultaneous operation across multiple channels. This arrangement allows each channel to independently perform drive or measurement functions while maintaining global phase and frequency synchronization. As a result, compared to traditional sequential testers, this system achieves high-throughput testing with reduced measurement bias and significantly shorter total test time, while maintaining precise timing correlation across all channels.

[0075] Other aspects of the disclosed technology may relate to a system for enhanced multi-channel parameter testing by integrating channel processing circuitry directly within each test channel, along with configurable switches and a dedicated direct digital synthesizer. This architecture allows each channel to be reconfigured as needed to act as a high channel, low channel, or measurement channel, providing flexibility in the test setup. The local processing circuitry can be configured to support analog-to-digital conversion and even frequency domain transformation, which reduces data transmission overhead and enables faster, more localized analysis. Combined with a DDS output calibrated to the system clock, the disclosed system allows for a scalable architecture where many channels can operate in parallel while delivering accurate, synchronous measurement data—something that some centralized systems cannot achieve without significant latency and / or complexity.

[0076] Some publicly available methods and systems will now be discussed in detail, examples of which are shown in the accompanying drawings.

[0077] Figure 1 A schematic diagram of a multi-channel parallel device test system 100 according to an embodiment of the present disclosure is shown. The multi-channel parallel device test system 100 may include a probe station 102, a test head manipulator 104, a probe station interface 106, and a cabinet 108.

[0078] The probe station 102 can be rotatably mounted on the test head manipulator 104 and can be electrically connected to components in the cabinet 108 via a high-density cable or blind-plug base plate for receiving power, clock, trigger signals, and data. The test head manipulator 104 can be mounted on one side of the probe station interface 106. The cabinet 108 can be mounted on the other side of the probe station interface 106. In some embodiments, the probe station interface 106 can be located between the test head manipulator 104 and the cabinet 108. The test head manipulator 104 can mechanically center, fix, and position the probe station 102 to align with the mating surface of the probe station interface 106. The probe station interface 106 can be located below the probe station 102 and dock with the test head manipulator 104.

[0079] When the test head manipulator 104 rotates, the probe station 102 can be lowered onto the device under test (DUT) held by the probe station interface 106, or raised away from the DUT. The cabinet 108 can be connected to the probe station 102 via a coaxial cable / differential harness or a blind-plug backplane to communicate with the host PC via Ethernet / PCIe.

[0080] In some embodiments, probe station 102 can serve as a main instrument module or test head located at the front of system 100. In some embodiments, probe station 102 may house parameter measurement electronics, such as a source measurement unit (SMU), switching circuitry, a timing generator, and associated control hardware. Probe station 102 can provide a primary electrical interface to the wafer or DUT and may be configured with high-density triaxial connectors, blind-mating coaxial assemblies, or differential interfaces to reduce insertion loss and signal distortion. In some embodiments, probe station 102 may also include shielding structures, protection paths, or integrated calibration circuitry to maintain low leakage current and high accuracy over a wide voltage and current range.

[0081] In some embodiments, cabinet 108 may house one or more parameter measurement units, switching assemblies, power distribution modules, and / or cooling systems. Cabinet 108 may be constructed from sheet metal, aluminum alloy, stainless steel, or a composite structure, depending on thermal and mechanical requirements. In some embodiments, cabinet 108 may include modular brackets or racks for housing resource cards or measurement modules, enabling flexible aisle expansion. Thermal management may be provided through forced air cooling, liquid cooling, or a hybrid configuration, and cabinet 108 may further include vibration-damping mounts or shock absorbers to reduce external interference during sensitive measurements.

[0082] The probe station 102 and test head manipulator 104 may be constructed of rigid, low-expansion materials, such as granite, ceramic composites, or stable metal alloys, to ensure positional accuracy and mechanical stability during wafer probing operations. In some embodiments, the test head manipulator 104 may include a linear actuator, pneumatic lifter, or rotary bearing to enable controlled movement during docking and disengaging of the probe station 102. The probe station interface 106 may include a receptacle connector, blind-mating triaxial contacts, or a custom high-density pin block to electrically couple the probe station to the cabinet 108. In alternative embodiments, the probe station interface 106 may incorporate a shielding structure or protective traces formed of conductive material to minimize electrical noise and crosstalk between adjacent test channels.

[0083] Figure 2 A top front view of the probe station 102 of a system 100 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the probe station 102 may include an interface panel 202 and a side panel 204. The interface panel 202 may be located on the upper front region of the probe station 102. The interface panel 202 may centrally house connectors for connecting the probe station 102 to the cabinet 108 and the test head manipulator 104. The interface panel 202 may house high-density signal connectors, power inputs, clock and trigger ports, high-speed data links, and interlock or status terminals. A ventilation grille visible near the interface panel 202 may provide airflow for cooling and may include dust filtration.

[0084] Side panel 204 can be a housing plate secured to the side of probe station 102 by multiple screws. Side panel 204 provides service access to internal channel electronics for the installation, maintenance, or replacement of modules such as HC and LC switches, analog front-ends, direct digital synthesizers, analog-to-digital converters, phase correction registers, and memories. Side panel 204 may incorporate electromagnetic interference (EMI) gaskets, grounding springs, and positioning features to maintain shielding and mechanical rigidity after reassembly.

[0085] In some embodiments, the probe station 102 may further include ventilation components integrated into the upper and lower regions of the housing. These ventilation components may be configured with forced-draft fans, heat exchangers, or liquid-cooled conduits to regulate the internal temperature of the high-density electronics. Ventilation grilles may be made of corrosion-resistant alloys or polymer composites and may incorporate removable filter media to prevent dust accumulation. The placement of these cooling features near the interface panel 202 enables localized thermal management in the vicinity of high-power connectors and data links.

[0086] The probe station 102 can also be constructed from a modular external panel including side panels 204 to facilitate flexible maintenance and upgrade paths. In some embodiments, the panel may be made of aluminum, stainless steel, or carbon fiber composite materials, depending on weight and shielding requirements. The housing may be sealed with EMI gaskets to reduce radiated emissions, and fasteners securing the panel may be configured for tool-free or quick-release access to accelerate maintenance cycles. Optional structural reinforcements, such as internal ribs or honeycomb panels, may be included within the probe station 102 to increase rigidity and reduce vibration transmission during sensitive measurements.

[0087] In alternative embodiments, interface panel 202 may incorporate additional or alternative connector types depending on the system configuration. For example, interface panel 202 may include fiber optic transceivers or wireless communication modules for high-bandwidth, low-latency data transmission to reduce cabling complexity in certain installations. Redundant power inputs and signal connectors may also be provided to support fault tolerance and hot-plugging capabilities. In some configurations, interface panel 202 may be reconfigurable or replaceable as a module, allowing for different connector layouts to be deployed based on application requirements or customer specifications.

[0088] Figure 3 A bottom rear view of the probe station 102 of a multi-channel parallel device test system 100 according to an embodiment of the present disclosure is shown. Figure 3 As shown, the probe station 102 may include a probe card interface 302 and a docking plane 304. The probe card interface 302 may be mounted at the center of the docking plane 304 of the probe station 102 via an annular frame having multiple fasteners and alignment features. The probe card interface 302 may carry a probe array arranged to contact wafer test points and electrically connected to the probe station 102 via a blind-mate connector that routes force and sensing signals to the front end of a channel within the probe station 102.

[0089] When testing a wafer DUT, the wafer can be raised to engage the probes of the probe card interface 302, while the probe station 102 provides mechanical alignment, shielding and thermal management, and communicates with the DUT to deliver excitation and acquire measurement data.

[0090] The mating plane 304 may also include mechanical guides, locating pins, and kinematic supports to ensure repeatable alignment between the probe card interface 302 and the mating connector within the probe stage 102. In some embodiments, the mating plane 304 may be made of aluminum alloy, stainless steel, or ceramic composite material to provide a stable, low-expansion platform that maintains positional accuracy under temperature variations. The mating plane 304 may also include a shielding layer or conductive coating to reduce electromagnetic interference and maintain signal integrity during high-precision measurements.

[0091] The probe card interface 302 can be configured with interchangeable probe arrays to accommodate different wafer technologies, device geometries, or pad layouts. In some embodiments, the probe card interface 302 may employ vertical probe tips, MEMS probe tips, or cantilever spring contacts, depending on the required spacing and current handling capability. The probe card may also include embedded passive components, such as decoupling capacitors or terminating resistors, to improve high-frequency performance. For thermal management, the probe card interface 302 and the mating plane 304 may be coupled to an integrated airflow channel or liquid cooling feature positioned along the underside of the probe stage 102.

[0092] The pins or connectors of the probe card interface 302 can be arranged in various configurations to allow for customization for different testing applications. In some embodiments, the pins can be organized in a linear array, radial pattern, or high-density grid to match the pad geometry of different wafers or packaged devices. The probe tips can be vertical spring probes, MEMS microsprings, or cantilever pins to accommodate variations in contact force, spacing, and current capacity. Alternative mechanisms may include adjustable probe blocks, replaceable pin inserts, or modular probe arrays, which allow for rapid reconfiguration without replacing the entire probe card assembly. This flexibility enables the probe card interface 302 to be used with logic devices, memory arrays, power semiconductors, or mixed-signal circuits with different electrical and mechanical requirements.

[0093] In some embodiments, the probe card interface 302 may further include calibration and alignment mechanisms to ensure consistent electrical contact across the entire pin array. Such mechanisms may include self-planarizing probe structures that adjust tip height during initial contact, an optical reference embedded in the mating plane 304 to guide an automated vision alignment system, or a mechanical micro-adjuster configured to fine-tune the vertical and lateral position of the probe array. Additional implementations may include an integrated height sensor, strain gauge, or capacitance sensor that detects flatness deviations and provides feedback for automatic compensation. These features enable the probe card interface 302 to maintain precise contact with the wafer pads under various topographic and thermal conditions, thereby improving repeatability and reducing setup time between tests.

[0094] Figure 4A front view of the probe station 102 of a multichannel parallel device test system 100 according to an embodiment of this disclosure is shown. An elongated I / O panel, located near the upper front, concentrates connectors and indicator lights for power inputs, clock and trigger signals, and high-speed data links. Ventilation grilles adjacent to the panel facilitate airflow. Fasteners and alignment features around the panel facilitate secure mounting and reliable mating to cable harnesses or blind-plug baseplates. A rectangular service cover in the lower middle region provides access for mounting, maintaining, or replacing internal channel electronics and cabling while maintaining housing shielding and rigidity. Along the lower edge, mating components protrude to define a mating interface for probe card interface 302, including an annular structure with mechanical guides and locking points that maintains flatness and repeatable alignment and provides electrical connection to the channel front end within the test head. The housing forms a rectangular rounded-corner enclosure with peripheral fasteners and seams that establish a rigid frame and define airflow paths for thermal management. The location, geometry, and number of the features shown are exemplary and can be varied to meet wiring, thermal, or mechanical requirements.

[0095] In some embodiments, the interface panel 202 may also include modular connector blocks that allow for customized layouts based on system configuration. These blocks may be designed to accommodate coaxial, triaxial, differential, or fiber optic terminations and may be arranged in interchangeable sub-panels to adapt the probe station 102 to different measurement environments. Indicator lights on the interface panel 202 may include LEDs for power status, clock synchronization, error reporting, and thermal alarms, while an optional LCD or touchscreen interface may provide direct operator feedback and local configuration.

[0096] The mating assembly coupled to the probe card interface 302 may be additionally configured with spring-loaded clamps, cam locks, or quick-release latches to allow for rapid probe card replacement without interfering with the mechanical calibration of the probe station 102. In some embodiments, the assembly may include precision locating pins, keyways, or optical references to ensure repeatable alignment during repeated mating cycles. To further maintain signal integrity, the annular structure of the mating assembly may include an embedded grounding ring or shielding ring that provides continuous electrical shielding when the probe card interface 302 is engaged.

[0097] Figure 5 A schematic diagram of a retractable electrical contact interface device 500 in a retracted position according to an embodiment of the present disclosure is shown. The retractable electrical contact interface device 500 may include an electrical contact interface assembly 502, an electrical connection point 504, a spring pin 506, a test head housing 508, and a retractable electrical contact interface module 510. The electrical connection point 504 may represent a target location for electrical connection, such as a probe card interface 302 or an interface of a calibration device.

[0098] The test head housing 508 mechanically supports a retractable electrical contact interface, defines an opening through which the assembly 502 travels, and provides structural alignment and electromagnetic shielding for connection to the probe card interface 302. The test head housing 508 is coupled to the test head frame and provides a reference plane that defines the Z-height and flatness relative to the probe stage. A retractable electrical contact interface module 510 is mounted to the test head housing 508. The retractable electrical contact module 510 may include a movable electrical contact interface assembly 502 carrying a spring pin 506 and is matable to an external electrical connection point 504 on the probe card interface 302.

[0099] exist Figure 5 In the retracted state shown, the electrical contact interface assembly 502 can be separated from the electrical connection point 504, so the spring pin 506 can be neither connected to nor pressed by the electrical connection point 504. The assembly 502 can be partially recessed into the test head housing 508 to shield and protect the tip of the spring pin 506 from accidental contact, debris, or electrostatic discharge. Figure 5 Conversely, an electrical connection is established when the electrical contact interface assembly 502 moves downward to allow the spring pin 506 to contact the electrical connection point 504.

[0100] Therefore, the retractable electrical contact interface device 500 of this disclosure allows the electrical contact interface assembly 502 to extend or retract from the electrical connection point 504. This is achieved by moving an actuator lever on the side of the multichannel parallel device test system 100, which rotates a cylindrical cam to move the entire retractable electrical contact interface device 500 into place.

[0101] By designing a retractable electrical contact interface device 500, the likelihood of damage to the spring pin 506 and wafer probe station is reduced when docking with a multi-channel parallel equipment test system 100, and tester accessories such as calibration equipment can be attached more reliably and more easily.

[0102] In addition, the test head housing 508 can shield the interface when not engaged to further reduce the risk of pin damage and improve EMI / ESD suppression and contamination control during docking and disengagement.

[0103] In some embodiments, the retractable electrical contact interface assembly 502 can be actuated by various mechanisms, including a motor-driven lead screw, a pneumatic cylinder, or a cam-based linkage, providing precise and repeatable vertical displacement. The actuation mechanism can also incorporate a position sensor, encoder, or limit switch to detect retraction and engagement states, enabling automated docking sequences under software control. This configuration reduces operator variability and ensures consistent contact force when the spring pin 506 engages the electrical connection point 504.

[0104] The spring pins 506 can be arranged in a customizable pattern to correspond to different electrical connection point geometries. For example, depending on the interface requirements of the probe card interface 302 or the external calibration module, the spring pins 506 can be distributed in concentric rings, staggered arrays, or high-density grids. Each spring pin may include a plunger and sleeve assembly formed of a conductive alloy, such as beryllium copper, plated with gold or palladium to enhance abrasion resistance and low contact resistance. Optional elastic bushings or elastomeric supports can also be incorporated to absorb mechanical stress and extend service life under repeated cycles.

[0105] The retractable electrical contact interface device 500 may also incorporate an environmental seal or contaminant barrier to maintain interface integrity. A retractable dust cover, gasket seal, or positive pressure airflow may be used to prevent debris from entering the test head housing 508 during retraction. In some embodiments, the retractable electrical contact module 510 may include an integrated shield or protective ring positioned adjacent to the spring pin 506, thereby reducing electromagnetic interference and crosstalk between high-frequency channels.

[0106] Figure 6 A schematic diagram of a power supply 600 for a top component according to an embodiment of the present disclosure is shown. Figure 6 As shown, the power supply 600 may include a high-current multi-pin power terminal 602, a circuit breaker 604, a circuit breaker stack 606, a control terminal 608, an AC contactor 610, a safety relay 612, a thermal protection module 614, a DC power distribution bus 616, a DC-DC power module 618, and a cable entry assembly 620.

[0107] Power supply 600 can provide voltage and current delivery to resource cards, test elements, and probe station interfaces. Power supply 600 can support various test requirements and can be combined with protection circuitry to prevent overvoltage, overcurrent, and overheating, using protective devices such as fuses or circuit breakers, contactors or relays, and thermal sensing. An external emergency stop button can be provided to quickly cut off power and enhance operational safety. The component locations shown are exemplary and can be changed without departing from the described functions.

[0108] A high-current, multi-pin power terminal 602 can distribute controlled power and ground to the test head backplane and / or resource card, and can employ bonding and locking features to prevent mis-insertion. A circuit breaker 604 provides first-level isolation and overcurrent protection for the AC input and can be connected to an emergency disconnect (EMO) circuit. A circuit breaker stack 606 provides protection for each branch and, in some embodiments, can incorporate current sensing elements for load telemetry. A control terminal 608 can accept interlock signals, trigger I / O, fan control, and status lines. An AC contactor 610 can close only when host authorization is present and all interlocks are satisfied, thus serving as a master connection / disconnect device. A safety relay 612 can converge high-voltage and ground interlock signals and cut off power upon detection of a fault.

[0109] Thermal protection module 614 monitors the case or power supply temperature and issues an alarm when the temperature is too high. DC power distribution bus 616 can fan out power rails such as +48V, +12V, and +5V to resource slots and can provide protection and test points for each branch. DC-DC power module 618 can convert AC input or intermediate bus to the required DC power rail and, in some embodiments, supports redundancy, hot-swapping, power factor correction, and EMI filtering. Cable entry assembly 620 guides incoming cable harnesses, provides stress relief, and can provide a centralized protective grounding connection point for enhanced electrical safety.

[0110] In normal operation, AC power passes through circuit breaker 604 and AC contactor 610 for isolation and protection before entering DC-DC power module 618 to generate the required DC power rails. These power rails can be distributed via DC distribution bus 616 and can be delivered to backplane and resource cards via high-current multi-pin power terminals 602. Control and safety signals can be handled via control terminals 608, safety relays 612, and thermal protection module 614 to ensure immediate power cut-off in the event of EMO activation or fault detection. The location and type of the aforementioned components can be changed without departing from the functionality and scope of power supply 600.

[0111] Figure 7 A block diagram 700 of a multi-channel parallel device test system 100 according to some embodiments of the present disclosure is shown. A main system controller 710 can coordinate timing, data movement, and system services. The main system controller 710 may include a processing system 711 and programmable logic 712 monitored by a system monitor 7127.

[0112] Within the processing system 711, the application processing unit 7111 can perform advanced test control. The memory 7112 can represent on-chip or attached memory. The system functions 7113 can provide timers and peripheral devices. The high-speed connectivity 7114 can provide fast I / O. The real-time processing unit 7115 can handle deterministic tasks. The platform management unit 7116 can handle health or telemetry. The configuration and security unit 7117 can manage secure boot or keys. The general-purpose connectivity 7118 can provide standard serial and general-purpose I / O (GPIO) interfaces. The programmable logic 712 can implement data plane functions, including storage and signal processing 7121, general-purpose I / O 7123, and high-speed connectivity 7125.

[0113] The main system controller 710 can interface with and debug external memory. The memory 7101 can be a 4-gigabyte DDR4 memory module with error correction codes (ECC) and can provide large working memory. The Real-Time Clock (RTC) battery backup 7103 can retain the RTC and reserved domains. The Joint Test Action Group (JTAG) 715 provides boundary scan and firmware debugging.

[0114] The Output / Front-End Field-Programmable Gate Array (OFPGA) 730 performs channel timing, capture, and allocation. It may include a local JTAG 731 for debugging, a quad-serial peripheral interface (QSPI) flash memory 732 for bitstream storage, and local memory 733 (e.g., 1 GB DDR4) for buffering vectors and results. A precision temperature-compensated crystal oscillator (TCXO) 735 feeds an equal-length fanout to a low-voltage differential signaling system (LVDS) 734, which allocates phase-aligned references to the controller and the OFPGA (and forward to resources). A system power supply 736 powers these subsystems.

[0115] Resources can reside in resource slots 1-4 740. Each slot can receive power distribution and clock / trigger lines and connect to a shared analog bus: a sensing bus 741 and a force bus 742 for Kelvin routing. The grounding subsystem includes a GNDU 750 (grounding / force unit) and an optional reference, as well as an analog / calibration bus 760 for injecting calibration excitation and routing the analog reference across slots. The OFPGA 730 fans out a high-speed serial link (e.g., GT~1.3 Gb / s), trigger outputs / inputs, and digital I / O OUT ×2 / I / O IN ×8 to resource slot 740 to support synchronous excitation and measurement.

[0116] In some embodiments, the main system controller 710 may further include redundant power domain management and monitoring circuitry, such as voltage monitors, detectors, and overcurrent protection. The processing system 711 and programmable logic 712 may be connected via a high-bandwidth internal bus for configuration, data movement, and control switching. Additionally, the system monitor 7127 may monitor temperature sensors, fan controls, and thermal alarms located on resource slots, the OFPGA 730, and analog / digital front-end modules. The controller may also establish secure communication with external devices via Ethernet and supported protocols such as TCP / IP, possibly via fiber optics, and may implement TLS or other encryption for data in transit.

[0117] The OFPGA 730 can receive a common system reference clock (e.g., a 100 MHz TCXO 735) and distribute phase-aligned clock and trigger signals to the resource slot 740 and the front-end measurement module. For example, the OFPGA 730 can drive LVDS lines with matched trace lengths to each resource slot to ensure synchronization.

[0118] Within resource slots 1-4 (e.g., 740), each slot may include several parameter channels for measurement using a shared analog common bus (sensing bus 741, forced bus 742). Each channel may also have a local digital-to-analog or analog-to-digital converter and may communicate with the OFPGA 730 via a dedicated high-speed line. The analog / calibration bus 760 allows calibration references (voltage, current) to be injected into the analog front end of each resource slot; these references may be provided by a precision digital-to-analog converter (DAC) or an external calibration source. Grounding via grounding unit 750 ensures a consistent common reference between slots and allows selection between internal chassis grounding, isolated analog grounding, or external grounding via jumpers or connectors.

[0119] Optional configurations can include more than four additional resource slots, linked by expansion connectors for large channel counts, or a hierarchical OFPGA for multi-layer synchronization. Optional filter networks, such as RC or LC filters, can be present in conjunction with the force lines or sensing paths used for noise suppression, and may be switchable depending on test requirements. Furthermore, the system can include programmable attenuation or scaling blocks in the force lines to support both high current (for traditional or power devices) and low current (for leakage current or modern small-size devices) within the same slot.

[0120] Commonly, components numbered 710-736 provide secure computing, storage, timing, and power for the digital backplane; components 740-742, 750, and 760 implement the analog / digital allocation and grounding of resources required for phase coherence and parallel parameter testing.

[0121] Figure 8A hub architecture and communication 800 according to an embodiment of this disclosure are illustrated. (As follows) Figure 8 As shown, the exemplary configuration of this disclosure provides a multi-FPGA hierarchical architecture, which includes a main FPGA 810, dedicated FPGAs (distributed field-programmable gate arrays (DFPGAs) 850 and DFPGA 860), and multiple resource channels 870 (shown as resource channels 872A and 872B). This three-layer structure enables large-scale parallel computing and multi-channel data processing.

[0122] like Figure 8 As shown, the main FPGA 810 can interface with the processor system 811 via ports 812, 815, 816 and 817. Each port can be implemented using the Advanced Extensible Interface (AXI) high-performance interface, which enables data flow between the programmable logic and the processor 813 and the peripheral / control logic 814.

[0123] External memory module 818 can be used as a buffer for high-capacity storage. Within the main FPGA 810, AXI interconnects 822 and 831 distribute AXI transactions between the master device, which includes processing core 813 and direct memory access (DMA) logic 821, and slave devices, which include DDR4 memory module 828 and multiple chip-to-chip (Chip2Chip) blocks 823, 824, 825, 826, 827, 833, 834, 835, 836, and 837. Blocks 851 and 861 represent the Chip2Chip and Aurora link endpoints connecting the main FPGA 810 to DFPGA 850 and DFPGA 860, respectively, thereby enabling high-speed serial link communication.

[0124] Furthermore, resource channel 870 may include a first resource channel 872A and a second resource channel 872B, each including components similar to those in the main FPGA 810 and DFPGAs 850 and 860. For example, the resource channels may utilize the AXI-HP interfaces 812A and 812B, control logic 814A and 814B, local DMA logic 852, and local DDR3 memory modules present on each resource channel board. Resource channel 870 may communicate uplink via Chip2Chip blocks 823-837 in the main FPGAs 810 / DFPGAs 850 and 860, thereby enabling scalable channel fan-out counting with local buffering, local control logic, and excitation / measurement path capabilities in each resource module.

[0125] The main FPGA 810 may also include a processor system 811 and programmable logic. The processor system 811 may include a processing core 813 and peripheral / control logic 814. Ports 812, 815, 816, and 817 (AXI-HP0 to AXI-HP3) exchange data with external DDR4 memory 818; DMA logic 821 handles high-volume transfers between the processor system 811 and the programmable logic. AXI interconnects 822 and 831 are used to route transactions between master and slave devices within the main FPGA 810, maintain consistency, and facilitate distributed communication between Chip2Chip blocks, resource channel interfaces, and memory 828.

[0126] The main FPGA 810 can communicate with the DFPGA 850 and 860 via a compact device-to-device interface (e.g., Chip2Chip and Aurora IP) for high-speed data transfer.

[0127] DFPGA 850 and DFPGA 860 can be used as intermediate aggregation and distribution nodes. Each DFPGA may include local memory and other processing or buffering logic. DFPGA 850 receives stimulus / control paths from the master FPGA 810 (via blocks such as 851, 861, 823-827, etc.) and fans out data and control to resource channels 872A / 872B through its respective endpoints.

[0128] One embodiment of this disclosure implements (i) centralized stimulus and control allocation via a main FPGA 810, (ii) parallel buffering, relaying, aggregation, and data fan-out via DFPGAs 850 and 860, and (iii) large-scale expansion of resource channels 872A / 872B for high channel count measurements. By integrating endpoints (blocks 823-837, 851, 861) with an AXI interconnect architecture (ports 812 / 812A / 812B, interconnects 822 / 831), local DMA logic (821, 852), and buffer memory (DDR4 818 / 828, DDR3 modules in the resource channels), the system provides high-throughput, scalable, low-latency multi-channel test capabilities.

[0129] In some embodiments, resource channel 870 may include an optional local buffer (e.g., DDR3 or DDR4) to accommodate bursts of measurement data, so that downstream DFPGAs 850 and 860 or the main FPGA 810 do not need to keep up continuously in real time. This buffering is helpful because measurement data (especially for waveforms, transient responses, capacitance scans, etc.) can occur in bursts. Furthermore, this architecture allows for local processing (filtering, averaging, correlation) within the resource channel to reduce the amount of data passed upstream.

[0130] Figure 9 A hub controller 900 of a multi-channel parallel device test system 100 according to an embodiment of the present disclosure is shown.

[0131] The HUB controller 910 communicates with the host computer via Ethernet and Universal Serial Bus (USB) interfaces and provides system-level triggering and clock distribution to synchronize downstream measurement modules. The system may further include an external analog bus and force / sensing / protection SMA connectors for precise electrical connection to the DUT.

[0132] The HUB controller 910 may include, but is not limited to, a hardware sequencer, dynamic random access memory (DRAM) for temporary data storage, flash memory for firmware and test programs, a trigger processor for generating or receiving trigger signals and distributing them to resource boards 920, and a clock distribution network providing a synchronous clock to each board. The HUB controller 910 communicates bidirectionally with each resource controller 990, such as... Figure 9 As shown by the double arrows in the image.

[0133] Each resource board 920 may include a resource controller 990 equipped with a hardware sequencer, DRAM, and flash memory for managing local timing and parameter configuration. The resource board 920 further includes multiple measurement and excitation modules, such as SMUs 930 and 960, which can supply precise voltage or current and perform corresponding measurements, while supporting Kelvin four-wire connections to minimize lead resistance. The resource board 920 may also include CMU / FMUs 940 and 970 for impedance, capacitance, or frequency-related measurements, and pulse generator units / parameter IV units (PGU / PIV) 950 and 980 for generating pulse signals and performing parametric current-voltage measurements.

[0134] The HUB controller 910 may also include status and monitoring outputs, including lines 916, 918, 922, and 924. Line 916 (“Force”) can transmit a force command or force bias to the force pin of the channel (e.g., to control source current or voltage). Line 918 (“Carrier Ground”) can provide a reference ground potential for the housing connected to the test head to ensure proper grounding and safety. Line 922 (“Interlock Normal”) can be set as a safety / status signal indicating that the interlock (mechanical or electrical) is in the appropriate state before enabling high-voltage or high-current operation. Line 924 (“OPIO”) can be used as an optional parallel I / O or operational I / O line for auxiliary signals, control, or multiplexed signals to / from external instruments or calibration equipment.

[0135] The external analog bus for each test head quadrant is accessed via an SMA (SubMiniature Version A) connector, such as connector 926, which carries multiple lines per channel, including force, sensing, and protection. These force / sensing / protection SMA connectors can be configured with a precision coaxial interface designed to maintain a low parasitic and low-noise path. The protection line helps protect the sensing line or ground line from leakage current or noise by surrounding the force or sensing conductor with a drive or protection potential.

[0136] Resource board 920 is shown as having multiple channel-specific modules: for example, SMU 930, 960 units serve as source measurement units that can both inject excitation (voltage or current) and measure response; CMU / FMU modules 940, 970 are used for capacitance or frequency measurement or front-end filtering / frequency measurement; and PGU / PIV units 950, 980 are pulse generator units or parametric IV units for pulse excitation (e.g., for memory cell programming) or performing dynamic IV scans. Channels such as channel 1 (912) and channel 2 (914) each include force, sensing, and protection connections configured via modules on the board.

[0137] Resource controller 990 coordinates among modules on resource board 920, managing local sequencing, configuration settings (e.g., compliance, range, measurement mode), and local timing. It can gate excitations, route measurement data, and regulate modules (SMU, CMU / FMU, PGU / PIV) based on instructions from HUB controller 910. Resource controller can also provide feedback via line 922 to ensure each module is safely connected and operated before excitation is applied.

[0138] The test head housing defines the physical separation between the HUB controller 910, resource board 920, and external connectors. The housing may include mounting hardware for the SMU, CMU / FMU, and PGU / PIV modules, cable harnesses from these modules to the external analog bus, and mechanical supports for the channels (912, 914). The entire assembly is arranged such that force / sensing / protection paths are tightly controlled, shielding or grounding is maintained, and signal integrity (low leakage current, low capacitance parasitics) is preserved.

[0139] Figure 10 A schematic circuit 1000 is shown for test channels 1010, 1020 in a multi-channel parallel device test system 100 according to an embodiment of the present disclosure. In some embodiments, circuit 1000 may implement one or more components in resource board 920. For example, circuit 1000 may implement one or more of SMU, CMU, FMU and / or PGU.

[0140] A multi-channel parallel device test system 100 may include multiple test channels 1010 and 1020. Each of the test channels 1010 and 1020 may include a high-current (HC) switch, a low-current (LC) switch, a potential node, a channel clock (e.g., a clock for each test channel), and a system clock. Figure 10 As shown, test channel 1010 may include HC switch 1011, potential node 1013, and LC switch 1015, and test channel 1020 may include HC switch 1021, potential node 1023, and LC switch 1025. Each channel clock may be configured with a phase offset. The phase offset compensates for the phase shift associated with each of test channels 1010 and 1020 during calibration.

[0141] Potential node 1013 can be configured to perform a high-potential (HP) test when HC switch 1011 is closed, and can be configured to perform a low-potential (LP) test when LC switch 1021 is closed. In other words, the test channels 1010, 1020 of this disclosure can have only one potential node, which is high when HC switch 1011 is closed and LC switch 1015 is open, and low when HC switch 1011 is open and LC switch 1015 is closed. Therefore, each test channel 1010, 1020 can be a high channel or a low channel. Furthermore, HC switch 1011 and LC switch 1015 can be configured to operate alternately, such that when one is closed, the other remains open.

[0142] In the multi-channel parallel device test system 100, test channels can operate under the same clock to ensure proper synchronization. When a common clock is allocated to each test channel 1010, 1020, measurement data across test channels 1010, 1020 can share a unified time reference that allows results to be accurately aligned and compared. For example, impedance or capacitance measurements rely on the precise phase relationship between voltage and current signals. If test channels 1010, 1020 do not share the same clock, phase shifts will occur, which can directly introduce errors into the calculated impedance, capacitance, or inductance values.

[0143] Several problems may arise if different test channels 1010 and 1020 operate on different clocks. First, measurement data from each test channel 1010 and 1020 may not correspond to the same moment, potentially making results incomparable between channels. Second, algorithms requiring simultaneous multi-channel data, such as pin-to-pin impedance calculations or multi-source excitation, may fail due to input misalignment. Third, the presence of multiple asynchronous clocks can introduce jitter, beat frequencies, or noise coupling between channels, reducing resolution and repeatability.

[0144] Therefore, this disclosure employs a centralized clock distribution system, enabling test channels 1010 and 1020 to share the same reference clock, which ensures phase coherence, synchronous triggering, and reliable high-precision parallel measurement.

[0145] In some embodiments, each test channel 1010, 1020 may have a channel clock. The channel clock in test channels 1010, 1020 has a frequency and a phase. However, in order to measure multiple DUTs 1030 in the multi-channel parallel device test system 100, the channel clocks need to be identical. Therefore, a system clock 1040 may be coupled to test channels 1010, 1020, and the system clock may be allocated to test channels 1010, 1020 for synchronizing the clock channels. As a result, the channel clock in each of test channels 1010, 1020 may have a frequency and phase synchronized with the system clock.

[0146] In some embodiments, each of test channels 1010, 1020 may further include a force line and a sensing line. The force line may be connected to potential nodes 1013, 1023 via HC switch 1011 or LC switch 1025. The force line may provide a signal to DUT 1050. The sensing line may be connected to potential nodes 1013, 1023. The sensing line may detect the voltage at the DUT.

[0147] Test channels 1010 and 1020 can each be arranged with multiple DDS blocks and an FFT + memory + voltage / analog-to-digital converter (VADC) front end. In channel 1010, two DDS blocks are fed into the circuitry that drives the HC path when the high current (HC) switch 1011 is closed; similarly, in channel 1020, the DDS blocks are fed into their HC paths via HC switch 1021. However, this is only one possible implementation, and other implementations are possible. Furthermore, the DDS blocks can generate periodic test waveforms under the control of the system or channel clock, which can be fed into the high voltage amplifier paths (HP) 1013 / 1023 or via HC / LC as configured. The FFT + memory cells in each channel are used to capture time-domain or frequency-domain data: signals from the VADC blocks are stored in memory and processed via the FFT engine to extract spectral content or phase information.

[0148] The VADC blocks in test channels 1010 and 1020 convert analog signals (from potential nodes 1013 / 1023 or from the sensing line) into digital form. The output of the VADC is routed to memory for buffering and to the FFT engine for analysis. The output of the DDS block is also routed to an amplifier that feeds test pins 1017 / 1027 via HC, HP, or LC switches. Signal paths may include amplifiers or gain stages (shown between the DDS and HC / HP / LC switches) to set the appropriate level for force or measurement. Resistive elements (e.g., small variable resistors in test channel 1010 shown in the HP or LC path) can be used to limit or adjust current or to implement compliance control.

[0149] The switches used for HC 1011 / 1021, HP 1013 / 1023, and LC 1015 / 1025 allow selection of different modes: the potential node (1013 / 1023) is in a high-potential mode when the HC switch is closed and the LC switch is open; and in a low-potential mode when the LC switch is closed and the HC switch is open. The HP switch can represent a high-precision or high-potential mode with different gain or compliance characteristics. These switches allow for flexible reconfiguration of individual potential nodes for each channel between high-potential and low-potential test modes. Test pins 1017 (for channel 1010) and 1027 (for channel 1020) are the actual electrical nodes that contact the DUT 1050, with load-bearing, sensing, and protection connections (protection may optionally be grounded or driven) depending on the measurement requirements.

[0150] The system clock 1040 can be configured to drive timing in two test channels 1010 and 1020. Each channel has its own channel clock derived from the system clock 1040, with a configurable phase offset for calibration. Synchronization ensures that data is aligned in time and phase when measurements are performed across both channels (e.g., simultaneous impedance, capacitance, or dual-channel excitation). Without a common reference (the system clock), measurements involving phase (such as impedance or reactance components) become uncertain.

[0151] The DUT 1050 can be connected to test pin 1017 (channel 1010) and test pin 1027 (channel 1020) for force / sensing / protection paths. Sensing lines from the DUT 1050 can return voltage to the sensing input of the corresponding channel (via a sensing path through a switch and VADC), and protection lines can be wrapped around or shielded from force / sensing to reduce leakage current or noise. Force lines drive the excitation (voltage or current) through switches and amplifiers. The LC / HP / HC paths carry different current or voltage ranges: LC is used for very low current / low potential measurements (e.g., leakage current), HP for higher accuracy or high-potential modes, and HC for high-current modes when needed.

[0152] like Figure 10 As shown, the system may include multiple test channels (e.g., 1010, 1020). Test channels 1010 and 1020 may include high-current (HC) switches 1011 and 1021, low-current (LC) switches 1015 and 1025, and potential nodes 1013 and 1023 coupled to corresponding test pins 1017 and 1027. Each test channel 1010 and 1020 may also be associated with a channel clock that is timed from the system clock 1040. Potential node 1013 may be configured to perform a high-potential (HP) test when HC switch 1011 is closed, and potential node 1023 may be configured to perform a low-potential (LP) test when LC switch 1025 is closed. The system clock 1040 allocates a common time base so that the channel clocks of test channels 1010 and 1020 are synchronized in frequency and phase.

[0153] In some embodiments, each test channel 1010, 1020 may further include a force line and a sensing line. For example, the force line may be coupled to a potential node 1013 via an HC switch 1011 or an LC switch 1015, and may transmit a signal from test channel 1010 to DUT 1050. The sensing line may be directly connected to the potential node 1013 and may detect the voltage generated at DUT 1050. Similarly, test channel 1020 may route its force line via an HC switch 1021 or an LC switch 1025, while its sensing line monitors DUT 1050 via potential node 1023.

[0154] In one embodiment, multiple test channels 1010, 1020 may be part of a larger channel array in system 100. First, second, and third test channels may be configured to set potential node 1013 to a first dynamic potential by coordinating their respective HC and LC switching states, while a fourth test channel may be configured to set potential node 1023 to a different dynamic potential. Using this arrangement, the multi-channel parallel device test system 100 can perform capacitance-voltage analysis by scanning the first dynamic potential across multiple channels and comparing capacitance as a function of a second dynamic potential provided by another channel.

[0155] like Figure 10As shown, each of test channels 1010 and 1020 may include a direct digital synthesizer (DDS) circuit. The DDS block can generate a periodic test signal whose frequency and phase are synchronized with the system clock 1040. For example, the DDS output in test channel 1010 can be routed to an amplifier and then applied to potential node 1013 via HC switch 1011 or LC switch 1015. Similarly, test channel 1020 can apply its DDS output to potential node 1023 via HC switch 1021 or LC switch 1025. By synchronizing all DDS circuitry to the system clock 1040, test channels 1010 and 1020 can measure the DUT 1050 while simultaneously deriving timing coherence from the system clock 1040.

[0156] Each of test channels 1010 and 1020 may also include a memory, first and second voltage-to-analog-to-digital converters (VADCs), and first and second DDS circuitry. For example... Figure 10 As shown, the outputs from potential nodes 1013 and 1023 can be digitized by corresponding VADC blocks, and the outputs of the VADC blocks are stored in memory. A first DDS can drive potential nodes 1013 or 1023, while a second DDS can be coupled to one or more in the VADC circuit to provide a sampling or reference signal. Thus, each channel 1010, 1020 can include both generation and measurement resources.

[0157] Furthermore, each channel clock of test channels 1010 and 1020 can include a programmable phase offset. During calibration, the processor can measure the relative phase shift introduced by each of test channels 1010 and 1020 when driven by system clock 1040, and can store the offset value in the corresponding channel clock. The stored phase offset compensates for the mismatch, enabling channels 1010 and 1020 to maintain phase coherence when performing parallel testing of DUT 1050.

[0158] In some embodiments, each of test channels 1010, 1020 may further include a Fast Fourier Transform (FFT) engine connected to the VADC output and memory. For example, the FFT block may process digitized data from potential node 1013 in channel 1010 or potential node 1023 in channel 1020. The FFT circuitry can transform the time-domain VADC output into a frequency-domain result, enabling accurate measurement of the amplitude and phase characteristics at DUT 1050.

[0159] At least one DDS circuit in each of test channels 1010 and 1020 can be configured to generate test signals for DUT 1050. For example, the DDS block in test channel 1010 can generate a sinusoidal excitation signal that is driven to potential node 1013 via HC switch 1011, while the DDS block in test channel 1020 can provide a synchronous reference signal or an independent excitation waveform for DUT 1050.

[0160] The multi-channel parallel device test system 100 may include eight or more test channels, such as channels 1010 and 1020. Each channel can be configured with phase and amplitude settings. By synchronizing the amplitude and phase on all channels with the system clock 1040, the system 100 can utilize the phase coherence between at least eight channels applied to the DUT array to perform high-density parallel measurements.

[0161] In some embodiments, system 100 may include a processor coupled to system clock 1040. Each of test channels 1010, 1020 may include a DDS. The processor may cause system clock 1040 to transmit calibration signals to test channels 1010, 1020. By comparing the response of the signal generated by the DDS with the calibration signal, the processor may measure the phase shift of each test channel and program the correction value into the phase shift register of the DDS circuit.

[0162] In one example, each DDS circuit in test channels 1010 and 1020 can implement a numerically controlled oscillator (NCO) driven by the system clock 1040. A programmable phase offset can be applied to the NCO to compensate for channel-specific delays in the measurements. As a result, the DDS signal applied to potential node 1013 via HC switch 1011 or LC switch 1015 remains in phase with the DDS signal applied to potential node 1023 via HC switch 1021 or LC switch 1025. Therefore, the DDS circuits in test channels 1010 and 1020 can be configured to generate test signals phase-aligned with the system clock 1040. This alignment ensures that measurements across channels 1010 and 1020 remain synchronized, enabling simultaneous multi-channel measurements of the DUT 1050.

[0163] like Figure 10 As shown, in some embodiments, each of test channels 1010, 1020 may include a high-potential (HP) circuit and a low-potential (LP) circuit. For example, test channel 1010 may route signals via potential node 1013 and HC switch 1011 for HP mode, or via potential node 1013 and LC switch 1015 for LP mode. By reconfiguring the HC and LC switches, the test channel can alternate between HP and LP operation according to test requirements.

[0164] In some embodiments, system 100 may include a processor coupled to test channels 1010, 1020. The processor may multiplex a reference signal into the HP and LP circuits by driving a system clock 1040. Synchronization with the trigger signal may align the phase across channels 1010, 1020. The processor may then calibrate the amplitude and phase of both the HP and LP circuits, generate an internally generated second signal to route to the HP circuit, and perform calibration based on a comparison between the first and second signals.

[0165] The first signal can be a sine wave provided by the system clock 1040, and the second signal can be generated by the DDS in test channels 1010 and 1020. The processor can measure the phase difference between the HP circuit and the LP circuit, such as the phase difference between the potential node in HP mode and the potential node in LP mode, and calibrate the LP circuit accordingly.

[0166] In some embodiments, the calibration results may be stored in the memory of test channels 1010, 1020. The correction values ​​may include amplitude gain or phase shift adjustments relative to the first calibration signal. The stored correction values ​​can then be applied during runtime to ensure accurate measurements at the DUT 1050.

[0167] The disclosed system can also support parallel testing modes. For example, the processor and system clock 1040 can configure test channels 1010, 1020, and additional channels to operate as high channels, low channels, or measurement channels based on the states of the HC and LC switches. Each channel can include a DDS, which can generate a test signal with a unique frequency or phase. By synchronizing with the system clock 1040, the test channels can simultaneously measure multiple pins of the DUT 1050.

[0168] In some embodiments, each test channel, such as 1010, 1020, may include a local processor or controller configured to perform an FFT operation on the digitized data from its VADC. By assigning different frequency offsets to the DDS waveform, the channel outputs can be isolated in the frequency space, thereby allowing the FFT module to isolate measurements of each channel even during simultaneous excitation of the DUT 1050.

[0169] Each DDS in test channels 1010 and 1020 may include a programmable phase shift register. The register can store a calibration offset unique to its corresponding channel. By applying the stored offset, the DDS waveforms across channels are aligned in phase, thereby ensuring synchronous measurements across the DUT 1050.

[0170] In some embodiments, each test channel 1010, 1020 may include channel processing circuitry, HC switches (1011, 1021), LC switches (1015, 1025), at least one potential node, and a DDS. Each channel may be configured to act as a high channel, a low channel, or a measurement channel. The DDS block may be configured to generate a test signal with a unique frequency or phase, calibrated to the system clock 1040. The channel processing circuitry may include a VADC, FFT, and memory, and may perform operations such as converting analog signals to digital signals, transforming time-domain signals to the frequency domain, or sending digital measurement data to a processor for analysis.

[0171] Reference Figure 11 The diagram illustrates a block diagram of an adaptable test channel 1100 according to an embodiment of the present invention. Channel 1100 interfaces with the device under test (DUT) via a +Sense conductor or line 1101 and a +Force conductor or line 1102 terminating at a pin interface 1103. Figure 11 As shown, in channel 1100, mode switch 1105 couples multiple instrument paths to a potential node within the component. This potential node, in turn, drives the + force conductor or line 1102 (and, in some embodiments, the accompanying sensing subnetwork in mode switch 1105 connects associated sensing leads to the + sensing conductor or line 1101 to maintain a Kelvin connection to the DUT).

[0172] Channel 1100 may include multiple instrumentation blocks: a source measurement unit (SMU) 1110, a capacitance measurement unit (CMU) 1120, a frequency measurement unit (FMU) 1130, a pulse IV unit 1140, and a pulse generator unit (PGU) 1150. In various embodiments, SMU 1110, CMU 1120, FMU 1130, and PGU 1150 may be collectively configured to provide measurement resources. Furthermore, PulseIV 1140 may be configured to provide pulse resources. For example, the measurement resources may have high-current (HC) and low-current (LC) switches to select the operating range, thereby establishing a high-potential (HP) or low-potential (LP) measurement mode at the potential node. In the illustrated example, CMU 1120 depicts selectable “high” and “low” paths that can implement HC and LC switching; in other embodiments, HC / LC selection may be distributed across the SMU, FMU, PGU, or a shared front end of the measurement resources.

[0173] Mode switch 1105 can enable selection of a multi-component network rather than a single device. As shown, mode switch 1105 may include independently controllable sub-switches 1112, 1122, 1132, 1142, and 1152 respectively located in the SMU, CMU, FMU, PulseIV, and PGU paths. Sub-switches may be relays, solid-state analog switches, cross-point structures, or combinations thereof, and may be grouped or interlocked to implement mutually exclusive selection. Sub-switch outputs converge at the potential node of mode switch 1105. In some embodiments, mode switch 1105 may also include break-before-make timing, bleed / clamp elements, or charge management networks to minimize transients during instrument switching.

[0174] In some implementations, when mode switch 1105 connects PulseIV 1140 (pulse resource) to the potential node, the potential node is configured to pulse test the DUT via +Force line 1102, while +Sense line 1101 monitors the pin potential. When mode switch 1105 connects the measurement resource to the potential node with HC switch closed, the potential node is configured for HP testing; when LC switch is closed, the potential node is configured for LP testing. Therefore, the mode switch determines whether the channel performs pulse generation or measurement, and the HC / LC selection within the measurement resource determines the potential range for that measurement.

[0175] Channel 1100 may represent one of multiple test channels coupled to a system clock. The system clock provides timing for synchronizing pulse test (transmission and measurement) events across channels. A controller or processor may issue timing and configuration strobe pulses to the sub-switches of mode switch 1105 and the HC / LC selection of measurement resources to achieve the disclosed operations, including rapid, deterministic reconfiguration between pulse measurements, HP measurements, and LP measurements at potential nodes, while maintaining Kelvin sensing and isolation from inactive resources.

[0176] In some embodiments, SMU 1110, CMU 1120, FMU 1130, and PGU 1150 collectively form a measurement resource selectable to the DUT, and PulseIV 1140 provides a pulse resource for delivering pulse excitation to the DUT. As an example, the SMU can force and measure voltages and / or currents for DC / parameter testing, the CMU can AC-biased excitation of the DUT to resolve capacitance / impedance for CV characterization, and the FMU can acquire frequency-domain quantities for a reference timing standard; the PGU can provide precise timing excitation for the measurement resource used in time-domain or frequency-domain measurements.

[0177] In some implementations, mode switch 1105 operates as a multi-component selection network rather than a single device. As shown, mode switch 1105 may include a set of independently controllable sub-switches, such as sub-switch 1112 aligned with the SMU path, sub-switch 1122 aligned with the CMU path, sub-switch 1132 aligned with the FMU path, sub-switch 1142 aligned with the PulseIV path, and sub-switch 1152 aligned with the PGU path. The outputs of the sub-switches converge to a potential node within mode switch 1105, which feeds in a +force wire 1102; in some embodiments, the accompanying sensing-side sub-network within mode switch 1105 also routes the sensing lead of the selected instrument to the +sensing line 1101 to maintain connection during measurement.

[0178] like Figure 11 As shown, CMU 1120 can internally present “high” and “low” paths (schematically shown) corresponding to high-range and low-range operating conditions; these paths can be embodied in high-current (HC) and low-current (LC) switches described elsewhere, allowing the system to be configured for high-potential (HP) or low-potential (LP) testing when mode switch 1105 connects the measurement resource to the node. When mode switch 1105 connects PulseIV 1140 to the potential node, the channel delivers a pulse waveform suitable for minimizing self-heating or capturing transient device behavior; examples of pulse IV techniques and pulse generator modules that can be used in these embodiments are well known in semiconductor parameter testing.

[0179] Figure 12 A block diagram of a resource card 1200 according to an embodiment of this disclosure is illustrated. Excitation and measurement functions can be implemented by a DDS 1220, a processor 1230, an SMU 1210, and a pulse daughterboard 1250. The DDS 1220 can be implemented as a four-channel direct digital synthesizer. The DDS 1220 can drive three high-speed front-ends, such as multiple VDACs, IADCs, and DDS units. A DDS path can be coupled to a frequency counter and a DAC for fine frequency or phase trimming.

[0180] As shown in the figure, the DDS output can be routed through nodes "P_Imeas" and "P_Vmeas", each of which can be selected using different switching elements and routed on the CMU line. In some embodiments, the CMU voltage path can be summed with the SMU line via a summing amplifier, and a bidirectional link can be connected to the pulse daughterboard 1250. The pulse daughterboard 1250 can provide four front panel connections that can route pulse drives, CMU virtual ground, CMU source drives, and CMU voltage or FMU measurements to the right-side I / O block identified as a probe card. The resource card 1200 can communicate with the chassis backplane, and the Sense Common can... Figure 12 The bottom provides a shared return reference.

[0181] The measurement path can be implemented using the SMU 1210. The SMU 1210 may include an IADC for high-resolution current capture, an IDAC as a precision current source, a VDAC as a precision voltage source, and a VADC for voltage measurement. A mode selector can switch between forced current and forced voltage, and a compensation loop can be closed around the output stage, while the measurement branch can sense the current.

[0182] Front-end connections may include force and sense connections to the probe card, a drive-and-guard (GND) to minimize leakage current, and a return-to-sense path with a large span (e.g., 100V to 0.5V). The processor 1230 is configurable with VDAC, IADC, VADC, FDAC, CMU, SMU units, and pulse daughterboard 1250, and can collect digitized data from the SMU 1210 for transmission via the chassis card slot.

[0183] like Figure 12 As shown, in some embodiments, the pulse daughterboard 1250 of resource card 1200 may expose discrete front panel connections, thereby allowing portions of the excitation / measurement chain to be isolated or used individually. This allows for the addition of external measurement paths or calibration modules without interfering with the core SMU circuitry.

[0184] exist Figure 12 In the CMU / AWG (Arbitrary Waveform Generator) path, separate measurement gating nodes (P_Imeas / P_Vmeas) and programmable gain amplifiers can improve control over which path is active and how to adjust that path.

[0185] Figure 13A schematic circuit diagram of a pulse daughterboard system 1300 according to an embodiment of the present invention is shown. In some embodiments, the pulse daughterboard system 1300 can be configured for pulse resources for each test channel and act as a pulse analyzer. Control and data plane functions can be partitioned between FPGA 1310 and pulse daughterboard 1320. Inside FPGA 1310, memory can store opcode sequences addressed by an opcode list at system clock using a pulse sequence generator. Sequence events can issue start / stop capture to the ADC, and the ADC results can be queued in the sample capture FIFO and transmitted to DDR. Analog observables from the daughterboard can be digitized by the ADC, while control waveforms or biases can be generated by the DAC and forwarded to the daughterboard.

[0186] On pulse daughterboard 1320, the DAC waveform can pass through a slew rate limiter before entering the source path. The high-voltage branch can include a programmable gain amplifier (PGA) and a selectable output range. Current range selection can guide the driver to the pulse IV path, where monitored nodes PIV Imaeas, PIV, and PIV Vmeas can be buffered for measurement. High-voltage feedback nodes HV Imaeas and HV Vmeas can return to the ADC in FPGA 1310 for closed-loop observation and averaging. Two logically distinct drivers can be provided on the output side. FPGA 1310 and pulse daughterboard 1320 can jointly generate a programmable pulse with a controlled slew rate, selectable voltage range, selectable current range, and real-time capture of voltage and current measurements at the high-voltage and pulse IV nodes. Furthermore, pulse daughterboard 1320 can include a high-speed switch located in the output stage to switch the drive path between the high-voltage pulse generation (HV-PG) branch and the pulse IV (PIV) branch. High-speed switches can be implemented using solid-state devices such as GaN or MOSFET-based driver networks capable of achieving fast switching times. When commanded by a control strobe pulse from the FPGA 1310, the switch rapidly connects or isolates the selected branch, enabling switching between voltage-driven and current-driven operation without external relays. In the HV-PG path, the high-speed switch applies a regulated high-voltage waveform generated by the PGA to the DUT pin, while in the PIV path, its output is routed via a precision current sensing and voltage measurement network for low-level pulse characterization. This configuration minimizes parasitic capacitance, maintains waveform fidelity during fast edge transitions, and allows for the delivery or measurement of precisely timed pulses with minimal distortion. As a result, the pulse daughterboard 1320 can generate tightly shaped pulses synchronized with the FPGA's sequencer timing, achieving high voltage accuracy and high-speed pulse control within the same hardware platform.

[0187] In some embodiments, control plane functions are performed by FPGA 1310, and analog excitation / measurement functions are performed by pulse daughterboard 1320. In such embodiments, within FPGA 1310, a step memory can store opcode sequences. An ADDR line provides addressing to the step memory, and a pulse sequencer can read the opcodes and issue control strobes at the system clock. In such embodiments, the sequencer can issue start / stop capture signals to the ADC processor / averaging block that performs per-pulse accumulation or averaging. Averaged samples are written to a sample capture FIFO (e.g., at 128K), and a DMA-to-DDR path streams the FIFO contents to system memory for host retrieval.

[0188] FPGA 1310 may also include a VI ADC (voltage / current acquisition ADC) and a DAC. The VI ADC digitizes the analog observables returned from daughterboard 1320 (described below) and provides those samples to the ADC processor / averaging block. The DAC generates an analog control / bias waveform that leaves FPGA 1310 and enters pulse daughterboard 1320 as a drive / control input to the excitation chain.

[0189] Furthermore, as previously mentioned, in some embodiments on the pulse daughterboard 1320, the DAC drive from the FPGA 1310 can be configured to first pass through a slew rate limiter, thereby shaping its edges before entering the analog front end. Additionally, in the high-voltage branch, the drive can be applied to a PGA (Programmable Gain Amplifier), whose gain is digitally set to match the desired output range. PGAs are typically used to extend dynamic range and maintain signal-to-noise ratio performance in the instrument front end.

[0190] Furthermore, in some embodiments, the board system 1300 may provide three buffered, individually routeable measurement nodes: PIV Imeas (pulse-IV current measurements), PIV ohm (measurements across a defined sensing path), and PIV Vmeas (pulse-IV voltage measurements). Additionally, a second PGA can be configured to regulate this branch, allowing the same VIADC in the FPGA 1310 to accurately digitize PIV observables over a wide dynamic range. The multiplexer notation at each measurement cluster indicates that, under pulse sequence generator control, any of the listed nodes can be selected to the VI-ADC return line. Solid-state analog switches / multiplexers are a standard way to route such analog measurement paths.

[0191] In some embodiments, the FPGA 1310 may include a high-speed pulse sequence generator that executes an opcode / operand program to control waveform synthesis. A sequencer operating from a step-memory under the system clock can decode opcodes with associated operands. By writing operand-defined data values ​​to the DAC at defined update intervals, the sequencer generates complex repetitive waveforms, such as stepped waves, ramps, pulse trains, multi-stage pedestal plus pulse patterns, or arbitrary sequences. The opcode stream can select lines for HV-PG or PulseIV paths, enabling coordinated switching and waveform shaping without firmware latency. The opcode stream can also schedule data acquisition. Capture-related opcodes assert start / stop gating, define sampling windows, and specify the number M of samples M directly acquired from the VI ADC during a given waveform interval (e.g., a pulse flat-top).

[0192] Furthermore, the on-FPGA averaging engine accumulates M samples to calculate the average (and optionally local difference or baseline subtraction), producing decimated, low-noise measurements aligned with the programmed waveform timing. The averaging result is written to a sample capture FIFO for DMA transfer, while an optional mode allows for raw sample streaming. Performing timing, sampling, and averaging entirely within the FPGA reduces host bandwidth, improves SNR, and maintains phase coherence alignment between excitation and measurement.

[0193] In some embodiments, the pulse subboard 1320 can be configured as a pulse resource and may include a first branch (e.g., Figure 13 The top branch), the second branch (e.g., Figure 13 The bottom branch) and the high-speed output switch coupled to both branches (e.g., Figure 13(High-speed switch in the FPGA). After edge shaping by the slew rate limiter, a common drive input to the pulse resource can be provided by the DAC path from the FPGA1310. The first branch can implement a voltage-oriented pulse generation path (HV-PG) and can include a pulse generator configured to synthesize a time-varying waveform from the DAC input, a programmable gain amplifier (PGA) to scale the waveform to an selectable output range, and a first branch switch located downstream of the PGA. The pulse generator can include a driver stage and associated conditioning networks configured to provide fast edge transitions with a controlled slew rate indicated by an opcode-scheduled DAC update, and the PGA can be digitally configured to maintain signal-to-noise ratio performance across multiple high voltage spans. The first branch switch can be implemented as a solid-state analog gated element (e.g., a back-to-back MOSFET or GaN device) that operates under pulse sequencer control to isolate the HV-PG path during the off interval, thereby pre-charging or maintaining a defined output potential and mitigating charge injection to downstream loads. A high-speed output switch, implemented using low parasitic, fast conversion devices, can be coupled to the output node of the first branch and arranged to selectively connect or isolate the node to the pin of the device under test (DUT), thereby directing conditioned high-voltage pulses to the DUT with minimal parasitic capacitance and preserved waveform fidelity.

[0194] The second branch can implement the pulse IV characterization path and may include circuitry for pulse current and voltage measurements, as well as a second branch switch for gating the measurement path. The measurement circuitry may include a precision current sensing element and a transimpedance / buffer stage to generate pulse current measurement signals (PIV Imeas), and a Kelvin reference voltage tap arranged to provide pulse voltage measurement signals (PIV Vmeas), and in some implementations, a defined resistance observation branch (e.g., a PIV ohm path) for calibration or range extension.

[0195] One or more conditioning amplifiers (which may include a PGA dedicated to the PulseIV path) can scale the sensed signal, enabling the VI ADC on the FPGA 1310 to be accurately digitized over a wide dynamic range. Multiplexer elements can be provided to route any selected measurement node (e.g., PIV Imeas, PIV Vmeas, or ohmic reference) back to the VI-ADC return for synchronous averaging under sequencer control. A second branch switch can be positioned between the excitation node and the PIV network to define a sampling window with sub-microsecond accuracy, protecting the measurement amplifier during high-energy events and reducing settling time by decoupling stray capacitances outside the effective interval. During operation, the pulse sequencer can coordinate the first branch switch, the second branch switch, and the high-speed output switch, allowing pulse resources to alternate in a time-deterministic manner between a voltage-driven mode that delivers the shaped HV-PG waveform to the DUT and a pulse-IV mode that routes the excitation through the current-sensing and voltage-sensing networks for acquisition, thereby achieving high-precision delivery and capture within a single hardware platform.

[0196] In some embodiments, the pulse resource includes a digital-to-analog converter (e.g., a DAC driven by FPGA 1310) fanning out to multiple programmable gain amplifiers on the pulse daughterboard 1320, wherein the PGA output can be selected by a high-speed switch located in the output stage. Alternatively, the pulse resource may include an analog-to-digital converter (VI ADC) for voltage / current coupled to a measurement buffer. For example, the DAC output may simultaneously drive a first PGA in the high-voltage pulse generation (HV-PG) branch and a second PGA in the PulseIV branch, with the high-speed switch directing the selected PGA output to a DUT pin to achieve the output range. The VI ADC can be coupled to a buffer network that includes, for example: (a) a unity-gain voltage follower isolating the Kelvin tap voltage nodes (HV Vmeas, PIV Vmeas) from the ADC sampling kickback; (b) a transimpedance amplifier (TIA) current buffer that converts the sensed current into a voltage for the PIV Imeas path and supports optional feedback elements for range scaling; and (c) an instrumentation amplifier or differential buffer that receives high-voltage feedback conditioned by a voltage divider for the HVI memeas path. In one configuration, the HV measurement option can use a resistive voltage divider with a high-voltage buffer entering the VI ADC to report HV Vmeas, while a current sensing element with a TIA provides HV Imeas. In another configuration, the PulseIV option, selectable by an on-board multiplexer, includes PIV Imeas (via a TIA buffer for low-level pulse current), PIV Vmeas, and an optional PIV 50-ohm branch for high-bandwidth measurements for calibration. These buffered measurement paths provide low source impedance to the VI ADC, reducing settling time during window sampling and allowing the controller to select among HV, PIV, and Imeas observables, while high-speed switching simultaneously selects the desired PGA-conditioned drive, thus supporting the architecture requiring protection.

[0197] Figure 14 A block diagram of an FMU reciprocal mode 1400 according to an embodiment of this disclosure is shown. Frequency and period measurements can be supervised by a microprocessor 1410, which calculates the frequency from timing data fed from a downstream counter. Edge timing from the device under test can be acquired by a VADC via a range selector that can switch between "ForceIV + Sense" and "ForceIV + Sense". A digitized stream can be applied to a frequency counter and a comparator whose reference can be set by an FDAC to establish an adjustable detection threshold.

[0198] The comparator edge can drive the cycle counter 1440 and also feed a signal to the gating logic 1430. The counter 1450 can provide a time base, and the digital threshold 1460 can accept a user-specified resolution, allowing counting to continue for a known number of DUT cycles. The gating logic 1430 can perform actions such as "stop at the next DUT edge after the digital threshold," thereby closing the measurement window and asserting capture after a user-defined cycle.

[0199] The cycle calculator 1420 can then use the counter value to determine the number of DUT cycles with known elapsed time, and the microprocessor 1410 can calculate the corresponding frequency. This arrangement can support input frequency while allowing threshold control and input range (e.g., selectable via + / -5V and / or + / -10V). However, other options are also possible and within the scope of the disclosed embodiments.

[0200] like Figure 14 As shown, in some embodiments, the DUT signal can be range-selectable (e.g., “±5V ForceIV+Sense” or “±10V ForceIV+Sense”) and routed in parallel to the VADC and a comparator whose transition point is set by the FDAC. The comparator can be configured to produce clean timing edges for counting; in some implementations, a small hysteresis window can be used to suppress noise-induced jitter and improve edge time repeatability.

[0201] Edges from a comparator or counter can be used to drive cycle counter 1440 and gating logic 1430. Counter 1450 can provide a time base, while digital threshold 1460 can accept user-selected timing. Gating logic 1430 can be configured to stop at the next DUT edge after the digital threshold, thus the window precisely spans the user-configured number of cycles.

[0202] Figure 14 The arrangement shown can have adjustable frequency and input via FDAC, range selection for the front end, and resolution limited by the time base. The parallel VADC path can also archive waveform snapshots for diagnostic or adaptive threshold setting, while overall accuracy benefits from a low jitter time base and clock (because sampling / clock jitter directly reduces high-speed measurement SNR and timing accuracy).

[0203] Figure 15 A measurement path 1500 of the CMU according to an embodiment of the present disclosure is shown.

[0204] The CMU 1510 can be contacted with the DUT 1520 using four terminals such as "Lc", "Lp", "Hp", and "Hc". The CMU 1510 can provide an AC excitation source, a voltmeter V, an ammeter A, and a high input impedance amplifier, allowing excitation to be applied to "Hp" and returned to "Hc", while simultaneously sensing the voltage across "Lp" and "Lc" to achieve four-terminal measurements of the DUT 1520.

[0205] exist Figure 15 In the diagram, CH1 can represent test channel 1530, and CH2 can represent test channel 1540. Test channel 1530 can be assigned as a low-side AC current measurement channel, denoted by A. Test channel 1540 can be assigned as a high-side source with voltage sensing, represented by V and a sinusoidal source, and "Hp + Hc" indicates the driven high node and its protected return. The channels can be connected to the same capacitors of the DUT 1520, indicating that any channel in the multi-channel system can be configured as source-side or current measurement-side to simulate the classic CMU four-terminal method. Therefore, this diagram does indeed correspond to the previously described multi-channel system and shows how a device under test can be measured without a single shared LCR meter while still maintaining four-wire accuracy.

[0206] In addition, such as Figure 15 As shown, in the four-terminal pair topology on the left, the CMU 1510 applies an AC excitation between Hp (high potential) and Hc (high current / return), senses the voltage between Lp (low potential) and Lc (low current), and measures the current in the Hc / Lc path. This can be implemented with an automatic balancing bridge: the ammeter is positioned in the low current return, the high impedance voltmeter senses Hp--Lp, and the drive clamp is protected / shielded to minimize stray admittance. Proper allocation and routing of Hc / Hp / Lp / Lc is standard practice for accurate CV / impedance operation.

[0207] Figure 15 The chuck-to-ground capacitance from the wafer chuck associated with Hc is also shown. In wafer probing, parasitics can shunt the measurement current unless protected or compensated; therefore, four-wire sensing and drive protection practices are applied, and open / short circuit (and, where applicable, load) compensation is performed at the clamp to remove residual cable / clamp errors.

[0208] Test channels 1530 and 1540 illustrate how the disclosed system can be configured to simulate CMU measurements: CH2 is configured for source + high-side voltage sensing (symbol V with a sine wave, "Hp + Hc / guard"), while CH1 is configured as a low-side current measurement channel (symbol A). Both channels are connected to the same DUT capacitor 1520, allowing current to be measured in the low return path while simultaneously sensing the voltage across individual potential leads, thus maintaining four-wire accuracy without a single shared LCR instrument. This arrangement implements the same four-terminal sensing principle used in precision impedance meters.

[0209] Figure 16 A block diagram 1600 of a CMU circuit configuration according to an embodiment of the present disclosure is shown. Programmable routing and amplification networks can establish relationships between measurement nodes, source nodes, and protection nodes in a multi-channel system. Inputs “AC_SENSE,” “SMU_DC,” and “CMU_AC” can enter a buffer chain. This path may include series elements (e.g., 50 ohms) and selectable switches SW6, SW5, SW4, and SW1, which can be implemented as MEMS or opto-MOS relays. The selectable switches can be dedicated to different potentials. For example, SW5 can be a high-side switch while SW2 can be a low-side switch. In one embodiment, SW5 (HP_SW5_in) resides in the high-potential branch, while SW2 (LP_SW2_in) resides in the low-potential branch; SW6 inserts a series element (e.g., 50Ω) for damping / protection, and SW1 provides output isolation to CMU_OUT during reconfiguration. Control is interlocked, so the HP and LP branches cannot be closed simultaneously, and a break-before-make sequence (with optional discharge / clamping) manages charge injection. When the LP branch is selected, the AC_GUARD driver follows the measurement node to suppress leakage current and stray capacitance. HP-rated switches prioritize withstand voltage and surge capability, while LP switches use ultra-low leakage current devices to maintain femtoampere-level accuracy.

[0210] Furthermore, programmable resistor networks and shunt nodes can be connected and their ranges and biases can be set. Similarly, switching blocks can be implemented using MEMS and / or opto-MOS relays, including combinations thereof. With these options, signals can be directed to output "CMU_OUT" for capacitance or other AC measurements.

[0211] In some embodiments, the CMU may use a high-speed operational amplifier configured as a buffer, followed by a coupling network that connects to different operational amplifiers configured for high-speed amplification. Furthermore, by switching SW4, SW5, and SW6, the system can change the gain and range while coordinating with the left-side measurement shunt network to maintain accuracy.

[0212] Furthermore, the CMU can set the effective gain and impedance using operational amplifiers configured for buffering and selectable resistor ladders. Cascaded operational amplifier stages can provide drive strength and stability, and can produce a protection output "AC_GUARD".

[0213] In combination, the operational amplifier and switches can provide flexible mixing between “AC_SENSE”, “SMU_DC” and “CMU_AC”, and can expose three key endpoints “CMU_OUT”, “CMU_SRC_MV” and “AC_GUARD”.

[0214] In some embodiments, inputs AC_SENSE, SMU_DC, and CMU_AC can be configured to enter a high-impedance buffer chain led by a FET input and a wideband operational amplifier to minimize the load on the high-impedance nodes. Downstream, selectable switches SW6, SW5, SW4, and SW1 can establish which source or sensing path is active and isolate inactive paths without contact bounce. Furthermore, in such embodiments, a programmable shunt / bias network can be configured to dynamically set the input range or DC bias during AC measurements.

[0215] In some embodiments, switch states SW4-SW6 can be selected to a gain / range combination coordinated with the left-side shunt network, ensuring that effective transconductance and voltage compliance remain within calibration across all ranges. Operational amplifiers can be used to implement this functionality, supporting multi-MHz excitation with a stable loop response under capacitive loads on the DUT and cables.

[0216] In some embodiments, a low-noise broadband buffer can be configured to feed an optional resistor ladder (e.g., 160 kΩ, 160 Ω, 1.6 kΩ, 16 kΩ) to protect the amplifier pair and set the effective gain / impedance. The output can be actively driven to track the potential of adjacent high nodes, thereby reducing leakage current and effective stray capacitance from cables, probe cards, and wafer chucks to ground.

[0217] In some implementations... Figure 16 The circuitry within can be used to select the input (AC_SENSE, SMU_DC, or CMU_AC), assert SW1-SW6 to configure the range and path, bias the nodes with a 100 MΩ / 100 kΩ network as needed, drive CMU_SRC_MV with a programmed excitation, and set the guard gain / filter so that AC_GUARD tracks the source node. Then, the measurement front end acquires CMU_OUT while monitoring the taps to verify excitation integrity.

[0218] Figure 17A block diagram of a circuit 1700 having a measurement unit 1710 with a TIA 1730 according to an embodiment of the present disclosure is shown. As previously mentioned... Figure 10-16 The front-end buffer 1711 discussed can present a high-impedance input, and the optional switch 1713 can shunt or bypass the input to establish a reference or protection path before the signal reaches the transimpedance amplifier TIA 1730.

[0219] The TIA 1730 enables precise current-to-voltage conversion. The operational amplifier in the 1730 can be configured with a feedback impedance to set the transimpedance gain, and the inverting node forms the summing point connected to the output of the measurement unit 1710. A protection or bootstrap buffer 1731 drives surrounding shielding or auxiliary nodes, reducing leakage current and stray capacitance at the summing node. A range selection switch 1735 allows insertion or removal of feedback elements to alter the TIA's effective gain or bandwidth. An output enable switch 1737 couples the regulated voltage to a downstream bus or converter, while a bypass switch 1739 routes the pre-regulated input directly to the output path when voltage sensing, rather than current sensing, is required.

[0220] In some embodiments, the measurement unit 1710 may be configured to regulate the current or voltage from the DUT and present it to the transimpedance stage. The front-end buffer 1711 may be configured as a high-input-impedance amplifier to minimize the load on the picoampere source; suitable devices include an electrometer amplifier with an integrated protection driver. An optional path with switch 1713 provides input protection and mode setting, such as a low-leakage-current relay or PhotoMOS, which can shunt the node to a reference during range changes, connect clamping elements, or short-circuit the input for zero / offset calibration before engaging the transimpedance path. A low-capacitance relay is advantageous here.

[0221] In some embodiments, the transimpedance amplifier 1730 may use an operational amplifier with a feedback impedance (Rf / / Cf) selected by a range selection switch 1735 to convert the input current to a voltage. For example, the switch 1735 may be selected between Rf values ​​(e.g., from 1 kΩ to 1 GΩ) using a parallel compensation capacitor. The inverting input of 1730 forms the summation point connected to the output of the measurement unit 1710; the non-inverting input may be referenced to a quiet analog ground or a programmable bias for offset.

[0222] In some embodiments, buffer 1731 can be configured as a protection / bootstrap buffer to drive surrounding shielding (e.g., PCB guard ring or coaxial cable protection) at approximately the same potential as the summing node, so that leakage current and parasitic capacitance from the board, socket, or cable do not shunt current from the DUT. In one embodiment, buffer 1731 may be an amplifier with integrated protection buffer or a dedicated unity-gain stage with protection planes and loops around the input of driver 1730; this layout may employ continuous guard rings, protection vias, and isolation zones around the inverting node to suppress leakage current.

[0223] The regulated output of TIA 1730 is routed to downstream circuitry, such as filters and ADC drivers, via output enable switch 1737. Furthermore, the control of 1713, 1735, 1737, and 1739 allows for several modes: (i) a high-sensitivity current mode using a large Rf and a small Cf for leakage current / photocurrent measurement; (ii) a wideband current mode selecting a smaller Rf and a larger Cf for higher-speed excitation; and (iii) a voltage mode that turns on switch 1739 and disables TIA 1730. Range switching can be implemented using a low-leakage-current relay.

[0224] Through coordinated control of 1713, 1735, 1737, and 1739, circuit 1700 can operate in multiple modes, including a high-sensitivity current measurement mode using the TIA 1730 and a through-voltage measurement mode using a bypass path. Buffer 1731, together with the optional feedback network in 1735, protects the front end and stabilizes the summing node.

[0225] Figure 18 A schematic circuit 1800 is shown for test channels 1810, 1830 of a multi-channel parallel device test system according to an embodiment of the present disclosure. Figure 18 As shown, the upper test channel 1810 and the lower test channel 1830 can be used in a multi-channel parallel device test system 100, wherein the multi-channel parallel device test system 100 can be connected to multiple DUTs via force lines 1850 and sensing lines 1870.

[0226] In some embodiments, circuit 1800 can be implemented using a dual-path test channel architecture having an upper test channel 1810 and a lower test channel 1830 terminating at a configurable switching block. The switch can be configured to connect independently selectable nodes to the device interface: force line 1850 and sensing line 1870.

[0227] In some embodiments, a given channel can be configured as a “high” channel (HC and HP closed) or a “low” channel (LC and LP closed) by means of an actuation switch, thereby enabling a Kelvin four-terminal connection in which current is forced onto a pair of lines while a voltage is sensed on the separate high-impedance pair to minimize lead voltage drop error.

[0228] The upper test channel 1810 may include an AC / DC source driver (upper left operational amplifier triangle) that feeds the switching block through a series resistor (shown in series) that provides current limiting, damping, and cable matching when the DUT is driven via force line 1850. A second amplifier may be configured to provide the high potential (HP) voltage sensing. When HP is selected, this node can be routed to the sensing line. In one embodiment, the driver may be configured as a wideband operational amplifier to provide DC or AC excitation.

[0229] The lower test channel 1830 can be configured to measure low-potential sensing. Alternatively, the lower test channel 1830 can be configured to provide complementary measurements. In the lower test channel 1830, an amplifier senses the current returning from the switching block; a symbolic resistor grounded represents the transimpedance- or shunt-based conversion of the DUT current to voltage for digitization. The amplifier can provide a low-potential voltage sensing lead. However, when the switch is selected as LC (for force) and LP (for sensing), the channel acts as a low-side measurement branch: measuring the current in the return while sensing a voltage with high impedance at the low-potential node, thus enabling accurate impedance / CV measurements even in the presence of series lead resistance and chuck-to-ground parasitic effects. Transimpedance conversion and protection techniques are commonly used for picoampere to milliampere AC measurements.

[0230] exist Figure 18 In this setup, the switches (shown as dashed lines) can be implemented using low-leakage-current analog switching elements (e.g., PhotoMOS or MEMS relays) selected to isolate inactive paths. In operation, any two channels in the multi-channel system can be paired: one configured as HC+HP to act as the drive source / sensing branch, and the other as LC+LP to act as the current measurement / low-sensing branch, thus simulating a classic LCR / CMU four-terminal setup without a single shared instrument. Channel roles can be reassigned under program control to test multiple DUT pins in parallel.

[0231] During measurement, when HC is closed, the AC / DC source in the upper test channel 1810 can drive the DUT through force line 1850; simultaneously, HP reports the terminal voltage applied on the sensing line 1870. When LC is closed, the DUT return current flows back to the AC current measurement stage through the lower path, and LP reports a low-potential terminal voltage.

[0232] Figure 19 A schematic circuit 1900 is shown for test channels 1910, 1930 of a multichannel parallel device test system 100 for a high-impedance DUT according to an embodiment of the present disclosure. Figure 19 A streamlined design optimized for high-impedance DUTs is described, which uses two-wire connections and omits unnecessary Kelvin separation.

[0233] exist Figure 19 In this configuration, a single force / sensing line in test channel 1910, driven by a compact channel switch, is connected to the DUT, instead of a switch with independent poles. The DUT is chosen to be bonded to either upper test channel 1810 or lower test channel 1830 as a two-wire connection. Kelvin separation can be intentionally omitted because the DUT impedance is large enough that the lead / contact resistance is negligible relative to the measured value.

[0234] Functionally, test channel 1810 can hold an AC / DC source driver (with series damping) and an HP monitor, while test channel 1830 can hold an LP monitor and an AC current measurement stage. Both HP and LP are routed to separate high-impedance sensing poles. Figure 18 different, Figure 19 The two voltage monitors in the circuit observe the same selected node at the channel selection output, so either branch can be sourced / measured without a separate sensing lead. The AC current stage continues to sense the return current for impedance / CV extraction; however, because only one external conductor is used for application and sensing, the reading reflects the DUT plus any small lead-in series elements (acceptable under high impedance conditions). This streamlining reduces the number of switches and associated leakage current / capacitance, which is advantageous when measuring very high impedances or small capacitances.

[0235] Some embodiments may combine circuits 1800 and 1900. Figure 18 The circuit 1800 can be configured as a four-terminal option for use when accuracy will be limited by lead resistance or contact voltage drop (separating HC / LC force and HP / LP sensing to force Kelvin), while Figure 19 It can be a two-terminal option used when the DUT impedance is high and a simpler topology improves throughput and minimizes parasitic effects.

[0236] In respectively Figure 18 and Figure 19 The circuits 1800 and 1900 shown can improve alternative systems using a single LCR meter. Figure 18 and Figure 19The multi-channel parallel device test system 100 with circuits 1800 and 1900 shown can measure multiple DUTs simultaneously because any test channel 1810, 1830, 1910, or 1930 can act as an LCR meter and can measure all test channels simultaneously.

[0237] Figure 20 A block diagram 2000 is shown illustrating a system having multiple test channels according to an embodiment of the present disclosure for a multi-channel parallel device test system. As shown in block diagram 2000, the system may include multiple test channels, which may be configured to have dual switches for upper test channels and lower test channels, such as in combination. Figure 18 The subject of discussion.

[0238] Figure 20 A scalable, per-channel LCR topology is described, which reflects Figure 18 The architecture is a dual-path design, but it is replicated across many channels. Four representative test channels, 2010, 2020, 2030, and 2040, are explicitly shown, with the additional channel 20x0 indicating continuation. Each test channel can integrate an LCR block, which provides four internal terminals: HC (high current force), LC (low current force / return), HP (high potential sensing), and LP (low potential sensing). These four nodes can implement a four-terminal topology within each channel, such that current is applied to a pair of lines while voltage is sensed on a separate high-impedance pair.

[0239] For example, in test channel 2010, four LCR nodes feed to a polarity switching module (shown in dashed outline), which presents dedicated force lines 2011 and sense lines 2013 to the probe station interface. The same structure is repeated for test channel 2020 with force lines 2021 and sense lines 2023, test channel 2030 with force lines 2031 and sense lines 2033, and test channel 2040 with force lines 2041 and sense lines 2043. In each instance, a switch selects which internal nodes (HC relative to LC, HP relative to LP) appear on the external force and sense conductors, thus allowing the channel to operate as either the high branch (HC+HP) or the low branch (LC+LP) of the four-terminal pair, as shown below. Figure 18 As described in the document. The additional channel 20x0 indicates that the same scheme extends to additional channels, each with its own force line 20x1 and sensing line 20x3.

[0240] During runtime, the controller programs each channel switch so that any channel can be used as a drive source / sensing branch (HC+HP) or a return / current measurement branch (LC+LP). Because each channel exposes its own force and sensing output (2011 / 2013, 2021 / 2023, 2031 / 2033, 2041 / 2043, 20x1 / 20x3), multiple DUT pins or multiple DUTs can be excited and measured in parallel, with each site maintaining true four-terminal accuracy. This "per-pin resource" type (one measurement resource per contact pin) is a recognized way to improve parallelism and eliminate long switching matrix paths that increase leakage current and capacitance.

[0241] Figure 20 This illustrates how the system scales: the left-hand LCR block in each channel generates AC excitation and performs voltage / current sensing; the dashed two-pole switches assign four internal nodes (HC / LC / HP / LP) to the force and sensing conductors specific to that channel; the conductors (2011 / 2013, 2021 / 2023, 2031 / 2033, 2041 / 2043, 20x1 / 20x3) are directly routed to the probe card. By combining four-terminal sensing at the channel with per-pin fan-out, this architecture achieves accurate impedance / CV results while supporting high throughput, multi-site testing—an approach consistent with best practices for Kelvin sensing and drive protection measurements in precision LCR operations.

[0242] Figure 21 A block diagram 2100 is shown illustrating a system having multiple test channels according to an embodiment of the present disclosure for a multi-channel parallel device test system. As shown in block diagram 2100, the system may include multiple test channels, which may be configured with compact switches for upper and lower test channels, such as in combination with... Figure 19 The discussion.

[0243] Figure 21 It shows from Figure 19 The two-wire configuration derives a multi-channel topology. Five representative channels are shown—test channels 2110, 2120, 2130, 2140, and 21x0. Each channel may include an LCR block exposing four internal nodes HC, HP, LP, and LC, but only the HP and LP nodes are forward-routed to a compact channel selection switch. The switch selects HP or LP to a single external conductor force line 2115, 2125, 2135, 2145, or 21x5 (one per channel). Figure 19 As shown, this achieves a two-wire, high-impedance connection where the same conductor carries the force and sensing functions used for the channel—appropriate when the DUT impedance is large enough that the lead / contact resistance is negligible compared to the measured value.

[0244] The per-channel HP / LP selection allows each point to be coupled to either the "high" branch (reference HP) or the "low" branch (reference LP) without requiring a separate Kelvin sense return. Internally, the LCR block can still use the channel's own voltage and current monitors to measure excitation and response, but the external cable can be reduced to a single force line per point. Relative to Figure 20 , Figure 21 The arrangement can reduce the number of cables and switching poles, reduce clamp capacitance / leakage current, and improve the practicality of high-Z components or structures with sufficient dual-wire accuracy.

[0245] Figure 21 The dashed channel selection switches in the diagram can be implemented using solid-state relays (e.g., PhotoMOS) or MEMS relays to maintain picoampere-level turn-off current and low parasitic capacitance at each point. These devices provide bounce-free operation and stable on-resistance throughout their lifespan, making them ideal for multiplexing high-impedance measurements without disrupting readings.

[0246] During operation, the controller programs the switch of each channel to connect the HP or LP to its force line, applies the desired AC / DC excitation from the LCR block, and internally acquires the voltage / current of each channel. Because only one conductor is brought out at each site, the wiring density on the probe card is increased, and the coupling between sites is reduced.

[0247] Figure 22 An alternative test system 2200 according to an embodiment of this disclosure is shown. Figure 22 In this configuration, a test channel 2210 can be coupled to multiple sensors and force lines using a high multiplexer 2230 and a low multiplexer 2250.

[0248] like Figure 22 As shown, in test system 2200, a single test channel 2210 exposes four nodes HC, HP, LP, and LC to high multiplexer 2230 and low multiplexer 2250. High multiplexer 2230 fans out the HC / HP pair to a set of external lines, labeled CH1 force lines 2221 to 2225 (plus extension port CHx force line 222x, indicating that additional force lines can be added) and CH1 sense lines 2231 to 2235 (plus CHx sense line 223x, indicating that additional sense lines can be included). Low multiplexer 2250 similarly fans out the LC / LP pair to CH1 force lines 2241 to 2245 (plus CHx force line 224x) and CH1 sense lines 2251 to CH5 sense lines 2255 (plus CHx sense line 225x).

[0249] In some embodiments, a selection is made in the high multiplexer 2230 and a selection is made in the low multiplexer 2250 such that the high (HC / HP) and low (LC / LP) terminals of the instrument are routed to the same DUT site, thereby maintaining a true four-terminal pair (4TP) connection. The 4TP scheme separates the force and sensing paths to eliminate lead voltage drop and is standard practice for precision LCR / impedance measurements.

[0250] Furthermore, in some embodiments, any one DUT site from the high group and one DUT site from the low group are selected because each pin can be configured independently. For example, the controller can sequence the two multiplexers such that, for measuring site 3, the system closes the HC→CH3 force line 2223 and HP→CH3 sensing line 2233 paths in the high multiplexer 2230, while simultaneously closing the LC→CH3 force line 2243 and LP→CH3 sensing line 2253 paths in the low multiplexer 2250.

[0251] Figure 22 The line groups in the diagram represent the scan topology. For example, CH1-CH5 force lines 2221-2225 (and 2241-2245) can be configured to carry current-forced terminals for the selected high and low branches, respectively; CH1-CH5 sensing lines 2231-2235 (and 2251-2255) carry the corresponding high-impedance voltage sensing returns. Extended identifiers 222x / 223x / 224x / 225x indicate that additional sites can be added in the same manner without altering test channel 2210.

[0252] Figure 23 An alternative test system 2300 for a high-impedance DUT according to an embodiment of this disclosure is shown. Alternative test systems 2200 and 2300 can use a single LCR meter multiplexed to any two pins. One pin receives the high-side AC source, while the other pin receives the low-side AC current measurement.

[0253] In test system 2300, the HC / HP and LC / LP of a single test channel 2310 (LCR) are shorted and routed. HC / HP is fed to high multiplexer 2330, which fans out to CH1 force line 2331, CH2 force line 2332, CH3 force line 2333, CH4 force line 2334, CH5 force line 2335, and extended output CHx force line 233x. Simultaneously, LC / LP is fed to low multiplexer 2350, which fans out to CH1 force line 2351, CH2 force line 2352, CH3 force line 2353, CH4 force line 2354, CH5 force line 2355, and CHx force line 235x (representing any number of force lines). During measurement, the controller closes one path in 2330 and one path in 2350, causing HC and LC to fall on the same position number, establishing a two-wire drive / measurement connection to the DUT pin.

[0254] In addition, such as Figure 23 As shown, the two multiplexers (2330 and 2350) are configured without a separate HP / LP sensor. Figure 22 In the middle, each side (high and low) has two groups (one for force and one for sensing) to maintain a four-terminal connection. Figure 23 By omitting two routes and relying instead on two lines, one advantage is the significant reduction in switching paths and connectors, which reduces additional leakage current and parasitic capacitance from the matrix and harness, speeds up scanning (fewer contacts need to be driven), and lowers cost / size—particularly beneficial for high-impedance DUTs where two lines are sufficiently accurate.

[0255] Figure 23 This configuration can be used in applications where the DUT impedance is relatively large compared to the lead resistance (e.g., high-Z components or structures), while Figure 22 The configuration can be selected for higher accuracy. In some embodiments, the multiplexers 2330 / 2350 are implemented with break-before-make low-leakage-current switching devices, such that only one point is connected per group during switching, and no two points are momentarily shorted. The use of solid-state relays with low C×R and low off-state leakage current maintains the accuracy of the high impedance source and sustains the bandwidth of the AC measurement. The CHx indicators (233x, 235x) indicate that additional points can be added without changing the test channel 2310, thereby allowing time-division multiplexed two-wire measurements across multiple DUT pins using a single precision LCR resource.

[0256] Figure 22 and Figure 23 The LCR meter of the alternative system shown can be multiplexed up to 24 times per pin pair in a single measurement. By using... Figure 18 and Figure 19 The circuit shown and Figure 20 and Figure 21 The multi-channel test system shown allows for faster measurements than a single LCR meter multiplexed. Therefore, the multi-channel parallel device test system 100 can provide faster test times, and faster test times can lead to lower test costs per DUT.

[0257] Figure 24 A schematic circuit 2400 for measuring the CV characteristics of a MOSFET on a wafer, according to an embodiment of the present disclosure, is shown, wherein a multi-channel parallel device test system 100 is mounted. Figure 24 As shown, the test channels may include a first test channel CH1, a second test channel CH2, a third test channel CH3, and a fourth test channel CH4. The multi-channel parallel device test system 100 can be configured to set the potential nodes of the first test channel CH1, the second test channel CH2, and the third test channel CH3 as a first dynamic potential. The multi-channel parallel device test system 100 can also set the potential node of the fourth test channel CH4 as a second dynamic potential. The second dynamic potential differs from the first dynamic potential. The multi-channel parallel device test system 100 can perform capacitance-voltage analysis by applying a voltage and measuring the capacitance as a function of the first and second dynamic potentials.

[0258] exist Figure 24 In the diagram, three high test channels, test channel 2470 (HC1 / HP1), test channel 2450 (HC2 / HP2), and test channel 2430 (HC3 / HP3), are routed to the DUT, which can be the D, B, and S terminals of a MOSFET 2490. The low test channel 2410 (node ​​LP / LC) is routed to the G terminal of the MOSFET 2490 to provide low-side reference and measurement return. The waveform plotted on the right shows that the three high channels can be driven with the same AC / DC excitation (equal amplitude, DC offset, frequency, and phase), while the gate is biased / scanned by the low channel to achieve CV measurement of the gate pair (D, S, B). This arrangement can be a functional equivalent of connecting the drain / source / body together and measuring the gate, i.e., standard MOSFET / MOS capacitor CV technology.

[0259] To achieve Figure 24 The three synchronous high-side drivers shown can have benefits such as each terminal being driven through its own calibration path, allowing for protection and leakage current control for each terminal; the drivers remain phase-locked, so D, S, and B track together, simulating the connection node conditions used in MOS CV practice; and the architecture can optionally introduce intentional known offsets (phase or DC) for advanced methods, such as split CV or body bias studies, without rewiring.

[0260] Test channels 2470 / 2450 / 2430 provide forced nodes (HCx) and high-impedance sensing nodes (HPx) to the DUT terminals (D / B / S), while test channel 2410 provides return (LC) and low-potential sensing (LP) to the G terminal. Three sinusoidal traces emphasize that HC1 / HC2 / HC3 are equal in amplitude, offset, frequency, and phase, while the gate bias is scanned by channel 2410.

[0261] Figure 25 A schematic circuit 2500 for measuring the CV characteristics of a DUT according to an embodiment of the present disclosure is shown. Figure 25 As shown, test channel 2540 can be configured as a high-side channel to drive a common node via a synchronous AC excitation and optional DC bias through a high-current switch HC3 and a potential node HP3. When the high-current switch HC3 is closed, the potential node HP3 can be configured to a high potential. A sine curve can indicate the applied AC excitation.

[0262] The common node can fan out to multiple branches to the device under test (DUT) 2550. Each lower terminal connects to a low-side channel, namely test channels 2510, 2520, and 2530. Each test channel 2510, 2520, and 2530 can be connected via corresponding low-potential nodes LP1, LP2, and LP3 and corresponding low-current switches LC1, LC2, and LC3 to provide separate low-side voltage sensing and AC current measurement paths.

[0263] In some embodiments, the branches of the DUT 2550 can be three parallel capacitors. In some embodiments, resistors, diodes, or other passive or nonlinear components can also be used. During measurement, a high-side drive from test channel 2540 can be generated by the DDS, and precise amplitude and phase are monitored at the high-potential node HP3.

[0264] exist Figure 25 In this configuration, test channel 2540 may include short-circuitable nodes HC3 (high current force) and HP3 (high potential sensing). When the common node of DUT 2550 is driven, HC3 is closed via a high current switch.

[0265] A common node from the high-side branches fans out to multiple branches within the DUT 2550, each terminating in a separate low-side test channel: test channels 2510, 2520, and 2530. Each of these utilizes its own low-potential node (LP1, LP2, LP3) and low-current switch (LC1, LC2, LC3). The LP nodes serve as voltage sensing points, while the LC switches provide either a return (force) or current measurement path depending on the routing. These low channels can each measure the capacitance or current associated with their respective branches, allowing the system to capture the capacitance of multiple branches in parallel under the same common drive. In practice, each low channel has internal calibration and sensing circuitry to resolve small currents and voltages with high fidelity.

[0266] Multi-branch configurations support capacitance-voltage (CV) scans, where the gate or common node is driven by a high-side channel, and the voltage at the gate (or low side) is varied or stepped by one of the low-side channels, or the response of each branch can be measured by using all low-side channels simultaneously. For example, in a MOS array where three source / drain / body terminals are connected together (or driven together), this configuration makes it possible to measure the total capacitance of these nodes as a function of gate bias.

[0267] Figure 26 A schematic circuit 2600 for testing a single high channel and other low channels according to an embodiment of the present disclosure is shown.

[0268] like Figure 26 As shown and previously discussed, HC node 2611, HP node 2613, LP node 2615, and LC node 2617 can be configured to be coupled for a two-wire connection configuration. Specifically, as described above, the potential nodes can be configured as high-potential nodes HP / HC and low-potential nodes LP / LC. In some embodiments, apart from brief transitions that may occur during calibration, Figure 26 The node connections shown may not be active simultaneously during normal measurements. This single-node, programmable role topology reduces parasitic effects and routing imbalances while maintaining four-wire Kelvin separation and amplitude and phase coherence, when channels are assigned to the high-side or low-side.

[0269] In some embodiments, circuit 2600 may be implemented as a single programmable switchable potential node to implement force / sensing separation without requiring separate physical sensing leads for high and low roles. For example... Figure 26 As shown, by reusing the same physical node under different switching states (HC closed → high potential sensing; LC closed → low potential sensing), the hardware avoids redundant wiring and associated parasitic capacitance, leakage current, and phase / amplitude mismatch between disconnected paths.

[0270] use Figure 26 The implementation in this system, due to the identical source amplifier and clock drive configurations, enables precise phase and amplitude matching between force and sensing during calibration. An example calibration routine involves closing HC, measuring the amplitude / phase at HP, opening HC, closing LC, measuring LP, and then storing the correction coefficients. These corrections compensate for delays or gain differences caused by switching and routing. This practice is common in precision LCR / CMU instruments.

[0271] Figure 26 Another benefit of this topology is that unused switches (HC or LC) can be disconnected during non-measurement modes (e.g., during calibration or idle periods), thus isolating inactive paths. This minimizes the chance of parasitic leakage current or capacitive coupling affecting measurements. Moreover, because the same physical nodes are reused, its capacitance and wiring layout can be symmetrical for both roles (HP vs. LP), which helps reduce systematic errors in phase or amplitude when switching roles.

[0272] Figure 27A A schematic circuit 2700 for high-speed pulse IV testing according to an embodiment of the present disclosure is also shown. (As...) Figure 27A As shown, two independent programmable test channels 2710 and 2730 can be used. Test channel 2710 can drive the gate G of the device under test via a pulsed IV remote sensing (PIV RS) module, and test channel 2730 can apply a pulse bias to the drain D and acquire voltage and current via another pulsed IV (PIV) remote sensing (RS) module. Each channel can provide force and ground return to its respective PIV RS module, which can then be connected to the device terminals. The PIV RS module may include a high-speed switch, a programmable source and measurement stage, a current sensing resistor, and impedance matching, such that the pulse edges are well controlled, peak current is limited, and sampled values ​​are reported to the controller.

[0273] like Figure 27A As shown, MOSFET 2750 may have a source terminal S, and body terminal B shorted to ground. The drain terminal D is driven by test channel 2730 through a force line with a corresponding ground loop, and the gate terminal G is biased by test channel 2710 with its own ground loop. The timing diagram on the right shows the drain waveform with an adjustable DC base and superimposed pulses, the gate waveform which may be a step or a pulse train, and the source and body held at ground potential. The vertical dashed line indicates the common trigger moment when the two channels can be aligned with their pulse edges to minimize timing jitter.

[0274] During the test sequence, the controller can program the pulse amplitude, width, rise time, fall time, and repetition rate of test channel 2730, and program the gate bias scan on test channel 2710. At the top of each pulse, the system can sample the drain voltage and current reported by the PIV RS module to form a single IV data point. Repeated scans can generate transfer characteristics, output characteristics, or pulse Rds_on. The pulsed approach can reduce self-heating and contact drift errors, and the PIV RS module can provide overvoltage, overcurrent, and short-circuit protection suitable for rapid wafer-level characterization.

[0275] In some embodiments, circuit 2700 can implement precise high-speed switching (for turning HC / LC switches on and off). For example, the configuration shown in circuit 2700 can allow pulse rise / fall times on the order of nanoseconds or faster, depending on device capacitance and measurement bandwidth.

[0276] Figure 27A A possible representation of the pulse resources in each test channel is described, including a first branch and a second branch coupled via a high-speed switch. Figure 27A In this configuration, the PIV-RS force lines define potential nodes at the drain and gate of the DUT, with each potential node coupled to the corresponding test pin via a ground loop. Mode switches in the test channel selectively couple the appropriate potential node to a pulse resource (e.g., a base bias pulse train with delivery edges aligned with the dashed timing marker) or a measurement resource. The dashed vertical trigger indicates timing derived from the common system clock, ensuring that pulse application and measurement windows are phase-aligned on the test channel.

[0277] Figure 27B A schematic diagram 2760 of a second high-speed pulse IV test according to an embodiment of the present disclosure is shown. As shown, four independent programmable test channels 2772, 2774, 2776, and 2778 can be used. Test channel CH0 (2778) can be configured to drive the gate G of the device under test (DUT) 2750 using pulse excitation (force lead shown). Test channel CH1 (2776) is configured as a low-impedance reference on the drain D; in the illustrated embodiment, CH1 forces the drain to a selected reference potential (e.g., ground), thereby providing a stable clamp and, when enabled, providing a measurement return of the drain voltage and / or current. Test channels CH2 (2774) and CH3 (2772) provide ground connections to the body B and source S terminals, respectively, thereby establishing well-defined references for pulse measurements. In an alternative embodiment, CH1 can instead force a fixed DC drain bias, while CH2 / CH3 continue to provide a body / source ground return.

[0278] The timing diagram on the right corresponds to Figure 27BThe configuration is as follows. The top trace depicts the drain potential maintained substantially constant by CH1 (ground or a programmed DC bias). The second trace depicts the gate waveform provided by CH0, which can be a pulse train with programmable amplitude, width, rise time, fall time, and repetition rate. The dashed traces below represent the body and source maintained at ground potential by CH2 and CH3. The vertical dashed lines represent the common trigger moment; the channel aligns its operation with this trigger to minimize timing jitter between the gate pulse and any sampling or monitoring performed on the drain clamping channel.

[0279] During the test sequence, the controller can program CH0 to generate the desired gate pulse distribution while commanding CH1 to maintain drain clamping and optionally report drain voltage and current. At each pulse peak (or other sampling window), the system can sample relevant quantities (e.g., reference gate current, clamping voltage) to form individual IV data points. Repeating the pulse sequence while scanning the gate amplitude allows for extraction of transfer characteristics (Id-Vg) under pulsed conditions; maintaining the drain at ground supports threshold voltage or gate charge-related measurements with minimal self-heating.

[0280] exist Figure 27B In this arrangement, force lines establish potential nodes coupled to the corresponding test pins at the gate and drain of the DUT, and dashed timing markers indicate triggering derived from the system clock. Mode switches in the gate drive channel can select pulse resources, allowing the gate potential nodes to receive pulse trains biased by the base; high-speed switches within the pulse resources can select between a shaping branch that may include a pulse generator and PGA, and a sampling / verification branch for pulse monitoring. By reconfiguring the switches associated with the pulse resources, the test channel can be designated as a pulse channel, and its operation can be phase-aligned to system clock triggering to support simultaneous pulse delivery and synchronous measurement (voltage or current measurement) consistent with the disclosed architecture.

[0281] Figure 27B The arrangement supplemented Figure 27A Configuration. Figure 27A Pulse IV Remote Sensing (PIV RS) modules are employed on the drain and gate paths to utilize remote sensing for delivering and measuring fast pulses. Figure 27B A simplified ground-clamped topology is illustrated, where an additional channel provides a dedicated ground or DC bias reference to the device terminals, while a separate channel handles the pulsed gate drive. In some embodiments, a PIV RS module can also be inserted. Figure 27B In the CH0 and / or CH1 paths, add information about... Figure 27AThe same remote sensing, current sensing resistor, impedance matching, and protection features are described, while maintaining the ground clamping operation mode shown here.

[0282] exist Figure 27B In this configuration, the system can designate any available test channel as a ground unit. Because this role assignment can be performed within the test system, users do not need to add external modules or modify probe cards to perform stress measurements such as NBTI (e.g., gate stress with source / body / drain clamped). The ground unit provides the required clamping, while another channel provides a programmed gate pulse or bias. As a result, voltage errors during pulse testing due to IR voltage drops in cables, probe contacts, or the on-resistance (R_on) of internal switches are essentially eliminated at the DUT terminals, resulting in accurate stress conditions and repeatable NBTI results without fixture changes.

[0283] Figure 28 A calibration block diagram 2800 according to an embodiment of the present disclosure is shown. In the block diagram, a trigger output block 2812 can send signals to a trigger input block 2814, both of which can be connected to a test or calibration sample 2805. Test channels 2820, 2830, 2840, 2850, and 2860 can be configured in CH1 LCR HP mode 2830, CH3 LCR HP mode 2840, CH4 LCR HP mode 2850, CH5 LCR HP mode 2860, and the representative CHn LCR HP mode 28xy. The system can issue a hardware synchronization signal on the trigger output block 2812 and route it to a trigger input generator 2810, which can be implemented as an external waveform generator 2810. Receiving a trigger at the trigger input of generator 2810 can initiate a sine wave source locked to the system clock.

[0284] The output of the external generator 2810 can be routed via a system-controlled switching network that sequentially connects reference signals to each channel undergoing calibration. In some embodiments, calibration may be sequential. For example, Figure 28 The dashed arrows in the diagram indicate this channel-by-channel switching process. When a given channel is selected, the LCR high-potential measurement node digitizes the applied sine wave, and on-board signal processing can estimate the amplitude and phase, for example, through coherent detection or FFT. The measurements can be compared to a known reference from an external source to calculate per-channel gain correction and phase shift.

[0285] Calibration can be performed at multiple frequencies and several input levels to cover the expected operating range. Gain and phase corrections obtained for each channel and frequency point can be stored in non-volatile memory associated with that channel and applied automatically during normal measurements. The same arrangement can be used for periodic self-verification in production, allowing the system to refresh calibration tables to compensate for temperature drift and long-term drift.

[0286] Furthermore, each of the HP mode test channels (2820-28x0) can be arranged with a measurement path to receive a reference sine wave from an external generator and generate its own AC voltage measurement, thereby capturing both amplitude and phase. The routing block can include a switch for each channel, selecting the calibration input. In this configuration, each channel can compare its internal sensed (amplitude / phase) measurement with an external reference to determine offset, gain, and phase errors. In this configuration, test channels in HP mode share a synchronized system clock and a common reference, ensuring consistent amplitude and phase calibration across channels. Proper calibration ensures that the internal phase and amplitude response of each channel is known and can be corrected when the DUT is later driven by an AC signal in LCR mode.

[0287] Figure 29 A flowchart of a calibration method 2900 according to an embodiment of the present disclosure is shown. Method 2900 may be executed by one or more processors. For example, method 2900 may be executed by elements in system 100. For example, method 2900 may be executed by processing system 711, processor 1230, and / or other processing systems described herein. While in some embodiments all steps may be executed by the same processing system, in other embodiments, different steps in method 2900 may be executed by different systems. For example, some steps in method 2900 may be executed by channel 1100, while other steps may be executed by other elements in processing system 711.

[0288] In step 2910, the processor can initiate AC voltage measurement calibration. For example, the processor can multiplex a waveform generator with a trace path length equal to that of each channel and then send a trigger. The processing system can initiate AC voltage measurement calibration by driving a known AC reference signal into the measurement circuitry of the test instrument. In some embodiments, the processor can also select a traceable AC waveform from an internal waveform generator and route it to the input of each test channel under calibration via a precision multiplexing network. The multiplexed paths to the channels can be equal in length (or otherwise time-aligned) to ensure that each channel receives a reference waveform with the same phase delay. The processing system can then issue a trigger signal (e.g., via trigger output 2812) to simultaneously initiate measurement capture on each channel receiving the reference. This coordinated initiation ensures that the phase of the acquired waveform can be consistently referenced across the channels during calibration.

[0289] In step 2920, the processor can configure the waveform generator to be multiplexed to each channel with equal trace path lengths before sending the trigger. For example, the processor can configure one or more DDSs in the test channel to generate unique test signal characteristics (frequency or phase). Furthermore, in step 2920, the processor can optionally configure the DDS module of the test channel to help distinguish or isolate the calibration signal for each channel. In one embodiment, the processor adjusts the waveform generator (or the routing to each channel) such that the reference signal for each test channel has unique identifying characteristics, such as a small difference in frequency or a known phase offset relative to a global reference. This configuration, performed by controlling the DDS of each channel through the processing system, can be used to ensure that even when multiple channels are calibrated simultaneously, their measurement data can be analyzed separately or individually without interference.

[0290] In some implementations, a unique phase offset is introduced between the test signals of the channels while maintaining the same amplitude, thereby allowing the processor to calibrate the phase measurement offset of each channel relative to a common trigger reference. By configuring the test signals in this way, step 2920 enables the calibration process to be applied to multiple channels simultaneously, and the processor can attribute any measurement differences to the response characteristics of a particular channel.

[0291] In step 2922, the processor can configure a traceable waveform generator to send a sine wave after triggering. For example, the processor can issue a hardware trigger (e.g., a trigger input from generator 2810) to an external traceable waveform generator and program its setpoint. The processor can write the calibration frequency and desired phase. In step 2922, the processor can also wait for the generator to lock and stabilize. The processor can then enable the generator's output and route the sine wave via fan-out or a multiplexer with equal trace lengths, ensuring that the phase delay to each selected channel is the same. The processor can record the generator identification, certificate number, and precise setpoint used, and compensate for command levels with known cable losses or clamp attenuation, ensuring voltage matching at the channel inputs.

[0292] In step 2924, the processor can configure each channel one at a time and perform digitization after triggering and FFT. For example, the processor can configure sequences by channel and perform coherent capture for each sequence. In some embodiments, the channel ADC can be configured to set the sampling rate, apply a window function, and receive the trigger edge. The processor can also acquire samples, compute the discrete Fourier transform, and extract the complex phasor. The processor can calculate the amplitude (e.g., Vrms after windowing and scaling correction) and phase relative to the trigger reference based on the phasor, and compute noise metrics from adjacent cells if necessary. Furthermore, in step 2924, the processor can repeat the capture to average the amplitude and phase.

[0293] In step 2930, the processor can determine whether to calibrate or verify each channel. For example, the processor can measure the AC waveform on the channel and acquire amplitude / phase data. For example, the processor can measure the response of each AC voltage measurement channel to a known reference signal. The ADC or measurement circuitry of each channel can capture the input AC waveform triggered in step 2910. The processor can read the digitized waveform data from the ADC of the measurement channel and calculate the observed amplitude and phase. In step 2930, the processor can also quantify the measurement error of each channel by comparing the measured amplitude and phase of the channel with expected reference values. Although Figure 29 Calibration and verification are shown as alternatives, but in some embodiments, these processes may be performed sequentially and / or serially.

[0294] If the processor determines in step 2930 that verification is required, it can proceed to step 2942. In step 2942, the processor can verify the amplitude and phase errors against specifications. For example, the processor can assess whether the measurement error for each channel is within acceptable limits. Furthermore, in step 2942, the processor can calculate the gain error and phase offset error of the channel measurement system. It then compares these errors with predetermined calibration tolerances or specifications stored in memory. If the amplitude and phase measurements of the channel already meet the accuracy specifications (i.e., the error is below a threshold), the processor can determine that no significant calibration adjustment is needed for that channel (the measurement system is already calibrated). If the error exceeds the permissible specifications, the processor marks the calibration adjustment in the next step.

[0295] In step 2944, the processor can stop the AC voltage measurement calibration. For example, the processor can terminate the verification run after confirming in step 2942 that the amplitude and phase meet the specifications. The processor can cancel the trigger, command the NIST traceable waveform generator to shut down its output, return the channel fan-out / multiplexer to the disconnected or safe default state, and restore the normal routing for each channel (e.g., disconnect the verification path and re-enable the standard measurement path).

[0296] If the processor determines that calibration is required in step 2930, it can proceed to step 2952. In step 2952, the processor can use calibration software and collect FFT, amplitude, and phase results from the different channels. For example, the processor can aggregate calibration outputs from the channels involved in the measurement by retrieving the complex FFT bin, the derived amplitude and phase values, and associated metadata including channel identifier, capture index, timestamp, temperature / voltage telemetry, selected range, gain setting, sampling rate, window type, record length, and number of averages for each channel. The processor can also acquire this data by initiating a DMA read of the ADC buffer for each channel and performing the FFT centrally, or by reading the registers of each channel while the FFT is computed locally on the channel.

[0297] In step 2952, the processor may also normalize each result for ADC full scale, window loss, and record length; convert the amplitude to configuration units (e.g., Vrms or Vpk); unwind and reference the phase to a common trigger; and apply any stored fixed delay (e.g., cable / clamp delay) to align the phase. Quality metrics such as coherence, SNR, residual noise floor, and chamber leakage are calculated to score each capture; outliers are removed, and if necessary, the processor refits the affected channels for replacement captures.

[0298] In step 2954, the processor may calculate the average of all phase and amplitude offsets. For example, the processor may calculate the summed offset per channel, per range, and per frequency from the capture set assembled in step 2952. In some embodiments, the processor may perform iterative calculations, including identifying discarded points and moving averages, to identify offsets and associated statistics indexed by channel identifiers, operating ranges, calibration frequencies, temperature ranges, and power supply telemetry.

[0299] In step 2960, the processor can calculate the amplitude and phase offset from the average value and store the calculated values. For example, the processor can perform a calibration process to determine the correction factors needed to align the channel's measurements with a reference. Based on the determined amplitude error (e.g., percentage gain error or offset) and any measured phase error (phase lead or lag), the processor can calculate new calibration coefficients for the measurement path of that channel. These coefficients may include gain correction factors to adjust the channel's measurement amplitude, and offset or phase correction values ​​to adjust timing or phase readings. The processor can then apply these calibration coefficients to the channel's calibration register or a software calibration table in the calibration circuitry. For example, the processor can program the calibration DAC or adjust the digital calibration filter in the measurement channel to implement the calculated gain correction and apply the phase calibration offset to the channel's timing or digital signal processing (DSP) algorithm. By applying these adjustments, the output of the measurement channel is virtually "calibrated" so that subsequent measurements accurately reflect the true amplitude and phase.

[0300] Also in step 2960, the processor can store calibration data and verify the calibration of the AC voltage measurement. For example, the processor can complete the calibration of the AC voltage measurement channel and store the updated calibration constants (gain and phase offset determined in step 2960) in the memory associated with test channel 2610 or in a dedicated calibration data storage.

[0301] In step 2980, the processor may set a verification flag. For example, the processor may set a per-channel bit in a register and write the corresponding system-level verification token. When asserting the verification flag, the processor may also: (i) mark the valid coefficient set as read-only to prevent unintentional editing until the flag is cleared; (ii) publish a calibration event to the host / controller and update any UI / telemetry; and / or (iii) bind the measurement pipeline to the verified coefficient map (e.g., by loading a fast register from a flag table) and record the verification period for auditing. The processor may also register protection conditions that automatically clear the verification flag if significant changes occur, such as frequency / range changes outside the verification envelope, device temperature drift exceeding a stored threshold, replacement of the reference source, or firmware / configuration mismatch detected by CRC / hash comparison.

[0302] Figure 30 A flowchart of a first calibration method 3000 according to an embodiment of the present disclosure is shown. Method 3000 may be executed by one or more processors. For example, method 3000 may be executed by elements in system 100. For example, method 3000 may be executed by processing system 711, processor 1230, and / or other processing systems described herein. Alternatively or additionally, while in some embodiments all steps may be executed by the same processing system, in other embodiments different steps in method 3000 may be executed by different systems. For example, some steps in method 3000 may be executed by processor system 811 or channel 1100, while other steps may be executed by other elements in processing system 711.

[0303] In step 3010, the processor can begin AC current measurement calibration and select a reference load. Step 3010 can be similar to combining... Figure 29 Step 2910 is described.

[0304] In step 3020, the processor can connect the channel voltage sources to their respective voltage measurements. For example, the processor can configure an internal switching matrix to loop the AC voltage source output of each selected channel back to its corresponding AC voltage measurement input. The processor can first force the source output to a safe state (output off or minimum amplitude), select the appropriate measurement range and input termination, and route the protection / shielding conductors as needed for the selected frequency band. Then, the processor can close the designated loopback relay for the channel being calibrated, verify continuity and isolation by reading the relay sensing / health bit or by issuing a low-level probe excitation and checking the measured impedance, and enable the digitizer. Once the loopback is confirmed, the processor records the channel identifier, range, relay status, and environmental telemetry, and transitions the source from a safe state to the programmed calibration setpoint, so that subsequent steps can acquire measurements of the channel's own output.

[0305] In step 3030, the processor can determine whether it is calibration or verification. For example, the processor can perform a combination... Figure 29 The determination described in step 2930 is similar to the determination.

[0306] In step 3042, the processor can verify that the amplitude and phase meet specifications. For example, the processor can perform a combination... Figure 29 The verification described in step 2942 is similar to the verification described therein.

[0307] In step 3044, the processor may stop AC voltage source calibration. For example, the processor may stop voltage source calibration, such as in conjunction with... Figure 29 As described in step 2944.

[0308] In step 3050, the processor can adjust the DDS phase and amplitude of the voltage source until the AC voltage measurement reaches the average value from the AC voltage calibration. For example, the processor can execute routines to program the DDS amplitude word and phase offset register of the channel and calculate the complex phase of the calibration tone. The processor can compare the measured voltage and phase with the average target generated during AC voltage calibration and derive the residual gain and phase error. The processor then increments or decrements the DDS amplitude scaler and phase offset by bounded steps, reapplies the waveform, and repeats the acquisition until both the amplitude and phase errors are within predetermined tolerances.

[0309] In step 3060, the processor can save the DDS phase and amplitude values. For example, the processor can write the converged amplitude scaler and phase offset to a non-volatile calibration image indexed by channel identifier, frequency band, range, and operating mode, calculate and store the checksum or hash value on the record. The processor can also provide a shadow copy for rollback, mark the new image as active in the channel's calibration catalog, and preload the corresponding fast registers so that the corrected coefficients are applied during normal operation.

[0310] In step 3070, the processor may store the calibration value or offset. And in step 3080, the processor may set a verification flag, as described above. Figure 29 As discussed in step 2980.

[0311] Figure 31 A flowchart of an exemplary method 3100 for calibrating the amplitude and phase accuracy of an AC voltage source output is shown. Method 3100 can be executed by one or more processors. For example, method 3000 can be executed by elements in system 100. For example, method 3100 can be executed by processing system 711, processor 1230, or any other processing system previously discussed. Alternatively or additionally, while in some embodiments all steps can be executed by the same processing system, in other embodiments, different steps in method 3100 can be executed by different systems. For example, some steps in method 3100 can be executed by processor system 811 or channel 1100, while other steps can be executed by other elements in processing system 711.

[0312] In step 3110, the processor can begin AC current measurement calibration and select a reference load. Step 3110 can be combined with... Figure 29 The steps described are similar to 2910.

[0313] In step 3120, the processor can select a reference load matched to each current range. For example, the processor can load a calibration routine that maps each source current range to one or more precision reference resistors whose values ​​produce the target calibration voltage drop and phase margin at the calibration frequency without overdriving the ADC or exceeding the resistor power. The processor can calculate the expected compliance requirements and verify that the source, relay ratings, and resistor power ratings are sufficient. The processor can then command the internal switching matrix to connect the selected reference resistor for the range under test.

[0314] In step 3130, the processor may select one current range at a time to measure the current using two different reference loads. For example, the processor may isolate a single source range, connect a first mapped reference resistor, program a calibration tone (frequency and amplitude), trigger coherent capture, and calculate the current based on the measured voltage using a calibration path. In some embodiments, the processor may store the measured values ​​and calculated corrections associated with the current range, frequency, and channel identifier.

[0315] In step 3140, the processor can determine whether it is calibration or verification. For example, the processor can perform a combination... Figure 29 The determination described in step 2930 is similar to the determination.

[0316] In step 3152, the processor can verify that the amplitude and phase meet specifications. For example, the processor can perform a combination of... Figure 29 The verification described in step 2942 is similar to the verification described therein.

[0317] In step 3154, the processor may stop AC voltage source calibration. For example, the processor may stop voltage source calibration, such as in conjunction with... Figure 29 As described in step 2944.

[0318] In step 3160, the processor may perform calibration to calculate the gain / offset of both amplitude and phase. For example, the processor may perform a combination of... Figure 29 The calibration described in step 2952 is similar to the calibration.

[0319] In step 3170, the processor may store the gain / offset values ​​for both amplitude and phase. For example, the processor may write the calculated amplitude scaling (gain) correction and phase offset values ​​into a channel-specific calibration table in non-volatile memory, thereby indexing each record by channel identifier, operating mode, range, and calibration frequency. The processor may append metadata including timestamps, firmware revisions, reference source identifiers, temperature and power telemetry data, and table revision numbers, calculate checksums or cryptographic hashes on the records, and perform read-after-write verification before marking an entry as valid. In some embodiments, the processor may also preload the corresponding runtime registers (e.g., DSP gain / offset coefficients and phase alignment values).

[0320] In step 3180, the processor may store the calibration value or offset. And in step 3190, the processor may set a verification flag, as described above. Figure 29 As discussed in step 2980.

[0321] Figure 32 A flowchart of an exemplary method 3200 for calibrating the amplitude and phase accuracy of an AC voltage source output is shown. Method 3200 can be executed by one or more processors. For example, method 3200 can be executed by elements in system 100. For example, method 3200 can be executed by processing system 711, processor 1230, or other processing devices discussed herein. Alternatively or additionally, while in some embodiments all steps can be executed by the same processing system, in other embodiments, different steps in method 3200 can be executed by different systems. For example, some steps in method 3200 can be executed by processor system 811 or channel 1100, while other steps can be executed by other elements in processing system 711.

[0322] In step 3210, the processor can configure a direct digital synthesizer in the test channel to generate a test signal with a unique frequency or phase. For example, the processor can select a set of resource channels and assign a different carrier scheme derived from a common system clock to each channel. Furthermore, in some embodiments, the processor can write the corresponding frequency tuning word and programmable phase offset to the DDS / NCO of each channel, load the amplitude setpoint per range, and apply previously stored calibration coefficients (gain / phase fine-tuning) to pre-compensate the analog path.

[0323] In step 3230, the processor can configure the direct digital synthesizer in the test channel to generate a test signal with a unique frequency or phase. For example, the processor can select a single carrier frequency for the participating channel and program different phase codes (e.g., evenly spaced in the DDS phase shift register of each channel) such that the response remains phase coherent and is distinguishable by phase-sensitive detection. Alternatively, or additionally, when spectral separation is preferred, the processor can assign a small selected frequency offset to place each tone in a dedicated FFT bin for a given capture length and sampling rate, thereby minimizing inter-bin leakage and crosstalk. In both cases, the processor can gate the channel with a common trigger and apply a per-channel correction table, so that the reported amplitude / phase is aligned with the central reference. This coordinated DDS programming allows for multi-pin, multi-DUT measurements with explicit channel separation in the frequency / phase domain, resulting in higher station counts, shorter dwell times, and better phase coherence compared to existing systems that rely on a single CMU and extensive switching.

[0324] Figure 33 A flowchart of a method 3300 for configuring a processor and / or a digital synthesizer according to an embodiment of the present disclosure is shown.

[0325] Method 3300 may be executed by one or more processors. For example, method 3300 may be executed by elements in system 100. For example, method 3300 may be executed by processing system 711, processor 1230, or any other processing system described herein. Alternatively or additionally, while in some embodiments all steps may be executed by the same processing system, in other embodiments different steps in method 3300 may be executed by different systems. For example, some steps in method 3300 may be executed by processor system 811 or channel 1100, while other steps may be executed by other elements in processing system 711.

[0326] In step 3310, the processor can configure the channel to operate as any of a high channel, a low channel, or a measurement channel based on the arrangement of the first and second configurable switches. For example, the processor can configure a given test channel to operate as any of a high channel, a low channel, or a measurement channel by appropriately controlling the first and second configurable switches in that channel. For example, the processor can set the switches such that one test channel is connected to provide a high channel output, while another channel is set to a low channel to serve as a return path for the excitation or a ground reference.

[0327] Alternatively, the processor can arrange the switches as sensitive measurement circuits with isolated channels, thus turning them into measurement channels for monitoring device responses (voltage, current, etc.) without actively driving the nodes. In practice, this means that any test channel can be dynamically assigned as a source or real-time measurement role, giving the system tremendous flexibility. This per-pin configurability eliminates the need for dedicated source / measurement units tied to specific pins; each channel can perform any function as needed.

[0328] This flexibility not only simplifies the hardware architecture (as the same channel can be used as a high-force output, low-return, or measurement unit) but also improves test coverage and efficiency. By enabling the "full per-pin resource" feature (i.e., each pin has all the resources available for forcing or measuring), the processor's control over the switches bridges the gap between benchtop and production test systems, allowing a single system to seamlessly handle legacy, advanced node, and even specialized tests without reconfiguration.

[0329] In step 3330, the processor can configure a direct digital synthesizer (DDS) in the test channels to generate test signals with unique frequencies or phases, and these signals are calibrated relative to the system clock. For example, the processor can configure a DDS in the test channels to generate test signals with unique frequencies or phases, all of which are calibrated relative to a common system clock. For example, the processor can program the DDS of one channel to output a sinusoidal voltage at f1 (e.g., 1.000 MHz), while the DDS of another channel outputs a signal at a different frequency f2 (e.g., 1.200 MHz), and a third channel can generate waveforms at the same frequency as the first channel but with a defined phase offset (ensuring a known phase relationship between the channels). Each DDS is driven by and synchronized with the system clock, so these output waveforms are highly stable and phase-coherent, with frequency accuracy inherited from the reference clock. In some embodiments, each channel can receive a unique signal. By providing a unique stimulus (different frequency or phase) to each test channel, the system can perform multiple test conditions simultaneously on a single device or even across multiple devices.

[0330] For example, one channel can excite the gate of a device with a small AC signal of one frequency, while another channel excites the substrate or drain of the device with a signal of another frequency; then, the measurement channels can be used to distinguish the effect of each signal through filtering or Fourier analysis. This parallel excitation method means that the response to each unique frequency can be independently isolated and analyzed, thus enabling concurrent multi-frequency testing.

[0331] In step 3350, the processing circuitry can be configured to convert analog measurements to digital measurements, transform signals from the time domain to the frequency domain, and / or send digital data to a processor. For example, the processor can be configured with circuitry (or an onboard data acquisition system) to process the input analog measurement results and prepare them for analysis. This circuitry can be responsible for converting analog measurements to digital form, performing signal processing (e.g., transforming signals from the time domain to the frequency domain), and transmitting the resulting digital data to a higher-level processor or host computer. For example, the processor can trigger a high-speed analog-to-digital converter to sample voltage or current waveforms obtained from one or more measurement channels, thereby digitizing the device's response at high resolution. Once converted to digital data, the processing circuitry can apply digital signal processing algorithms.

[0332] In some implementations, the system can use a frequency domain spectrum, which allows the system to extract frequency-specific response components, such as measuring the amplitude and phase at test frequencies f1 and f2 injected by the DDS source in step 3330. By analyzing the frequency domain data, the tester can directly determine device parameters that are difficult to separate in the raw time-domain signal (e.g., capacitance, resistance, or gain and phase margin at certain frequencies). The ability to perform this transformation internally means that the system can perform functions similar to an LCR meter or on-chip spectrum analysis, consistent with advanced parameter testing features (e.g., measuring gate capacitance at high frequencies even in the presence of leakage current). Additionally, the processor can compress, filter, or average the digital data as needed to reduce noise and data volume, and then transmit the refined digital results to an external controller or software suite for further evaluation.

[0333] In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary with different implementations. Certain modifications and changes may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in consideration of the specification and practice of the invention disclosed herein. The specification and examples are to be considered exemplary only. It is also intended that the order of steps shown in the figures is for illustrative purposes only and is not intended to limit one to any particular order of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order when implementing the same method.

[0334] This disclosure can be described in the general context of custom hardware capable of executing custom preloaded instructions, such as computer-executable instructions for executing program modules. Program modules may include one or more of routines, programs, objects, variables, commands, scripts, functions, applications, components, data structures, etc., which may perform a specific task or implement a specific abstract data type. The disclosed embodiments can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in local and / or remote computer storage media, including memory storage devices.

[0335] This technology includes a computer-readable storage medium for storing instructions, and a system for performing any of the methods embodied in the instructions set forth in the following terms of this technology.

[0336] Clause i. A system for multi-channel parameter testing, the system comprising: a plurality of test channels, each of the plurality of test channels including: a pulse resource; a measurement resource including a high-current (HC) switch and a low-current (LC) switch; a mode switch coupled to the pulse resource, the measurement resource, and a potential node, the potential node being coupled to a test pin; and a system clock coupled to the plurality of test channels. The potential node is configured to perform a pulse test when the mode switch connects the pulse resource to the potential node; the potential node is configured to perform a high-potential (HP) test when the HC switch is closed and the mode switch connects the measurement resource to the potential node; and the potential node is configured to perform a low-potential (LP) test when the LC switch is closed and the mode switch connects the measurement resource to the potential node.

[0337] Clause ii. The system as described in Clause i, wherein the plurality of test channels includes a per-test-channel clock; the per-test-channel clock of each test channel has a frequency and phase synchronized with the system clock; the channel clock is configured with a programmable phase offset to compensate for the phase shift associated with each test channel in the test channels during calibration; and the LC switch and the HC switch operate alternately such that when one is closed, the other remains open.

[0338] Clause iii. A system as described in any of Clauses i or ii, wherein each test channel includes a force line coupled to a potential node via at least one of a mode switch, an HC switch, or an LC switch, and a sensing line coupled to a measurement resource and a device under test (DUT); wherein the force line is configured to provide a signal to the DUT, and the sensing line is configured to detect a voltage at the DUT.

[0339] Clause iv. A system as described in any one of Clauses i-iii, wherein the measurement resources include a capacitance measurement unit (CMU) and a source measurement unit (SMU), and the plurality of test channels include a first test channel, a second test channel, a third test channel, and a fourth test channel. The system is configurable to: set the potential nodes of the first, second, and third test channels to a first dynamic potential; set the potential node of the fourth test channel to a second dynamic potential different from the first dynamic potential; and perform capacitance-voltage (CV) analysis by applying a voltage and measuring the capacitance as a function of the first and second dynamic potentials.

[0340] Clause v. A system as described in any of Clauses i-iv, wherein each test channel includes a direct digital synthesizer (DDS) configurable to generate a test signal synchronized with a system clock in phase and frequency; and the plurality of test channels are configured to simultaneously measure the DUT using timing derived from the system clock.

[0341] Clause vi. A system as described in any of Clauses iv, wherein each test channel comprises: a memory; a first analog-to-digital converter (ADC) coupled to the potential node and the memory; a second ADC coupled to the potential node and the memory; a first digital-to-digital converter (DDS) coupled to the potential node; and a second DDS coupled to at least one of the first ADC or the second ADC.

[0342] Clause vii. A system as described in any of Clauses i-vi, wherein each test channel further comprises: a first Fast Fourier Transform (FFT) circuit coupled to the first ADC and the memory; and a second FFT circuit coupled to the second ADC and the memory.

[0343] Clause viii. The system as described in any one of Clauses i-vii, wherein at least one of the first DDS or the second DDS is configured to generate a test signal for measuring the DUT.

[0344] Clause ix. The system as described in any one of Clauses i-viii, wherein the plurality of test channels comprises at least eight channels, each configurable with programmable phase and amplitude; the phase and amplitude are synchronized on the channels; the pulse resources include digital-to-analog converters (DACs) driving a plurality of programmable gain amplifiers (PGAs), the outputs of which are selectable by high-speed switches.

[0345] Clause x. A system as described in any of Clauses i-ix further includes a processor coupled to a system clock, wherein each of a plurality of test channels includes a DDS. The processor is configured to: cause the system clock to provide a calibration signal to the plurality of test channels; measure the phase shift of each test channel; and program the measured phase shift into a phase shift register of the corresponding DDS.

[0346] Clause xi. The system as described in any one of Clause ix, wherein each DDS is configured to generate a test signal using a numerically controlled oscillator (NCO) driven by a system clock, and a programmable phase offset is applied to the NCO to compensate for phase shift in the corresponding test channel.

[0347] Clause xii. The system as described in any one of Clauses i-xi, wherein the DDS in each test channel is configured to generate test signals in phase with the system clock.

[0348] Clause xiii. The system as described in any one of Clauses i-xii, wherein each test channel includes a high-potential circuit and a low-potential circuit, and each test channel can be configured to alternate between the high-potential circuit and the low-potential circuit based on at least one of HC or LC switches.

[0349] The system of any one of the provisions of Articles XIV. i-xiii further includes a processor configured to: multiplex a first signal to each of the high-potential and low-potential circuits; synchronize the first signal with a trigger signal to align the phase across the test channel; calibrate the amplitude and phase of each high-potential and low-potential circuit based on the first signal; generate a second signal and route it to the high-potential circuit; and calibrate the amplitude and phase of the high-potential circuit by comparing the first and second signals.

[0350] Clause XV. The system as described in any one of Clauses I-XIV, wherein the first signal is a sine wave, the second signal is generated internally, and the processor is further configured to measure the phase difference between the high-potential circuit and the low-potential circuit after calibrating the high-potential circuit, and to calibrate the low-potential circuit based on the measured phase difference.

[0351] Clause xvi. The system as described in any one of Clauses i-xv, wherein the processor is configured to store a correction value in the memory of the test channel, the correction value including at least one of amplitude gain or phase shift relative to the first signal.

[0352] Clause xvii. A system for parallel testing, the system comprising: one or more processors; a system clock; and a plurality of test channels coupled to the processors, each of the test channels comprising: a pulse resource; a measurement resource including a first configurable switch, a second configurable switch, and a direct digital synthesizer; a mode switch coupled to the pulse resource and the measurement resource; and a potential node coupled to a test pin and the mode switch. Based on the configuration of these switches, any channel from the plurality of test channels can be configured as a high channel, a low channel, a pulse channel, or a measurement channel, and the processor is configured to: control a DDS unit to generate a test signal having a specific frequency or phase, and simultaneously measure a set of multiple test channels having a phase and frequency determined based on the system clock.

[0353] Clause xviii. The system as described in Clause xvii, wherein the plurality of test channels include a local processor configured to perform a Fast Fourier Transform (FFT) on the acquired data; the plurality of test channels are configured with a frequency offset of the FFT bin to isolate channel measurements; and the pulse resource includes a pulse board having a programmable gain amplifier coupled to a slew rate limiter and a high-speed switch.

[0354] Clause xix. The system as described in any one of Clauses xvii-xviii, wherein each DDS includes a programmable phase shift register that stores the offset of the corresponding test channel.

[0355] Clause xx. A system for multi-channel parameter testing, the system comprising: a plurality of test channels, each of the plurality of test channels including a pulse resource, a measurement resource including a first configurable switch and a second configurable switch, and a direct digital synthesizer; channel processing circuitry; and a mode switch coupled to the pulse resource, the measurement resource, and the processing circuitry. Each test channel is configurable via a processor to operate as any of a high channel, a low channel, a pulse channel, or a measurement channel based on the arrangement of the first configurable switch, the second configurable switch, and the mode switch. A DDS unit in the test channel is configured to generate a test signal having a unique frequency or phase and calibrated to the system clock, and the channel processing circuitry performs operations including at least one of: converting analog measurements to digital data, transforming a time-domain signal to the frequency domain, or transmitting digital data to the processor.

[0356] Clause xxi. A system for multi-channel parameter testing, the system comprising: a plurality of test channels. The plurality of test channels include: a high-current (HC) switch; a low-current (LC) switch; a potential node coupled to a test pin, the HC switch, and the LC switch; a channel clock; and a system clock coupled to the plurality of test channels. Further, the potential node is configured to perform a high-potential (HP) test when the HC switch is closed; the potential node is configured to perform a low-potential (LP) test when the LC switch is closed; and the channel clock in each of the plurality of test channels has a frequency and phase synchronized with the system clock.

[0357] Clause xxii. The system as described in Clause xxi, wherein each of the test channels further includes: a force line connected to the potential node via the LC switch or the HC switch, the force line being configured to provide a signal to the device under test (DUT); and a sensing line connected to the potential node, the sensing line being configured to detect the voltage at the DUT.

[0358] Clause xxiii. A system as described in Clause xxi or xxii, wherein: the plurality of test channels include a first test channel, a second test channel, a third test channel, and a fourth test channel; and the system is configurable to: set the potential nodes of the first test channel, the second test channel, and the third test channel as a first dynamic potential; set the potential node of the fourth test channel as a second dynamic potential, the second dynamic potential being different from the first dynamic potential; and perform capacitance-voltage analysis by applying a voltage and measuring the capacitance as a function of the first dynamic potential and the second dynamic potential.

[0359] Clause xxiv. A system as described in any one of Clauses xxi-xxiii, wherein each channel clock is configured with a phase offset that compensates for the phase shift associated with each of the plurality of test channels during calibration.

[0360] Clause xxv. A system as described in any one of Clauses xxi-xxiv, wherein: each of the test channels includes a direct digital synthesizer (DDS) configured to generate a test signal; the test signal is configured to be synchronized with the system clock in phase and frequency; and the test channel is configured to simultaneously measure the device under test (DUT) using timing derived from the system clock.

[0361] Clause xxvi. The system as described in any one of Clauses xxi-xxv, wherein each of the test channels comprises: a memory; a first analog-to-digital converter (ADC) coupled to the potential node and the memory; a second ADC coupled to the potential node and the memory; a first direct digital synthesizer (DDS) coupled to the potential node; and a second DDS coupled to at least one of the first ADC and the second ADC.

[0362] Clause xxvii. The system as described in any one of Clauses xxi-xxvi, wherein each of the test channels further comprises: a first Fast Fourier Transform (FFT) circuit coupled to the first ADC and the memory; and a second FFT circuit connected to the second ADC and the memory.

[0363] Clause xxviii. The system as described in any one of Clauses xxi-xxvii, wherein at least one of the first DDS or the second DDS is configured to generate a test signal for measuring the device under test (DUT).

[0364] Clause xxix. The system as described in any one of Clauses xxi-xxviii, wherein: the test channel comprises at least eight channels; each of the at least eight channels is configurable with phase and amplitude, and the phase and amplitude are synchronized in each of the at least eight channels.

[0365] Clause xxx. The system as described in any one of Clauses xxi-xxix further includes: a processor coupled to the system clock; wherein each of the plurality of channels includes a direct digital synthesizer (DDS); and the processor is configured to: provide a calibration signal from the system clock to the plurality of test channels; measure the phase shift of each test channel; and program the phase shift into a phase shift register of the corresponding DDS.

[0366] Clause xxxi. The system as described in any one of Clauses xxi-xxx, wherein: the DDS is configurable to generate test signals using a numerically controlled oscillator (NCO) driven by a system clock, and a programmable phase offset is applied to the NCO to compensate for phase shifts in the corresponding test channels.

[0367] Clause xxxii. The system as described in any one of Clauses xxi-xxxi, wherein the DDS in each of the plurality of test channels is configured to generate test signals in phase according to the system clock.

[0368] Clause xxxiii. The system as described in any one of clauses xxi-xxxii, wherein: each test channel includes a high-potential circuit and a low-potential circuit; and each of the test channels is configurable to alternate between the high-potential circuit and the low-potential circuit using at least one of the HC switch or the LC switch.

[0369] Clause xxxiv. A system as described in any of clauses xxi-xxxiii further includes a processor, wherein the processor is configured to: multiplex a first signal to each of a high-potential circuit and a low-potential circuit in a test channel; synchronize the first signal with a trigger signal to align phase across the test channel; calibrate the amplitude and phase of each of the high-potential circuit and the low-potential circuit based on the first signal; generate a second signal and route it to the high-potential circuit; and calibrate the amplitude and phase of the high-potential circuit based on a comparison of the first signal and the second signal.

[0370] Clause xxxv. The system as described in any one of Clauses xxi-xxxiv, wherein: the first signal is a sine wave; the second signal is internally generated; and the processor is further configured to: measure the current phase difference between the high-potential circuit and the low-potential circuit after calibrating the amplitude and phase of the high-potential circuit; and calibrate the low-potential circuit based on the measured phase difference.

[0371] Clause xxxvi. A system as described in any one of Clauses xxi-xxxv, wherein the processor is configured to store correction values ​​in the memory of a plurality of test channels, the correction values ​​including at least one of amplitude gain or phase shift relative to a first signal.

[0372] Clause xxxvii. A system for parallel testing, the system comprising: one or more processors; a system clock; and a plurality of test channels coupled to the one or more processors, each of the plurality of test channels comprising: a potential node coupled to a test pin; a first configurable switch coupled to the potential node; a second configurable switch coupled to the potential node; and a direct digital synthesizer. Furthermore, based on the configuration of the corresponding first and second configurable switches in the plurality of test channels, any channel from the plurality of test channels can be configured as a high channel, a low channel, or a measurement channel; and the one or more processors can be configured to perform operations including: configuring the direct digital synthesizer in the test channel to generate a test signal having a unique frequency or phase; and simultaneously measuring a set of the plurality of pins by configuring the corresponding direct digital synthesizer to generate test signals having a phase and frequency determined based on the system clock.

[0373] Clause xxxviii. The system as described in Clause xxxvii, wherein the test channels include a local processor configured to perform FFT, and the plurality of test channels are configured with frequency offsets of the FFT bins to isolate channel measurements.

[0374] Clause xxxix. The system described in Clause xxxvii, wherein the DDS includes a programmable phase shift register, and the phase shift register stores the offset of a corresponding channel among the plurality of channels.

[0375] Clause xl. A system for multi-channel parameter testing, the system comprising: a plurality of test channels, each of the plurality of test channels including: channel processing circuitry; a first configurable switch; a second configurable switch; a node coupled to a test pin, the first configurable switch, and the second configurable switch; and a direct digital synthesizer. Furthermore, each test channel is configurable via a processor to operate as any one of a high channel, a low channel, or a measurement channel based on an arrangement of the first and second configurable switches; the direct digital synthesizer in the test channel is configured to generate a test signal having a unique frequency or phase and calibrated relative to a system clock; and the processing circuitry is configured to perform operations including at least one of: converting an analog measurement to a digital measurement, or transforming a signal from the time domain to the frequency domain, or sending digital data to the processor.

Claims

1. A system for multi-channel parameter testing, the system comprising: Multiple test channels, the multiple test channels including: Pulse resources; Measurement resources, including high-current (HC) switches and low-current (LC) switches; A mode switch coupled to the pulse resource, the measurement resource, and a potential node, the potential node being coupled to a test pin; and in: The potential node is configured to perform a pulse test when the mode switch connects the pulse resource to the potential node; The potential node is configured to perform a high-potential (HP) test when the HC switch is closed and the mode switch connects the measurement resource to the potential node; and The potential node is configured to perform a low potential (LP) test when the LC switch is closed and the mode switch connects the measurement resource to the potential node.

2. The system according to claim 1, wherein: The system includes a system clock coupled to multiple test channels; The multiple test channels include a clock for each test channel; Each test channel clock has a frequency and phase synchronized with the system clock; The channel clocks are configured with a phase offset that compensates for the phase shift associated with each of the plurality of test channels during calibration. as well as The LC switch and the HC switch operate alternately such that when one is closed, the other remains open.

3. The system according to claim 1, wherein the plurality of test channels comprises: Force lines, which are coupled to at least one of the mode switch, the LC switch or the HC switch and the potential node; as well as Sensing lines, which are coupled to the measurement resource and the device under test (DUT), in: The force lines are configured to provide signals to the DUT; as well as The sensing line is configured to detect the voltage at the DUT.

4. The system according to claim 1, wherein: The measurement resources include a capacitance measurement unit and a source measurement unit; The plurality of test channels includes a first test channel, a second test channel, a third test channel, and a fourth test channel; and The system is configured to: Set the potential nodes of the first test channel, the second test channel, and the third test channel as the first dynamic potential; The potential node of the fourth test channel is set as a second dynamic potential, which is different from the first dynamic potential; as well as Capacitance-voltage analysis is performed by applying a voltage and measuring the capacitance as a function of the first dynamic potential and the second dynamic potential.

5. The system according to claim 1, wherein: Each of the test channels includes a direct digital synthesizer (DDS) that can be configured to generate a test signal; The test signal is configured to be synchronized with the system clock in both phase and frequency; as well as The multiple test channels are configured to simultaneously measure the device under test (DUT) using timing derived from the system clock.

6. The system according to claim 1, wherein, Each of the test channels includes: Memory; A first analog-to-digital converter (ADC) is coupled to the potential node and the memory; A second ADC is coupled to the potential node and the memory; A first direct digital synthesizer (DDS) coupled to the potential node; and A second DDS is coupled to at least one of the first ADC and the second ADC.

7. The system according to claim 6, wherein the test channel further comprises: A first Fast Fourier Transform (FFT) circuit is coupled to the first ADC and the memory; as well as A second FFT circuit is connected to the second ADC and the memory.

8. The system of claim 6, wherein at least one of the first DDS or the second DDS is configured to generate a test signal for measuring the device under test (DUT).

9. The system according to claim 1, wherein: The multiple test channels include at least eight channels; Each of the at least eight channels can be configured with phase and amplitude. Synchronize phase and amplitude in each of the at least eight channels; and The pulse resources include one or more of the following: A digital-to-analog converter that drives multiple programmable gain amplifiers, the outputs of which can be selected by a high-speed switch; as well as An analog-to-digital converter coupled to a buffer.

10. The system according to claim 1, further comprising: A processor coupled to the system clock; The multiple channels mentioned above include a direct digital synthesizer (DDS); as well as The processor can be configured to: The system clock provides calibration signals to the multiple test channels; Measure the phase shift of each test channel; as well as The phase shift is programmed into the phase shift register of the corresponding DDS.

11. The system according to claim 10, wherein: The DDS can be configured to generate test signals using a numerically controlled oscillator (NCO) driven by the system clock, and A programmable phase offset is applied to the NCO to compensate for the phase shift in the corresponding test channel.

12. The system according to claim 10, characterized in that, The DDS in each of the plurality of test channels is configured to generate test signals in phase with the system clock.

13. The system according to claim 1, wherein: Each test channel includes a high-potential circuit and a low-potential circuit; and Each of the plurality of test channels can be configured to alternate between the high-potential circuit and the low-potential circuit using at least one of the HC switch or the LC switch.

14. The system of claim 13, further comprising a processor, in, The processor is configured to: The first signal is multiplexed to each of the high-potential circuit and the low-potential circuit in the test channel; Synchronize the first signal with the trigger signal to align the phase across the test channel; The amplitude and phase of each of the high-potential circuit and the low-potential circuit are calibrated based on the first signal; A second signal is generated and routed to the high-potential circuit; as well as The amplitude and phase of the high-potential circuit are calibrated by comparing the first signal and the second signal.

15. The system according to claim 14, wherein: The first signal is a sine wave; The second signal is generated internally; Furthermore, the processor is configured to: After calibrating the amplitude and phase of the high-potential circuit, the current phase difference between the high-potential circuit and the low-potential circuit is measured; and The low-potential circuit is calibrated based on the measured current phase difference.

16. The system of claim 14, wherein the processor is configured to store correction values ​​in the memory of the plurality of test channels, the correction values ​​including at least one of amplitude gain or phase shift relative to the first signal.

17. A system for parallel testing, the system comprising: One or more processors; System clock; as well as Multiple test channels coupled to the one or more processors, each of the multiple test channels including one or more of the following: The pulse resource includes a first branch and a second branch, as well as a high-speed switch coupled to the first branch and the second branch; or Measurement resources, including a first configurable switch, a second configurable switch, and a direct digital synthesizer; A potential node, which is coupled to a test pin and one or more of the pulse resource or the measurement resource; in: The first branch includes a pulse generator, a PGA, and a first branch switch; The second branch includes circuitry for pulse current and voltage measurement and a second branch switch; Based on the configuration of the corresponding first and second configurable switches, any channel from the plurality of test channels can be configured as a high channel, low channel, pulse channel, or measurement channel; and The one or more processors may be configured to perform operations, including: The direct digital synthesizer is configured in the test channel to generate a test signal with a unique frequency or phase; and A set of multiple test channels can be simultaneously measured by configuring a corresponding direct digital synthesizer to generate test signals, the test signals having phase and frequency determined based on the system clock.

18. The system of claim 17, wherein The plurality of test channels also include a mode switch coupled to one or more of the pulse resource and the measurement resource; The multiple test channels include a local processor configured to perform a Fast Fourier Transform (FFT); The multiple test channels are configured with frequency offsets of FFT bins to isolate channel measurements; as well as The pulse resource includes a pulse board, which includes a programmable gain amplifier coupled to a slew rate limiter and a high-speed switch.

19. The system of claim 17, wherein the direct digital synthesizer includes a programmable phase shift register, and the phase shift register stores the offset of a corresponding channel among the plurality of channels.

20. A system for multi-channel parameter testing, the system comprising: Multiple test channels, the multiple test channels including: Resources, which include one or more of pulse resources and measurement resources; Channel processing circuit; A mode switch coupled to one or more of the pulse resource, the measurement resource, and the processing circuitry; and Nodes, which are coupled to the mode switch and the test pin; and in: The pulse resources include high-speed switches and programmable gain amplifiers; The measurement resources include a first configurable switch, a second configurable switch, and a direct digital synthesizer; The plurality of test channels can be configured by the processor to operate as any of a high channel, a low channel, a pulse channel, or a measurement channel based on the arrangement of the first configurable switch, the second configurable switch, and the mode switch. The direct digital synthesizer in the test channel is configured to generate a test signal with a unique frequency or phase and is calibrated relative to the system clock; and The processing circuit is configured to perform at least one of the following operations: converting analog measurements into digital measurements, transforming signals from the time domain to the frequency domain, or sending digital data to the processor.

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