A high-precision probe card layout wire group length testing machine and testing method

Abstract

The application discloses a high-precision probe card layout wire group length testing machine and a testing method. The testing machine automatically connects two test points of the same differential wire pair through two test branches on a backboard, a double-channel step excitation and high-speed sampling module and a switch board with two groups of gating networks; the relative time delay of the step excitation and the sampling clock is changed in multiple excitation cycles, an equivalent time sampling waveform is reconstructed and a round-trip propagation time is extracted. At least two groups of differential reference paths with different known electrical lengths are used to establish double-channel calibration parameters, and the lengths of the two wires are calculated in combination with board-level parameters and channel offset. The system automatically outputs the differential length difference, the qualified state and the theoretical compensation electrical length and generates a test report, and is suitable for batch high-precision measurement of probe card mass differential wires.

Description

Technical Field

[0001] This invention relates to the field of high-speed electronic testing and time-domain reflectometry, specifically to a high-precision probe card layout trace length tester and test method. Background Technology

[0002] High-speed chip probe cards are located between the test equipment and the chip under test, and typically contain a large number of probe connections, connectors, and layout traces. For high-speed differential signals, to reduce the delay deviation between the two signal paths, the two layout traces of the same differential pair are usually designed to be of equal length during the probe card design phase. However, due to factors such as substrate dielectric parameters, etching dimensions, vias, connectors, solder joints, and assembly tolerances, the actual electrical length after manufacturing may still deviate from the design value.

[0003] Existing time-domain reflectometry (TD-RS) equipment can analyze the impedance changes and propagation distance of a single transmission line based on the reflected waveform. However, in scenarios where the probe card has a large number of differential traces, manual and repeated connection of test ports is usually required, making it difficult to achieve automatic selection of multiple test points, dual-channel consistency calibration, batch length comparison, and automatic generation of test reports. At the same time, the fixed delays and additional reflections introduced by the internal backplane, switching devices, connecting cables, adapter structures, and test fixtures will be superimposed on the end reflections of the traces under test. If only a single sampling is used or no layered calibration is performed, it is difficult to obtain stable differential trace length comparison results at the millimeter level.

[0004] Therefore, there is a need for a length testing machine and method capable of automatically gating, performing dual-channel measurement, equivalent time waveform reconstruction, and path error calibration for a large number of differential traces on probe cards. Summary of the Invention

[0005] This invention aims to address the problems of numerous differential layout traces in probe cards, low efficiency of manual connection, fixed delays and additional reflections introduced by different test paths, insufficient sampling time resolution, and difficulty in automatically generating differential comparison reports from test results. It provides a test machine and method capable of automated, high-consistency testing of massive differential traces. To achieve the above objectives, this invention provides a high-precision probe card layout trace group length tester, comprising a backplane, an FPGA control module, a clock module, a step excitation module, a dual-channel high-speed sampling module, at least one switch board, probe card connection components, a calibration module, and a data processing module.

[0006] The backplane is equipped with a first test branch, a second test branch, and a board-level connection interface. A step excitation module provides timing-corresponding step excitation signals to the first and second test branches, respectively. A dual-channel high-speed sampling module acquires the incident waveform and reflected response waveform from each of the two test branches. Each test branch preferably adopts a preset single-ended characteristic impedance design, which can be 50Ω. Corresponding branches from the backplane to each board-level connection interface are laid out with the same designed electrical length.

[0007] Each switchboard has multiple test point connection terminals, a first common test terminal, a second common test terminal, and a first and second independently controlled gating network. The FPGA control module first determines the target switchboard, and then sends the on-board channel information to the target switchboard, so that the first and second gating networks respectively connect two test points in the same differential trace pair to the first and second test branches.

[0008] The probe card connection assembly includes a multi-channel shielded cable assembly, an adapter board, and a test fixture. The multi-channel shielded cable assembly preferably consists of multiple independent coaxial transmission units or controlled impedance shielded transmission units; the adapter board connects each transmission unit to the test fixture according to the channel mapping relationship; the test fixture contacts the test points of the probe card under test via probes, spring pins, or connectors.

[0009] The calibration module includes at least two sets of differential reference paths with different known electrical lengths. Each set of differential reference paths includes two reference traces corresponding to the first and second test branches, respectively. The two reference traces in the same set have the same known electrical length, dielectric material, conductor structure, interface structure, and end condition; the effective electrical lengths of the reference traces in different sets are different. The time-length conversion factor and fixed path delay for the two test branches are established based on the measurement results of the two sets of reference paths.

[0010] The FPGA control module repeatedly controls the step excitation module to output step excitation within multiple excitation cycles, and the relative delay between the step excitation and the sampling clock is successively changed by a programmable delay unit or a programmable phase adjustment unit. The dual-channel high-speed sampling module acquires reflection response data at different relative delay positions. The FPGA control module performs timing rearrangement and interpolation of the sampled data according to the relative delay of each excitation cycle to form an equivalent time sampling waveform.

[0011] The data processing module establishes a mapping between differential pairs, test points, and switchboard channels based on the structured test task file, calls calibration parameters to calculate the calibration conversion length of the two traces under test, obtains the differential length difference and compares it with the allowable length difference, outputs the qualified status and the theoretical compensation electrical length that the shorter trace needs to add.

[0012] This invention also provides a high-precision probe card layout trace group length testing method, which includes, in sequence, task import and mapping, safety status confirmation, calibration parameter acquisition, target differential pair gating, successive relative delay excitation and dual-channel sampling, equivalent time waveform reconstruction, incident and end reflection edge extraction, calibration conversion, differential comparison and report generation.

[0013] The beneficial effects of this invention are as follows: 1. This invention utilizes two test branches to perform dual-channel sampling on the same differential trace pair. The two traces complete the measurement under the same clock and environmental conditions, reducing system drift caused by time-division measurement.

[0014] 2. By successively changing the relative delay between the step excitation and the sampling clock in multiple excitation cycles, the sampled data at different phase positions are rearranged and interpolated, which can improve the equivalent time resolution without changing the physical sampling rate of the high-speed sampling module.

[0015] 3. By using at least two sets of differential reference paths with different known electrical lengths, obtain the time-length conversion factor and fixed path delay for the two test branches respectively, and combine them with board-level calibration parameters and test point channel offset to compensate for path differences caused by backplane, switchboard, cable, adapter board and fixture.

[0016] 4. By using multiple switch boards and two sets of independent gating networks, the differential trace pairs can be automatically selected to correspond to two test points, enabling continuous scanning of a large number of layout traces and avoiding manual repeated plugging and unplugging of test ports.

[0017] 5. By establishing differential pairing and channel mapping through structured test task files, the calibration conversion length, differential length difference, qualified status and theoretical compensation electrical length of the two traces are automatically output, which facilitates manufacturing deviation analysis and subsequent compensation processing. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a functional module connection diagram of the high-precision probe card layout trace group length tester of the present invention.

[0019] Figure 2 This is a flowchart of the high-precision probe card layout trace group length testing method of the present invention; Figure 3 A schematic diagram of the physical structure of the layout routing test machine; Figure 4 This is a schematic diagram of the physical structure of the coaxial cable connection from the device to the layout for testing. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0022] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0023] Secondly, the present invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0024] Example 1

[0025] like Figure 1 As shown, the test machine in this embodiment adopts a modular backplane structure. The backplane can be installed inside the chassis and is provided with board-level connection interfaces for connecting multiple switch boards. The chassis structure facilitates the plugging, unplugging, maintenance, and expansion of switch boards, but the specific shape of the chassis and the specific number of switch boards are not limited.

[0026] The FPGA control module, clock module, step excitation module, dual-channel high-speed sampling module, memory, power conversion module, and communication interface can be mounted on the backplane or the control core board connected to the backplane. The original module connection diagram shows a device combination including an XC7A100T series FPGA, an ADCMP572 high-speed comparator, an AD9680 dual-channel high-speed analog-to-digital converter, a Si5430 clock generator, DDR3 memory, and PCIe, Ethernet, and USB interfaces. The specific models mentioned above are only for illustrating one feasible device selection; devices with the same function or meeting the performance requirements can be substituted.

[0027] Figure 1The FPGA control module can be implemented by a single FPGA device, or it can be implemented by a master FPGA and a measurement FPGA. When using a single FPGA, the FPGA is responsible for channel scheduling, excitation timing, sampling control, waveform reconstruction, and communication management. When using dual FPGAs, the master FPGA is responsible for task scheduling, communication, and data management, while the measurement FPGA is responsible for excitation control, sampling data reception, and propagation time extraction related to high-speed timing.

[0028] The step excitation module preferably includes a high-speed comparator. The FPGA control module provides a digital pulse signal to one input of the high-speed comparator, and the threshold setting module provides a comparison threshold to the other input of the high-speed comparator. The threshold setting module preferably includes a digital-to-analog converter. The FPGA control module sets the comparison threshold during equipment calibration, test mode switching, or signal amplitude adaptation, and keeps the comparison threshold unchanged during the same round of trace testing.

[0029] The two complementary outputs of the high-speed comparator constitute the first step excitation output and the second step excitation output, respectively. The first step excitation output is connected to the first common test terminal of the first sampling channel and the switch board via the first test branch; the second step excitation output is connected to the second common test terminal of the second sampling channel and the switch board via the second test branch. Damping resistors can be connected in series at the source terminals of the two test branches. In the example connection diagram of the original module, the resistance value is 22Ω, used to match the impedance of the subsequent transmission path and the comparator output characteristics, reducing source-end ringing.

[0030] The step excitation signal has a sub-nanosecond rise time. In one implementation, the rise time is no greater than 0.1 ns, allowing the step signal to contain high-frequency spectral components on the order of gigahertz, thereby improving the time resolution of the reflection edge. Here, 0.1 ns represents the rise time scale and is not expressed as a single sinusoidal signal with a frequency equal to 10 GHz.

[0031] The dual-channel high-speed sampling module is controlled by the same clock reference, acquiring waveforms from the first and second test branches respectively. For cases where the complementary outputs of the comparators cause opposite incident step directions in the two channels, the FPGA control module or data processing module first performs baseline correction, then multiplies the entire waveform of one channel by negative one according to the incident step direction, thus unifying the incident step directions of the two channels. This polarity normalization does not use absolute value calculations to preserve reflection polarity information.

[0032] Each switchboard has multiple test point connection terminals, a first common test terminal, a second common test terminal, a first gating network, and a second gating network. Both the first and second gating networks can be constructed from multi-level relay gating networks and are independently controlled by the FPGA control module. After gating is completed, the FPGA control module waits for a preset stabilization time before initiating the step excitation to reduce the impact of relay contact bounce on the reflected waveform.

[0033] The FPGA control module employs a two-level addressing system, consisting of board-level selection and in-board channel selection. Preferably, each switch board corresponds to an independent SPI chip select branch or an independent SPI port. The FPGA control module first selects the target switch board and then sends the in-board channel control data. The original disclosed scheme can configure up to 16 switch boards, each with 288 single-ended TP test point connections, resulting in a maximum of 4608 single-ended test points for the entire device. These quantities are merely parameters for an embodiment; the 288 represents the total number of single-ended test points connected to a single switch board, not that each of the two selection networks has 288 test points.

[0034] During differential testing, the first and second gating networks select the first and second test points corresponding to the same differential trace pair from the test point connection terminals of the same or different switch boards, and connect them to the first and second test branches respectively. The differential pairing relationship is determined by the structured test task file and does not automatically change the formal pairing relationship based on the test point name; the P / N, positive / negative, or other polarity identifiers in the test point name are only used for consistency verification.

[0035] The probe card connection assembly is located between the switch board and the external probe card. Each transmission unit of the multi-channel shielded cable assembly connects to the test point connection terminal of the switch board and the adapter board, respectively. The adapter board is then connected to the corresponding TP test point of the probe card via a test fixture. The test paths inside the tester, the shielded cable, and the adapter board are preferably designed based on a 50Ω single-ended characteristic impedance. The layout traces on the probe card under test are the object being tested, and their characteristic impedance is determined according to the probe card's own design.

[0036] The calibration module uses differential reference trace pairs as calibration benchmarks. The first differential reference path group includes two short reference traces connecting the first test branch and the second test branch, respectively. The known one-way electrical length of both short reference traces is [missing information]. The second differential reference path set includes two long reference traces connecting the first test branch and the second test branch, respectively. The known one-way electrical length of both long reference traces is [missing information]. ,and Greater than .

[0037] Two reference traces in the same group use the same dielectric material, conductor structure, trace width, reference plane, via structure, characteristic impedance, interface path, and termination state. The main difference lies in the effective electrical length of the two reference trace groups. The known electrical length of the reference trace is preferably determined in advance using standard instruments or standard calibration procedures, not only based on the layout geometry. The termination of the internal reference trace is preferably fixed as an open circuit, corresponding to the formal open-circuit reflection length measurement mode.

[0038] For the j-th test branch, where j is 1 or 2, the round-trip propagation times for the short and long reference routes are respectively... and The round-trip propagation time coefficient corresponding to a unit one-way travel length is:

[0039] Fixed path delay is:

[0040] For the target test point channel m measured via the j-th test branch, the round-trip propagation time between the incident edge and the terminal reflection edge is measured as follows: The channel delay offset of this test point channel relative to the board-level reference channel is: The calibrated and converted cable length is then:

[0041] The above-mentioned trace lengths all refer to the one-way electrical length from the test point interface to the reflection end; , and All are round-trip transmission times. Defined as the round-trip propagation time corresponding to a unit one-way electrical length, therefore, it is no longer multiplied or divided by 2 in the formula.

[0042] The calibration module can also employ layered calibration. A common reference path is provided on the backplane for calibrating excitation, sampling, and the common backplane link; each switchboard has a board-level reference channel to obtain its board-level calibration parameters; the external calibration interface connects to a standard test board for verifying the complete test path, including the switchboard, shielded cables, adapter boards, and test fixtures. The external standard test board can be configured with open circuit, short circuit, and known impedance loads. The open circuit is used for length measurement verification, the short circuit for verifying reflection polarity, and the known impedance load for checking impedance matching.

[0043] The channel offset of the test point can be measured and stored channel by channel using a standardized external calibration fixture at the factory. Board-level online calibration is performed before each power-on or test; after replacing the switch board, shielded cable, adapter board, or test fixture, the affected channels are recalibrated channel by channel.

[0044] The clock module provides a common clock reference to both the FPGA control module and the dual-channel high-speed sampling module. The FPGA control module includes a timing control unit and a programmable delay or phase adjustment unit. Within multiple excitation cycles, the timing control unit changes the step excitation output time according to a preset delay sequence; alternatively, it can keep the step excitation time constant and adjust the sampling clock phase. Both methods are used to change the relative delay between the step excitation and the sampling clock.

[0045] Let the actual sampling interval of the dual-channel high-speed sampling module be . The relative time delay corresponding to the r-th excitation cycle is If a delayed step excitation output time is used, then the equivalent sampling time of the nth sampled value in the rth excitation cycle relative to the step excitation can be calculated as follows: The symbol is determined based on the direction of phase adjustment when the sampling clock phase is adjusted. The FPGA control module assigns equivalent sampling times to each sample value based on the known relative delay, and after sorting, forms an equivalent time sampling waveform through linear interpolation, spline interpolation, or other reconstruction methods.

[0046] The original module connection diagram example uses a 50MHz repetition frequency, a 10ps relative delay step, and 10 excitation cycles. These values ​​can be used for fine reconstruction of a local time window of approximately 100ps near the located reflection edge; if it is necessary to cover the complete sampling interval of approximately 1ns for the high-speed sampling module, the number of relative delay positions should be increased. The actual relative delay step, number of excitation cycles, and reconstruction time window are determined based on the actual sampling interval, the range of the edge to be analyzed, and the target time resolution, ensuring that all relative delay positions cover the time window to be reconstructed.

[0047] Multiple excitation cycles with different relative time delays in a single trace length measurement are used to construct an equivalent time sampling waveform; repeating the complete measurement on the same differential trace pair is used to evaluate the stability of the results. These two are repetitive processes at different levels.

[0048] The coarse timing of the FPGA control module is used to determine the sampling window, while the actual propagation time used for length measurement is based on the difference between the incident step edge time and the end reflection edge time in the same equivalent time sampling waveform. This reduces the impact of FPGA instruction latency, the inherent latency of the programmable delay unit, and the propagation latency of the high-speed comparator on the measurement results.

[0049] The data processing module determines the expected arrival time of the end reflection and the reflection search time window based on the design reference length, allowable length deviation, and current channel calibration parameters in the structured test task file. During calibration, it saves the time-length conversion parameters, fixed path delay, channel delay offset, and the occurrence time interval, polarity, amplitude range, edge width, or local waveform characteristics of fixed reflections along the common path. During formal testing, it is not required to directly subtract the complete calibration waveform from the waveform under test point by point; instead, the calibration reflection characteristics are used to identify and exclude fixed reflections along the common path.

[0050] Within the reflection search time window, the end reflection edge can be determined based on its proximity to the expected time, amplitude, polarity, correlation with the standard end reflection waveform, and continuity before and after the edge. Both the incident edge and the end reflection edge can be located using a constant fraction method, i.e., the edge time is defined as the position where the change in amplitude from the local baseline to the stable value reaches a preset proportion, and interpolation is performed on adjacent equivalent sampling points. The preset proportion can be 50%, or other proportions can be set according to the waveform morphology.

[0051] The far end of the differential trace pair under test is preferably in an open-circuit state, with the open-circuit end forming a total reflection corresponding to the incident signal. A short-circuit state can be used to assist in verifying the reflection polarity, and a known impedance load is used to check the test link matching status. If a significant reflection of the same polarity occurs before the expected time window and the converted length is significantly less than the design reference length, it can be marked as a suspected premature open circuit or open circuit; if a significant reflection of opposite polarity occurs, it can be marked as a suspected short circuit; if there are multiple indistinguishable candidate reflections or obvious waveform distortion, a retest is performed, and if the retest still cannot determine the cause, it is marked as a manual verification.

[0052] For the same differential trace pair, multiple complete measurements are performed by default. After discarding abnormal results such as those without detected effective reflection edges, waveform saturation, amplitude below the threshold, or deviation from other results exceeding the threshold, the average or median value is calculated for the remaining length results. When the range, standard deviation, or median absolute deviation exceeds the stability threshold, the number of measurements is automatically increased or a retest is marked.

[0053] The structured test task file is preferably an Excel spreadsheet, but CSV or other structured spreadsheet files are also acceptable. The task file must include at least the test point number, switch board number, on-board channel number, differential pair number, positive / negative terminal field, design reference length, allowable length deviation for a single trace, allowable length difference for differential pairs, expected end condition, and test sequence. The host computer uses the differential pair number and positive / negative terminal field as the basis for formal pairing and performs consistency verification using identifiers such as P / N in the test point name.

[0054] The FPGA control module is preferably responsible for real-time switching control, excitation timing, sampled data reception, equivalent time waveform reconstruction, and propagation time extraction. The data processing module is preferably implemented by a local host computer connected via PCIe, used to call calibration parameters, calculate trace lengths, perform differential analysis, and generate test reports. Ethernet and USB ports can be used for task import, result export, or remote transmission. The data processing module can also be integrated into a processor or industrial computer within the chassis.

[0055] The calibration conversion lengths of the two traces under test for the same differential pair are respectively and The difference in length is when When the difference is not greater than the allowed length difference in the task file, the output difference is of equal length and acceptable; when When the difference exceeds the allowable length, the shorter trace is identified, and its required theoretical compensation electrical length ΔLe is output. Preferably, ΔLe is equal to the difference between the calibrated converted lengths of the two traces; when the process sets a target margin, a preset correction amount can be added to ΔLe.

[0056] The theoretical electrical compensation length is not directly equivalent to the physical length of the compensating conductor. When the unit physical length of the compensating conductor corresponds to an electrical length of η, the physical length of the compensating conductor can be calculated as follows: The conversion is performed. The compensating wires can be flying wires, jumpers, bonding wires, or other conductive connecting wires soldered to the corresponding connection positions on the probe card. The specific materials, wire diameters, and arrangement methods are determined according to the probe card process. The testing machine itself does not include an automatic soldering mechanism.

[0057] The test report should at least record the differential pair number, the numbers of the two test points, the switchboard and channel number, the incident and reflected edge times, the round-trip propagation time, the calibration parameter version, the calibration conversion length, the differential length difference, the allowable length difference, the pass / fail status, the test points for shorter traces, the theoretical compensation electrical length, and any abnormal conditions. The original handover plan can automatically generate an Excel test report.

[0058] This test method is performed with the probe card powered off and in a passive state. Before the test begins, the external power supply and function signals of the probe card are turned off. The safety protection module detects the static voltage of the differential trace pair under test through the static voltage detection unit; the discharge unit releases residual charge; the test interlock unit only allows the switch board to select and the step excitation module to output when the static voltage meets the safety conditions. If an over-limit voltage is detected, the test is prohibited and an alarm is output.

[0059] A complete batch testing process is as follows: import the task file; perform equipment and probe card safety checks; perform or verify online calibration; select the target differential pair according to the test order; wait for the selected network to stabilize; perform successive relative delay dual-channel sampling; reconstruct the equivalent time waveform; extract the reflection time and complete the validity judgment of repeated measurements; calculate the length of the two traces, the length difference, and the theoretical compensation electrical length; save the results and switch to the next differential pair; generate a test report after all tasks are completed.

[0060] In one chassis embodiment disclosed in the original specification, a maximum of 16 switch boards are installed, each connecting 288 single-ended TP test points, covering 4608 single-ended traces in the entire device. Through automatic addressing and differential pair scanning, the number of manual connections can be reduced. Combined with equivalent time reconstruction and layered calibration, when the equipment, fixture, and test object meet the design requirements, a trace length measurement accuracy within 5mm can be achieved. This accuracy is a performance indicator of the embodiment and does not constitute a limitation on the scope of the claims.

[0061] It should be understood that numerous specific implementation decisions can be made during the development of any practical implementation, such as in any engineering or design project. Such development efforts may be complex and time-consuming, but for those skilled in the art who benefit from this disclosure, the development effort will be a routine work of design, manufacturing, and production without requiring much experimentation.

[0062] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-precision probe card layout trace group length testing machine, characterized in that, It includes a backplane, an FPGA control module, a clock module, a step excitation module, a dual-channel high-speed sampling module, at least one switch board, a probe card connection assembly, a calibration module, and a data processing module; The backplane is provided with a first test branch, a second test branch, and a board-level connection interface for connecting the switch board; The step excitation module has a first step excitation output terminal and a second step excitation output terminal that are respectively connected to the first test branch and the second test branch. The dual-channel high-speed sampling module has a first sampling channel and a second sampling channel that are respectively connected to the first test branch and the second test branch; Each of the switchboards is provided with multiple test point connection terminals, a first common test terminal connecting the first test branch, a second common test terminal connecting the second test branch, and a first and second selection networks that are independently controlled. The first and second selection networks are used to select two target test points corresponding to the same differential trace pair from the multiple test point connection terminals. The probe card connection assembly includes a multi-channel shielded cable assembly, an adapter board, and a test fixture, which are used to connect the multiple test point connection terminals to the test points of an external probe card under test. The calibration module includes at least two sets of differential reference paths that can be selectively connected to the first test branch and the second test branch. The two reference traces in each set of differential reference paths have the same known electrical length, and the known electrical lengths of different sets of differential reference paths are different. The FPGA control module is used to control the switch board to select the target differential trace pair, control the step excitation module to output the step excitation signal in multiple excitation cycles and change the relative time delay between the step excitation signal and the sampling clock one by one, control the dual-channel high-speed sampling module to collect the reflection response data of the two traces under test, and reconstruct the equivalent time sampling waveform and determine the round-trip propagation time based on the relative time delay corresponding to each excitation cycle. The data processing module is used to calculate the calibration conversion length, differential length difference, and theoretical compensation electrical length of the two traces under test based on the calibration parameters generated by the calibration module, and to generate a test report.

2. The high-precision probe card layout trace group length testing machine according to claim 1, characterized in that, The step excitation module includes a high-speed comparator and a threshold setting module. The threshold setting module includes a digital-to-analog converter controlled by the FPGA control module, which is used to provide a comparison threshold to the high-speed comparator before the test begins. The first step excitation output terminal and the second step excitation output terminal are two complementary output terminals of the high-speed comparator, used to output a first step excitation signal and a second step excitation signal with opposite polarities and corresponding timing.

3. The high-precision probe card layout trace group length testing machine according to claim 1, characterized in that, The FPGA control module includes a timing control unit and a programmable delay unit or a programmable phase adjustment unit; The timing control unit controls the programmable delay unit or the programmable phase adjustment unit according to a preset delay sequence, so that the relative delay positions corresponding to different excitation cycles cover the time window to be reconstructed. The FPGA control module performs timing rearrangement and interpolation on the sampled data of multiple excitation cycles according to the relative delay, to obtain an equivalent time sampling waveform with a time resolution higher than the actual sampling interval of the dual-channel high-speed sampling module.

4. The high-precision probe card layout trace group length testing machine according to claim 1, characterized in that, The first gating network and the second gating network each include a plurality of controlled switch units, wherein the controlled switch unit is a relay; The FPGA control module selects the target switch board through the serial control branch corresponding to each switch board, and sends the board channel control information to the target switch board, so that at the same time the first gating network and the second gating network respectively connect a target test point to the first common test terminal and the second common test terminal. The corresponding test branches on the backplane, from the step excitation module and the dual-channel high-speed sampling module to each board-level connection interface, are arranged with the same design electrical length and preset characteristic impedance.

5. The high-precision probe card layout trace group length testing machine according to claim 1, characterized in that, The calibration module also includes a board-level reference channel and an external calibration interface; The data processing module is used to establish round-trip propagation time coefficients and fixed path delays corresponding to unit single-trip electrical lengths for the first test branch and the second test branch, respectively, and, based on board-level calibration parameters, call the channel delay offset of each test point channel relative to the board-level reference channel. The external calibration interface is used to connect to an external standard test board to verify the overall test path of the device, which includes the switch board, the multi-channel shielded cable assembly, the adapter board, and the test fixture.

6. The high-precision probe card layout trace group length testing machine according to claim 1, characterized in that, It also includes a security protection module and a communication interface; The safety protection module includes a static voltage detection unit, a discharge unit, and a test interlock unit, which are used to allow the switch board to be turned on and the step excitation module to output when the probe card is in a power-off and passive state and the static voltage of the differential wiring pair under test meets the preset safety conditions. The data processing module is connected to the FPGA control module through the communication interface and is used to import structured test task files containing differential pairing relationships, test point and switch board channel mapping relationships, design reference length and allowable length difference, and output round-trip propagation time, calibration conversion length, differential length difference, qualified status and theoretical compensation electrical length.

7. A method for testing the length of a high-precision probe card layout trace group using the testing machine described in any one of claims 1 to 6, characterized in that, include: Obtain the structured test task file, establish the mapping relationship between each differential trace pair in the probe card under test and the test channel of the switch board, and confirm that the probe card under test is in a power-off and passive state. Obtain validated calibration parameters and common test path reflection characteristics, wherein the calibration parameters are obtained by measuring at least two sets of differential reference paths with different known electrical lengths, or are retrieved from stored and validated calibration parameters; According to the mapping relationship, the first gating network and the second gating network are controlled to select the two test traces of the target differential trace pair respectively; The timing-corresponding step excitation signal is output to the two traces under test in multiple excitation cycles, the relative time delay between the step excitation signal and the sampling clock is changed successively, and the reflection response data of the two traces under test are collected by a dual-channel high-speed sampling module. Based on the relative time delay corresponding to each excitation cycle, the reflection response data is time-sequence rearranged and interpolated to reconstruct the equivalent time sampling waveforms corresponding to the two traces under test. The end reflection search time window is determined according to the design reference length. Fixed reflections corresponding to the common test path are excluded based on the reflection characteristics of the common test path. The incident step edge and end reflection edge are determined from each equivalent time sampling waveform to obtain the corresponding round-trip propagation time. Call the calibration parameters corresponding to the test branch, switchboard and test point channel, calculate the calibration conversion length of the two traces to be tested respectively, calculate the differential length difference and compare it with the allowable length difference, output the qualified status and the theoretical compensation electrical length required for the shorter trace, and generate a test report.

8. The high-precision probe card layout trace group length testing method according to claim 7, characterized in that, For the j-th test branch, where j is 1 or 2, let the known one-way electrical lengths of the two sets of differential reference paths be respectively... and The corresponding measured round-trip propagation times are respectively and Then the round-trip propagation time coefficient corresponding to a unit one-way electrical length is: Fixed path delay is: For the target test point channel measured via the j-th test branch, let its round-trip propagation time be... Channel delay offset is The calibration conversion length of the trace to be tested is: 。 9. The high-precision probe card layout trace group length testing method according to claim 7, characterized in that, Baseline correction is performed on the waveforms of the two sampling channels respectively, and polarity normalization is performed on the waveforms of the two sampling channels according to the direction of change of the incident step. Within the end reflection search time window, the end reflection edge is determined by combining the arrival time, amplitude, polarity, correlation with the calibration reflection characteristics, and waveform continuity of the candidate reflection edge. The edge moment is taken as the position where the change in edge amplitude reaches a preset proportion, and fine time is obtained by interpolation of adjacent equivalent sampling points. Repeatedly perform a complete measurement on the same differential trace pair, discard results that do not meet the validity conditions, calculate the statistical results, and perform a retest or mark as abnormal when the dispersion exceeds the preset threshold.

10. The high-precision probe card layout trace group length testing method according to claim 7, characterized in that, The test report shall include at least the differential pair number, the two test point numbers, the switch board number, the channel number within the board, the round-trip propagation time, the calibration parameter identifier used, the calibrated converted lengths of the two traces under test, the differential length difference, the allowable length difference, the pass / fail status, the test point corresponding to the shorter trace, and the theoretical compensation electrical length. When the electrical length corresponding to the unit physical length of the compensating conductor is pre-stored, the actual physical length of the compensating conductor is calculated based on the theoretical compensating electrical length.

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