Display panel and driving method thereof

Abstract

The application belongs to the technical field of display driving, and particularly relates to a display panel and a driving method thereof. The display panel comprises a color film substrate, an array substrate, a backlight module, a timing controller, a gate driving circuit and a source driving circuit. The application realizes adaptive switching between a normal mode and a high refresh rate mode on the same display panel through the synergistic effect of retaining the field sequential output of the color filter and the timing controller, the simultaneous driving of multiple rows of the gate driving circuit and the simultaneous output of multiple columns of the same color of the source driving circuit, and taking into account the performance requirements of high image quality and high refresh rate.

Description

Technical Field

[0001] This disclosure belongs to the field of display driver technology, specifically relating to a display panel and its driving method. Background Technology

[0002] Dual-mode display technology can be compatible with both normal mode and high refresh rate mode on the same display panel, meeting the needs of users in various scenarios from office audio-visual to e-sports games, and has become an important development direction in the field of high-end displays.

[0003] To further improve refresh rates, dual-mode display solutions typically introduce Field Sequential Color (FSC) technology for compression in the time dimension. However, these FSC solutions either remove the color filter, leading to color crosstalk and color separation issues, or retain the color filter but are incompatible with both normal and FSC modes, making it difficult to achieve both high image quality and high refresh rate on a single panel.

[0004] Therefore, how to achieve adaptive switching between normal mode and high refresh rate mode on the same display panel while retaining the color filter has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a display panel and its driving method. By retaining the color filter, the field sequence output of the timing controller, the simultaneous driving of multiple rows of the gate driving circuit, and the simultaneous output of multiple columns of the same color by the source driving circuit, this application achieves adaptive switching between normal mode and high refresh rate mode on the same display panel, thus taking into account the performance requirements of high image quality and high refresh rate.

[0006] In a first aspect, this application provides a display panel, the display panel comprising: a color filter substrate, wherein a color filter is disposed on the color filter substrate; an array substrate, disposed opposite to the color filter substrate, wherein the array substrate is disposed with multiple data lines, multiple scan lines and multiple pixel units arranged in an array, each pixel unit including a red sub-pixel, a green sub-pixel and a blue sub-pixel; a backlight module, including multiple backlight units disposed corresponding to the multiple pixel units, each backlight unit including a red LED, a green LED and a blue LED; and a timing controller, connected to the backlight module and configured to: in a high refresh rate mode, sequentially output red field sequence data, green field sequence data and blue field sequence data within one frame period, and sequentially drive the red LED in the backlight module. The LEDs, including the green and blue LEDs, emit light. A gate driving circuit, connected to the multiple scan lines, is configured to simultaneously drive M adjacent scan lines in a high refresh rate mode. A source driving circuit, connected to the timing controller and the multiple data lines, is configured to: in the high refresh rate mode, during the red field period, convert the red field sequence data into a red grayscale voltage and simultaneously output it to the data lines corresponding to N columns of red sub-pixels; during the green field period, convert the green field sequence data into a green grayscale voltage and simultaneously output it to the data lines corresponding to N columns of green sub-pixels; and during the blue field period, convert the blue field sequence data into a blue grayscale voltage and simultaneously output it to the data lines corresponding to N columns of blue sub-pixels; wherein M and N are integers greater than 1.

[0007] Secondly, this application provides a driving method for a display panel. In a high refresh rate mode, the driving method includes: a timing controller sequentially outputting red field sequence data, green field sequence data, and blue field sequence data within one frame period, and sequentially driving the red LED, green LED, and blue LED in the backlight module to emit light; a gate driving circuit simultaneously driving adjacent M rows of scan lines; a source driving circuit converting the red field sequence data into red grayscale voltage during the red field period and simultaneously outputting it to the data lines corresponding to N columns of red sub-pixels, converting the green field sequence data into green grayscale voltage during the green field period and simultaneously outputting it to the data lines corresponding to N columns of green sub-pixels, and converting the blue field sequence data into blue grayscale voltage during the blue field period and simultaneously outputting it to the data lines corresponding to N columns of blue sub-pixels.

[0008] The technical solution provided in this application has at least the following beneficial effects:

[0009] This application achieves high-quality display at full resolution by coordinating a timing controller, gate drive circuit, and source drive circuit while retaining the color filter. It also performs resolution compression simultaneously in both time and spatial dimensions, resulting in a 3×M×N multiplier refresh rate increase without altering the physical bandwidth of the data link. Furthermore, by switching the data format from concurrent RGB to monochromatic field-sequential transmission, this application ensures that each data packet is valid, avoiding bandwidth waste due to invalid color channels and eliminating the limitation of data link overload on refresh rate improvement. Simultaneously, the retention of the color filter prevents color crosstalk and color separation issues, guaranteeing display quality in high refresh rate mode.

[0010] Therefore, by retaining the synergistic effect of the color filter, the field sequence output of the timing controller, the simultaneous multi-row driving of the gate driving circuit, and the simultaneous output of multiple columns of the same color by the source driving circuit, this application achieves adaptive switching between normal mode (high image quality) and high refresh rate mode (ultra-high refresh rate) on the same display panel, taking into account the performance requirements of high image quality and high refresh rate, thereby meeting the usage requirements of the display panel in multiple scenarios. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 The diagram shown illustrates the driving mechanism of a white backlight combined with a colored green light sheet, as provided by related technologies.

[0013] Figure 2 The diagram shown is a schematic of the RGB three-color backlight driver provided by related technologies.

[0014] Figure 3 The image shown is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application.

[0015] Figure 4 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0016] Figure 5 The diagram shown is a driving timing diagram in normal mode provided by an embodiment of this application.

[0017] Figure 6 The diagram shown is a driving timing diagram for a high refresh rate mode provided in an embodiment of this application.

[0018] Figure 7 The image shown is a schematic diagram of a pixel image in normal mode according to an embodiment of this application.

[0019] Figure 8 The image shown is a schematic diagram of a pixel image in a high refresh rate mode provided in an embodiment of this application.

[0020] Figure 9 The image shown is a schematic diagram of pixel brightness and darkness during the red field in a high refresh rate mode according to an embodiment of this application.

[0021] Figure 10 The diagram shown is a schematic representation of pixel brightness and darkness during the green field in a high refresh rate mode according to an embodiment of this application.

[0022] Figure 11 The diagram shown is a schematic representation of pixel brightness and darkness during the blue field in a high refresh rate mode according to an embodiment of this application.

[0023] Figure 12 The diagram shown is a schematic diagram of a source drive circuit provided in an embodiment of this application.

[0024] Figure 13 The diagram shown is a schematic representation of the correspondence between a sub-pixel and an output channel provided in an embodiment of this application.

[0025] Figure 14 The diagram shown is a schematic diagram of the mapping relationship after pixel rearrangement provided in an embodiment of this application.

[0026] Figure 15 The diagram shown is a schematic representation of a pixel-copying mapping relationship provided in an embodiment of this application.

[0027] Figure 16 The diagram shown is a schematic diagram of another source drive circuit provided in an embodiment of this application.

[0028] Figure 17 The diagram shown is a schematic diagram of a data selection circuit provided in an embodiment of this application.

[0029] Figure 18 The diagram shown is a schematic diagram of the conduction of a data selection circuit during the red field period according to an embodiment of this application.

[0030] Figure 19 The diagram shown is a schematic of the conduction of a data selection circuit during the green field according to an embodiment of this application.

[0031] Figure 20 The diagram shown is a schematic of the conduction of a data selection circuit during the blue field period according to an embodiment of this application.

[0032] Figure 21The diagram shown is a schematic diagram of another data selection circuit provided in an embodiment of this application.

[0033] Figure 22 The diagram shown is a schematic diagram of a data selection circuit forming a charge exchange channel according to an embodiment of this application.

[0034] Figure 23 The diagram shown is a flowchart illustrating a driving method for a display panel according to an embodiment of this application.

[0035] Figure 24 The diagram shown is a schematic diagram of the first backlight driving timing provided in the embodiment of this application.

[0036] Figure 25 The diagram shown is a second backlight driving timing diagram provided in an embodiment of this application.

[0037] Figure 26 The figure shown is a schematic diagram of the third backlight driving timing provided in the embodiment of this application.

[0038] Figure 27 The figure shown is a schematic diagram of the fourth backlight driving timing provided in the embodiment of this application.

[0039] Explanation of reference numerals in the attached figures: 10. Display panel; 100. Color filter substrate; 110. Color filter; 200. Array substrate; 210. Pixel unit; 300. Liquid crystal layer; 400. Backlight module; 410. Backlight unit; 500. Timing controller; 600. Gate drive circuit; 700. Source drive circuit; 710. Data buffer; 711. Data receiver; 712. Sampling memory; 713. Shift register; 720. Pixel rearranger; 730. Pixel replicator; 740. Voltage output device; 741. Holding memory; 742. Level shifter; 743. Digital-to-analog converter; 744. Output buffer; 800. Data selection circuit; M0, main switch; Mr, first switch; Mg, second switch; Mb, third switch. Detailed Implementation

[0040] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0041] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0042] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0043] In related technologies, thin-film transistor liquid crystal displays (TFT-LCDs) use the principle of spatial color mixing to achieve color display (i.e., normal mode), such as... Figure 1 As shown, this mode uses a constantly lit white backlight combined with a color filter to filter light into specific wavelengths, which are then spatially represented by tiny red, green, and blue sub-pixels. Color display is achieved by controlling the grayscale brightness of each sub-pixel separately.

[0044] In addition, to further improve transmittance and pixel density, methods such as... have been proposed. Figure 2 The field-sequential color (FSC) technology is shown. In this technology, color filters are removed, and alternating RGB backlighting combined with time-division deflection of the liquid crystal is used to achieve temporal color mixing, relying on the persistence of vision in the human eye. However, current FSC technology suffers from severe color crosstalk and color separation problems.

[0045] Current dual-mode display technology can only compress resolution in the spatial dimension, supporting a maximum frequency multiplication of 4. For example, a display panel with a resolution of 3840×2160 and a refresh rate of 240Hz can achieve a resolution of 1920×1080 and a refresh rate of 960Hz through spatial compression. To further increase the refresh rate, FSC technology needs to be introduced in the temporal dimension. However, this faces challenges such as the inability of the driving architecture to simultaneously support normal mode and FSC mode after retaining the color filter, and bandwidth overload caused by the transmission of invalid color channels in the display interface.

[0046] Therefore, in order to solve the above problems, this application provides a display panel, specifically including the following embodiments: Figure 3 The image shown is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application; as shown Figure 3As shown, the display panel 10 provided in this embodiment includes a color filter substrate 100 and an array substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the color filter substrate 100 and the array substrate 200. Specifically, a color filter 110 is disposed on the color filter substrate 100, including a red filter, a green filter and a blue filter. In normal mode, after the white backlight passes through the liquid crystal layer 300, it is filtered by the color filter 110 into three specific wavelengths of light: red, green and blue, which are emitted from the red sub-pixel, the green sub-pixel and the blue sub-pixel, respectively, thereby realizing spatial color mixing.

[0047] In this embodiment, the array substrate 200 is provided with multiple data lines, multiple scan lines, and multiple pixel units 210 arranged in an array. Each pixel unit 210 includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Specifically, the data lines extend along the column direction and are used to transmit the grayscale voltage output by the source driving circuit 700. The scan lines extend along the row direction and are used to transmit the scan signal output by the gate driving circuit 600. The three sub-pixels in each pixel unit 210 share a pixel area and are controlled by their respective independent thin-film transistor switches. In addition, each red sub-pixel, each green sub-pixel, and each blue sub-pixel are respectively configured to correspond to a red filter, a green filter, and a blue filter.

[0048] like Figure 3 As shown, the display panel 10 in this embodiment also includes a backlight module 400, which in turn includes a plurality of backlight units 410 corresponding to the plurality of pixel units 210. Each backlight unit 410 includes a red LED, a green LED, and a blue LED. The LEDs of the three colors can be independently controlled to emit light, so that the backlight color can be switched according to the current display mode. For example, in normal mode, the three colors emit light at the same time to form a white backlight, and in high refresh rate mode, the three colors emit light in sequence to achieve field-sequential color illumination.

[0049] Figure 4 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application; as follows: Figure 4 As shown, the display panel 10 in this embodiment also includes a timing controller 500, a gate driving circuit 600, and a source driving circuit 700. Specifically, the timing controller 500 is connected to the backlight module 400, the gate driving circuit 600, and the source driving circuit 700, respectively, and is used to output data signals to the source driving circuit 700, output control signals to the gate driving circuit 600, and control the light emission timing of each color LED in the backlight module 400. In addition, the gate driving circuit 600 is connected to multiple scan lines and is used to drive the scan lines line by line or simultaneously. The source driving circuit 700 is connected to multiple data lines and is used to convert the data signals into grayscale voltages and output them to the data lines.

[0050] The operation of the display panel 10 in this embodiment is described below: (1) In normal mode: the timing controller 500 drives all red, green, and blue LEDs in the backlight module 400 to emit light simultaneously, producing white backlight; at this time, the gate drive circuit 600 drives multiple scan lines row by row, that is, within one frame period, it outputs gate conduction signals sequentially from the first line to the last line, turning on the pixel unit 210 of each line row by row, ensuring that each pixel unit 210 gets one data writing opportunity in each frame, thereby realizing a complete screen update. Figure 5 As shown, in normal mode, a vertical synchronization signal is triggered once per frame cycle, and the display panel 10 refreshes a complete frame within that frame cycle.

[0051] Meanwhile, the image data output by the timing controller 500 is in RGB concurrent format, meaning that the red, green, and blue data of each pixel are packaged together and transmitted simultaneously to the source driver circuit 700. After receiving the RGB concurrent format image data, the source driver circuit 700 converts the digital grayscale value into the corresponding analog grayscale voltage through its internal digital-to-analog converter and outputs it to the data line corresponding to each sub-pixel. During the line-by-line scanning process, when the gate drive signal is turned on, the thin-film transistor of each row of pixel unit 210 is turned on, and the grayscale voltage on the data line is written to the pixel electrode, driving the liquid crystal molecules to deflect to the corresponding angle, thereby modulating the backlight transmittance and realizing the display of different grayscale levels. After all rows have completed the data writing in sequence, a complete color image is formed.

[0052] In normal mode, the display panel 10 operates at full resolution and high image quality, which is suitable for scenarios with high image quality requirements such as office work and audio-visual entertainment. This mode is also known as high image quality mode.

[0053] (2) In high refresh rate mode: The timing controller 500 outputs red field sequence data, green field sequence data, and blue field sequence data sequentially within one frame period. Specifically, during the red field, the timing controller 500 only outputs the red brightness data of all pixels in the frame image, and does not output green and blue data; during the green field, the timing controller 500 only outputs the green brightness data of all pixels; during the blue field, the timing controller 500 only outputs the blue brightness data of all pixels. Thus, a complete color image frame is divided into three monochrome subfields for sequential transmission. The data volume of each subfield is only one-third of the data volume of a complete frame in normal mode, so the transmission time of each subfield is also shortened to one-third of that in normal mode.

[0054] At the same time, the timing controller 500 sequentially drives the red, green, and blue LEDs in the backlight module 400 to emit light; such as Figure 6As shown, during the red field, the backlight module 400 emits red light. Combined with the deflection state of the red field data in the liquid crystal layer 300, the red light passes through the liquid crystal layer 300 and the color filter 110, forming a red sub-field image. During the green field, the backlight module 400 emits green light; during the blue field, the backlight module 400 emits blue light. The three monochrome sub-fields switch rapidly in time. During the red field, only the red sub-pixels have brightness data, while the green and blue sub-pixels are black; during the green field, only the green sub-pixels have brightness data; and during the blue field, only the blue sub-pixels have brightness data. Relying on the persistence of vision, the three monochrome sub-fields are visually superimposed into a complete color image.

[0055] It should be noted that the backlight emission sequence corresponds to the data output sequence, i.e., red LEDs emit light during the red field, green LEDs emit light during the green field, and blue LEDs emit light during the blue field. However, the timing alignment between the backlight and the data field can be flexibly adjusted according to actual needs, such as... Figure 6 As shown, in this embodiment, the corresponding color LED is driven to emit light only after the image data has been output for a period of time. This ensures that the LED emits light only after the pixel has finished charging, avoiding misdisplay. In addition, in high refresh rate mode, only one color of data needs to be processed per frame cycle, reducing the GPU rendering time to one-third of that in normal mode.

[0056] To further break through the refresh rate ceiling in terms of time dimension, the high refresh rate mode also simultaneously enables resolution compression in the spatial dimension; specifically: ① In the vertical direction: The gate drive circuit 600 simultaneously drives adjacent M rows of scan lines, that is, it turns on the thin-film transistors of M rows of pixel units 210 at once, so that these M rows of pixel units 210 simultaneously receive the grayscale voltage transmitted by the data lines. Since the M rows of pixel units 210 write the same data, the vertical resolution is reduced to 1 / M of the original, but the vertical scan time is also shortened to 1 / M of the original. Figure 7 As shown, an image of H×V=2×4 complete pixels is displayed. The source drive circuit 700 also receives image data of 8 complete pixels, with pixels P1~P8 displayed as (R1,G1,B1)~(R8,G8,B8) respectively; as Figure 8 As shown, in the high refresh rate mode of this embodiment, the vertical direction is compressed from 2 rows to 1 row.

[0057] ② In the horizontal direction: The source drive circuit 700 simultaneously outputs each data signal to the data lines corresponding to the N columns of sub-pixels of the same color, meaning one data signal simultaneously drives N columns of sub-pixels of the same color. Since the N columns of sub-pixels of the same color receive the same grayscale voltage, the horizontal resolution is reduced to 1 / N of its original value. However, the amount of data transmitted in the horizontal direction is also reduced to 1 / N of its original value; that is, the time required to transmit N columns of data is now reduced to transmitting only one column of data. Figure 8 As shown, the horizontal direction is compressed from 4 columns to 2 columns.

[0058] Therefore, in the high refresh rate mode of this embodiment, the time-division transmission of three monochrome fields in the time dimension increases the refresh rate by 3 times, and the horizontal N-fold compression and vertical M-fold compression in the spatial dimension increase the refresh rate by M×N times, for a total refresh rate increase of 3×M×N. Taking M=2 and N=2 as an example, the horizontal and vertical compressions in the spatial dimension are each 2 times, increasing the refresh rate by 4 times. Combined with the 3 times compression in the time dimension, the total frequency is increased by 12 times.

[0059] In the high refresh rate mode of this embodiment, such as Figure 9 As shown, during the red field, only the red subpixels have brightness data, while the green and blue subpixels are both black; as Figure 10 As shown, during the green field, only the green subpixels have brightness data, while the red and blue subpixels are both black; as Figure 11 As shown, during the blue field, only the blue subpixels have brightness data, while the red and green subpixels are both black; finally, the data from the three fields are superimposed to form a complete color image.

[0060] In normal operating mode, display panel 10 operates at a resolution of 3840×2160 and a refresh rate of 240Hz, employing spatial color mixing principles with 100% bandwidth utilization. In high refresh rate mode (e.g., M=2, N=2), display panel 10 operates at a resolution of 1920×1080 and a refresh rate of 2880Hz, employing a display principle combining temporal color mixing and spatial compression, while maintaining 100% bandwidth utilization. Therefore, this embodiment achieves at least a 12x increase in refresh rate without changing the physical bandwidth of the data link, enabling the same display panel 10 to flexibly switch between normal mode (high image quality, low refresh rate) and high refresh rate mode (low resolution, ultra-high refresh rate), meeting the needs of various usage scenarios from office audio-visual to e-sports games.

[0061] In summary, this application, by retaining the color filter 110 and setting the timing controller 500, gate drive circuit 600, and source drive circuit 700 to work together, enables the display panel 10 to achieve high-quality display at full resolution. It can also perform resolution compression in both time and space dimensions, thereby achieving a refresh rate increase of 3×M×N times without changing the physical bandwidth of the data link. Furthermore, this application switches the data format from RGB concurrent transmission to monochrome field sequence transmission, ensuring that each data packet is valid data, avoiding bandwidth waste due to the transmission of invalid color channels, and eliminating the limitation of data link overload on refresh rate improvement. At the same time, due to the retention of the color filter 110, color crosstalk and color separation problems are avoided, ensuring the display quality in high refresh rate mode. Therefore, by retaining the synergistic effect of the color filter 110, the field sequence output of the timing controller 500, the multi-row simultaneous drive of the gate drive circuit 600, and the simultaneous output of multiple columns of the same color by the source drive circuit 700, this application achieves adaptive switching between normal mode (high image quality) and high refresh rate mode (ultra-high refresh rate) on the same display panel 10, taking into account the performance requirements of high image quality and high refresh rate, thereby meeting the usage requirements of the display panel 10 in multiple scenarios.

[0062] Figure 12 The diagram shown is a schematic representation of a source drive circuit according to an embodiment of this application; as follows: Figure 12 As shown, the source drive circuit 700 of this embodiment includes a data buffer 710, connected to the timing controller 500, for receiving and buffering the data signals output by the timing controller 500. Specifically, the data buffer 710 includes a data receiver 711, a sampling memory 712, and a shift register 713. The data receiver 711 receives differential serial signals (such as LVDS or mini-LVDS signals) sent by the timing controller 500, recovers the sampling clock from the serial data through an internal clock data recovery circuit, and unpacks the serial data into parallel data. The sampling memory 712 is connected to the data receiver 711 and, under the control of the shift register 713, stores and temporarily stores the unpacked parallel data bit by bit. The shift register 713, under the control of the sampling clock, generates enable signals to sequentially select each memory cell, ensuring that data is stored sequentially into each memory cell of the sampling memory 712.

[0063] For example, such as Figure 13As shown, taking a row of 4 pixel units 210, each pixel unit 210 contains three sub-pixels: R, G, and B, for a total of 12 columns of sub-pixels, and the source drive circuit 700 has 12 output channels, namely CH1~CH12. In normal mode, the differential signal received by the data receiver 711 is unpacked to obtain 12 sub-pixel data: R1, G1, B1, R2, G2, B2, R3, G3, B3, R4, G4, B4. The sampling memory 712 stores these 12 data sequentially under the control of the shift register 713, and all 12 memory units are filled. In high refresh rate mode, taking the red field as an example, the timing controller 500 only outputs the red field sequence data. After the data receiver 711 unpacks the data, it obtains two red data: R1 and R3. The sampling memory 712 only stores these two valid data, and the remaining 10 memory units are either empty or filled with default values.

[0064] like Figure 12 As shown, the source drive circuit 700 in this embodiment also includes a pixel reorderer 720, connected to the data buffer 710, used to sequentially map the monochrome field data output by the data buffer 710 to the corresponding output channels in high refresh rate mode. Specifically, the pixel reorderer 720 receives a mode selection signal sent by the timing controller 500, identifies the current display mode according to the signal, and selects the corresponding data mapping rule. In normal mode, the pixel reorderer 720 directly maps the data to the corresponding output channels according to the RGB arrangement order, without changing the arrangement order of the data. In high refresh rate mode, the pixel reorderer 720 identifies the currently received data as monochrome field data, and blocks the conventional RGB serial unpacking rule, that is, it no longer unpacks the data in groups of 3 RGB pixels, but treats all input data as a data stream of the same color channel and sequentially maps it to the output channel of the corresponding color sub-pixel.

[0065] For example, such as Figure 14 As shown, during the red field, the two red data points R1 and R3 are mapped to the 1st and 7th output channels, respectively. R1 corresponds to the red sub-pixel of the first pixel unit 210, and R3 corresponds to the red sub-pixel of the third pixel unit 210. The remaining output channels are left empty. The mapping method during the green and blue fields is the same as that during the red field, and will not be repeated here. It should be explained that the red data points R2 and R4 are not sent in this example because, under horizontal 2x replication, adjacent first and second pixel units 210 share the R1 data, and third and fourth pixel units 210 share the R3 data. Therefore, the timing controller 500 only needs to send the two red data points R1 and R3.

[0066] Thus, the pixel rearranger 720 achieves correct data mapping under different data formats, that is, sequential transmission in RGB concurrent format and rearrangement by color channel in monochrome field order format, so that the source drive circuit 700 can be compatible with two completely different data formats.

[0067] Continue as Figure 12 As shown, the source drive circuit 700 in this embodiment also includes a pixel replicator 730, connected to the pixel rearranger 720. In response to a replication ratio enable signal sent by the timing controller 500, the pixel replicator 730 simultaneously replicates each data signal output by the pixel rearranger 720 to the output channel corresponding to the N columns of sub-pixels of the same color. Specifically, the pixel replicator 730 receives a replication ratio enable signal (such as 2x, 3x, or 4x replication) sent by the timing controller 500 and internally contains a CMOS cross-connection switch array. This switch array is configured with different fan-out topologies according to the replication ratio enable signal: a 1:1 topology in pass-through mode, a 1-to-2 topology in 2x replication mode, a 1-to-3 topology in 3x replication mode, and a 1-to-4 topology in 4x replication mode. The CMOS cross-connection switch array is a purely physical layer electrical signal connection network, where the same grayscale voltage is simultaneously routed to multiple output wires at the same time, without involving clock delay or digital domain data processing.

[0068] Let's take the 2x replication mode as an example. Figure 15 As shown, in the valid data output by the pixel rearranger 720, R1 is in channel 1 and R3 is in channel 7. The pixel replicator 730 routes R1 from channel 1 to output channels 1 and 4 simultaneously, and routes R3 from channel 7 to output channels 7 and 10 simultaneously, expanding the red field data, which originally had only 2 valid inputs, to 4 valid data. At this time, the data of output channels CH1 and CH4 are both R1, the data of output channels CH7 and CH10 are both R3, and the remaining channels are empty during the red field.

[0069] Therefore, the pixel replicator 730 realizes the data expansion from a small amount of input data to filling all output channels, and the expansion process is completed at the physical layer without consuming additional clock cycles, so that horizontal pixel replication can be completed at hardware-level speed without affecting the timing margin at high refresh rates.

[0070] Continue as Figure 12 As shown, the source drive circuit 700 in this embodiment also includes a voltage output device 740, which is connected to the pixel replicator 730 and multiple data lines. Under the control of the latch trigger signal sent by the timing controller 500, it latches all channel data output by the pixel replicator 730 in parallel and converts them into grayscale voltages before outputting them to the corresponding data lines.

[0071] In one embodiment, the voltage output unit 740 includes a holding memory 741, a level shifter 742, a digital-to-analog converter 743, and an output buffer 744. The input terminal of the holding memory 741 is connected to the output terminal of the pixel replicator 730, and the number of its storage units is the same as the number of output channels. When the timing controller 500 sends a latch trigger signal, the holding memory 741 latches the data of all input channels simultaneously, ensuring that all channels are updated synchronously. After latching, the level shifter 742 boosts the voltage domain of the digital signal to the operating voltage range required by the digital-to-analog converter 743. The digital-to-analog converters 743 operate in parallel, and each channel's digital-to-analog converter 743 outputs the corresponding analog grayscale voltage according to the input grayscale data through a lookup table. The output buffer 744 amplifies the analog voltage and outputs it to the corresponding data line to drive the capacitive load of the panel data line.

[0072] Therefore, this embodiment uses the pixel rearranger 720 to identify the monochrome field data in the data buffer 710 and shield the conventional RGB unpacking rules, mapping the input monochrome data sequentially to the corresponding color output channels. This allows the source drive circuit 700, originally designed for concurrent RGB format, to correctly receive and process the monochrome field sequence data. Furthermore, the pixel replicator 730 routes a small amount of input data to multiple output channels simultaneously, filling all physical channels without consuming additional clock cycles, thus providing a hardware foundation for horizontal space compression. The voltage output unit 740, under the control of the latch trigger signal, latches all channel data in parallel, ensuring that all output channels are updated simultaneously, avoiding display anomalies caused by asynchronous outputs after data replication.

[0073] Figure 16 The diagram shown is a schematic of another source drive circuit provided in an embodiment of this application; this embodiment and Figure 12 The difference in the source drive circuit 700 shown is that it does not include the pixel rearranger 720 and the pixel replicator 730. The field sequence drive in high refresh rate mode is achieved by multiple data selection circuits 800 set on the panel side.

[0074] like Figure 16 As shown, the source drive circuit 700 of this embodiment includes a data buffer 710 and a voltage output device 740; wherein, the structure and function of the data buffer 710 and the voltage output device 740 are the same as those of the data buffer 710 and the voltage output device 740. Figure 12 The embodiments shown are the same, and will not be described again here.

[0075] In one embodiment, the display panel 10 further includes multiple data selection circuits 800; the input terminal of each data selection circuit 800 is connected to one output channel of the voltage output device 740, and the three output terminals are respectively connected to the three data lines corresponding to the red sub-pixel, green sub-pixel, and blue sub-pixel in the same pixel unit 210. That is, one output channel of the source drive circuit 700 is connected to the three data lines of the same pixel unit 210 in a time-division manner through the data selection circuit 800, rather than being directly connected to a fixed data line.

[0076] Figure 17 This illustrates one specific implementation of the data selection circuit 800. For example... Figure 17 As shown, the data selection circuit 800 includes a first switch Mr, a second switch Mg, and a third switch Mb. The control terminal of the first switch Mr is connected to the timing controller 500 or the source drive circuit 700. Its first terminal is connected to an output channel of the voltage output unit 740, and its second terminal is connected to the data line corresponding to the red sub-pixel. The control terminal of the second switch Mg is connected to the timing controller 500 or the source drive circuit 700. Its first terminal is connected to the first terminal of the first switch Mr (i.e., connected to the same output channel), and its second terminal is connected to the data line corresponding to the green sub-pixel. The control terminal of the third switch Mb is connected to the timing controller 500 or the source drive circuit 700. Its first terminal is connected to the first terminal of the first switch Mr, and its second terminal is connected to the data line corresponding to the blue sub-pixel. The three switches can be implemented using thin-film transistors (TFTs) fabricated on the array substrate 200 using high-mobility materials (such as LTPS or HMO). These TFTs feature fast switching speed and low on-resistance, meeting the requirements of high-frequency switching. The control terminals of the first switch Mr, the second switch Mg, and the third switch Mb are connected to the timing controller 500 or the source drive circuit 700. In other words, the three switches can be turned on and off by the timing controller 500 or by the source drive circuit 700.

[0077] It should be noted that the data selection circuit 800 works by controlling the on / off state of three switching transistors to select which sub-pixel to write the grayscale voltage of the source drive circuit 700's output channel to. At any given time, the data selection circuit 800 only turns on one switching transistor, while the other two are off, thus connecting the output channel to the corresponding data line; for example... Figure 18 As shown, during the red field period, only the first switch Mr is turned on; as Figure 19 As shown, during the green field period, only the second switch Mg is turned on; as Figure 20 As shown, during the blue field, only the third switch Mb is turned on.

[0078] Figure 21This illustrates another specific implementation of the data selection circuit 800; such as Figure 21 As shown, the data selection circuit 800 in Figure 17 The data selection structure shown is supplemented by a master switch M0. Specifically, the control terminal of the master switch M0 is connected to the timing controller 500 or the source drive circuit 700, and its first terminal is connected to one output channel of the voltage output device 740. The second terminal of the master switch M0 is connected to the first terminal of the first switch Mr, the first terminal of the second switch Mg, and the first terminal of the third switch Mb, respectively. Other connection methods for the first switch Mr, the second switch Mg, and the third switch Mb are the same as those for the third switch Mb. Figure 17 The embodiments shown are the same, so they will not be described again here.

[0079] The function of the master switch M0 in this embodiment is as follows: when charge sharing is required, the master switch M0 is first turned off to disconnect the source drive circuit 700 from the panel side, and then the first switch Mr and the second switch Mg (or the second switch Mg and the third switch Mb, the first switch Mr and the third switch Mb) are turned on at the same time, so that a charge exchange path is formed between the storage capacitors of adjacent sub-pixels.

[0080] Specifically, after the red field charging is complete, the storage capacitors of each red sub-pixel store a grayscale voltage representing the red brightness. Before entering the green field, to reduce the power consumption of the source drive circuit 700, such as... Figure 22 As shown, firstly, the main switch M0 is turned off, disconnecting the output channel of the source drive circuit 700 from the panel side to prevent the source drive circuit 700 from being affected during charge neutralization. Then, the first switch Mr and the second switch Mg are simultaneously turned on, forming a charge exchange path between the storage capacitors of the red sub-pixel and the green sub-pixel. Since the red sub-pixel storage capacitor stores a high voltage and the green sub-pixel storage capacitor stores a low voltage (initial state or residual voltage from the previous frame), the charges of the two are neutralized through the charge exchange path, and the voltage tends to be averaged.

[0081] Furthermore, after charge neutralization is complete, the main switch M0 is turned on again, and the first switch Mr and the second switch Mg are turned off. The source drive circuit 700 then begins to output green field data. Since the storage capacitor of the green sub-pixel already contains the neutralized intermediate voltage, the source drive circuit 700 does not need to start driving from zero voltage or the reference voltage, but instead drives from the neutralized intermediate voltage to the target voltage, significantly reducing the required drive current and power consumption. Simultaneously, because some of the charge of the red sub-pixel is transferred to the green sub-pixel, the residual charge of the red sub-pixel is effectively discharged, avoiding image retention or display abnormalities caused by the accumulation of residual charge. Similarly, during the switching process from the green field to the blue field and from the blue field to the red field, charge sharing between the corresponding color sub-pixels is achieved in the same manner, which will not be elaborated further here.

[0082] Figure 23 The diagram shown is a flowchart illustrating a driving method for a display panel according to an embodiment of this application; as follows: Figure 23 As shown, this driving method mainly includes the following steps: In step S100, the timing controller outputs red field sequence data, green field sequence data and blue field sequence data sequentially within one frame period, and drives the red LED, green LED and blue LED in the backlight module to emit light sequentially.

[0083] Step S200: The gate driving circuit simultaneously drives the adjacent M rows of scan lines; Step S300: During the red field period, the source drive circuit converts the red field sequence data into red grayscale voltage and outputs it to the data lines corresponding to the N columns of red sub-pixels. During the green field period, it converts the green field sequence data into green grayscale voltage and outputs it to the data lines corresponding to the N columns of green sub-pixels. During the blue field period, it converts the blue field sequence data into blue grayscale voltage and outputs it to the data lines corresponding to the N columns of blue sub-pixels.

[0084] In one embodiment, when the source driving circuit includes a data buffer, a pixel rearranger, a pixel replicator, and a voltage outputter, the source driving circuit converts red field sequence data into red grayscale voltage during the red field period and outputs it simultaneously to the data lines corresponding to N columns of red sub-pixels; converts green field sequence data into green grayscale voltage during the green field period and outputs it simultaneously to the data lines corresponding to N columns of green sub-pixels; and converts blue field sequence data into blue grayscale voltage during the blue field period and outputs it simultaneously to the data lines corresponding to N columns of blue sub-pixels. This includes: the data buffer receiving and buffering the timing controller sequentially... The output consists of red, green, and blue field sequence data. The pixel rearranger rearranges the monochrome field sequence data cached in the data buffer so that each monochrome field sequence data is mapped to the corresponding output channel. The pixel replicator, based on the replication ratio enable signal sent by the timing controller, simultaneously replicates each data signal output by the pixel rearranger to the output channel corresponding to the N columns of sub-pixels of the same color. Under the control of the latch trigger signal sent by the timing controller, the voltage outputter latches all channel data output by the pixel replicator in parallel and converts them into grayscale voltage before outputting them to the corresponding data line.

[0085] In another embodiment, the source driving circuit includes a data buffer and a voltage output device. When the display panel further includes multiple data selection circuits, the source driving circuit converts red field sequence data into red grayscale voltage during the red field and outputs it simultaneously to the data lines corresponding to N columns of red sub-pixels; converts green field sequence data into green grayscale voltage during the green field and outputs it simultaneously to the data lines corresponding to N columns of green sub-pixels; and converts blue field sequence data into blue grayscale voltage during the blue field and outputs it simultaneously to the data lines corresponding to N columns of blue sub-pixels. This includes: the data buffer receiving and buffering the red field sequence data, green field sequence data, and blue field sequence data sequentially output by the timing controller. Under the control of the latch trigger signal sent by the timing controller, the voltage output unit latches all channel data output by the data buffer in parallel and converts them into corresponding grayscale voltages. During the red field, the data selection circuit only conducts the path of the data line corresponding to the red sub-pixel, so that the red grayscale voltage output by the voltage output unit is transmitted to the red sub-pixel. During the green field, the data selection circuit only conducts the path of the data line corresponding to the green sub-pixel, so that the green grayscale voltage output by the voltage output unit is transmitted to the green sub-pixel. During the blue field, the data selection circuit only conducts the path of the data line corresponding to the blue sub-pixel, so that the blue grayscale voltage output by the voltage output unit is transmitted to the blue sub-pixel.

[0086] It should be noted that the working principle of the above driving method is the same as that of the above display panel, so it will not be repeated here.

[0087] In one embodiment, the timing controller sequentially drives the red, green, and blue LEDs in the backlight module to emit light, specifically including the following driving scheme: (1) such as Figure 24 As shown, the timing controller drives the red LED to continue emitting light from the red field after charging is completed until at least a portion of the green field, and drives the green LED to continue emitting light from the green field after charging is completed until at least a portion of the blue field.

[0088] It should be noted that in traditional FSC technology without a color filter, because there is no color filter to block it, the red field pixel cannot light up the red LED immediately after charging. Instead, a black screen period (i.e., the backlight is turned off) is required. The red LED can only be lit after the pixel voltage reaches the target voltage. Otherwise, the human eye will see unstable brightness changes during the charging process, which leads to a serious loss of PWM duty cycle.

[0089] In this application, because the display panel retains color filters, even if the red LED is still lit during the green field, the green filter above the green sub-pixel will block the red light from passing through, so the red light will not be emitted from the green sub-pixel; similarly, the blue filter above the blue sub-pixel will also block the red light. That is, the light-emitting time of the red LED can be extended into the green field or even the blue field without causing color crosstalk. Therefore, in this embodiment, the timing controller drives the red LED to continue emitting light after the red field charging is completed, extending its light-emitting time to at least a portion of the green field; similarly, it drives the green LED to continue emitting light after the green field charging is completed, extending its light-emitting time to at least a portion of the blue field. By extending the light-emitting time of each color LED, the PWM duty cycle of the backlight is effectively improved, reducing the driving current of the LED LEDs or reducing the number of LEDs at the same target brightness, thereby saving costs.

[0090] (2) such as Figure 25 As shown, the timing controller drives the red LED to continue emitting light after the red field is fully charged, and drives the green LED to emit light after the green field is fully charged, so that the red LED and the green LED emit light simultaneously for at least part of the time period.

[0091] It should be noted that the timing controller drives the red LED to continuously emit light after the red field is fully charged, and simultaneously drives the green LED to light up immediately after the green field is fully charged, so that the red and green LEDs emit light simultaneously for at least part of the time. Due to the presence of the color filter, red light can only pass through the red filter to reach the red sub-pixel, and green light can only pass through the green filter to reach the green sub-pixel, so the two will not interfere with each other. Because this solution has a longer backlight overlap time, the PWM duty cycle is further improved, resulting in higher luminous efficiency, and the cost of LED chips can be further reduced under the same brightness requirements.

[0092] (3) such as Figure 26As shown, after the timing controller completes the charging of all color fields in a frame, it drives the red, green, and blue LEDs to emit light simultaneously.

[0093] Specifically, after the timing controller completes charging of all color fields (red, green, and blue) in a frame, it drives the red, green, and blue LEDs to emit light simultaneously. At this time, the three colors of LEDs are lit at the same time, creating a white or high-brightness fill light effect. Since all sub-pixels have been fully charged and reached the target voltage at this time, there is no color crosstalk problem when the three-color backlight is lit simultaneously. This solution further extends the backlight emission window, maximizes the PWM duty cycle and backlight efficiency, and is suitable for applications with high brightness requirements.

[0094] (4) such as Figure 27 As shown, the timing controller turns off the red LEDs and drives the green and blue LEDs to light up simultaneously during the red field period, turns off the green LEDs and drives the red and blue LEDs to light up simultaneously during the green field period, and turns off the blue LEDs and drives the red and green LEDs to light up simultaneously during the blue field period.

[0095] This solution turns off only the LED corresponding to the currently charging color during each monochrome field, while keeping the LEDs of the other two colors lit, thus ensuring that at least two colors of LEDs are on at any given moment. Specifically, when charging the red sub-pixel in the red field, to avoid display abnormalities due to the liquid crystal voltage not yet reaching the target voltage, the timing controller turns off the red LED while driving the green and blue LEDs to emit light; when charging the green sub-pixel in the green field, the green LED is turned off while driving the red and blue LEDs to emit light; when charging the blue sub-pixel in the blue field, the blue LED is turned off while driving the red and green LEDs to emit light.

[0096] Although this solution turns off the LEDs of the current charging color during each monochrome field, the LEDs of the other two colors remain lit. Therefore, the overall luminous efficiency of the backlight is still high, while avoiding display abnormalities caused by LEDs being lit during charging.

[0097] In summary, all four backlight driving methods in this embodiment utilize the wavelength selective filtering characteristics of color filters. By extending or overlapping the backlight emission time between different color fields, the PWM duty cycle and backlight luminous efficiency are effectively improved. Under the same target brightness, the driving current of LED beads can be reduced or the number of beads can be reduced, thereby saving costs.

[0098] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0099] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0100] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display panel, characterized in that, The display panel includes: A color filter substrate, wherein a color filter is disposed on the color filter substrate; An array substrate is disposed opposite to the color filter substrate. The array substrate is provided with multiple data lines, multiple scan lines, and multiple pixel units arranged in an array. Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The backlight module includes multiple backlight units corresponding to the multiple pixel units, and each backlight unit includes a red LED, a green LED and a blue LED. A timing controller, connected to the backlight module, is configured to: in high refresh rate mode, sequentially output red field sequence data, green field sequence data and blue field sequence data within one frame period, and sequentially drive the red LED, the green LED and the blue LED in the backlight module to emit light; The gate driving circuit, connected to the plurality of scan lines, is configured to simultaneously drive M adjacent scan lines in high refresh rate mode. The source drive circuit, connected to the timing controller and the multiple data lines, is configured to: in the high refresh rate mode, convert the red field sequence data into red grayscale voltage and output it simultaneously to the data lines corresponding to N columns of red sub-pixels during the red field period; convert the green field sequence data into green grayscale voltage and output it simultaneously to the data lines corresponding to N columns of green sub-pixels during the green field period; and convert the blue field sequence data into blue grayscale voltage and output it simultaneously to the data lines corresponding to N columns of blue sub-pixels during the blue field period; wherein M and N are integers greater than 1.

2. The display panel according to claim 1, characterized in that, The timing controller is also configured to drive all the red LEDs, all the green LEDs and all the blue LEDs in the backlight module to emit light simultaneously in normal mode. The gate drive circuit is also configured to drive the multiple scan lines line by line in normal mode; The source drive circuit is also configured to: in normal mode, in response to the RGB concurrent format image data output by the timing controller, output grayscale voltage to the corresponding sub-pixel.

3. The display panel according to claim 1, characterized in that, The source drive circuit includes: A data buffer, connected to the timing controller, is configured to receive and buffer the data signals output by the timing controller; A pixel rearranger, connected to the data buffer, is configured to sequentially map monochrome field data output by the data buffer to the corresponding output channels in the high refresh rate mode. A pixel replicator, connected to the pixel rearranger, is configured to, in response to a replication factor enable signal sent by the timing controller, simultaneously replicate each data signal output by the pixel rearranger to the output channel corresponding to N columns of sub-pixels of the same color. A voltage output device, connected to the pixel replicator and the multiple data lines, is configured to, under the control of a latch trigger signal sent by the timing controller, latch all channel data output by the pixel replicator in parallel, convert it into grayscale voltage, and then output it to the corresponding data line.

4. The display panel according to claim 1, characterized in that, The source drive circuit includes: A data buffer, connected to the timing controller, is configured to receive and buffer the data signals output by the timing controller; A voltage output unit, connected to the data buffer and the multiple data lines, is configured to, under the control of the latch trigger signal sent by the timing controller, latch all channel data output by the data buffer in parallel and convert them into corresponding grayscale voltages. The display panel further includes: Multiple data selection circuits are provided, the input terminal of which is connected to one output channel of the voltage output device, and the three output terminals of the data selection circuit are respectively connected to the three data lines corresponding to the red sub-pixel, green sub-pixel and blue sub-pixel in the same pixel unit. The data selection circuit is configured to: in the high refresh rate mode, during the red field of a frame, only the path between the output channel and the data line corresponding to the red sub-pixel is turned on; during the green field, only the path between the output channel and the data line corresponding to the green sub-pixel is turned on; and during the blue field, only the path between the output channel and the data line corresponding to the blue sub-pixel is turned on.

5. The display panel according to claim 4, characterized in that, The data selection circuit includes: The first switching transistor has its control terminal connected to the timing controller or the source drive circuit, its first terminal connected to an output channel of the voltage output device, and its second terminal connected to the data line corresponding to the red sub-pixel. The second switch is connected to the timing controller or the source drive circuit, the first end of the second switch is connected to the first end of the first switch, and the second end of the second switch is connected to the data line corresponding to the green sub-pixel. The third switch is connected to the timing controller or the source drive circuit, the first end of the third switch is connected to the first end of the first switch, and the second end of the third switch is connected to the data line corresponding to the blue sub-pixel.

6. The display panel according to claim 4, characterized in that, The data selection circuit includes: A master switch transistor, the control terminal of which is connected to the timing controller or the source drive circuit, and the first terminal of which is connected to an output channel of the voltage output device; The first switching transistor has its control terminal connected to the timing controller or the source drive circuit, its first terminal connected to the second terminal of the main switching transistor, and its second terminal connected to the data line corresponding to the red sub-pixel. The second switch is connected to the timing controller or the source drive circuit, the first end of the second switch is connected to the first end of the first switch, and the second end of the second switch is connected to the data line corresponding to the green sub-pixel. The third switch is connected to the timing controller or the source drive circuit, the first end of the third switch is connected to the first end of the first switch, and the second end of the third switch is connected to the data line corresponding to the blue sub-pixel.

7. A driving method for a display panel, characterized in that, Applied to the display panel according to any one of claims 1-6, in high refresh rate mode, the driving method includes: The timing controller outputs red field sequence data, green field sequence data and blue field sequence data sequentially within one frame period, and drives the red LED, green LED and blue LED in the backlight module to emit light sequentially; The gate drive circuit simultaneously drives M adjacent scan lines; The source drive circuit converts the red field sequence data into a red grayscale voltage during the red field period and outputs it to the data lines corresponding to the N columns of red sub-pixels. During the green field period, it converts the green field sequence data into a green grayscale voltage and outputs it to the data lines corresponding to the N columns of green sub-pixels. During the blue field period, it converts the blue field sequence data into a blue grayscale voltage and outputs it to the data lines corresponding to the N columns of blue sub-pixels.

8. The driving method for the display panel according to claim 7, characterized in that, The timing controller sequentially drives the red LED, the green LED, and the blue LED in the backlight module to emit light, including: The timing controller drives the red LED to continue emitting light after the red field is fully charged until at least a portion of the green field, and drives the green LED to continue emitting light after the green field is fully charged until at least a portion of the blue field; Alternatively, the timing controller drives the red LED to continue emitting light after the red field is fully charged, and drives the green LED to emit light after the green field is fully charged, so that the red LED and the green LED emit light simultaneously for at least a portion of the time. Alternatively, after the timing controller has completed charging of all color fields in a frame, it drives the red LED, the green LED, and the blue LED to emit light simultaneously. Alternatively, the timing controller may turn off the red LED during the red field and drive the green and blue LEDs to emit light simultaneously, turn off the green LED during the green field and drive the red and blue LEDs to emit light simultaneously, and turn off the blue LED during the blue field and drive the red and green LEDs to emit light simultaneously.

9. The driving method for the display panel according to claim 7, characterized in that, When the source driving circuit includes a data buffer, a pixel rearranger, a pixel replicator, and a voltage outputter, the source driving circuit converts the red field sequence data into red grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of red sub-pixels during the red field period; converts the green field sequence data into green grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of green sub-pixels during the green field period; and converts the blue field sequence data into blue grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of blue sub-pixels during the blue field period. This includes: The data buffer receives and buffers the red field sequence data, green field sequence data and blue field sequence data output sequentially by the timing controller; The pixel rearranger rearranges the monochrome field order data cached in the data buffer so that each monochrome field order data is mapped to the corresponding output channel. The pixel replicator, according to the replication ratio enable signal sent by the timing controller, simultaneously replicates each data signal output by the pixel rearranger to the output channel corresponding to the N columns of sub-pixels of the same color. Under the control of the latch trigger signal sent by the timing controller, the voltage output device latches all channel data output by the pixel replicator in parallel, converts it into grayscale voltage, and then outputs it to the corresponding data line.

10. The driving method for a display panel according to claim 7, characterized in that, The source driving circuit includes a data buffer and a voltage output device. When the display panel further includes multiple data selection circuits, the source driving circuit converts the red field sequence data into red grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of red sub-pixels during the red field period; converts the green field sequence data into green grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of green sub-pixels during the green field period; and converts the blue field sequence data into blue grayscale voltage and outputs it simultaneously to the data lines corresponding to N columns of blue sub-pixels during the blue field period. This includes: The data buffer receives and buffers the red field sequence data, green field sequence data and blue field sequence data output sequentially by the timing controller; Under the control of the latch trigger signal sent by the timing controller, the voltage output device latches all channel data output by the data buffer in parallel and converts them into corresponding grayscale voltages. During the red field, the data selection circuit only conducts the path of the data line corresponding to the red sub-pixel, and transmits the red grayscale voltage output by the voltage output device to the red sub-pixel. During the green field, the data selection circuit only conducts the path of the data line corresponding to the green sub-pixel, and transmits the green grayscale voltage output by the voltage output device to the green sub-pixel. During the blue field, the data selection circuit only conducts the path of the data line corresponding to the blue sub-pixel, and transmits the blue grayscale voltage output by the voltage output device to the blue sub-pixel.

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