Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a first substrate, a common signal line, a black insertion signal line, a pixel electrode and a black insertion gate line. The common signal line, the black insertion signal line, the pixel electrode and the black insertion gate line are arranged on the first substrate. The pixel electrode is electrically connected to the black insertion signal line through a black insertion switch, and the black insertion gate line is used for controlling the black insertion switch. In the area covered by the pixel electrode, the common signal line is located between the black insertion signal line and the pixel electrode. Specifically, the common signal line is arranged between the black insertion signal line and the pixel electrode, the common signal line is used for shielding the capacitive coupling of the black insertion signal line to the pixel electrode, the influence of the voltage change of the black insertion signal line on the potential of the pixel electrode is reduced, the unintended voltage deviation of the pixel electrode is reduced, and the display voltage of the pixel electrode is kept stable.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Existing self-insertion pixel structures typically add a thin film transistor (TFT) and an insertion signal line to a regular pixel structure. During the insertion phase, the insertion signal is written to the pixel electrode through the insertion TFT, causing the pixel to enter a black state. For normally black display modes such as Vertical Alignment (VA), since the black state display voltage can be a common voltage and the insertion signal can be a DC signal, the parasitic capacitance formed between the insertion signal line and the pixel electrode has a relatively small impact on the display.

[0003] However, for normally white display modes such as Twisted Nematic (TN), the black state display requires AC drive voltages corresponding to positive and negative frames. The black signal line needs to transmit AC changing black state voltage, which causes fluctuations in pixel electrode voltage, leading to problems such as grayscale shift, display crosstalk, or flicker. Summary of the Invention

[0004] To address the aforementioned issues, this application provides an array substrate that reduces parasitic coupling between the black insertion signal lines and the pixel electrodes, thereby maintaining a stable display voltage for the pixel electrodes.

[0005] To address the aforementioned problems, the first technical solution provided in this application is: to provide an array substrate, comprising: First substrate; A common signal line is disposed on the first substrate; A black signal line is inserted and disposed on the first substrate; A pixel electrode is disposed on the first substrate; the pixel electrode is electrically connected to the black insertion signal line via a black insertion switch. A black gate line is disposed on the first substrate and is used to control the black gate switch; The black insertion signal line passes through the area covered by the pixel electrode, and within the area covered by the pixel electrode, the common signal line is located between the black insertion signal line and the pixel electrode.

[0006] In one embodiment, the common signal line completely covers the black insertion signal line within the area covered by the pixel electrode.

[0007] In one embodiment, the array substrate further includes: A first metal layer is disposed on the first substrate; the first metal layer includes a first gate electrode, the black-inserted gate line, and the black-inserted signal line. A first insulating layer is disposed on the first substrate and covers the first metal layer; Semiconductor layer, including a first active layer; A second metal layer is disposed on the side of the first insulating layer away from the first substrate; the second metal layer includes a first source electrode, a first drain electrode, and the common signal line; the first gate electrode, the first source electrode, the first drain electrode, and the first active layer constitute a first thin-film transistor, which serves as the black-plug switch; A second insulating layer is disposed on the first insulating layer and covers the second metal layer; A transparent conductive layer is disposed on the side of the second insulating layer away from the first substrate; the transparent conductive layer includes the pixel electrode; The black signal line is electrically connected to the first drain electrode; the first source electrode is electrically connected to the pixel electrode through a third via.

[0008] In one embodiment, the transparent conductive layer further includes a first bridging portion; the black signal line is electrically connected to one end of the first bridging portion through a first via, and the other end of the first bridging portion is electrically connected to the first drain electrode through a second via; The first metal layer further includes a charging gate line, which is spaced apart from the black insertion gate line; the black insertion signal line is disposed between the charging gate line and the black insertion gate line, and close to the black insertion gate line; the black insertion signal line includes a first main body extending along the black insertion gate line and a first protrusion extending from the first main body to the black insertion gate line; the first bridging portion is located between the first main body and the black insertion gate line, and the first protrusion is electrically connected to one end of the first bridging portion through the first via.

[0009] In one embodiment, the pixel electrode includes a second body portion and a second protrusion extending from the second body portion toward the black gate line; the first source electrode is electrically connected to the second protrusion through the third via.

[0010] In one embodiment, the common signal line includes a first extension extending along the black gate line, the width of the first extension being greater than or equal to the width of the first body portion; the first extension completely covers the first body portion and exposes the first protrusion within a length range of the first extension; the first extension has a first edge and a second edge, the first edge being close to the first protrusion, and a third edge of the second body portion being located between the first edge and the second edge.

[0011] In one embodiment, the array substrate further includes: A first metal layer is disposed on the first substrate; the first metal layer includes a first gate electrode, a first black insertion extension, a first common extension, and the black insertion gate line. A first insulating layer is disposed on the first substrate and covers the first metal layer; Semiconductor layer, including a first active layer; A second metal layer is disposed on the side of the first insulating layer away from the first substrate; the second metal layer includes a first source electrode, a first drain electrode, a second black insertion extension, a third black insertion extension, and a second common extension; the first gate electrode, the first source electrode, the first drain electrode, and the first active layer constitute a first thin film transistor, and the first thin film transistor serves as the black insertion switch. A second insulating layer is disposed on the first insulating layer and covers the second metal layer; A transparent conductive layer is disposed on the side of the second insulating layer away from the first substrate; the transparent conductive layer includes the pixel electrode; The first black insertion extension segment, the second black insertion extension segment, and the third black insertion extension segment are electrically connected to form the black insertion signal line; the first common extension segment and the second common extension segment are electrically connected to form the common signal line; the black insertion signal line is electrically connected to the first drain electrode, and the first source electrode is electrically connected to the pixel electrode.

[0012] In one embodiment, the transparent conductive layer further includes a second bridging portion, a third bridging portion, and a fourth bridging portion; the first black insertion extension segment and the second black insertion extension segment are bridged through the second bridging portion, and the first black insertion extension segment and the third black insertion extension segment are bridged through the fourth bridging portion, thereby forming the black insertion signal line; the first common extension segment and the second common extension segment are bridged through the third bridging portion, thereby forming the common signal line; the first corner of the pixel electrode has a first notch, and the second bridging portion and the third bridging portion are located within the first notch; the second corner of the pixel electrode has a second notch, and the fourth bridging portion is located within the second notch.

[0013] In one embodiment, the first metal layer further includes a charging gate line, and the first common extension is located between the charging gate line and the black-insertion gate line; the first common extension includes a first sub-common extension and a second sub-common extension; the first sub-common extension extends along the black-insertion gate line and is close to the black-insertion gate line; the first sub-common extension intersects with the second sub-common extension; the second common extension intersects with the first sub-common extension, and the second common extension is bridged to the end of the first sub-common extension away from the second sub-common extension through the third bridging portion.

[0014] To address the aforementioned problems, the second technical solution provided in this application is: to provide a display panel, comprising: For the substrate; The array substrate described in any of the above embodiments; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0015] The beneficial effect of this application is that, unlike the prior art, the array substrate provided in this application includes a first substrate, a common signal line, a black-insertion signal line, a pixel electrode, and a black-insertion gate line. The common signal line, black-insertion signal line, pixel electrode, and black-insertion gate line are all disposed on the first substrate. The pixel electrode is electrically connected to the black-insertion signal line via a black-insertion switch, and the black-insertion gate line is used to control the black-insertion switch. Within the area covered by the pixel electrode, the black-insertion signal line passes through the area covered by the pixel electrode, and the common signal line is located between the black-insertion signal line and the pixel electrode. Specifically, this application, by setting a common signal line between the black-insertion signal line and the pixel electrode, utilizes the common signal line to shield the capacitive coupling of the black-insertion signal line to the pixel electrode, reducing the impact of voltage changes in the black-insertion signal line on the pixel electrode potential, thereby reducing unexpected voltage deviations of the pixel electrode and maintaining a stable display voltage for the pixel electrode. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the structure of the display panel provided in this application; Figure 2 This is a schematic diagram of a pixel driving circuit with black pixel insertion function in the prior art; Figure 3 This is a schematic diagram of the structure of the array substrate provided in the first embodiment of this application; Figure 4 A schematic diagram of the fabrication process of the array substrate provided in the first embodiment of this application; Figure 5 for Figure 3 A magnified view of a section at point A in the middle; Figure 6 A schematic diagram of the structure of the black signal line in the first embodiment provided in this application; Figure 7 A schematic diagram of the pixel electrode structure provided in the first embodiment of this application; Figure 8 A schematic diagram showing the positional relationship between the first extension and the first main body in the first embodiment provided in this application; Figure 9 This is a schematic diagram of the structure of the third protrusion in the second embodiment provided in this application; Figure 10 This is a schematic diagram of the shielding structure of the second embodiment provided in this application; Figure 11 This is a schematic diagram of the array substrate of the third embodiment provided in this application; Figure 12 This is a schematic diagram of the fabrication process of the array substrate provided in the third embodiment of this application; Figure 13 This is a schematic diagram of the first metal layer structure of the third embodiment provided in this application; Figure 14 This is a schematic diagram of the second metal layer structure of the third embodiment provided in this application; Figure 15 A schematic diagram of the third notch structure of the fourth embodiment provided in this application.

[0017] Label Explanation: 100. Display panel; 10. Array substrate; 20. Alignment substrate; 30. Liquid crystal layer; 11. First substrate; 12. First metal layer; 121. Charging gate line; 122. Black insertion gate line; 123. Black insertion signal line; 12301. First main body portion; 12302. First protrusion; 12311. First black insertion extension; 12312. Second black insertion extension; 12313. Third black insertion extension; 13. Semiconductor layer; 131. First active layer; 14. Second metal layer; 141. First source electrode; 142. First drain electrode; 143. Common signal line; 14301. First extension portion; 14311. First common extension; 143111. First sub-sub- 143112, Second Sub-Common Extension; 14312, Second Common Extension; 143121, Third Main Body; 14321, Third Protrusion; 15, Transparent Conductive Layer; 151, Pixel Electrode; 1511, Second Main Body; 1512, Second Protrusion; 152, First Bridging Part; 153, Second Bridging Part; 154, Third Bridging Part; 155, Fourth Bridging Part; 156, First Corner; 1561, First Notch; 157, Second Corner; 1571, Second Notch; 158, Shielding Structure; 159, Third Notch; 16, Black Switch; 171, First Via; 172, Second Via; 173, Third Via; 174, Fourth Via. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications will change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0022] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0023] See Figure 1 , Figure 1This is a schematic diagram of the structure of the display panel provided in this application. The display panel 100 typically includes a counter substrate 20, an array substrate 10, and a liquid crystal layer 30. The counter substrate 20 is disposed opposite to the array substrate 10, and the liquid crystal layer 30 is disposed between the array substrate 10 and the counter substrate 20.

[0024] Specifically, the substrate 20 may be provided with structures such as a color filter layer, a black matrix, and a common electrode. The color filter layer is used to realize color display, the black matrix is ​​used to block non-display areas to reduce light leakage, and the common electrode is used to provide a common voltage reference to the liquid crystal layer 30. The array substrate 10 may include a pixel driving structure, such as a pixel electrode 151, to provide display data voltage to the pixel. The liquid crystal molecules in the liquid crystal layer 30 are deflected under the action of the electric field formed between the pixel electrode 151 and the common electrode, thereby adjusting the backlight transmittance and realizing different grayscale displays.

[0025] Furthermore, due to the limited response speed of liquid crystals and the persistence of vision in the human eye, ghosting can easily occur when switching between adjacent frames. To improve the ghosting problem, a black state display stage can be inserted between two adjacent normally displayed frames, i.e., black insertion display, to reduce the visual persistence caused by the previous frame to the human eye and improve the clarity of dynamic display.

[0026] To achieve black pixel insertion, a black pixel insertion thin-film transistor and a black pixel insertion signal line are added to the existing pixel driving structure. During the normal display phase, the charging thin-film transistor is turned on, and the display data voltage on the data line is written to the pixel electrode; during the black pixel insertion phase, the black pixel insertion thin-film transistor is turned on, and the black state voltage on the black pixel insertion signal line is written to the pixel electrode, causing the pixel to enter the black state.

[0027] For constant black display modes such as VA mode, the black state voltage can be close to the common voltage, and the black insertion signal line can transmit a relatively stable DC black insertion signal. The parasitic capacitance formed between the black insertion signal line and the pixel electrode has little impact on the display.

[0028] However, for normally white display modes such as TN mode, black state display requires a black state voltage with a certain voltage difference relative to the common voltage. In order to avoid liquid crystal polarization, the black state voltage usually needs to be reversed between the black state voltage of the positive frame and the black state voltage of the negative frame. Therefore, the black insertion signal line needs to transmit an alternating black insertion signal.

[0029] When the black insertion signal line transmits an AC black insertion signal, the parasitic coupling capacitance between the black insertion signal line and the pixel electrode will couple the voltage change of the black insertion signal to the pixel electrode, causing the pixel electrode potential to shift unexpectedly, which in turn causes problems such as grayscale deviation, flickering or uneven display.

[0030] See Figure 2 , Figure 2This is a schematic diagram of a pixel driving circuit with black bar insertion function in the prior art. The pixel driving circuit includes data lines, black bar insertion signal lines, charging gate lines, black bar insertion gate lines, charging thin-film transistors, black bar insertion thin-film transistors, and pixel electrode nodes.

[0031] The charging thin-film transistor is connected between the data line and the pixel electrode node, and is used to write the display data voltage on the data line to the pixel electrode node during the normal display phase. The black insertion thin-film transistor is connected between the black insertion signal line and the pixel electrode node, and is used to write the black state voltage on the black insertion signal line to the pixel electrode node during the black insertion phase, so that the pixel enters the black state. A liquid crystal capacitor is formed between the pixel electrode node and the common electrode, and a storage capacitor is formed between the pixel electrode node and the storage common terminal. Since the black insertion signal line and the pixel electrode are arranged adjacent to each other, a parasitic coupling capacitance is also formed between them. When the black insertion signal line transmits an alternating black insertion signal, the voltage change can easily be coupled to the pixel electrode node through the parasitic coupling capacitance, causing an unexpected shift in the pixel electrode potential.

[0032] This application provides an array substrate 10 to improve the above-mentioned problems.

[0033] Figure 3 This is a schematic diagram of the array substrate provided in the first embodiment of this application, showing only one sub-pixel unit. See also... Figure 3 The first embodiment of this application proposes an array substrate 10, including a first substrate 11, a common signal line 143, a black gate line 122, a pixel electrode 151, and a black signal line 123.

[0034] The common signal line 143, the black insertion signal line 123, the pixel electrode 151 and the black insertion gate line 122 are all disposed on the first substrate 11. The pixel electrode 151 is electrically connected to the black insertion signal line 123 through the black insertion switch 16, and the black insertion gate line 122 is used to control the black insertion switch 16.

[0035] Specifically, the common signal line 143 is used to transmit a common voltage signal; the black insertion signal line 123 is used to transmit a black insertion voltage signal; the pixel electrode 151 is used to receive the display data voltage or the black insertion voltage, and cooperates with the common electrode of the substrate 20 to form an electric field that drives the liquid crystal molecules to deflect; the black insertion switch 16 is connected between the black insertion signal line 123 and the pixel electrode 151, and the black insertion gate line 122 is connected to the control terminal of the black insertion switch 16 to control the black insertion switch 16 to be turned on or off.

[0036] Understandably, during the normal display phase, the black insertion gate line 122 controls the black insertion switch 16 to be turned off, and the pixel electrode 151 receives the display data voltage, causing the pixel to display the corresponding gray level; during the black insertion phase, the black insertion gate line 122 controls the black insertion switch 16 to be turned on, and the black insertion voltage on the black insertion signal line 123 is written to the pixel electrode 151 through the black insertion switch 16, causing the pixel to enter the black state.

[0037] Furthermore, the black insertion signal line 123 passes through the area covered by the pixel electrode 151, and within the area covered by the pixel electrode 151, the common signal line 143 is located between the black insertion signal line 123 and the pixel electrode 151. That is, a portion of the common signal line 143 located in the projection area of ​​the pixel electrode 151 at least partially covers a portion of the black insertion signal line 123 located in the projection area of ​​the pixel electrode 151. The portion of the common signal line 143 and the portion of the black insertion signal line 123 located outside the projection area of ​​the pixel electrode 151 can be completely or partially misaligned. It is understood that "the black insertion signal line 123 passes through the area covered by the pixel electrode 151" means that in the direction perpendicular to the first substrate 11, the black insertion signal line 123 passes through the area corresponding to the orthographic projection of the pixel electrode 151 on the first substrate 11, and the projection of the black insertion signal line 123 on the first substrate 11 overlaps with the projection of the pixel electrode 151 on the first substrate 11.

[0038] Specifically, the common signal line 143 is used to transmit a common voltage signal, resulting in more stable potential changes. When the common signal line 143 is located between the black insertion signal line 123 and the pixel electrode 151, the common signal line 143 can act as an electric field shielding structure between the black insertion signal line 123 and the pixel electrode 151, reducing the parasitic coupling capacitance formed between the black insertion signal line 123 and the pixel electrode 151, and improving the stability of the potential of the pixel electrode 151.

[0039] In this embodiment, by providing a common signal line 143 between the black insertion signal line 123 and the pixel electrode 151, the common signal line 143 can shield the capacitive coupling of the black insertion signal line 123 to the pixel electrode 151, reducing the impact of voltage changes in the black insertion signal line 123 on the potential of the pixel electrode 151, thereby reducing unexpected voltage deviations of the pixel electrode 151 and maintaining a stable display voltage for the pixel electrode 151; at the same time, the common signal line 143 can also form a storage capacitor with the pixel electrode 151.

[0040] The common signal line 143 located in the projection area of ​​the pixel electrode 151 can cover more than 50%, 60%, 70%, 80%, or 90% of the area of ​​the black insertion signal line 123 located in the projection area of ​​the pixel electrode 151. In the first embodiment, the common signal line 143 completely covers the black insertion signal line 123 within the area covered by the pixel electrode 151.

[0041] Understandably, complete coverage means that the orthographic projection of a portion of the common signal line 143 located in the projection area of ​​the pixel electrode 151 on the first substrate 11 completely covers the orthographic projection of a portion of the black insertion signal line 123 located in the projection area of ​​the pixel electrode 151 on the first substrate 11.

[0042] Furthermore, since the common signal line 143 completely covers the black insertion signal line 123, it is not easy for the black insertion signal line 123 and the pixel electrode 151 to form a coupling region in the direction perpendicular to the array substrate 10, and the electric field change generated by the black insertion signal line 123 can be shielded by the common signal line 143.

[0043] In this embodiment, by making the common signal line 143 completely cover the black insertion signal line 123, the parasitic coupling capacitance between the black insertion signal line 123 and the pixel electrode 151 is further reduced, the influence of the voltage change of the black insertion signal line 123 on the potential of the pixel electrode 151 is reduced, and the pixel electrode 151 maintains a stable display voltage.

[0044] For a clearer explanation of the structure and fabrication process of the array substrate 10, please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram illustrating the fabrication process of the array substrate according to the first embodiment of this application. First, see... Figure 4 In step (a), a first metal layer 12 is formed on a first substrate 11, and the first metal layer 12 is patterned to form a charging gate line 121, a black-placing gate line 122, a black-placing signal line 123, and related signal traces; then, a first insulating layer (not shown) is formed on the first metal layer 12, covering the first metal layer 12. See also Figure 4 In section (b), a semiconductor layer is formed on the side of the first insulating layer away from the first substrate 11, and the semiconductor layer is patterned to form a first active layer 131 in the corresponding region of the thin-film transistor. Further, see... Figure 4 In section (c), a second metal layer 14 is formed on the side of the first insulating layer away from the first substrate 11, and the second metal layer 14 is patterned to form structures such as a common signal line 143, a first source electrode 141, and a first drain electrode 142. Further, a second insulating layer (not shown) is formed on the second metal layer 14, covering the second metal layer 14. See [reference needed]. Figure 4 In section (d), the second insulating layer is patterned to form vias for connecting different conductive layers, such as first via 171, second via 172, third via 173, and fourth via 174. Finally, see... Figure 4In step (e), a transparent conductive layer 15 is formed on the side of the second insulating layer away from the first substrate 11, and the transparent conductive layer 15 is patterned to form pixel electrodes 151 and other structures. Thus, an array substrate 10 with black insertion function can be formed.

[0045] See Figure 3 and Figure 4 In the first embodiment, the array substrate 10 further includes a first metal layer 12 and a first insulating layer. The first metal layer 12 and the first insulating layer are both disposed on the first substrate 11, and the first insulating layer covers the first metal layer 12.

[0046] The array substrate 10 further includes a semiconductor layer 13, which includes a first active layer 131. The first active layer 131 is disposed on the side of the first insulating layer away from the first metal layer 12, so that the first gate electrode (not shown) in the first metal layer 12 can control the conduction state of the first active layer 131 through the first insulating layer.

[0047] Optionally, in this embodiment, the material of the semiconductor layer 13 may be selected from at least one or more of amorphous silicon, polycrystalline silicon, metal oxide semiconductor, and organic semiconductor, and is not limited herein.

[0048] Furthermore, the array substrate 10 also includes a second metal layer 14, a second insulating layer, and a transparent conductive layer 15; wherein, the second metal layer 14 is disposed on the side of the first insulating layer away from the first substrate 11, the second insulating layer is disposed on the first insulating layer and covers the second metal layer 14, the transparent conductive layer 15 is disposed on the side of the second insulating layer away from the first substrate 11, and the transparent conductive layer 15 includes a pixel electrode 151.

[0049] Specifically, the second metal layer 14 includes a first source electrode 141, a first drain electrode 142, and a common signal line 143.

[0050] Furthermore, the first active layer 131, the first gate electrode located on the first metal layer 12, the first source electrode 141 located on the second metal layer 14, and the first drain electrode 142 constitute the first thin film transistor, and the first thin film transistor is the black switch 16 in the above embodiment.

[0051] The black signal line 123 is electrically connected to the first drain electrode 142; the first source electrode 141 is electrically connected to the pixel electrode 151 through the third via 173. For example, the black signal line 123 and the first drain electrode 142 can be directly electrically connected through a via, or they can be electrically connected by bridging.

[0052] Specifically, the third via 173 penetrates the second insulating layer and is disposed corresponding to the first source electrode 141, exposing at least a portion of the surface of the first source electrode 141. A portion of the material of the pixel electrode 151 extends into the third via 173 and contacts the first source electrode 141, thereby achieving an electrical connection between the pixel electrode 151 and the first source electrode 141.

[0053] Specifically, during the black insertion stage, the black insertion gate line 122 provides an enable signal to the first gate electrode, causing the first active layer 131 to form a conductive channel between the first source electrode 141 and the first drain electrode 142, thus turning on the first thin-film transistor. At this time, the black insertion signal on the black insertion signal line 123 can be transmitted sequentially through the first drain electrode 142, the first active layer 131, the first source electrode 141, and the third via 173 to the pixel electrode 151, thereby adjusting the potential of the pixel electrode 151 to the black insertion potential, and the corresponding pixel appears black.

[0054] During the display phase, the first gate electrode receives a cutoff signal, causing the first thin-film transistor to turn off. At this time, the electrical connection between the black insertion signal line 123 and the pixel electrode 151 is broken, and the voltage change on the black insertion signal line 123 is not written to the pixel electrode 151. The pixel electrode 151 can receive display data voltage for normal grayscale display.

[0055] Meanwhile, since the common signal line 143 is located in the second metal layer 14 and is disposed between the black insertion signal line 123 and the pixel electrode 151, the common signal line 143 shields the black insertion signal line 123, thereby reducing the parasitic coupling effect of the voltage change of the black insertion signal line 123 on the pixel electrode 151.

[0056] In this embodiment, by setting a first thin-film transistor composed of a first gate electrode, a first active layer 131, a first source electrode 141, and a first drain electrode 142 on the array substrate 10, and using the first thin-film transistor as a black-insertion switch 16, the black-insertion potential of the pixel electrode 151 can be controlled without the need for an additional complex external black-insertion control structure. At the same time, by realizing the electrical connection between the first source electrode 141 and the pixel electrode 151 through the third via 173, the stability of the black-insertion signal transmission to the pixel electrode 151 can be improved, enabling the pixel electrode 151 to quickly switch to the black-insertion potential during the black-insertion stage, thereby improving the black-insertion response efficiency.

[0057] In the first embodiment, the transparent conductive layer 15 further includes a first bridging portion 152, see [link to previous embodiment]. Figure 5 , Figure 5 for Figure 3A partial enlarged view of point A. The black signal line 123 is electrically connected to one end of the first bridging portion 152 via the first via 171, and the other end of the first bridging portion 152 is electrically connected to the first drain electrode 142 via the second via 172. The first bridging portion 152 can be used to realize the electrical connection between the black signal line 123 and the first drain electrode 142.

[0058] Understandably, the black insertion signal line 123 first transmits the black insertion signal to the first bridging part 152 through the first via 171, and then transmits the black insertion signal to the first drain electrode 142 through the first bridging part 152 and the second via 172.

[0059] Specifically, see Figure 3 and Figure 5 During the black insertion stage, the black insertion gate line 122 controls the first thin film transistor to be turned on, and the black insertion signal on the black insertion signal line 123 can be transmitted to the pixel electrode 151 in sequence through the first via 171, the first bridging part 152, the second via 172, the first drain electrode 142, the first active layer 131, the first source electrode 141 and the third via 173, so that the potential of the pixel electrode 151 is adjusted to the black insertion potential, and the corresponding pixel appears black.

[0060] The first metal layer 12 also includes a charging gate line 121, see [link to documentation]. Figure 4 In (a), the charging gate line 121 and the black gate line 122 are spaced apart; specifically, the charging gate line 121 and the black gate line 122 are spaced apart by a black signal line 123, and the black signal line 123 is disposed between the charging gate line 121 and the black gate line 122, and close to the black gate line 122.

[0061] Understandably, the black signal line 123 is close to the first thin-film transistor controlled by the black gate line 122, which can shorten the connection distance between the black signal line 123 and the first drain electrode 142 and reduce the transmission path of the black signal.

[0062] Further, see Figure 6 , Figure 6 This is a schematic diagram of the structure of the black insertion signal line according to the first embodiment of this application. The black insertion signal line 123 includes a first main body portion 12301 extending along the black insertion gate line 122 and a first protrusion portion 12302 extending from the first main body portion 12301 toward the black insertion gate line 122; see also Figure 5 and Figure 6 The first bridging portion 152 is located between the first main body portion 12301 and the black gate line 122, and the first protrusion 12302 is electrically connected to one end of the first bridging portion 152 through the first via 171.

[0063] Understandably, since the common signal line 143 is located between the black insertion signal line 123 and the pixel electrode 151, and shields the first main body portion 12301 of the black insertion signal line 123, directly setting the first via 171 on the first main body portion 12301 would be easily blocked by the common signal line 143. By setting the first protrusion 12302, the black insertion signal line 123 can be led out from the shielded first main body portion 12301 to the connection area where the first via 171 is located, so that the black insertion signal line 123 can be electrically connected to the first bridging portion 152 through the first protrusion 12302, the first via 171, and the first bridging portion 152. This ensures that the common signal line 143 has a shielding effect on the first main body portion 12301 while realizing the connection between the black insertion signal line 123 and the first drain electrode 142. Moreover, it avoids the first drain electrode 142 from extending into the pixel aperture area, thereby improving the aperture ratio.

[0064] In this embodiment, by placing the black insertion signal line 123 between the charging gate line 121 and the black insertion gate line 122, and placing the black insertion signal line 123 close to the black insertion gate line 122, the black insertion signal line 123 can be placed closer to the control area of ​​the black insertion switch 16, shortening the black insertion signal transmission path and improving the black insertion signal transmission efficiency. By providing the first protrusion 12302 and the first bridging portion 152, the black insertion signal line 123 can be led out and electrically connected to the first drain electrode 142 when the common signal line 143 blocks the black insertion signal line 123. This ensures the shielding effect of the common signal line 143 on the black insertion signal line 123, and also enables the writing of the black insertion signal to the pixel electrode 151, improving the reliability of the black insertion display.

[0065] In the first embodiment, see Figure 7 , Figure 7 This is a schematic diagram of the structure of a pixel electrode according to the first embodiment of this application. The pixel electrode 151 includes a second main body portion 1511 and a second protrusion portion 1512 extending from the second main body portion 1511 toward the black gate line 122. The first source electrode 141 is electrically connected to the second protrusion portion 1512 through a third via 173.

[0066] It is understood that the second main body 1511 is used to form the main display area of ​​the pixel, and the second protrusion 1512 is used to lead the pixel electrode 151 to a position close to the first source electrode 141, so that the first source electrode 141 does not need to extend into the main display area of ​​the pixel electrode 151, and can be electrically connected to the pixel electrode 151 through the third via 173.

[0067] Specifically, during the black insertion stage, the black insertion signal on the black insertion signal line 123 is transmitted to the first source electrode 141 via the first thin film transistor, and can then be transmitted to the second protrusion 1512 via the third via 173, and further transmitted to the second main body 1511, so that the potential of the pixel electrode 151 is adjusted to the black insertion potential.

[0068] In this embodiment, by providing a second protrusion 1512 extending from the second main body 1511 towards the black gate line 122, the connection distance between the pixel electrode 151 and the first source electrode 141 can be shortened, facilitating the placement of the third via 173. Furthermore, it avoids the first source electrode 141 extending into the pixel aperture region, thereby improving the aperture ratio.

[0069] In the first embodiment, the common signal line 143 includes a first extension 14301 extending along the black gate line 122, and the width of the first extension 14301 is greater than or equal to the width of the first main body 12301.

[0070] In this embodiment, the example is given where the width of the first extension 14301 is greater than the width of the first main body 12301. See [link to previous section]. Figure 8 , Figure 8 A schematic diagram showing the positional relationship between the first extension and the first main body of the first embodiment provided in this application.

[0071] Understandably, by setting the width of the first extension 14301 to be greater than the width of the first main body 12301, the first extension 14301 can cover the first main body 12301 in a direction perpendicular to the first substrate 11. That is, within the length range of the first extension 14301, the orthographic projection of the first extension 14301 on the first substrate 11 covers the orthographic projection of the first main body 12301 on the first substrate 11.

[0072] Within the length range of the first extension 14301, the first extension 14301 completely covers the first main body 12301 and exposes the first protrusion 12302.

[0073] Specifically, see Figure 5 and Figure 8 The first extension 14301 covers the first main body 12301 of the black signal line 123 to reduce the capacitive coupling of the first main body 12301 to the pixel electrode 151. Simultaneously, the first extension 14301 does not cover the first protrusion 12302, allowing the first protrusion 12302 to be electrically connected to the first bridging portion 152 through the first via 171. While ensuring that the common signal line 143 has a shielding effect on the black signal line 123, the connection position between the black signal line 123 and the first bridging portion 152 is preserved.

[0074] Further, see Figure 7 and Figure 8 The first extension 14301 has a first edge and a second edge disposed opposite to each other, the first edge being close to the first protrusion 12302 and the second edge being away from the first protrusion 12302; the second body portion 1511 of the pixel electrode 151 has a third edge, and the third edge is located between the first edge and the second edge.

[0075] Understandably, the orthographic projection of the third edge of the second main body portion 1511 onto the first substrate 11 falls within the width range of the first extension portion 14301, resulting in an overlapping area between the second main body portion 1511 and the first extension portion 14301. That is, the first extension portion 14301 protrudes beyond the third edge of the second main body portion 1511, thereby reducing the parasitic coupling capacitance between the third edge of the second main body portion 1511 and the first protrusion 12302 in a direction parallel to the array substrate 10.

[0076] In other words, at the edge of the overlapping area between the pixel electrode 151 and the black insertion signal line 123, a portion of the black insertion signal line 123 is also covered by the common signal line 143. At the edge of the pixel electrode 151, the common signal line 143 partially protrudes from the pixel electrode 151. Thus, a coupling region is less likely to form between the black insertion signal line 123 and the pixel electrode 151 in the direction perpendicular to the array substrate 10, further reducing the coupling capacitance between the black insertion signal line 123 and the pixel electrode 151.

[0077] Specifically, in this embodiment, the dimension of the first extension 14301 along its width direction is defined as the first width, and the distance between the third edge of the second main body 1511 and the first edge of the first extension 14301 is defined as the first distance. The first distance is greater than 20% of the first width and less than 50% of the first width, so that the first extension 14301 can be more fully located between the pixel electrode 151 and the first main body 12301 of the black insertion signal line 123, thereby reducing or avoiding the formation of lateral parasitic coupling capacitance between the black insertion signal line 123 and the pixel electrode 151, and further improving the shielding effect.

[0078] In this embodiment, by setting the third edge of the second main body portion 1511 to be located between the first edge and the second edge of the first extension portion 14301, the first extension portion 14301 can be at least partially located below the pixel electrode 151, and a shielding area is formed between the pixel electrode 151 and the first main body portion 12301 of the black insertion signal line 123, thereby reducing the parasitic coupling effect of the first main body portion 12301 on the pixel electrode 151; the overlapping area between the first extension portion 14301 and the pixel electrode 151 can also serve as As part of the storage capacitor, it improves the ability to maintain the potential of the pixel electrode 151; furthermore, by making the first extension 14301 completely cover the first main body 12301 and expose the first protrusion 12302, it can improve the shielding effect of the common signal line 143 on the black insertion signal line 123, and also ensure the connection space between the first protrusion 12302 and the first via 171, so that the black insertion signal line 123 can be connected to the first drain electrode 142 through the first bridging part 152, thus taking into account both coupling shielding and black insertion signal.

[0079] In the second embodiment, see Figure 9 , Figure 9 This is a schematic diagram of the structure of the third protrusion in the second embodiment provided in this application. The common signal line 143 also includes a third protrusion 14321 extending from the first extension 14301 toward the black gate line 122. See [link to relevant documentation]. Figure 7 and Figure 9 The third protrusion 14321 is located between the second protrusion 1512 and the first bridging portion 152, or the third protrusion 14321 is located between the second protrusion 1512 and the first protrusion 12302.

[0080] Optionally, the third protrusion 14321 extends from the first extension 14301 toward the black gate line 122. Preferably, in this embodiment, the third protrusion 14321 is disposed at least partially corresponding to the region where the first active layer 131 of the first thin-film transistor is located. That is, the third protrusion 14321 is located between the second protrusion 1512 and the first drain electrode 142.

[0081] Understandably, the second protrusion 1512 extends from the second main body 1511 of the pixel electrode 151 toward the black gate line 122 and is electrically connected to the first source electrode 141 through the third via 173. Therefore, the second protrusion 1512 is electrically connected to the pixel electrode 151 and is at the pixel potential. The first bridging portion 152 is used to electrically connect the black signal line 123 to the first drain electrode 142. The first drain electrode 142, the first active layer 131 and the first source electrode 141 jointly participate in the transmission of the black signal to the pixel electrode 151. Therefore, in the first thin film transistor off state, the first protrusion 12302, the first bridging portion 152 and the first drain electrode 142 have the same potential and are all prone to forming parasitic coupling capacitance with the second protrusion 1512 in a direction parallel to the array substrate 10.

[0082] Especially during the display stage, there are still potential changes on the black signal line 123, the first bridging part 152 or the first drain electrode 142, while the third protrusion 14321 is formed by extending the first extension 14301 of the common signal line 143, which can maintain the common potential and shield the lateral coupling path near the second protrusion 1512.

[0083] In this embodiment, by setting the third protrusion 14321 between the second protrusion 1512 and the first bridging portion 152, the third protrusion 14321 can shield the lateral coupling effect of potential changes near the first bridging portion 152, the first drain electrode 142, or the first thin film transistor.

[0084] In the second embodiment, see Figure 10 , Figure 10 This is a schematic diagram of the shielding structure of the second embodiment provided in this application. The transparent conductive layer 15 also includes a shielding structure 158, and the shielding structure 158 partially surrounds the second protrusion 1512. The shielding structure 158 is electrically connected to the third protrusion 14321 in the second metal layer 14 through the fourth via 174.

[0085] The shielding structure 158, after being electrically connected to the third protrusion 14321 through the fourth via 174, can receive the common voltage signal transmitted by the common signal line 143.

[0086] Specifically, the shielding structure 158 may be concave or semi-enclosed and is spaced apart from and insulated from the pixel electrode 151.

[0087] In this embodiment, since the shielding structure 158 is disposed in the same layer as the second protrusion 1512 and surrounds the second protrusion 1512, and the shielding structure 158 is electrically connected to the common signal line 143, the shielding structure 158 can better form a common potential shielding area around the second protrusion 1512, reducing the lateral coupling effect of potential changes of the black signal line 123, the first bridging part 152, the first drain electrode 142 or the structure near the first thin film transistor on the second protrusion 1512.

[0088] This application presents a third embodiment.

[0089] In the third embodiment, the array substrate 10 has a similar basic structure to the array substrate 10 in the first embodiment.

[0090] See Figure 11 , Figure 11 This is a schematic diagram of the array substrate according to the third embodiment of this application. Specifically, the array substrate 10 includes a first substrate 11, a common signal line 143, a black-insertion signal line 123, a pixel electrode 151, a black-insertion gate line 122, and a black-insertion switch 16. Within the area covered by the pixel electrode 151, the common signal line 143 is located between the black-insertion signal line 123 and the pixel electrode 151 to shield the black-insertion signal line 123. The array substrate 10 may also include a first metal layer 12, a first insulating layer, and a semiconductor layer 13.

[0091] To facilitate the explanation of the structure of the array substrate 10 in the third embodiment and the layer-change connection relationship between the common signal line 143 and the black-inserted signal line 123, please refer to... Figure 12 , Figure 12 This is a schematic diagram illustrating the fabrication process of the array substrate provided in the third embodiment of this application. First, see... Figure 12 In step (a), a first metal layer 12 is formed and patterned on the first substrate 11 to form structures such as a charging gate line 121, a black-insertion gate line 122, a first black-insertion extension 12311, and a first common extension 14311; subsequently, see [reference needed]. Figure 12 In step (b), a first insulating layer is formed covering the first metal layer 12, and a semiconductor layer 13 is formed and patterned on the side of the first insulating layer away from the first substrate 11 to form a first active layer 131. Further, see [link to documentation]. Figure 12 In step (c), a second metal layer 14 is formed and patterned on the first insulating layer to form structures such as a first source electrode 141, a first drain electrode 142, a second black insertion extension 12312, a third black insertion extension 12313, a second common extension 14312, and data lines; then, a second insulating layer is formed covering the second metal layer 14, and the second insulating layer is patterned to form vias for connecting different conductive layers. Finally, see [link to documentation]. Figure 12In section (d), a transparent conductive layer 15 is formed and patterned on the side of the second insulating layer away from the first substrate 11 to form structures such as pixel electrode 151, second bridging portion 153, third bridging portion 154 and fourth bridging portion 155.

[0092] See Figure 13 , Figure 13 This is a schematic diagram of the first metal layer structure of the third embodiment provided in this application. In this embodiment, the first metal layer 12 includes a first gate electrode (not shown), a first black insertion extension 12311, a first common extension 14311, and a black insertion gate line 122.

[0093] The first gate electrode can be connected to the black gate line 122 as the control terminal of the black switch 16.

[0094] Furthermore, the array substrate 10 also includes a second metal layer 14, a second insulating layer and a transparent conductive layer 15, and the transparent conductive layer 15 includes a pixel electrode 151. The stacking relationship and function of the second metal layer 14, the second insulating layer and the transparent conductive layer 15 can be found in the aforementioned first embodiment and figures, and will not be repeated here.

[0095] Specifically, see Figure 14 , Figure 14 The diagram below shows the structure of the second metal layer in the third embodiment of this application. The second metal layer 14 includes a first source electrode 141, a first drain electrode 142, a second black insertion extension 12312, a third black insertion extension 12313, a second common extension 14312, and other traces such as data lines.

[0096] Furthermore, the first gate electrode, the first source electrode 141, the first drain electrode 142, and the first active layer 131 constitute the first thin-film transistor, and the first thin-film transistor is the aforementioned black-plug switch 16.

[0097] Among them, see Figure 13 and Figure 14 The first black plug extension section 12311, the second black plug extension section 12312 and the third black plug extension section 12313 are electrically connected to form the black plug signal line 123; the first common extension section 14311 and the second common extension section 14312 are electrically connected to form the common signal line 143.

[0098] Furthermore, the black insertion signal line 123 is electrically connected to the first drain electrode 142, and the first source electrode 141 is electrically connected to the pixel electrode 151. During the black insertion stage, the black insertion voltage on the black insertion signal line 123 can be transmitted to the pixel electrode 151 through the first thin film transistor, adjusting the potential of the pixel electrode 151 to the black insertion potential, so that the corresponding pixel appears black.

[0099] The first black plug extension section 12311, the second black plug extension section 12312 and the third black plug extension section 12313 are electrically connected by bridging.

[0100] See Figure 11 Specifically, the black insertion signal line 123 switches from the second metal layer 14 to the first metal layer 12 in the region near the pixel electrode 151 to form a first black insertion extension 12311, and the common signal line 143 switches from the first metal layer 12 to the second metal layer 14 in the same region to form a second common extension 14312. When the second common extension 14312 is located between the first black insertion extension 12311 and the pixel electrode 151, the second common extension 14312 can shield the first black insertion extension 12311, reducing the capacitive coupling effect of the first black insertion extension 12311 on the pixel electrode 151.

[0101] In this embodiment, by setting the black insertion signal line 123 and the common signal line 143 to be formed by multiple extension segments electrically connected in different metal layers, the film layer positions of the two can be adjusted in the local area covered by the pixel electrode 151, so that the common signal line 143 is located between the black insertion signal line 123 and the pixel electrode 151, reducing the parasitic coupling effect of the voltage change of the black insertion signal line 123 on the pixel electrode 151 and improving the stability of the potential of the pixel electrode 151.

[0102] In the third embodiment, see Figure 11 , Figure 12 , Figure 13 and Figure 14 The transparent conductive layer 15 also includes a second bridging portion 153, a third bridging portion 154 and a fourth bridging portion 155.

[0103] The first black bar extension segment 12311 and the second black bar extension segment 12312 are bridged by the second bridging part 153, and the first black bar extension segment 12311 and the third black bar extension segment 12313 are bridged by the fourth bridging part 155 to form the black bar signal line 123; the first common extension segment 14311 and the second common extension segment 14312 are bridged by the third bridging part 154 to form the common signal line 143.

[0104] Furthermore, the first corner 156 of the pixel electrode 151 has a first notch 1561, and the second bridging portion 153 and the third bridging portion 154 are located within the first notch 1561; the second corner 157 of the pixel electrode 151 has a second notch 1571, and the fourth bridging portion 155 is located within the second notch 1571.

[0105] Understandably, the first notch 1561 and the second notch 1571 are used to provide space for the bridging structure in the transparent conductive layer 15, preventing short circuits between the bridging portion and the pixel electrode 151. Further, the first common extension 14311 includes a first sub-common extension 143111, which extends along and is close to the black gate line 122. At the first notch 1561, the first sub-common extension 143111 bends towards the side close to the black gate line 122 to form a clearance area. The first notch 1561 and the clearance area together constitute a transition area, facilitating the bridging of the first black extension 12311 and the second black extension 12312 through the second bridging portion 153, and the bridging of the first common extension 14311 and the second common extension 14312 through the third bridging portion 154.

[0106] In this embodiment, by placing the second bridging portion 153, the third bridging portion 154, and the fourth bridging portion 155 within the corner notch of the pixel electrode 151, the common signal line 143 and the black insertion signal line 123 are connected by utilizing the corner area of ​​the pixel electrode 151, reducing the occupation of the main opening area of ​​the pixel. At the same time, the common signal line 143 is positioned between the black insertion signal line 123 and the pixel electrode 151 in the long side area of ​​the pixel electrode 151, thereby improving the shielding effect of the common signal line 143 on the black insertion signal line 123 and reducing the parasitic coupling effect of the black insertion signal line 123 on the pixel electrode 151.

[0107] In the third embodiment, see Figure 13 The first metal layer 12 also includes a charging gate line 121, and a first common extension 14311 is located between the charging gate line 121 and the black gate line 122.

[0108] The first common extension 14311 includes a first sub-common extension 143111 and a second sub-common extension 143112. The first sub-common extension 143111 extends along and is close to the black gate line 122. At the same time, the first sub-common extension 143111 and the second sub-common extension 143112 intersect.

[0109] Furthermore, the second common extension 14312 intersects with the first sub-common extension 143111, and the second common extension 14312 is bridged to the end of the first sub-common extension 143111 away from the second sub-common extension 143112 via the third bridging part 154.

[0110] In this embodiment, by placing the first sub-common extension 143111 close to the black insertion gate line 122 and electrically connecting it with the second common extension 14312, the common signal is introduced from the first metal layer 12 into the second metal layer 14, thereby shielding the black insertion signal line 123 extending along the long side of the pixel and reducing the parasitic coupling effect of the black insertion signal line 123 on the pixel electrode 151.

[0111] In the third embodiment, see Figure 11 and Figure 14 The second common extension 14312 includes a third main body 143121 and a third protrusion 14321. The free end of the third protrusion 14321 extends to the area of ​​the first notch 1561, and the width of the third main body 143121 is greater than or equal to the width of the first black insertion extension 12311.

[0112] Specifically, within the length range of the third main body 143121, the third main body 143121 completely covers the first black insertion extension 12311.

[0113] Understandably, the orthographic projection of the third main body 143121 in the direction perpendicular to the first substrate 11 covers the orthographic projection of the first black insertion extension 12311 on the first substrate 11, thereby using the common potential of the third main body 143121 to shield the electric field change of the first black insertion extension 12311 and reduce the parasitic coupling effect of the first black insertion extension 12311 on the pixel electrode 151.

[0114] Furthermore, by utilizing the clearance space at the first corner 156 of the pixel electrode 151, the free end of the third protrusion 14321 extends to the area of ​​the first notch 1561, reducing the occupation of the main display area of ​​the pixel electrode 151 and increasing the aperture ratio.

[0115] In this embodiment, by setting the third main body 143121 to completely cover the first black insertion extension 12311, the parasitic coupling effect of the first black insertion extension 12311 on the pixel electrode 151 can be reduced, and the potential stability of the pixel electrode 151 can be improved. At the same time, by setting the third protrusion 14321 to extend to the area of ​​the first notch 1561, the clearance space at the corner of the pixel electrode 151 can be utilized to reduce the occupation of the main display area of ​​the pixel.

[0116] Furthermore, the pixel electrode 151 includes a second body portion 1511 and a second protrusion 1512 extending from the second body portion 1511 toward the black gate line 122; the first source electrode 141 is electrically connected to the second protrusion 1512 through a third via 173.

[0117] It is understood that the second main body 1511 is used to form the main display area of ​​the pixel, and the second protrusion 1512 is used to lead the pixel electrode 151 to a position close to the first source electrode 141, so that the first source electrode 141 does not need to extend into the main display area of ​​the pixel electrode 151, and can be electrically connected to the pixel electrode 151 through the third via 173.

[0118] Specifically, during the black insertion stage, the black insertion signal on the black insertion signal line 123 is transmitted to the first source electrode 141 via the first thin film transistor, and can then be transmitted to the second protrusion 1512 via the third via 173, and further transmitted to the second main body 1511, so that the potential of the pixel electrode 151 is adjusted to the black insertion potential.

[0119] In this embodiment, by providing a second protrusion 1512 extending from the second main body 1511 to the black gate line 122, the connection distance between the pixel electrode 151 and the first source electrode 141 can be shortened, which facilitates the arrangement of the third via 173 and improves the reliability of the electrical connection between the first source electrode 141 and the pixel electrode 151.

[0120] In the fourth embodiment, see Figure 15 , Figure 15 The third notch structure diagram of the fourth embodiment provided in this application shows that the charging gate line 121 has a third notch 159 on the side near the black insertion gate line 122. One end of the first black insertion extension 12311 extends into the third notch 159 and realizes the transition between the first black insertion extension 12313 and the third black insertion extension 12313 within the third notch 159.

[0121] Understandably, by setting a third notch 159 and extending one end of the first black insertion extension 12311 into the third notch 159, and achieving a transition between the third notch 159 and the third black insertion extension 12313, the second notch 1571 can be eliminated at the second corner 157 of the pixel electrode 151, reducing the occupation of the second main body 1511 area of ​​the pixel electrode 151 by the fourth bridging portion 155, and improving the pixel aperture ratio.

[0122] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. An array substrate, characterized in that, include: First substrate; A common signal line is disposed on the first substrate; A black signal line is inserted and disposed on the first substrate; A pixel electrode is disposed on the first substrate; The pixel electrode is electrically connected to the black-insertion signal line via a black-insertion switch; A black gate line is disposed on the first substrate and is used to control the black gate switch; The black insertion signal line passes through the area covered by the pixel electrode, and within the area covered by the pixel electrode, the common signal line is located between the black insertion signal line and the pixel electrode.

2. The array substrate according to claim 1, characterized in that, Within the area covered by the pixel electrode, the common signal line completely covers the black insertion signal line.

3. The array substrate according to claim 1, characterized in that, Also includes: A first metal layer is disposed on the first substrate; the first metal layer includes a first gate electrode, the black-inserted gate line, and the black-inserted signal line. A first insulating layer is disposed on the first substrate and covers the first metal layer; Semiconductor layer, including a first active layer; A second metal layer is disposed on the side of the first insulating layer away from the first substrate; the second metal layer includes a first source electrode, a first drain electrode, and the common signal line; the first gate electrode, the first source electrode, the first drain electrode, and the first active layer constitute a first thin-film transistor, which serves as the black-plug switch; A second insulating layer is disposed on the first insulating layer and covers the second metal layer; A transparent conductive layer is disposed on the side of the second insulating layer away from the first substrate; the transparent conductive layer includes the pixel electrode; The black signal line is electrically connected to the first drain electrode; the first source electrode is electrically connected to the pixel electrode through a third via.

4. The array substrate according to claim 3, characterized in that, The transparent conductive layer further includes a first bridging portion; the black signal line is electrically connected to one end of the first bridging portion through a first via, and the other end of the first bridging portion is electrically connected to the first drain electrode through a second via. The first metal layer further includes a charging gate line, which is spaced apart from the black insertion gate line; the black insertion signal line is disposed between the charging gate line and the black insertion gate line, and close to the black insertion gate line; the black insertion signal line includes a first body portion extending along the black insertion gate line and a first protrusion portion extending from the first body portion to the black insertion gate line; the first bridging portion is located between the first body portion and the black insertion gate line, and the first protrusion portion is electrically connected to one end of the first bridging portion through the first via.

5. The array substrate according to claim 4, characterized in that, The pixel electrode includes a second body portion and a second protrusion extending from the second body portion toward the black gate line; the first source electrode is electrically connected to the second protrusion through the third via.

6. The array substrate according to claim 5, characterized in that, The common signal line includes a first extension extending along the black gate line, the width of the first extension being greater than or equal to the width of the first body portion; within the length of the first extension, the first extension completely covers the first body portion and exposes the first protrusion; the first extension has a first edge and a second edge, the first edge being close to the first protrusion, and a third edge of the second body portion being located between the first edge and the second edge.

7. The array substrate according to claim 1, characterized in that, Also includes: A first metal layer is disposed on the first substrate; the first metal layer includes a first gate electrode, a first black insertion extension, a first common extension, and the black insertion gate line. A first insulating layer is disposed on the first substrate and covers the first metal layer; Semiconductor layer, including a first active layer; A second metal layer is disposed on the side of the first insulating layer away from the first substrate; the second metal layer includes a first source electrode, a first drain electrode, a second black insertion extension, a third black insertion extension, and a second common extension; the first gate electrode, the first source electrode, the first drain electrode, and the first active layer constitute a first thin film transistor, and the first thin film transistor serves as the black insertion switch. A second insulating layer is disposed on the first insulating layer and covers the second metal layer; A transparent conductive layer is disposed on the side of the second insulating layer away from the first substrate; the transparent conductive layer includes the pixel electrode; The first black insertion extension segment, the second black insertion extension segment, and the third black insertion extension segment are electrically connected to form the black insertion signal line; the first common extension segment and the second common extension segment are electrically connected to form the common signal line; the black insertion signal line is electrically connected to the first drain electrode, and the first source electrode is electrically connected to the pixel electrode.

8. The array substrate according to claim 7, characterized in that, The transparent conductive layer further includes a second bridging portion, a third bridging portion, and a fourth bridging portion; the first black insertion extension segment and the second black insertion extension segment are bridged through the second bridging portion, and the first black insertion extension segment and the third black insertion extension segment are bridged through the fourth bridging portion, thereby forming the black insertion signal line; the first common extension segment and the second common extension segment are bridged through the third bridging portion, thereby forming the common signal line; the first corner of the pixel electrode has a first notch, and the second bridging portion and the third bridging portion are located within the first notch; the second corner of the pixel electrode has a second notch, and the fourth bridging portion is located within the second notch.

9. The array substrate according to claim 8, characterized in that, The first metal layer further includes a charging gate line, and the first common extension is located between the charging gate line and the black insertion gate line; the first common extension includes a first sub-common extension and a second sub-common extension; the first sub-common extension extends along the black insertion gate line and is close to the black insertion gate line; the first sub-common extension intersects with the second sub-common extension; the second common extension intersects with the first sub-common extension, and the second common extension is bridged to the end of the first sub-common extension away from the second sub-common extension through the third bridging portion.

10. A display panel, characterized in that, include: For the substrate; The array substrate according to any one of claims 1-9; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

Images