A diffraction mask and a preparation method of a high-voltage LED chip using the same

Abstract

The application provides a diffraction mask and a preparation method of a high-voltage LED chip using the same. The diffraction mask comprises a plurality of diffraction mask bodies arranged in sequence according to the sequence of crystal grain electrode connection; a crystal grain bridging channel arranged between two adjacent diffraction mask bodies; and light shielding components arranged in sequence according to the sequence of crystal grain electrode connection, wherein the light shielding components are arranged on one side of the diffraction mask bodies, the light shielding components comprise a plurality of first grating areas arranged on the side of the diffraction mask bodies facing the crystal grain bridging channel, the first grating areas comprise a first light shielding area arranged close to the crystal grain bridging channel and a first light transmission area arranged on the side of the first light shielding area away from the crystal grain bridging channel; and a second grating area is further arranged in the first light transmission area, wherein the second grating area comprises a second light shielding area and a second light transmission area arranged in the first light transmission area in sequence along the length direction of the first light transmission area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a diffraction mask and a method for preparing a high-voltage LED chip using the diffraction mask. Background Technology

[0002] In LED manufacturing, photolithography is crucial, as it defines key patterns such as steps (mesa), electrodes, and insulating layers. Conventional LEDs are single dies with relatively low operating voltages, typically between 2.8V and 3.6V. High-voltage LEDs, on the other hand, consist of multiple micro-dies connected in series on the same chip, and their operating voltage is a multiple of that of a single die. High-voltage LEDs offer superior performance with high luminous efficiency and low thermal resistance. The development and manufacturing of low-cost, high-efficiency high-voltage products has become a competitive trend in the industry. To address increasingly fierce market competition and customers' ever-increasing demands for cost and efficiency, an in-depth evaluation of existing LED high-voltage product production lines has been conducted.

[0003] While the current dual-bridging process can meet product quality standards, it has drawbacks such as complex production process, long cycle, high resource consumption and high overall cost.

[0004] In the existing technology, in order to manufacture high-voltage LED products and achieve the required morphology for bridging between chips, the traditional approach requires two exposure processes, which are complex and costly. Moreover, there are overlay errors between multiple photolithography processes, which may cause deviations in the position of the chip pattern structure and the light-emitting area, thereby affecting the chip yield. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a diffraction mask and a method for fabricating a high-voltage LED chip using the diffraction mask. By utilizing the characteristics of the diffraction mask, the functional pattern and optical pattern of the chip can be formed simultaneously in a single exposure and a subsequent etching, thereby simplifying the process, reducing production costs, and improving chip performance.

[0006] A diffraction mask, comprising: Several diffraction mask bodies are arranged sequentially according to the order of grain electrode connection; A grain bridging channel is set between two adjacent diffraction mask bodies; The light-shielding components are arranged sequentially according to the order of the grain electrode connection. The light-shielding components are disposed on one side of the diffraction mask body. The light-shielding components include a plurality of first grating regions arranged on the side of the diffraction mask body facing the grain bridging channel. The first grating region includes a first light-shielding region disposed near the grain bridging channel and a first light-transmitting region disposed on the side of the first light-shielding region away from the grain bridging channel. A second grating area is also provided within the first light-transmitting area. The second grating area includes a second light-blocking area and a second light-transmitting area arranged sequentially along the length of the first light-transmitting area within the first light-transmitting area.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: By setting a composite structure of a grain bridging channel, a first grating region, and a second grating region, and utilizing the diffraction effect generated by the different spatial arrangements of each region, functional patterns and optical microstructure patterns can be formed on the photoresist in a single exposure, while the traditional solution requires two exposures to complete all functions; by merging the functional patterns and optical patterns onto the same diffraction mask, the number of masks is reduced from two to one, directly saving the cost of diffraction mask plates; at the same time, the amount of photoresist used, chemical reagents used, and energy consumption are reduced; since all patterns are designed on the same diffraction mask and transferred through a single exposure, the operation step of "the second exposure needs to be aligned with the first pattern" in the traditional solution is eliminated, fundamentally eliminating the inherent defect of overlay misalignment error.

[0008] Furthermore, the width of the grain bridging channel is 7μm-10μm.

[0009] Furthermore, the width of the first light-shielding area is 1μm-1.5μm.

[0010] Furthermore, the width of the first light-transmitting area is 0.5μm-0.9μm.

[0011] Furthermore, the widths of both the second light-shielding area and the second light-transmitting area are 0.5μm-0.9μm, and the length of the second light-transmitting area gradually decreases along the direction away from the grain bridging channel.

[0012] On the other hand, the present invention also provides a method for fabricating a high-voltage LED chip, using the diffraction mask as described above, the fabrication method comprising: S1. A sapphire substrate LED wafer is provided, wherein the surface of the sapphire substrate LED wafer has undergone epitaxial growth and mesa etching. S2. A layer of positive photoresist is uniformly coated on the surface of the LED wafer on the sapphire substrate. After coating, a soft baking process is performed to remove the solvent and enhance the adhesion of the photoresist film. S3. The sapphire substrate LED wafer coated with positive photoresist in step S2 is loaded into a projection exposure machine. The diffraction mask is loaded onto the mask stage of the exposure machine, and an exposure operation is performed to transfer the pattern on the diffraction mask onto the positive photoresist. S4. A developing solution is coated on the sapphire substrate LED wafer exposed in step S3. The photoresist in the exposed area is selectively dissolved. After development, a photolithographic pattern is presented on the surface of the sapphire substrate LED wafer. The photolithographic pattern includes functional patterns and optical microstructure patterns. S5. Dry etching is performed on the sapphire substrate LED wafer after development in step S4. The etching process transfers the photolithographic pattern on the positive photoresist to the epitaxial layer of the sapphire substrate LED wafer to form a micron-level three-dimensional structure. S6. Remove the residual positive photoresist on the sapphire substrate LED wafer after dry etching in step S5, and continue with subsequent processes.

[0013] Furthermore, in step S2, the thickness of the positive photoresist coating is 10μm-15μm.

[0014] Furthermore, in step S5, the etching depth of the dry etching is 1μm-3μm.

[0015] Furthermore, in step S5, the sidewall inclination angle of the bridging structure formed after etching is 30°-55°, and the sidewall inclination angle of the passageway structure is 50°-85°.

[0016] Furthermore, in step S6, subsequent processes include: preparing a transparent conductive layer; preparing an electrode; depositing a passivation protective layer; backside grinding and thinning; dicing and separation; and testing and sorting. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the diffraction mask in Embodiment 1 of the present invention; Figure 2 for Figure 1 A magnified schematic diagram of part A in the middle; Figure 3 This is a schematic diagram of the fabrication method of the high-voltage LED chip in Embodiment 2 of the present invention; Figure 4 This is a bridging morphology view of the high-voltage LED chip prepared by Example 2 of the present invention under a FIB electron microscope; Figure 5 This is a view of the channel morphology of the high-voltage LED chip prepared by Example 2 of the present invention under a FIB electron microscope; Figure 6 This is a bridging morphology view of the high-voltage LED chip prepared by Example 3 of the present invention under a FIB electron microscope; Figure 7 This is a view of the channel morphology of the high-voltage LED chip prepared by Example 3 of the present invention under a FIB electron microscope; Figure 8This is a bridging morphology view of a high-voltage LED chip obtained through two processes, IS1 and IS2, under a FIB electron microscope. Figure 9 This is a view of the channel morphology of a high-voltage LED chip obtained through two processes, IS1 and IS2, under a FIB electron microscope. Explanation of key component symbols:

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figures 1 to 2 The diffraction mask in Embodiment 1 of the present invention includes: Several diffraction mask bodies 10 are arranged sequentially according to the order of grain electrode connection; A grain bridging channel 20 is provided between two adjacent diffraction mask bodies 10; The light-shielding components 30 are arranged sequentially according to the order of the grain electrode connection. The light-shielding components 30 are disposed on one side of the diffraction mask body 10. The light-shielding components 30 include a plurality of first grating regions 31 arranged on the side of the diffraction mask body 10 facing the grain bridging channel 20. The first grating region 31 includes a first light-shielding region 311 disposed near the grain bridging channel 20 and a first light-transmitting region 312 disposed on the side of the first light-shielding region 311 away from the grain bridging channel 20. A second grating area 32 is also provided in the first light-transmitting area 312. The second grating area 32 includes a second light-blocking area 321 and a second light-transmitting area 322 arranged sequentially in the first light-transmitting area 312 along the length direction of the first light-transmitting area 312.

[0023] Understandably, by setting up the composite structure of the grain bridging channel 20, the first grating region 31, and the second grating region 32, and utilizing the diffraction effect generated by the different spatial arrangements of each region, functional patterns and optical microstructure patterns can be formed on the photoresist in a single exposure, whereas the traditional solution requires two exposures to complete all functions. By merging the functional and optical patterns onto the same diffraction mask, the number of diffraction masks is reduced from two to one, directly saving the cost of diffraction mask plates. At the same time, the amount of photoresist, chemical reagents, and energy consumption are reduced. Since all patterns are designed on the same diffraction mask and transferred through a single exposure, the operation step of "the second exposure needs to be aligned with the first pattern" in the traditional solution is eliminated, fundamentally eliminating the inherent defect of overlay misalignment error.

[0024] Furthermore, the width of the grain bridging channel 20 is 7μm-10μm.

[0025] Specifically, in this embodiment, the width of the grain bridging channel 20 is 8.5 μm.

[0026] Understandably, the width of the grain bridging channel 20 is set between 7μm and 10μm. As the main light-transmitting channel, the grain bridging channel 20 ensures that the photoresist in this area receives sufficient exposure (the width of the light-transmitting area is large enough to avoid diffraction loss). After development, it is fully open, thereby forming a reliable and low-resistance current connection path between the grains, ensuring uniform current transmission between the series-connected grains in the high-voltage LED chip. This width range is much larger than the exposure wavelength (usually 365nm for i-line), so the diffraction effect here can be ignored, and it is approximately geometric optical imaging.

[0027] Furthermore, the width of the first light-shielding area 311 is 1μm-1.5μm.

[0028] Specifically, in this embodiment, the width of the first light-shielding area 311 is 1.25 μm.

[0029] Understandably, the width of the first light-shielding area 311 is close to or slightly larger than the exposure wavelength, and it is located in the Fresnel diffraction region. When the light beam passes through the edges of these first light-shielding areas 311, a significant diffraction broadening effect is generated, forming controllable intensity side lobes in adjacent areas. The intensity of these side lobes is just enough to make the photoresist in the adjacent area reach a partial exposure dose, forming a tilted or gradient sidewall profile after development. By precisely controlling the width of the first light-shielding area 311, the distribution pattern of diffraction intensity can be adjusted, thereby achieving precise control of the tilt angle of the microstructure sidewall after etching. This provides a structural basis for obtaining the ideal angles of 30°-55° for bridging structures and 50°-85° for passageway structures. In other words, without this specific width of 1-1.5μm, the required diffraction sidelobe intensity distribution cannot be generated in a single exposure, and it is impossible to obtain two different sidewall angles.

[0030] Furthermore, the width of the first light-transmitting area 312 is 0.5μm-0.9μm.

[0031] Specifically, in this embodiment, the width of the first light-transmitting area is 0.7 μm.

[0032] Understandably, the width of the first light-transmitting area 312 is near the wavelength scale, and together with the first light-shielding area 311, it forms the first grating area 31. The narrow slit-shaped light-transmitting area produces a significant diffraction effect in the Fresnel diffraction region. Together with the adjacent first light-shielding area 311, it forms a light field with a specific intensity distribution on the photoresist surface. This non-uniformity of light intensity distribution is transformed into a periodically changing microscopic three-dimensional morphology after passing through the threshold response of the photoresist. The width design of 0.5μm-0.9μm takes into account both diffraction efficiency and process resolution requirements. It is through the differentiated width combination of the first light-transmitting area 312 and the first light-shielding area 311 that the functional channel pattern and the grating microstructure pattern can be formed simultaneously in one exposure.

[0033] Furthermore, the widths of the second light-shielding area 321 and the second light-transmitting area 322 are both 0.5μm-0.9μm, and the length of the second light-transmitting area 322 gradually decreases along the direction away from the grain bridging channel 20.

[0034] Specifically, in this embodiment, the widths of the second light-shielding area 321 and the second light-transmitting area 322 are both 0.7 μm.

[0035] Understandably, the widths of the second light-shielding region 321 and the second light-transmitting region 322 are near the wavelength scale, at which the diffraction effect is more intense. The spacing strategy of the second light-shielding region 321 and the second light-transmitting region 322 causes adjacent diffracted wavefronts to interfere with each other, forming constructive interference enhancement regions and destructive interference reduction regions at specific locations. After the threshold response of the photoresist, this interference pattern is transformed into a periodically changing microscopic three-dimensional morphology. The length of the second light-transmitting region 322 gradually decreases along the direction away from the grain bridging channel 20, making the diffracted light... The light intensity is gradually distributed along the direction away from the grain bridging channel 20 (the length of the second light-transmitting area 322 decreases, and the light intensity gradually weakens), thus forming a microstructure with a gradually changing aspect ratio after etching. This gradually changing structure can effectively change the propagation behavior of photons inside the chip, reduce the loss caused by total internal reflection, and increase the probability of photons escaping from the chip surface. Since the interference pattern formed by the second grating area 32 has a smoothing effect on the light intensity distribution, the sensitivity of the photolithography process to exposure energy fluctuations and focal length shifts is reduced, which is equivalent to expanding the ISO process window by about 15%-25%.

[0036] Example 2 Please see Figure 3 Embodiment 2 of the present invention also provides a method for fabricating a high-voltage LED chip, using the diffraction mask as described above, the fabrication method comprising: S1. A sapphire substrate LED wafer is provided, wherein the surface of the sapphire substrate LED wafer has undergone epitaxial growth and mesa etching. It should be noted that, specifically in this embodiment, the surface of the sapphire substrate LED wafer is etched using photolithography and chlorine etching to create a mesa.

[0037] S2. A layer of positive photoresist is uniformly coated on the surface of the LED wafer on the sapphire substrate. After coating, a soft baking process is performed to remove the solvent and enhance the adhesion of the photoresist film. Furthermore, in step S2, the thickness of the positive photoresist coating is 10μm-15μm.

[0038] Specifically, in this embodiment, the thickness of the positive photoresist coating is 10 μm.

[0039] Understandably, the thickness of the positive photoresist coating is 10μm-15μm, based on the following considerations: a sufficiently thick photoresist can withstand the long-term bombardment of subsequent dry etching without causing the photoresist layer to perforate or the sidewalls to collapse; this thickness range takes into account both resolution requirements and etching selectivity, that is, while ensuring pattern fineness, it has sufficient etching resistance; a thicker photoresist layer is conducive to forming microstructure patterns with a certain aspect ratio, providing sufficient etching mask margin for subsequent micron-level three-dimensional structures with an etching depth of 1μm-3μm.

[0040] S3. The sapphire substrate LED wafer coated with positive photoresist in step S2 is loaded into a projection exposure machine. The diffraction mask is loaded onto the mask stage of the exposure machine, and an exposure operation is performed to transfer the pattern on the diffraction mask onto the positive photoresist. Understandably, the pattern design of the diffraction mask fully utilizes the principle of light diffraction. Specifically, different transparent regions on the diffraction mask have different geometric dimensions and spatial arrangements. When a parallel beam passes through these differentiated transparent regions, due to the diffraction effect, a non-uniform intensity distribution is formed in the light field reaching the photoresist surface. This difference in light intensity caused by diffraction, where the light intensity is relatively weak or strong, corresponds precisely to the pattern contour required by the target microstructure. Therefore, the functional channel pattern and the optical microstructure pattern can be defined simultaneously in a single operation without two exposures.

[0041] S4. A developing solution is coated on the sapphire substrate LED wafer exposed in step S3. The photoresist in the exposed area is selectively dissolved. After development, a photolithographic pattern is presented on the surface of the sapphire substrate LED wafer. The photolithographic pattern includes functional patterns and optical microstructure patterns. It should be noted that the functional images include, for example, inter-grain current connection channels and electrode contact windows; the optical microstructure patterns include, for example, regularly arranged micron-scale protrusions / grooves arrays for light extraction enhancement.

[0042] S5. Dry etching is performed on the sapphire substrate LED wafer after development in step S4. The etching process transfers the photolithographic pattern on the positive photoresist to the epitaxial layer of the sapphire substrate LED wafer to form a micron-level three-dimensional structure. It should be noted that, specifically in this embodiment, inductively coupled plasma (ICP) etching is used, and the etching gas is a mixture of Cl2, BCl3 and Ar, which matches the material characteristics of chlorine etching in step S1.

[0043] Furthermore, in step S5, the etching depth of the dry etching is 1μm-3μm.

[0044] Specifically, in this embodiment, the etching depth of dry etching is 1 μm.

[0045] Understandably, in step S5, the etching depth of dry etching is 1μm-3μm. The adjustable range of etching depth 1μm-3μm can be flexibly adjusted according to product design requirements. This depth range can ensure that the two-dimensional pattern on the photoresist is fully transferred to the wafer epitaxial layer (forming a micron-level three-dimensional structure with light extraction enhancement function after removing the photoresist), while avoiding over-etching and affecting the electrical performance of the chip. Within this depth range, due to the use of a single exposure scheme based on the diffraction principle, the etched microstructure has a natural uniqueness in morphology. Parameters such as aspect ratio and sidewall tilt angle in different regions show regular changes due to the differences in the diffraction light field. This change helps to optimize the propagation path of photons inside the chip and improve light extraction efficiency.

[0046] Furthermore, in step S5, the sidewall inclination angle of the bridging structure formed after etching is 30°-55°, and the sidewall inclination angle of the passageway structure is 50°-85°.

[0047] Please see Figures 4-5 The image shows the bridging morphology view and the channel morphology view of the high-voltage LED chip prepared by Example 2 of the present invention under a FIB electron microscope.

[0048] Specifically, in this embodiment, the high-voltage LED chip prepared by Embodiment 2 of the present invention has a left tilt angle of 41° for the sidewall of the bridging structure under a FIB electron microscope, a right tilt angle of 41.2° for the sidewall of the bridging structure under a FIB electron microscope, a left tilt angle of 76° for the sidewall of the passageway structure under a FIB electron microscope, and a right tilt angle of 78.5° for the sidewall of the passageway structure under a FIB electron microscope.

[0049] S6. Remove the residual positive photoresist on the sapphire substrate LED wafer after dry etching in step S5, and continue with subsequent processes.

[0050] Furthermore, in step S6, subsequent processes include: preparing a transparent conductive layer; preparing an electrode; depositing a passivation protective layer; backside grinding and thinning; dicing and separation; and testing and sorting.

[0051] Example 3 Embodiment 3 of the present invention also provides a method for fabricating a high-voltage LED chip, using the diffraction mask as described above. The difference between this fabrication method and Embodiment 2 is that: Specifically, in this embodiment, the thickness of the positive photoresist coating is 15 μm.

[0052] Specifically, in this embodiment, the etching depth of dry etching is 1 μm.

[0053] Please see Figures 6-7The image shows the bridging morphology view and the channel morphology view of the high-voltage LED chip prepared by Example 3 of the present invention under a FIB electron microscope.

[0054] Specifically, in this embodiment, the high-voltage LED chip prepared by Embodiment 2 of the present invention has a left tilt angle of 40.9° for the sidewall of the bridging structure under a FIB electron microscope, a right tilt angle of 42.5° for the sidewall of the bridging structure under a FIB electron microscope, a left tilt angle of 58.3° for the sidewall of the passageway structure under a FIB electron microscope, and a right tilt angle of 55.1° for the sidewall of the passageway structure under a FIB electron microscope.

[0055] Comparative Example 1 Please see Figures 8-9 The image shows the bridging morphology and channel morphology of the high-voltage LED chip obtained through the IS1 and IS2 processes under a FIB electron microscope.

[0056] Specifically, in this comparative example, the high-voltage LED chip obtained through the IS1 and IS2 processes has a left tilt angle of 41° for the sidewall of the bridging structure under a FIB electron microscope, a right tilt angle of 40.6° for the sidewall of the bridging structure under a FIB electron microscope, a left tilt angle of 78.3° for the sidewall of the passage structure under a FIB electron microscope, and a right tilt angle of 77.6° for the sidewall of the passage structure under a FIB electron microscope.

[0057] It should be noted that the original process of LED high voltage chip bridging was an IS1 (for creating the channel pattern) and IS2 (for creating the bridging pattern) photolithography process. The bridging and channel angles were not consistent through the two processes of IS1 and IS2.

[0058] Understandably, through FIB electron microscopy morphology verification, the preparation methods of Examples 2 and 3 of this invention can simultaneously obtain two different tilt angles: the sidewall tilt angle of the bridging structure is 30°-55°, and the sidewall tilt angle of the passageway structure is 50°-85°, after a single exposure and one etching. This directly proves that the diffraction mask can simultaneously define two different angle requirements in a single process, achieving all the functions that traditional methods require at least two exposures to complete; and ensuring no double-segment angle phenomenon, avoiding the problems caused by two exposures in traditional double-bridging processes. The problem of poor pattern connection caused by photolithography deviation; the sidewall tilt angle of the bridging structure formed after etching is 30°-55°, and the sidewall tilt angle of the passage structure is 50°-85°, both of which meet the process requirements of high voltage LED products, ensuring the reliability of the current connection between chips (the smaller the bridging angle, the smoother the current channel and the better the coverage) and the integrity of the insulation layer coverage (the steeper the passage angle, the higher the space utilization); the comparison data between the original process and the new process show that the new process fully meets the original standard in terms of angle control, verifying the feasibility of the single bridging process replacing the double bridging process.

[0059] Understandably, Embodiments 2 and 3 of this invention combine the fabrication of functional and optical patterns into a single exposure, reducing the original two-layer lithography cycle (IS1 for pass patterning, IS2 for bridging patterning) to a single layer. This reduces the number of process nodes on the entire production line by approximately 30%-40%, and simplifies the high-voltage product process from a dual-bridging process to a single-bridging process, significantly simplifying the process flow. The number of diffraction masks is reduced from two to one, reducing photoresist usage, chemical reagent usage, and energy consumption. The overall manufacturing cost per wafer can be reduced by 15%-25%, resulting in a significant reduction in production costs. All chip bridging patterns originate from the same exposure, eliminating the traditional step of "aligning the second exposure with the first pattern," fundamentally eliminating overlay misalignment. The relative positional accuracy between the functional pattern and the optical pattern depends solely on the manufacturing precision of the diffraction mask itself, which is far higher than the overlay alignment precision of the Stepper equipment (±0.5μm level), ensuring the stability of appearance and electrical properties and eliminating overlay errors. The special microstructure formed by the diffraction interference design of the composite grating formed by the combination of the first grating area and the second grating area improves the light efficiency by 3%-8%. The cumulative yield improvement brought about by the simplification of the process, coupled with the increased process tolerance brought about by the increase in the ISO window, can improve the overall yield by 2-5 percentage points, improving both light efficiency and yield. It ensures that the side wall tilt angle of the bridging structure is 30°-55° and the side wall tilt angle of the passage structure is 50°-85°, both of which meet the process requirements and ensure that there is no double-segment angle phenomenon, resulting in stable product quality.

[0060] In summary, the diffraction mask and the fabrication method of the high-voltage LED chip using the diffraction mask in the above embodiments of the present invention, by setting a composite structure of a grain bridging channel, a first grating region, and a second grating region, utilizes the diffraction effect generated by the different spatial arrangements of each region, so that functional patterns and optical microstructure patterns can be formed on the photoresist in a single exposure, while the traditional solution requires two exposures to complete all functions; by merging the functional patterns and optical patterns onto the same diffraction mask, the number of masks is reduced from 2 to 1, directly saving the cost of diffraction mask plates; at the same time, the amount of photoresist used, the amount of chemical reagents used, and energy consumption are reduced; since all patterns are designed on the same diffraction mask and transferred through a single exposure, the operation step of "the second exposure needs to be aligned with the first pattern" in the traditional solution is eliminated, fundamentally eliminating the inherent defect of overlay misalignment error.

[0061] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0062] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A diffraction mask, characterized in that, include: Several diffraction mask bodies are arranged sequentially according to the order of grain electrode connection; A grain bridging channel is set between two adjacent diffraction mask bodies; The light-shielding components are arranged sequentially according to the order of the grain electrode connection. The light-shielding components are disposed on one side of the diffraction mask body. The light-shielding components include a plurality of first grating regions arranged on the side of the diffraction mask body facing the grain bridging channel. The first grating region includes a first light-shielding region disposed near the grain bridging channel and a first light-transmitting region disposed on the side of the first light-shielding region away from the grain bridging channel. A second grating area is also provided within the first light-transmitting area. The second grating area includes a second light-blocking area and a second light-transmitting area arranged sequentially along the length of the first light-transmitting area within the first light-transmitting area.

2. The diffraction mask according to claim 1, characterized in that, The width of the grain bridging channel is 7μm-10μm.

3. The diffraction mask according to claim 1, characterized in that, The width of the first light-shielding area is 1μm-1.5μm.

4. The diffraction mask according to claim 1, characterized in that, The width of the first light-transmitting area is 0.5μm-0.9μm.

5. The diffraction mask according to claim 1, characterized in that, The widths of the second light-shielding area and the second light-transmitting area are both 0.5μm-0.9μm, and the length of the second light-transmitting area gradually decreases along the direction away from the grain bridging channel.

6. A method for fabricating a high-voltage LED chip, using the diffraction mask as described in any one of claims 1-5, characterized in that, The preparation method includes: S1. A sapphire substrate LED wafer is provided, wherein the surface of the sapphire substrate LED wafer has undergone epitaxial growth and mesa etching. S2. A layer of positive photoresist is uniformly coated on the surface of the LED wafer on the sapphire substrate. After coating, a soft baking process is performed to remove the solvent and enhance the adhesion of the photoresist film. S3. The sapphire substrate LED wafer coated with positive photoresist in step S2 is loaded into a projection exposure machine. The diffraction mask is loaded onto the mask stage of the exposure machine, and an exposure operation is performed to transfer the pattern on the diffraction mask onto the positive photoresist. S4. A developing solution is coated on the sapphire substrate LED wafer exposed in step S3. The photoresist in the exposed area is selectively dissolved. After development, a photolithographic pattern is presented on the surface of the sapphire substrate LED wafer. The photolithographic pattern includes functional patterns and optical microstructure patterns. S5. Dry etching is performed on the sapphire substrate LED wafer after development in step S4. The etching process transfers the photolithographic pattern on the positive photoresist to the epitaxial layer of the sapphire substrate LED wafer to form a micron-level three-dimensional structure. S6. Remove the residual positive photoresist on the sapphire substrate LED wafer after dry etching in step S5, and continue with subsequent processes.

7. The method for preparing a high-voltage LED chip according to claim 6, characterized in that, In step S2, the thickness of the positive photoresist coating is 10μm-15μm.

8. The method for preparing a high-voltage LED chip according to claim 6, characterized in that, In step S5, the etching depth of dry etching is 1μm-3μm.

9. The method for preparing a high-voltage LED chip according to claim 6, characterized in that, In step S5, the sidewall inclination angle of the bridging structure formed after etching is 30°-55°, and the sidewall inclination angle of the passageway structure is 50°-85°.

10. The method for preparing a high-voltage LED chip according to claim 6, characterized in that, In step S6, subsequent processes include: preparing a transparent conductive layer; preparing an electrode; depositing a passivation protective layer; backside grinding and thinning; dicing and separation; and testing and sorting.

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