Photolithography mask layout optimization method and device, storage medium and electronic equipment

Abstract

The application discloses a photolithography mask layout optimization method and device, a storage medium and an electronic device. The photolithography mask layout optimization method comprises the following steps: obtaining an original mask layout, screening all Jogs from the original mask layout, and dividing all the Jogs into multiple Jog processing groups; constructing a three-layer hierarchical control architecture, wherein the three-layer hierarchical control architecture comprises a global control center, multiple regional control centers corresponding to the Jog processing groups, and multiple Jog processing units corresponding to the Jogs; under the three-layer hierarchical control architecture, a loop optimization step is performed until a preset termination condition is met, and an optimized mask layout is output. The application can effectively reduce the risk of new imaging defects caused by improper removal.

Description

Technical Field

[0001] This application relates to the field of photolithographic mask layout design technology, specifically to a photolithographic mask layout optimization method, apparatus, storage medium, and electronic device. Background Technology

[0002] As semiconductor manufacturing processes continue to evolve towards smaller nodes, lithography resolution is increasingly approaching physical limits, leading to an exponential increase in the complexity of mask design. In chip manufacturing, Optical Proximity Correction (OPC) is a crucial step in ensuring the quality of lithography imaging. Mask patterns contain numerous tiny jogs, which are minute bumps or depressions caused by directional changes during integrated circuit layout wiring. Before OPC correction, the mask pattern typically needs preprocessing to optimize or eliminate jogs that could lead to abnormal OPC calculations or manufacturing defects.

[0003] Currently, the preprocessing of jogs in a mask layout is usually as follows: traverse the vertices of the layout graphic, filter jogs according to preset geometric size thresholds (such as length, width, etc.), and then perform removal or smoothing operations on all filtered jogs according to uniform size rules.

[0004] However, the current jog screening and processing process is relatively simple, relying solely on geometric size thresholds for screening. It cannot accurately determine the surrounding map environment and adjacent graphic layout before removing or adjusting a jog, nor can it effectively predict the actual impact of jog removal on the local imaging quality. This results in preprocessing results that lack specificity and may even lead to new imaging defects due to improper removal. Summary of the Invention

[0005] This application provides a method, apparatus, storage medium, and electronic device for optimizing photolithographic mask layouts, which can effectively reduce the risk of new imaging defects caused by improper removal.

[0006] In a first aspect, embodiments of this application provide a method for optimizing photolithographic mask layouts, including: Obtain the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; A three-tiered hierarchical control architecture is constructed, comprising a global control center, multiple regional control centers corresponding to each of the Jog processing groups, and multiple Jog processing units corresponding to each of the Jogs. Under the three-layer hierarchical control architecture, a loop optimization step is executed until the preset termination condition is met, and the optimized mask layout is output. The loop optimization step includes: Each of the Jog processing units scores its corresponding Jog to generate a processing request; Each of the aforementioned regional control centers coordinates and arbitrates the processing requests and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information. The global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions. Each of the Jog processing units performs a local modification operation on the corresponding Jog according to its corresponding target execution instruction.

[0007] In the photolithographic mask layout optimization method provided in this application embodiment, the step of filtering out all Jogs from the original mask layout includes: Traverse all graphic vertices in the original mask layout and sequentially determine whether the directional change angle of the two adjacent edges at each graphic vertex is within a preset obvious turning angle range; If it is within the obvious turning angle range, then it is further determined whether the shorter side length at the vertex of the graphic is within the preset nanometer length range, and whether the vertical line width at the vertex of the graphic is within the preset nanometer width range. If all the above conditions are met, then the short side corresponding to the vertex of the graphic is marked as Jog.

[0008] In the photolithography mask layout optimization method provided in this application embodiment, the step of coordinating and arbitrating each processing request and resolving inter-group boundary conflicts by each of the aforementioned regional control centers to generate intra-group execution instructions and report status information includes: Each of the aforementioned regional control centers receives the corresponding processing request, coordinates and arbitrates each processing request, and resolves conflicts in the boundary areas between adjacent Jog processing groups. Based on the results of coordination, arbitration, and border conflict resolution, execution instructions are generated within the group, and the group's status information is reported to the global control center.

[0009] In the photolithographic mask layout optimization method provided in this application embodiment, the coordination and arbitration of processing requests within the group includes: Each of the aforementioned regional control centers shall compile statistics on the total number of Jogs currently requesting deletion and the total number of vacant positions requesting the addition of new Jogs within the corresponding Jog processing group; Calculate the maximum allowable change in a single round for the Jog processing group based on the current total number of Jogs in the group. When the total number of requested JOGs exceeds the maximum change amount, they are sorted from low to high according to their comprehensive impact score. From the sorted Jogs, the top N Jogs are selected for deletion, and the remaining Jogs that request deletion are downgraded to fine-tuning operations, where N is the value of the maximum change.

[0010] In the photolithographic mask layout optimization method provided in this application embodiment, the conflict resolution of the boundary region between adjacent Jog processing groups includes: Each of the aforementioned regional control centers extracts the modification plan for the Jog located in the physical boundary region of its corresponding target Jog processing group, and sends the modification plan to the adjacent regional control center corresponding to the adjacent Jog processing group; Receive the modification plan fed back by the target area control center corresponding to the adjacent Jog processing group; Determine whether the modification plans for the target Jog processing group and the adjacent Jog processing groups will cause the graphic spacing at the boundary to violate the preset design rules; If it is determined that the preset design rules are violated, the target area control center and the adjacent area control center shall each reduce the modification range of the boundary Jog according to a preset ratio until the violation is eliminated.

[0011] In the photolithography mask layout optimization method provided in this application embodiment, the step of maintaining global indicators by the global control center based on the status information reported by each regional control center, and issuing cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions includes: The global control center receives the status information reported by each of the regional control centers, maintains the total number of global Jogs and the global average quality score, and performs a global full-scale statistical analysis once every preset number of rounds to correct accumulated errors. Determine the overall direction of increase or decrease based on the deviation between the current total number of global Jogs and the preset target total number; Based on the average quality score within each group in the aforementioned status information, low-quality Jog processing groups are identified. Based on the overall increase / decrease direction and the low-quality Jog processing group, cross-group control instructions are generated and sent to each of the regional control centers, so that each of the regional control centers can adjust the execution instructions within the group according to the cross-group control instructions and generate target execution instructions.

[0012] In the photolithography mask layout optimization method provided in this application embodiment, the step of generating cross-group control instructions based on the overall increase / decrease direction and the low-quality Jog processing group includes: If the overall increase / decrease direction is decrease, the generated cross-group control instruction includes an allocation strategy that allocates the number of Jogs that need to be reduced to the low-quality Jog processing group. If the overall increase / decrease direction is increase, the generated cross-group control instruction includes an allocation strategy that distributes the number of Jogs that need to be increased to the remaining Jog processing groups other than the low-quality Jog processing group.

[0013] Secondly, embodiments of this application provide a photolithographic mask layout optimization apparatus, including: The acquisition module is used to acquire the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; The building module is used to build a three-layer hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each of the Jog processing groups, and multiple Jog processing units corresponding to each of the Jogs. The loop module is used to execute loop optimization steps under the three-layer hierarchical control architecture until a preset termination condition is met, and output the optimized mask layout. The loop optimization steps include: each Jog processing unit scores its corresponding Jog to generate a processing request; each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information; the global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the intra-group execution instructions and generate target execution instructions; each Jog processing unit performs local modification operations on its corresponding Jog according to its target execution instructions.

[0014] Thirdly, this application provides a storage medium storing a plurality of instructions that are adapted for loading by a processor to execute the photolithographic mask layout optimization method described in any of the preceding claims.

[0015] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the photolithographic mask layout optimization method described in any of the preceding claims.

[0016] In summary, the photolithography mask layout optimization method provided in this application includes obtaining the original mask layout, filtering out all JOGs from the original mask layout, and dividing all JOGs into multiple JOG processing groups; constructing a three-layer hierarchical control architecture, the three-layer hierarchical control architecture including a global control center, multiple region control centers corresponding to each JOG processing group, and multiple JOG processing units corresponding to each JOG; and executing a cyclic optimization step under the three-layer hierarchical control architecture until a preset termination condition is met, and outputting the optimized mask layout; the cyclic optimization step includes... The process includes: each Jog processing unit scoring its corresponding Jog to generate a processing request; each regional control center coordinating and arbitrating the processing requests and resolving inter-group boundary conflicts to generate intra-group execution instructions and report status information; the global control center maintaining global indicators based on the status information reported by each regional control center and issuing cross-group control instructions based on the global indicators to adjust the intra-group execution instructions and generate target execution instructions; and each Jog processing unit performing local modification operations on its corresponding Jog according to the target execution instructions. This embodiment of the application scores each Jog's corresponding Jog and generates targeted processing requests based on the scoring results, avoiding the problem of untargeted preprocessing results and effectively reducing the risk of new imaging defects caused by improper removal. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram illustrating an application scenario of the photolithographic mask layout optimization method provided in the embodiments of this application.

[0019] Figure 2 This is a schematic flowchart of the photolithographic mask layout optimization method provided in the embodiments of this application.

[0020] Figure 3 This is a flowchart illustrating the iterative optimization steps provided in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the structure of the photolithography mask layout optimization device provided in the embodiments of this application.

[0022] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0025] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0026] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0027] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] The current jog screening and processing process is relatively simple, relying solely on geometric size thresholds for screening. It cannot accurately determine the surrounding map environment and adjacent graphic layout before removing or adjusting a jog, nor can it effectively predict the actual impact of jog removal on the local imaging quality. This results in preprocessing results that lack specificity and may even lead to new imaging defects due to improper removal.

[0029] Based on this, embodiments of this application provide a photolithographic mask layout optimization method, apparatus, storage medium, and electronic device. Specifically, the photolithographic mask layout optimization apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablet computers, laptops, and personal computers (PCs), etc. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0030] For example, such as Figure 1 As shown, the electronic device can acquire the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; construct a three-layer hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog; under the three-layer hierarchical control architecture, perform cyclic optimization steps until a preset termination condition is met, and output the optimized mask layout; the cyclic optimization steps include: each Jog processing unit scores its corresponding Jog to generate a processing request; each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information; the global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust intra-group execution instructions and generate target execution instructions; each Jog processing unit performs local modification operations on its corresponding Jog according to its target execution instructions.

[0031] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0032] Please see Figure 2 , Figure 2 This is a schematic flowchart of the photolithographic mask layout optimization method provided in an embodiment of this application. The specific flow of the photolithographic mask layout optimization method is as follows: 101. Obtain the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups.

[0033] It should be noted that, in the embodiments of this application, "Jog" refers to a short edge in the mask layout that meets preset geometric conditions, and is composed of graphic vertices. During the screening process, short edges that meet the preset geometric conditions are found by traversing the graphic vertices and marked as Jogs. The initial attribute parameters set for each Jog include geometric attributes and the process influence factors of its layout environment, where the geometric attributes include the vertex coordinate information of the edges that make up the Jog. Subsequent data statistics and quality score calculations are performed at the Jog granularity.

[0034] The original mask layout data includes multiple graph vertices P_i (i=0,1,2,…,n) and the connection relationships between these vertices. In some embodiments, the specific process of filtering out all Jogs from the original mask layout can be as follows: First, we can iterate through all the graphic vertices in the original mask layout and determine in turn whether the angle of change of the direction of the two adjacent edges at each graphic vertex is within the preset obvious turning angle range.

[0035] The calculation method for the change in direction angle is as follows: For three consecutive vertices v_{i-1}, v_i, and v_{i+1}, calculate the edge vector from v_{i-1} to v_i, denoted as a = v_i - v_{i-1}, and the edge vector from v_i to v_{i+1}, denoted as b = v_{i+1} - v_i. The change in direction angle Δθ between the two edge vectors is calculated using the formula Δθ = min(|θ_i - θ_{i-1}|, 360° - |θ_i - θ_{i-1}|), where θ_i and θ_{i-1} are two adjacent direction angles, and the smaller of the two is taken as the minimum angle, ranging from 0 degrees to 180 degrees. Using this formula avoids the direction angle crossing the 360-degree boundary (for example, the difference between 350 degrees and 10 degrees is 20 degrees instead of 340 degrees).

[0036] In this embodiment, the preset obvious turning angle range is greater than or equal to 15 degrees and less than or equal to 165 degrees. By setting this obvious turning angle range, turns that are close to a straight line (less than 15 degrees) and close to the opposite direction (greater than 165 degrees) can be excluded, and only obvious and non-flat angle directional changes are retained as the primary condition for screening Jog.

[0037] If the directional change angle of the two adjacent sides at the vertex of the graphic is within the obvious turning angle range, then it is further determined whether the length of the shorter side at the vertex of the graphic is within the preset nanometer length range, and whether the vertical line width at the vertex of the graphic is within the preset nanometer width range.

[0038] Wherein, the shorter side length L = min(len_{i-1}, len_i), that is, the length of the shorter of the two adjacent sides of the vertex of the graphic; the nanometer-level length range is greater than or equal to 5 nanometers and less than or equal to 50 nanometers. The vertical linewidth W refers to the linewidth dimension perpendicular to the Jog direction, that is, the vertical distance between the two parallel sides at the turning point; the nanometer-level width range is greater than or equal to 3 nanometers and less than or equal to 20 nanometers. By setting this nanometer-level length range and nanometer-level width range, the screening range can be limited to small protrusions or depressions at the nanoscale, which are most prone to imaging distortion due to optical proximity effect during photolithography.

[0039] If all the above conditions are met, the shorter side corresponding to the vertex of the figure is marked as a Jog. Furthermore, during the Jog marking process, the concavity / convexity attribute of the Jog can be determined based on the sign of the cross product of the two adjacent edge vectors at the vertex. Specifically, for three consecutive vertices v_{i-1}, v_i, and v_{i+1}, the cross product cross = (v_i - v_{i-1}) × (v_{i+1} - v_i), i.e., cross = a × b. The specific calculation method for the cross product is as follows: for two-dimensional vectors a = (x_1, y_1) and b = (x_2, y_2), the cross product is a scalar x_1 × y_2 - y_1 × x_2. If cross ≠ 0, it means that the three points are not collinear, satisfying the precondition for convexity / concavity judgment. The cross judgment rule is: when sign(cross) = +1, it is marked as a convex Jog; when sign(cross) = -1, it is marked as a concave Jog. In a standard coordinate system (x to the right, y to the up), if cross > 0, it indicates a counter-clockwise rotation from a to b, and the vertex is a convex point; if cross < 0, it indicates a clockwise rotation, and the vertex is a concave point. This convexity / concavity attribute can serve as an important reference for subsequent scoring and processing strategy formulation.

[0040] In some embodiments, after filtering out all Jogs, a fast Jog pattern matching operation can be performed. This operation can be based on an angle-length dual hash index algorithm, which is designed for large-scale Jog pattern mining scenarios and can quickly identify Jog patterns from standard cell libraries or massive layouts.

[0041] Specifically, each Jog can be represented as a multidimensional feature (Δθ, L, W, sign), where Δθ is the angle difference (0 to 180 degrees), L is the length of the Jog (nanometers), W is the width of the Jog (nanometers), and sign is the concavity / convexity (+1 or -1). Since the above features are all continuous quantities or small-range integers, they need to be discretized before hashing. For example, the angle is quantized by a preset step size (e.g., 5 degrees), and the length is quantized by a preset step size (e.g., 1 nanometer). The discretized multidimensional features are encoded to generate hash key values. Jogs with the same hash key value are considered geometrically equivalent (under a given discrete precision). The generated hash key value is used to search in a pre-built global hash table. If the search is successful, the historical optimization processing strategy corresponding to the hash key value is directly called as the initial processing reference for the current Jog, thereby realizing the ability to quickly determine whether a Jog has appeared (O(1) search), automatically cluster similar Jog patterns, and support statistical analysis and pattern library construction. This hash matching mechanism can effectively improve the efficiency of subsequent processing.

[0042] The specific method for dividing all Jogs into multiple Jog processing groups can be as follows: calculate the spatial distance between each Jog based on the physical spatial coordinates of each Jog in the original mask layout; then use a clustering algorithm based on spatial density to group all Jogs whose spatial distance meets the preset neighborhood radius and are interconnected into the same Jog processing group.

[0043] In this embodiment, the spatial density-based clustering algorithm can be the DBSCAN density clustering algorithm, which can automatically identify noise points. Specifically, it can mark isolated Jogs with fewer than a preset minimum sample size in their neighborhood as noise points. These noise points are processed individually by the global control center without participating in the coordination and arbitration process of the regional control center. Through the above grouping strategy, all Jogs within the map can be grouped into the same Jog processing group according to the principle of regional proximity. Each group manages no more than 50 Jogs, and this number can be configured by the user based on the actual map size and computing resources.

[0044] In this embodiment, by introducing a Jog filtering mechanism based on multi-dimensional geometric conditions, combined with fast hash key matching and spatial density clustering, accurate identification, efficient classification and reasonable grouping of Jog are achieved, providing an accurate data foundation for subsequent hierarchical collaborative optimization, and effectively avoiding the problem of missing environmental information caused by traditional solutions that rely solely on a single geometric size threshold for filtering.

[0045] 102. Construct a three-tiered hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog.

[0046] Specifically, the three-tiered hierarchical control architecture can be constructed as follows: First, a global control center (L1 layer) is set up at the top level. This global control center is responsible for monitoring global metrics, allocating cross-group resources, and performing global calibrations periodically to avoid error accumulation. The global control center is the highest decision-making layer in the three-layer architecture. It does not directly handle specific Jog modification operations, but rather controls the overall optimization direction from a macro perspective.

[0047] Next, multiple regional control centers (L2 layer) are set up in the intermediate layer. Each regional control center corresponds to a specific Jog processing group, meaning each Jog processing group has one regional control center. Each regional control center is responsible for coordination and arbitration within its corresponding Jog processing group, quota balancing, and boundary coordination between adjacent Jog processing groups. Each regional control center manages all Jogs within its corresponding Jog processing group, up to a maximum of 50 Jogs, a number that can be configured by the user according to actual needs. Multiple regional control centers can execute processing tasks in parallel without interference, only exchanging information and coordinating when Jog modifications involve boundary regions.

[0048] Finally, multiple Jog processing units (L3 layer) are set up at the bottom layer, with each Jog processing unit corresponding to a specific Jog; that is, each Jog is configured with one Jog processing unit. Each Jog processing unit is responsible for calculating the comprehensive impact score based on the attribute parameters of the corresponding Jog, and performing specific modification operations such as removal, supplementation, or fine-tuning based on the score and the received instructions from the upper layer.

[0049] In this embodiment, by constructing a three-tiered hierarchical control architecture, global macro-control, regional coordination and arbitration, and individual execution operations can be decoupled into layers, resulting in clear responsibilities and reasonable division of labor among each layer. The global control center focuses on maintaining global indicators and allocating cross-group resources, the regional control centers focus on intra-group coordination and boundary resolution, and the Jog processing unit focuses on individual scoring and execution. The three layers work collaboratively, ensuring both overall optimization from a global perspective and achieving autonomy and parallel processing within each region, significantly improving the system's processing efficiency and scalability.

[0050] 103. Under the three-layer hierarchical control architecture, execute the loop optimization steps until the preset termination condition is met, and output the optimized mask layout.

[0051] In the embodiments of this application, such as Figure 3 As shown, this iterative optimization step may include the following steps: 1031. Each Jog processing unit scores its corresponding Jog to generate a processing request.

[0052] In some embodiments, each Jog processing unit can calculate the comprehensive impact score F_score of the Jog under the current process conditions based on the geometric attributes of the corresponding Jog and the process impact factors of its surrounding layout environment. This comprehensive impact score can be used to measure the overall impact of the Jog on imaging quality, area efficiency, and manufacturing cost. A higher score indicates that the Jog is more valuable and should be retained, while a lower score indicates that the Jog needs to be processed or removed.

[0053] Specifically, the formula for calculating the comprehensive impact score F_score is: F_score = w1 × S_image + w2 × S_area + w3 × S_cost. Here, w1, w2, and w3 are weighting coefficients, which can be customized by the user according to the actual manufacturing process requirements of the layout. S_image is the image quality impact factor, S_area is the area occupancy impact factor, and S_cost is the manufacturing cost impact factor. The factors considered in calculating this comprehensive impact score are highly flexible and can be adjusted according to the manufacturing process requirements of the layout, adding or removing factor items involved in the scoring.

[0054] The imaging quality impact factor S_image is calculated as follows: S_image = max(0, 1 - PV_band / CD). PV_band is the process variation band, and CD is the preset target linewidth (i.e., the critical dimension expected to be obtained in the photolithography process). In the EDA field, PV_band has various calculation methods depending on the layout process of different sizes, and different calculation methods can be used for different sizes of process layouts. For example, in the embodiments of this application, PV_band = 2 × (CD_nominal × Δ_proce) can be used, where CD_nominal is the target linewidth, and Δ_proce is the process fluctuation coefficient (reflecting the range of size fluctuations caused by factors such as exposure dose and focus offset during the photolithography process). The physical meaning of S_image is: when the process variation band PV_band approaches or exceeds the target linewidth CD, the probability of imaging failure (such as pattern breakage or bridging) at that Jog increases significantly, and the imaging quality impact factor approaches zero.

[0055] The formula for calculating the area occupancy impact factor S_area is: S_area = min(1, A_target / A_actual). Here, A_target is the target area or the known optimal area (i.e., the minimum allowable area for the Jog's location), and A_actual is the actual area. The physical meaning of S_area is: the closer the actual area is to or smaller than the target area, the higher the area efficiency and the higher the factor score; the larger the area, the lower the score, but not exceeding 1.

[0056] The manufacturing cost impact factor S_cost is calculated using the formula: S_cost = min(1, 1 - (N_layer / N_ref_layer × A_total / A_ref)). Where N_layer is the actual number of metal layers used, N_ref_layer is the reference number of layers (baseline design or target value), A_total is the actual total area, and A_ref is the reference area (baseline design or target value). The physical meaning of this factor is: the more layers and the larger the area, the higher the manufacturing cost, and the lower the score of this factor. This formula limits the lower limit of the score to 0 (i.e., 0 when the numerator is negative) to avoid excessive penalty, while limiting the upper limit of the score to 1.

[0057] In some embodiments, an adaptive precision grading strategy can be used when calculating the overall impact score. The core principle of this strategy is that not all jogs need to be calculated with high precision, thereby significantly improving computational efficiency in a layout of millions of jogs. Approximately 70% of the jogs are classified as low priority, which can save 50% to 70% of the computational load.

[0058] Specifically, priority levels can be set based on the angle size or the ratio of adjacent side lengths of a jog. For high-priority jogs with sharp angles (e.g., less than 60 degrees) or significantly disparate adjacent side lengths (e.g., side length ratio less than 0.3), all scoring factors, including the image quality impact factor S_image, area occupancy impact factor S_area, and manufacturing cost impact factor S_cost, are precisely calculated and weighted summed. For medium-priority jogs with angles in the middle range (e.g., 60 to 120 degrees), only the image quality impact factor S_image and manufacturing cost impact factor S_cost are calculated and weighted summed. For low-priority jogs with gentle angles (e.g., nearly straight, angle greater than 120 degrees), approximate estimates or historical cached scores are used directly without recalculation.

[0059] Finally, each Jog processing unit can generate a processing request based on the overall impact score F_score and its corresponding priority level. The types of processing requests include requests for deletion, requests for fine-tuning, or requests to maintain the status quo.

[0060] Specifically, when the overall impact score F_score is lower than a preset first threshold (e.g., below 40 points), a deletion request is generated; when the overall impact score F_score is in a preset middle range (e.g., 40 to 80 points), a fine-tuning request is generated; and when the overall impact score F_score is higher than a preset second threshold (e.g., above 80 points), a status quo request is generated. These thresholds can be customized by the user according to actual process requirements.

[0061] In this embodiment, by performing a comprehensive impact score on each Jog, the processing decision for each Jog has a multi-dimensional evaluation basis, avoiding the blindness of simply screening based on geometric size thresholds in traditional schemes. Simultaneously, through an adaptive precision grading strategy, the computational complexity is significantly reduced while ensuring evaluation quality.

[0062] 1032. Each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information.

[0063] Specifically, each regional control center can first receive the corresponding processing request, coordinate and arbitrate the processing requests, and resolve conflicts in the boundary areas between adjacent Jog processing groups; then, based on the results of coordination, arbitration and boundary conflict resolution, generate intra-group execution instructions and generate the group's status information to report to the global control center.

[0064] Specifically, the coordination and arbitration of various processing requests within the group can be carried out as follows: First, each regional control center receives processing requests reported by all Jog processing units within the corresponding Jog processing group, and counts the total number of Jogs currently requested to be deleted (R_remove) and the total number of vacant positions requested to be filled with new Jogs (A_add) within the corresponding Jog processing group.

[0065] It should be noted that each regional control center can also calculate the current total number of Jogs in its group, S_total; the average quality score Q_avg of all Jogs in the group; and the total cost score C_total of the group. Specifically, the current total number of Jogs in the group, S_total = ΣJog quantity; the average quality score Q_avg = (ΣS_quality) / S_total (i.e., the sum of the comprehensive impact scores of all Jogs in the group divided by the total number of Jogs); and the total cost C_total = ΣC_cost (i.e., the sum of the manufacturing cost scores of all Jogs in the group).

[0066] Next, based on the current total number of Jogs S_total in the Jog processing group, the maximum allowable change Δ_max for a single round in this group is calculated. This maximum change represents the upper limit of the number of Jogs that can be executed in this round of the group, and its calculation formula is: Δ_max=max(0.2×S_total,5), which is the larger value between 20% of the current total number of Jogs in the group and the preset minimum change value of 5.

[0067] When the total number of requested deletions, R_remove, exceeds the maximum change Δ_max, the Jobs can be sorted from lowest to highest according to their comprehensive impact score, F_score. From this sorted list, the top N Jobs are selected for deletion, while the remaining requested deletions are downgraded to fine-tuning operations, where N is the value of the maximum change Δ_max. This mechanism ensures that the change in Jobs within a single round remains within a controllable range, preventing oscillations caused by large-scale deletions or additions.

[0068] Similarly, for supplementary requests, when the total number of vacant positions A_add for supplementing new Jogs exceeds the maximum change Δ_max, the vacant positions can be sorted from highest to lowest according to their overall potential score, and the number of supplementary positions allocated equal to the maximum change Δ_max can be assigned. This overall potential score can be evaluated based on the surrounding map environment of the vacant position; the higher the potential of the vacant position to improve local imaging quality or reduce manufacturing costs, the higher its overall potential score.

[0069] In this embodiment of the application, conflict resolution of the boundary region between adjacent Jog processing groups can be specifically performed as follows: Each regional control center extracts the modification plan for the Jog located in the physical boundary region of its corresponding target Jog processing group and sends the modification plan to the adjacent regional control center corresponding to the adjacent Jog processing group; it receives the modification plan fed back by the target regional control center corresponding to the adjacent Jog processing group; it determines whether the modification plans of the target Jog processing group and the adjacent Jog processing group will cause the graphic spacing at the boundary to violate the preset design rules; if it is determined that the preset design rules are violated, the target regional control center and the adjacent regional control center reduce the modification range of the boundary Jog according to the preset ratio until the violation is eliminated.

[0070] This boundary conflict resolution mechanism ensures that the processing decisions of adjacent Jog processing groups are coordinated in the boundary area, avoiding problems such as one group deleting a Jog while the adjacent group adds a Jog, resulting in boundary spacing violations, or two groups simultaneously making conflicting modifications to the same Jog at the boundary.

[0071] Finally, each regional control center can generate intra-group execution instructions based on the results of the above-mentioned coordination, arbitration and boundary conflict resolution, and report the group's status information to the global control center.

[0072] In this embodiment, the status information may include: the current total number of Jogs in the group (S_total), the average quality score of all Jogs in the group (Q_avg), the current total cost score of the group (C_total), the number of deletion operations actually performed in this round (R_remove_actual), the number of addition operations actually performed in this round (A_add_actual), and the trend of the average quality score of the group compared to the previous round (quality_trend). The trend (quality_trend) is calculated as: quality_trend = Q_avg_current - Q_avg_prev, which is the average quality score within the group in the current round minus the average quality score within the group in the previous round. A positive value indicates an improvement in quality, a negative value indicates a decrease in quality, and a zero value indicates no change.

[0073] In some embodiments, the status information reported by each regional control center can be represented as: {group_id, S_total, Q_avg, C_total, R_remove_actual, A_add_actual, quality_trend}, where group_id is the unique identifier of the Jog processing group.

[0074] In this embodiment, the regional control center can perform quota balancing arbitration for requests within a group, effectively avoiding system overload or instability caused by the number of requests exceeding processing capacity. The inter-group boundary conflict resolution mechanism solves the problem of conflicting processing results between adjacent regions caused by considering only local factors in traditional solutions. The reporting of status information provides real-time and accurate data support for the macro-level decision-making of the global control center.

[0075] 1033. The global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions.

[0076] In this embodiment of the application, the global control center can receive the status information reported by each regional control center and maintain the total number of global Jogs G_total and the global average quality score G_quality.

[0077] The global metrics are maintained as follows: Global total number of Jogs G_total = Σ S_total_i (the sum of the total number of Jogs in all Jog processing groups). Global average quality score G_quality = Σ (S_total_i × Q_avg_i) / G_total (the sum of the total number of Jogs in each group multiplied by the average quality scores of each group, divided by the global total number of Jogs). Global total cost G_cost = Σ C_total_i (the sum of the total costs in all Jog processing groups).

[0078] Specifically, in each round of optimization, the global control center only receives the changes in the number and quality of Jogs reported by each regional control center. This change is then added to the previous round's global total to obtain the current global total. This incremental update method eliminates the need for full statistics in each round, significantly reducing computational complexity. While full calculations can be performed in each round for smaller layouts, in large-scale layouts, incremental updates are used within each group, with periodic global round calibration.

[0079] Furthermore, every set number of rounds (e.g., 100 to 1000 rounds, customizable by the user based on the layout size; generally, the larger the layout size, the greater the calibration interval), the global control center performs a full global statistical analysis. This recalculates the total number of Jogs (G_total), the global average quality score (G_quality), and the global total cost (G_cost) across all Jog processing groups to correct for accumulated errors that may occur during incremental updates. This combined strategy of "incremental updates + periodic full calibration" ensures both computational efficiency and the accuracy of global metrics.

[0080] Next, the global control center determines the overall increase / decrease direction based on the deviation between the current global total number of Jogs (G_total) and the preset target total number. Specifically, if the current global total number of Jogs is greater than the preset target total number, the overall increase / decrease direction is determined to be "decrease"; if the current global total number of Jogs is less than the preset target total number, the overall increase / decrease direction is determined to be "increase".

[0081] Then, the global control center can identify low-quality Jog processing groups based on the group's average quality score Q_avg in each status information. These low-quality Jog processing groups are those whose group's average quality score is lower than the global average.

[0082] Next, cross-group control instructions are generated based on the overall increase / decrease direction and the low-quality Jog processing group.

[0083] Specifically, if the overall increase / decrease direction is decrease, the generated cross-group control instruction includes an allocation strategy that prioritizes allocating the number of Jogs to be reduced to the low-quality Jog processing group; if the overall increase / decrease direction is increase, the generated cross-group control instruction includes an allocation strategy that prioritizes allocating the number of Jogs to be increased to the remaining Jog processing groups other than the low-quality Jog processing group.

[0084] Understandably, the core principle of this allocation strategy is that when the number of jogs needs to be reduced, priority is given to reducing them from lower-quality groups, meaning that low-quality groups receive more removal quotas; when the number of jogs needs to be increased, priority is given to all groups other than low-quality groups, meaning that high-quality groups receive more supplementary budgets.

[0085] Finally, the global control center sends the cross-group control instructions to each regional control center. Each regional control center adjusts the execution instructions within the group according to the received cross-group control instructions, generates the target execution instructions, and sends the target execution instructions to the corresponding Jog processing units.

[0086] In this embodiment, the global control center can aggregate and analyze the status information of each regional control center and maintain global indicators, thereby achieving macro-level control over the overall optimization direction. Through an indicator maintenance mechanism of "incremental updates + periodic full calibration," data accuracy is ensured while maintaining efficiency in large-scale map processing. A cross-group control instruction generation mechanism based on deviation direction and low-quality group identification enables the rational allocation of cross-group resources, guiding the overall optimization towards a direction where the total number of Jogs is controllable and the overall quality is improved.

[0087] 1034. Each Jog processing unit performs local modification operations on the corresponding Jog according to its corresponding target execution instructions.

[0088] In some embodiments, each Jog processing unit may receive a target execution instruction issued by its corresponding regional control center and perform a local modification operation on the corresponding Jog according to the target execution instruction.

[0089] It should be noted that the embodiments of this application involve two types of instructions, which differ in their source, function, and execution level. The intra-group execution instruction is generated by the regional control center after completing intra-group coordination arbitration and boundary conflict resolution. It includes the specific action type (delete, move, or add) for each Jog within the group and the corresponding operation location information. The cross-group control instruction is generated by the global control center based on the status information reported by each regional control center and issued to each regional control center. It includes the Jog quantity quota target for each Jog processing group (i.e., the number of Jogs that need to be reduced or increased), used at the macro level to guide each regional control center in adjusting the total number of Jogs within the corresponding Jog processing group.

[0090] After receiving the cross-group control instruction, the regional control center adjusts the group execution instructions based on the quota target contained in the cross-group control instruction, combined with the comprehensive impact score of each Jog in the group and the specific content of the current group execution instructions. This adjustment includes, but is not limited to, adjusting the Jogs that need to be deleted or added and their specific operation positions, thereby generating the target execution instructions and issuing the target execution instructions to the corresponding Jog processing units.

[0091] Based on the above mechanism, in practice, each Jog processing unit receives and executes the target execution instruction, and performs corresponding local modification operations based on the target execution instruction. Cross-group control instructions are received by the regional control center, transformed into target execution instructions, and then issued to the Jog processing units. The Jog processing units do not directly execute cross-group control instructions. The regional control center adjusts the intra-group execution instructions according to the quota targets of the cross-group control instructions, ensuring that the adjusted target execution instructions retain the rationality of intra-group coordination arbitration and boundary conflict resolution, while also reflecting the macro-control direction of the global control center.

[0092] Specifically, if a deletion command is received, the Jog is removed from the original mask layout, and the vertices of the two adjacent edges before and after the Jog are directly connected to smooth out the transition. If a move command is received, the Jog is offset by a set distance along the bisector of the angle at the transition point. This set distance can be dynamically determined based on the Jog's overall impact score and the surrounding layout environment. If a add command is received, a new Jog is inserted at the equidistant position of the target edge to form a new Jog structure. The specific position and shape of the new Jog can be determined based on the evaluation results of the vacant position.

[0093] In this embodiment, the aforementioned partial modification operation can be performed based on a doubly linked list data structure. This doubly linked list is used to sequentially store all Jogs within the current Jog processing group and their spatial coordinate information. Each node records its coordinates, layer, and a snapshot of the design rule check attributes. When performing a deletion operation, the predecessor and successor nodes of the current node in the doubly linked list can be directly connected. When performing a move operation, the spatial coordinates of the current node in the doubly linked list can be updated. When performing an addition operation, a new node is inserted at the corresponding position in the doubly linked list.

[0094] In some embodiments, after each local modification operation, a design rule check can be immediately performed on the affected local layout area. This design rule check only performs local verification (e.g., spacing check, short-circuit check) on the current node affected by the modification and its adjacent edges in the doubly linked list, rather than performing a design rule check on the entire chip layout. This local design rule check mechanism significantly reduces the computational overhead of the check while ensuring that the modification result conforms to the design rules. If the check result is a violation, the modification operation is revoked and the state before the modification is restored. This "probe-rollback" mechanism ensures the safety of the modification operation and avoids layout failure due to violations.

[0095] In another embodiment, to improve the optimization effect, the local perturbation annealing algorithm can be used to perform the above-mentioned local modification operations.

[0096] Specifically, for any Jog, a "local perturbation annealing algorithm" can be used, maintaining only a doubly linked list, local design rule checks, and an incremental resistor-delay update table. The incremental resistor-delay update table only updates the local network whose electrical properties change due to Jog changes, eliminating the need to re-extract resistor-delay parameters across the entire chip, thus ensuring operational efficiency. During algorithm execution, multiple random selections of non-endpoint Jogs in the linked list are used to perform exploratory operations such as deletion, movement, or addition (i.e., neighborhood perturbation). After each operation, a local design rule check is immediately performed. If the operation is successful (no design rule violations), it is retained; otherwise, it is immediately rolled back. This algorithm does not require a global cost function, gradually eliminating redundant points and violations through multiple local trials, and does not accept any inferior solutions. Through this annealing scheduling mechanism, for most layouts, a sufficient number of random trials can eliminate most redundant Jogs and minor violations, achieving a 90% optimization effect, minimizing complexity, and meeting the needs of practical engineering.

[0097] In this embodiment, three types of local modification operations (deletion, movement, and addition) provide a complete graphical modification means for the Jog processing unit. A doubly linked list data structure ensures efficient CRUD operations for Jog. Local design rule checks and violation rollback mechanisms significantly reduce checking overhead while ensuring the compliance of modification results. Multiple random trials using a local perturbation annealing algorithm achieve excellent optimization results with extremely low computational complexity.

[0098] By repeatedly executing steps 1031 to 1034 until the preset termination condition is met, the optimized mask layout can be obtained and output.

[0099] In this embodiment of the application, the preset termination condition includes any of the following termination scenarios: The first termination scenario: The total number of global jogs reaches the preset target range (e.g., within ±2% of the preset target total), and the global average quality score is higher than the preset health threshold (e.g., 80 points). This termination scenario indicates that the system has reached an ideal optimization state, and both the number of jogs and the quality score have met the expected goals.

[0100] The second termination scenario: The total number of iterations in the loop optimization step reaches the user-defined maximum number of iterations (e.g., 10,000 iterations). This termination scenario serves as a protection mechanism to prevent infinite loops, ensuring that the system can exit normally even in extreme cases.

[0101] The third termination scenario: In a series of iterations for a preset number of rounds (e.g., 200 rounds), the changes in both the total number of global Jogs and the global average quality score are less than a preset stagnation threshold. This termination scenario indicates that the system has entered a plateau phase, and further iterations are unlikely to yield further optimization benefits. To avoid wasting computing power, the loop is terminated.

[0102] Once any of the above termination conditions are met, the optimized doubly linked list data structure can be converted into a standard mask layout format (e.g., GDS format) for output. This output mask layout can be directly used for subsequent optical proximity correction processes or directly used for mask fabrication.

[0103] In this embodiment, a multi-round iterative optimization of Jogs in the mask layout is achieved by constructing a cyclic optimization step. Each cycle goes through four stages: individual scoring, regional coordination arbitration, global overall control, and local execution modification. The three-layer architecture forms a complete closed loop of "individual evaluation → regional coordination → global control → execution feedback". As the cycle iterates, the total number of Jogs gradually approaches the preset target, the overall quality score gradually improves, and finally converges to an optimized state that meets engineering requirements, realizing multi-objective collaborative optimization of Jog total control, imaging quality assurance, and manufacturing cost constraints.

[0104] The following example illustrates the photolithographic mask layout optimization method shown in the embodiments of this application through a practical application scenario.

[0105] In a chip design at a certain 12nm process node, the photomask layout contains approximately 1.2 million jogs, with a layout area of ​​approximately 100 square millimeters. Preprocessing is performed using the photolithographic photomask layout optimization method provided in this application embodiment: First, the original mask layout is obtained. All vertices of the graphic are traversed, and all Jogs that meet the criteria are selected according to the obvious turning angle range of 15 degrees to 165 degrees, the length range of 5 nanometers to 50 nanometers, and the width range of 3 nanometers to 20 nanometers. Then, the DBSCAN density clustering algorithm is used to divide all Jogs into approximately 24,000 Jog processing groups according to spatial distance, with approximately 50 Jogs in each group.

[0106] Then, a three-tiered hierarchical control architecture is constructed, and loop optimization is initiated. In the first loop, each Jog processing unit performs a comprehensive impact score for each Jog: F_score = w1 × S_image + w2 × S_area + w3 × S_cost. High-priority Jogs (angle less than 60 degrees) have their imaging quality, area efficiency, and manufacturing cost factors precisely calculated, while low-priority Jogs (angle greater than 120 degrees) directly use historical cached scores. The regional control center arbitrates requests within each group, and the maximum change Δ_max in a single round is constrained by the larger of 20% of the total number of Jogs in the current group and 5. The global control center maintains the total number of global Jogs G_total using an incremental update method, and performs a global full calibration every 500 rounds to correct errors.

[0107] After approximately 300 iterations, the total number of global Jogs decreased from the initial 1.2 million to the preset target value of approximately 950,000, and the global average quality score increased from the initial 62 to 84. At this point, the system detected that the total number of global Jogs had reached within ±2% of the preset target range and the global average quality score was higher than 80, triggering the first termination condition and outputting the optimized mask layout.

[0108] In this practical application, the processing speed was improved by about 4 times compared to the traditional one-by-one processing method. The optimized mask layout did not show any bridging or depression defects caused by Jog during the subsequent OPC correction process, and the chip tape-out yield was improved by about 3 percentage points.

[0109] In summary, the photolithography mask layout optimization method provided in this application, through each Jog processing unit performing a comprehensive impact score based on the geometric attributes of the corresponding Jog and the process influence factors of its layout environment, avoids the problems of missing environmental information and lack of targeted preprocessing caused by screening solely based on geometric size thresholds, effectively reducing the risk of new imaging defects caused by improper removal. By coordinating and arbitrating processing requests within the corresponding Jog processing group through each area control center, dynamically calculating the maximum allowable change per round for the group based on the current total number of Jogs, and combining the comprehensive impact score of each Jog to execute differentiated processing strategies, different layout areas receive processing intensity matching their needs, avoiding the problems of damaged imaging quality in critical areas and insufficient cost optimization in non-critical areas under uniform size rules. By dividing all Jogs into multiple Jog processing groups, each area... The domain control center performs parallel intra-group coordination arbitration and inter-group boundary conflict resolution for each Jog processing group, while the global control center maintains global indicators and issues cross-group control commands. This achieves parallel and efficient collaboration and global coordination among Jog processing groups, significantly improving processing speed and avoiding conflicts or performance degradation caused by local optimization results on a global scale. By constructing a three-tiered hierarchical control architecture consisting of a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog, the Jog processing units perform individual scoring, the regional control centers perform intra-group coordination arbitration and boundary conflict resolution, and the global control center maintains global indicators and issues cross-group control commands. This achieves multi-objective hierarchical collaborative optimization of the total number of Jogs, imaging quality, and manufacturing cost, effectively overcoming the technical challenge of traditional single-objective optimization strategies finding a reasonable balance among multiple objectives.

[0110] Therefore, the embodiments of this application achieve maximum optimization of Jog distribution while ensuring or improving photolithography accuracy, reducing mask manufacturing costs and improving chip yield. It has the advantages of high processing efficiency, strong global overall optimization capability, and high degree of preprocessing intelligence. It also has strong scalability, good robustness, and fast convergence speed, which can effectively accelerate local response speed and achieve multi-objective collaborative optimization.

[0111] To facilitate better implementation of the photolithographic mask layout optimization method provided in this application embodiment, this application embodiment also provides a photolithographic mask layout optimization apparatus. The meanings of the terms used are the same as in the photolithographic mask layout optimization method described above, and specific implementation details can be found in the descriptions in the method embodiments.

[0112] Please see Figure 4 , Figure 4This is a schematic diagram of the structure of a photolithography mask layout optimization device provided in an embodiment of this application. The photolithography mask layout optimization device may include an acquisition module 201, a construction module 202, and a loop module 203. The acquisition module 201 is used to acquire the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; Module 202 is used to build a three-layer hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog. The loop module 203 is used to execute loop optimization steps under a three-layer hierarchical control architecture until a preset termination condition is met, and output the optimized mask layout. The loop optimization steps include: each Jog processing unit scores its corresponding Jog to generate a processing request; each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information; the global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the intra-group execution instructions and generate target execution instructions; each Jog processing unit performs local modification operations on its corresponding Jog according to its target execution instructions.

[0113] For specific implementation methods of each of the above units, please refer to the embodiments of the photolithography mask layout optimization method described above, which will not be repeated here.

[0114] In summary, the photolithography mask layout optimization apparatus provided in this application embodiment can acquire the original mask layout through the acquisition module 201, filter out all JOGs from the original mask layout, and divide all JOGs into multiple JOG processing groups; the construction module 202 constructs a three-layer hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each JOG processing group, and multiple JOG processing units corresponding to each JOG; the loop module 203 executes loop optimization steps under the three-layer hierarchical control architecture until a preset termination condition is met, and outputs the optimized result. The optimized mask layout; the iterative optimization steps include: each Jog processing unit scores its corresponding Jog to generate a processing request; each regional control center coordinates and arbitrates the processing requests and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information; the global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the intra-group execution instructions and generate target execution instructions; each Jog processing unit performs local modification operations on its corresponding Jog according to its target execution instructions. This embodiment of the application scores each Jog processing unit's corresponding Jog and generates targeted processing requests based on the scoring results, avoiding the problem of untargeted preprocessing results and effectively reducing the risk of new imaging defects caused by improper removal. Furthermore, by constructing a three-tiered hierarchical control architecture consisting of a global control center, regional control centers, and Jog processing units, based on a comprehensive impact score for each Jog, the regional control centers coordinate and arbitrate processing requests within a group and resolve conflicts in boundary areas between adjacent Jog processing groups. The global control center maintains the total number of global Jogs and the global average quality score and issues cross-group control instructions. This achieves differentiated processing of different layout areas, parallel and efficient collaboration between groups, and multi-objective joint optimization of the total number of Jogs, imaging quality, and manufacturing cost. Under the premise of ensuring or improving lithography accuracy, the Jog distribution is optimized to the maximum extent, reducing mask manufacturing costs and improving chip yield.

[0115] This application also provides an electronic device that may integrate the photolithographic mask layout optimization device of this application, such as... Figure 5 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 5 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or the methods provided in this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0116] The memory 302 can be used to store software programs and the methods provided in this application. The processor 301 executes various functional applications and data processing by running the software programs stored in the memory 302 and the methods provided in this application. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0117] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows: Obtain the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; A three-tiered hierarchical control architecture is constructed, which includes a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog. Under the three-layer hierarchical control architecture, the loop optimization steps are executed until the preset termination condition is met, and the optimized mask layout is output. The iterative optimization steps include: Each Jog processing unit scores its corresponding Jog to generate a processing request; Each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information. The global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions. Each Jog processing unit performs local modification operations on the corresponding Jog according to its corresponding target execution instructions.

[0118] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0119] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps: Obtain the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; A three-tiered hierarchical control architecture is constructed, which includes a global control center, multiple regional control centers corresponding to each Jog processing group, and multiple Jog processing units corresponding to each Jog. Under the three-layer hierarchical control architecture, the loop optimization steps are executed until the preset termination condition is met, and the optimized mask layout is output. The iterative optimization steps include: Each Jog processing unit scores its corresponding Jog to generate a processing request; Each regional control center coordinates and arbitrates each processing request and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information. The global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions. Each Jog processing unit performs local modification operations on the corresponding Jog according to its corresponding target execution instructions.

[0120] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0121] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0122] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0123] The above provides a detailed description of the photolithographic mask layout optimization method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for optimizing photolithographic mask layout, characterized in that, include: Obtain the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; A three-tiered hierarchical control architecture is constructed, comprising a global control center, multiple regional control centers corresponding to each of the Jog processing groups, and multiple Jog processing units corresponding to each of the Jogs. Under the three-layer hierarchical control architecture, a loop optimization step is executed until the preset termination condition is met, and the optimized mask layout is output. The loop optimization step includes: Each of the Jog processing units scores its corresponding Jog to generate a processing request; Each of the aforementioned regional control centers coordinates and arbitrates the processing requests and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information. The global control center maintains global indicators based on the status information reported by each regional control center, and issues cross-group control instructions based on the global indicators to adjust the execution instructions within the group and generate target execution instructions. Each Jog processing unit performs a local modification operation on the corresponding Jog according to its corresponding target execution instruction.

2. The photolithographic mask layout optimization method as described in claim 1, characterized in that, The step of filtering all Jogs from the original mask layout includes: Traverse all graphic vertices in the original mask layout and sequentially determine whether the directional change angle of the two adjacent edges at each graphic vertex is within a preset obvious turning angle range; If it is within the obvious turning angle range, then it is further determined whether the shorter side length at the vertex of the graphic is within the preset nanometer length range, and whether the vertical line width at the vertex of the graphic is within the preset nanometer width range. If all the above conditions are met, then the short side corresponding to the vertex of the graphic is marked as Jog.

3. The photolithographic mask layout optimization method as described in claim 1, characterized in that, The process of coordinating and arbitrating the processing requests and resolving inter-group boundary conflicts by each of the aforementioned regional control centers to generate intra-group execution instructions and report status information includes: Each of the aforementioned regional control centers receives the corresponding processing request, coordinates and arbitrates each processing request, and resolves conflicts in the boundary areas between adjacent Jog processing groups. Based on the results of coordination, arbitration, and border conflict resolution, execution instructions are generated within the group, and the group's status information is reported to the global control center.

4. The photolithographic mask layout optimization method as described in claim 3, characterized in that, The coordination and arbitration of processing requests within the group includes: Each of the aforementioned regional control centers shall compile statistics on the total number of Jogs currently requesting deletion and the total number of vacant positions requesting the addition of new Jogs within the corresponding Jog processing group; Calculate the maximum allowable change in a single round for the Jog processing group based on the current total number of Jogs in the group. When the total number of requested JOGs exceeds the maximum change amount, they are sorted from low to high according to their comprehensive impact score. From the sorted Jogs, the top N Jogs are selected for deletion, and the remaining Jogs that request deletion are downgraded to fine-tuning operations, where N is the value of the maximum change.

5. The photolithographic mask layout optimization method as described in claim 3, characterized in that, The conflict resolution of the boundary region between adjacent Jog processing groups includes: Each of the aforementioned regional control centers extracts the modification plan for the Jog located in the physical boundary region of its corresponding target Jog processing group, and sends the modification plan to the adjacent regional control center corresponding to the adjacent Jog processing group; Receive the modification plan fed back by the target area control center corresponding to the adjacent Jog processing group; Determine whether the modification plans for the target Jog processing group and the adjacent Jog processing groups will cause the graphic spacing at the boundary to violate the preset design rules; If it is determined that the preset design rules are violated, the target area control center and the adjacent area control center shall each reduce the modification range of the boundary Jog according to a preset ratio until the violation is eliminated.

6. The photolithographic mask layout optimization method as described in claim 1, characterized in that, The process involves each global control center maintaining global indicators based on the status information reported by its respective regional control centers, and issuing cross-group control instructions based on these global indicators to adjust the execution instructions within the group and generate target execution instructions, including: The global control center receives the status information reported by each of the regional control centers, maintains the total number of global Jogs and the global average quality score, and performs a global full-scale statistical analysis once every preset number of rounds to correct accumulated errors. Determine the overall direction of increase or decrease based on the deviation between the current total number of global Jogs and the preset target total number; Based on the average quality score within each group in the aforementioned status information, low-quality Jog processing groups are identified. Based on the overall increase / decrease direction and the low-quality Jog processing group, cross-group control instructions are generated and sent to each of the regional control centers, so that each of the regional control centers can adjust the execution instructions within the group according to the cross-group control instructions and generate target execution instructions.

7. The photolithographic mask layout optimization method as described in claim 6, characterized in that, The generation of cross-group control instructions based on the overall increase / decrease direction and the low-quality Jog processing group includes: If the overall increase / decrease direction is decrease, the generated cross-group control instruction includes an allocation strategy that allocates the number of Jogs that need to be reduced to the low-quality Jog processing group. If the overall increase / decrease direction is increase, the generated cross-group control instruction includes an allocation strategy that distributes the number of Jogs that need to be increased to the remaining Jog processing groups other than the low-quality Jog processing group.

8. A photolithographic mask layout optimization device, characterized in that, include: The acquisition module is used to acquire the original mask layout, filter out all Jogs from the original mask layout, and divide all Jogs into multiple Jog processing groups; The building module is used to build a three-layer hierarchical control architecture, which includes a global control center, multiple regional control centers corresponding to each of the Jog processing groups, and multiple Jog processing units corresponding to each of the Jogs. The loop module is used to perform loop optimization steps under the three-layer hierarchical control architecture until the preset termination condition is met, and output the optimized mask layout. The loop optimization step includes: each of the Jog processing units scores its corresponding Jog to generate a processing request; Each of the aforementioned regional control centers coordinates and arbitrates the processing requests and resolves inter-group boundary conflicts to generate intra-group execution instructions and report status information. The global control center maintains global indicators based on the status information reported by each of the aforementioned regional control centers and issues cross-group control instructions based on the global indicators to adjust the intra-group execution instructions and generate target execution instructions. Each of the aforementioned Jog processing units performs local modification operations on the corresponding Jog according to its corresponding target execution instructions.

9. A storage medium, characterized in that, The storage medium stores multiple instructions, which are applicable to a processor for loading to execute the photolithographic mask layout optimization method according to any one of claims 1-7.

10. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the photolithographic mask layout optimization method as described in any one of claims 1-7.

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