Mask manufacturing method, device, storage medium and electronic equipment

Abstract

This application discloses a mask manufacturing method, apparatus, storage medium, and electronic device. The mask manufacturing method includes: acquiring an original layout, the original layout including a metal pattern with a first pitch; acquiring a sub-pattern, the seed pattern being a metal pattern with a second pitch, the second pitch being larger than the first pitch, and the seed pattern satisfying preset manufacturing design rules; using the seed pattern as a matching template, performing a pattern matching operation on the original layout to locate at least one target region matching the seed pattern; for each target region, replacing the entire metal pattern within the target region with the seed pattern to increase the metal pattern pitch of the target region from the first pitch to the second pitch, obtaining a target layout; performing optical proximity correction on the target layout to generate a mask pattern, and performing mask manufacturing based on the mask pattern. This application can improve the processing efficiency of layout pitch relaxation.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, specifically to a mask manufacturing method, apparatus, storage medium, and electronic device. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards smaller dimensions, the size of metal patterns in the back-end chip fabrication process continues to shrink, and the spacing and pitch (the distance from center to center of adjacent metal lines) between adjacent metal lines are approaching the limits of photolithography resolution. Even with resolution enhancement techniques such as customized light sources, optical proximity correction (OPC), and sub-resolution auxiliary patterning, when the pitch of the metal layer is too small, the photolithography imaging quality will still deteriorate sharply, leading to increased edge placement errors, a smaller process window, and even the inability to accurately reproduce the design pattern on the wafer. Therefore, before delivering the mask for manufacturing, performing pitch relaxation on metal patterns with excessively small pitches in the original layout to increase the spacing between adjacent metal lines has become a necessary preprocessing step to ensure manufacturability.

[0003] Currently, the industry mainly uses two methods to achieve pitch relaxation in metal patterns. The first method is the iterative movement method, which involves moving the position of each metal line outwards sequentially from the outside of the pattern to the inside. After each movement, it checks whether the current pitch has reached the target value (e.g., 80nm). If not, it continues to move the next line until the pitch between all metal lines meets the requirement. The second method is the batch calculation one-time movement method, which pre-calculates the amount of displacement required for each metal line in the pattern, and then moves all metal lines to the target position simultaneously according to the calculated displacement, thus avoiding multiple iterations.

[0004] However, for the line-by-line iterative move method, the computation time increases dramatically with the number of metal lines due to the need for multiple iterations, making it extremely inefficient for large-scale layouts. While the batch calculation one-time move method reduces the number of iterations, the displacement calculation itself still involves complex iterative operations. Furthermore, after moving all metal lines outwards, the spacing between the metal lines and other metal patterns in adjacent areas may violate the minimum spacing rule, introducing Manufacturing Rule Check (DRC) or Manufacturing Rule Check (MRC) violations, requiring additional correction and verification. Therefore, the current solutions have significant shortcomings in both processing efficiency and layout quality assurance. Summary of the Invention

[0005] This application provides a mask manufacturing method, apparatus, storage medium, and electronic device that can improve the processing efficiency of layout pitch relaxation.

[0006] In a first aspect, embodiments of this application provide a mask manufacturing method, including: Obtain the original layout, which includes a metal graphic with a first pitch; Obtain a seed pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfies a preset manufacturing design rule; Using the seed graphic as a matching template, a pattern matching operation is performed on the original layout to locate at least one target region that matches the seed graphic. For each target region, the metal pattern within the target region is replaced entirely with the seed pattern to increase the pitch of the metal pattern in the target region from the first pitch to the second pitch, thereby obtaining the target layout. Optical proximity correction is performed on the target pattern to generate a mask pattern, and a mask is fabricated based on the mask pattern.

[0007] In the mask manufacturing method provided in this application embodiment, the seed pattern includes: a core line group, which is composed of multiple parallel metal lines, each of which has the same line width and the same length; Wherein, the sum of the spacing between adjacent metal lines and the line width is equal to the second pitch.

[0008] In the mask manufacturing method provided in this application embodiment, the seed pattern further includes: A bounding box is used to define the matching range of the seed graphic, and the size of the bounding box is larger than the outer envelope size of the core line group; the bounding box is used to limit the size of the scanning window in the pattern matching operation to locate the target area that matches the overall outline of the seed graphic. An anchor point, located at a predetermined position within the bounding box, is used to precisely place the seed graphic into the coordinate position of the target region using the anchor point as an insertion reference during the overall replacement.

[0009] In the mask manufacturing method provided in this application embodiment, the step of using the seed pattern as a matching template and performing a pattern matching operation on the original layout to locate at least one target region that matches the seed pattern includes: Extract the first set of geometric features of the seed graphic; The original layout is traversed according to a predetermined scanning rule, and the second set of geometric features of the metal graphic within the current scanning window is extracted at each scanning position. Calculate the similarity between the first geometric feature set and the second geometric feature set; The similarity is compared with a preset threshold. When the similarity reaches the preset threshold, the region corresponding to the current scanning window is marked as the target region.

[0010] In the mask manufacturing method provided in this application embodiment, replacing the entire metal pattern in the target area with the seed pattern includes: Based on the coordinates of the target area, delete all metal graphics within the target area from the original map. Place the seed graphic entirely into the coordinates of the target region.

[0011] In the mask manufacturing method provided in this application embodiment, before obtaining the target layout after replacing the entire metal pattern in the target area with the seed pattern, the method further includes: Detect the distance between the boundary of each replaced target region and the adjacent unreplaced metal pattern; When the spacing is less than a predetermined minimum spacing threshold, the metal lines at the boundary of the seed pattern are finely adjusted so that the spacing meets the manufacturing design rules. When the spacing is greater than or equal to the predetermined minimum spacing threshold, the current boundary state is maintained.

[0012] In the mask manufacturing method provided in this application embodiment, after obtaining the target pattern and before performing the optical proximity effect correction, the method further includes: Perform manufacturing rule checks on the target layout; Perform an optical proximity effect correction compatibility assessment on the target layout and output the assessment index; When the evaluation index does not meet the preset conditions, a replacement seed graphic with a larger pitch is selected from the seed graphic library, and the pattern matching operation and the overall replacement are re-executed.

[0013] Secondly, embodiments of this application provide a mask manufacturing apparatus, comprising: The first acquisition unit is used to acquire the original layout, the original layout including a metal pattern with a first pitch; The second acquisition unit is used to acquire a seed pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule. A pattern matching unit is used to perform a pattern matching operation on the original layout using the seed graphic as a matching template to locate at least one target region that matches the seed graphic. A graphic replacement unit is used to replace the metal graphic in each target area with the seed graphic, thereby increasing the metal graphic pitch in the target area from the first pitch to the second pitch, to obtain the target layout. The mask generation unit is used to perform optical proximity effect correction on the target pattern, generate a mask pattern, and manufacture a mask based on the mask pattern.

[0014] Thirdly, this application provides a storage medium storing a plurality of instructions that are adapted for loading by a processor to execute the mask manufacturing method described in any of the preceding claims.

[0015] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the mask manufacturing method described in any of the preceding claims.

[0016] In summary, the mask manufacturing method provided in this application includes obtaining an original layout, the original layout including a metal pattern with a first pitch; obtaining a seed pattern, the seed pattern being a metal pattern with a second pitch, the second pitch being larger than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; using the seed pattern as a matching template, performing a pattern matching operation on the original layout to locate at least one target region matching the seed pattern; for each target region, replacing the metal pattern within the target region entirely with the seed pattern to increase the pitch of the metal pattern in the target region from the first pitch to the second pitch, obtaining a target layout; performing optical proximity correction on the target layout to generate a mask pattern, and performing mask manufacturing based on the mask pattern. This application embodiment can quickly convert small-pitch metal patterns into large-pitch metal patterns through pattern matching and overall pattern replacement, improving the processing efficiency of layout pitch relaxation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram illustrating an application scenario of the mask manufacturing method provided in the embodiments of this application.

[0019] Figure 2This is a schematic flowchart of the mask manufacturing method provided in the embodiments of this application.

[0020] Figure 3 This is a schematic diagram of the mask manufacturing apparatus provided in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0024] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0025] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0026] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Current pitch relaxation schemes for metal graphics have significant shortcomings in terms of processing efficiency and layout quality assurance.

[0028] Based on this, embodiments of this application provide a mask manufacturing method, apparatus, storage medium, and electronic device. Specifically, the mask manufacturing apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablet computers, laptops, and personal computers (PCs), etc. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0029] For example, such as Figure 1 As shown, the electronic device can acquire an original layout, which includes a metal pattern with a first pitch; acquire a sub-pattern, the seed pattern being a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; use the seed pattern as a matching template to perform a pattern matching operation on the original layout to locate at least one target region that matches the seed pattern; for each target region, replace the entire metal pattern within the target region with the seed pattern to increase the pitch of the metal pattern in the target region from the first pitch to the second pitch, thereby obtaining the target layout; perform optical proximity correction on the target layout to generate a mask pattern, and perform mask manufacturing based on the mask pattern.

[0030] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0031] Please see Figure 2 , Figure 2 This is a schematic flowchart of the mask manufacturing method provided in an embodiment of this application. The specific flow of the mask manufacturing method can be as follows: 101. Obtain the original layout, which includes a metal graphic with a first pitch.

[0032] The original layout is typically a layout data file in GDSII or OASIS format, which can be obtained from the chip design front end through the physical design flow. The original layout contains graphic data of multiple process layers. In this application embodiment, the specific object is the metal pattern in the metal layer, such as the parallel metal line pattern in the first metal layer (M1), the second metal layer (M2), or a higher metal interconnect layer.

[0033] In this embodiment, the metal pattern in the original layout has a first pitch. Here, pitch refers to the distance between the centers of two adjacent parallel metal lines. The value of the first pitch is typically small, for example, reaching 76nm, 74nm, or even smaller, which is close to or reaches the resolution limit of current photolithography processes. When the pitch of the metal pattern is too small, even with subsequent resolution enhancement techniques such as optical proximity correction (OPC), the photolithographic imaging quality is still difficult to guarantee. Therefore, pitch relaxation preprocessing is required for the original layout.

[0034] In practical applications, the original layout can be a complete layout of an entire chip, a layout of a functional module within the chip, or a layout of a tiled region after preliminary division. This application does not limit the scope or size of the original layout.

[0035] 102. Obtain a seed pattern, which is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying the preset manufacturing design rules.

[0036] Understandably, this seed graphic is the core template used for subsequent pattern matching and overall replacement operations, and its essence is a metal graphic unit with a target pitch.

[0037] In some embodiments, the seed pattern may include a core line group consisting of multiple parallel metal lines, each with the same linewidth and length. The sum of the spacing between adjacent metal lines and the linewidth equals a second pitch. For example, if the second pitch is 80 nm and the linewidth is 20 nm, then the spacing between adjacent metal lines is 60 nm. This second pitch is greater than the first pitch in the original layout (e.g., 76 nm) and is the target pitch value expected to be achieved in this pitch relaxation process.

[0038] In some embodiments, the seed graphic may further include a bounding box and anchor points. The bounding box defines the matching range of the seed graphic, and its size is larger than the outer envelope size of the core line group. That is, the bounding box reserves a certain amount of extra space around the core line group, which is used for boundary stitching and spacing detection after subsequent replacement operations. The anchor points are located at predetermined positions within the bounding box, such as the lower left corner vertex or the center point of the bounding box, and are used as insertion references during overall replacement to accurately place the seed graphic into the coordinate position of the target region.

[0039] It's important to note that after the seed pattern is constructed, it needs to be pre-verified through Manufacturing Rule Check (DRC) to ensure that its linewidth, spacing, and pattern density meet the manufacturing design rules of the target wafer fab. In other words, the seed pattern is a "pre-certified" pattern unit that meets the preset manufacturing design rules. This seed pattern can be pre-stored in a seed pattern library, which can contain multiple seed patterns. Each sub-pattern corresponds to a different target pitch value (e.g., 80nm, 90nm, 100nm) and different combinations of metal linewidth and spacing to adapt to the requirements of different process nodes and design rules.

[0040] In practical applications, pre-designed seed pattern files can be read from local storage media, downloaded from a remote server or cloud database, or automatically generated in real time according to the design rules of the current process node. For example, in one embodiment, when the original layout uses a 28nm process node, a seed pattern corresponding to an 80nm target pitch is automatically selected from the seed pattern library as a matching template; in another embodiment, when the original layout uses a 14nm process node, a seed pattern corresponding to a 64nm target pitch is selected.

[0041] In this embodiment, the seed pattern pre-satisfies the manufacturing design rules, avoiding the iterative process of repeatedly checking design rules in subsequent replacement operations, thereby significantly improving the overall efficiency of pitch relaxation. Simultaneously, the setting of bounding boxes and anchor points ensures clear boundary definitions and precise positioning benchmarks for pattern matching and replacement operations, guaranteeing the spatial accuracy of the replaced layout. By establishing a seed pattern library, it can flexibly adapt to different process nodes and different target pitch requirements, exhibiting good scalability.

[0042] 103. Using the seed graphic as a matching template, perform a pattern matching operation on the original layout to locate at least one target region that matches the seed graphic.

[0043] In this application embodiment, the following three optional pattern matching schemes are provided, which can be flexibly selected according to the size of the original layout, the complexity of the graphics, and hardware resources in practical applications. The details are as follows: The first method is a matching scheme based on geometric feature vectors. This scheme is the preferred implementation method and is particularly suitable for metal layer layouts with regular graphic structures and high repetition.

[0044] First, a first set of geometric features of the seed graphic can be extracted. This first set of geometric features is used to characterize the geometric properties of the seed graphic, and may include, but is not limited to, the following dimensions: the width of the metal lines, the spacing between adjacent metal lines, the length of the metal lines, the number of metal lines in the core line group (i.e., the number of repetition cycles), the overall outer envelope shape of the core line group, the size of the bounding box, etc. These geometric features, after being encoded, can form a "geometric fingerprint" or feature vector of the seed graphic. In one embodiment, the geometric feature vector can be stored in the form of a multidimensional array, such as a 6-dimensional vector [line width, spacing, length, number of lines, bounding box width, bounding box height].

[0045] Then, the original layout is traversed according to a predetermined scanning rule, and a second set of geometric features of the metal pattern within the current scanning window is extracted at each scanning position. This scanning rule can be a pixel-by-pixel sliding window scan, i.e., moving one unit step to the right or up each time (e.g., 1 nm), extracting the geometric features of the metal pattern within the current scanning window at each scanning position; or it can be a scan with larger step sizes (e.g., skip scans in units of pitch values) to speed up processing. It should be noted that the size of each scanning window is consistent with the bounding box size of the seed pattern.

[0046] Next, the similarity between the first geometric feature set and the second geometric feature set is calculated. This similarity can be calculated in various ways, such as by calculating the Euclidean distance between the two feature vectors (a smaller Euclidean distance indicates higher similarity); or by using cosine similarity, which calculates the cosine of the angle between the two feature vectors (a cosine value closer to 1 indicates higher similarity); or by using more complex graph matching algorithms such as polygon topology-based comparison methods. In one embodiment, cosine similarity can be used for calculation, with similarity values ​​ranging from 0 to 100%.

[0047] Finally, the similarity is compared with a preset threshold. When the similarity reaches the preset threshold, the region corresponding to the current scanning window is marked as the target region. This preset threshold can be set according to actual needs, for example, to 85% or 90%. A higher threshold results in a stricter match and a lower false positive rate, but may reduce the recall rate; a lower threshold results in a higher recall rate, but may match non-target patterns. In practical applications, this preset threshold can be flexibly adjusted according to the regularity of the layout. In one embodiment, for a highly regular memory chip layout, a high threshold of 95% can be used to ensure zero false positives; for a logic chip layout with more pattern variations, a medium threshold of 80% can be used to balance recall and accuracy.

[0048] In some embodiments, the scheme also supports a tolerance mechanism. Specifically, tolerance parameters can be set, including line width tolerance, line spacing tolerance, and line length tolerance. When the deviation between the size of the metal graphic and the seed graphic within the scanning window is within this tolerance range, it is still considered a match. For example, the line width tolerance can be set to ±2nm to ±5nm, the line spacing tolerance to ±2nm to ±5nm, and the line length tolerance to ±10nm or allow extended matching. This tolerance mechanism allows the embodiments of this application to adapt to graphic differences caused by design diversity in real-world layouts, such as slight misalignment of line ends or minor changes in line width, thereby improving the recall rate of the match.

[0049] Understandably, the extraction and comparison of geometric feature vectors are both numerical calculations, requiring no complex polygonal geometric operations, thus resulting in extremely fast computation speeds, making it particularly suitable for large-scale layouts containing tens or even hundreds of thousands of metal lines. Furthermore, by adjusting the similarity threshold and tolerance parameters, the accuracy of the matching can be flexibly controlled to adapt to the needs of different types of layouts.

[0050] The second method is a precise matching scheme based on polygon Boolean operations. This scheme is suitable for scenarios with extremely high matching accuracy requirements, such as when there are multiple similar but different graphic structures in the layout, and it is necessary to ensure zero error in the matching result.

[0051] In this scheme, both the seed graphic and the metal graphic in the original layout can be represented as a set of polygons. Each metal line is represented as one or more rectangular polygons, and the polygons are defined by a sequence of vertex coordinates.

[0052] Specifically, first, candidate regions with the same size as the seed graphic's bounding box are extracted from the original map, and all metal graphics within these candidate regions are converted into a first polygon set. Then, the core line group of the seed graphic is converted into a second polygon set. Next, a geometric intersection operation is performed on the first and second polygon sets, calculating the proportion of the intersection portion to the total area of ​​the seed graphic. If this proportion reaches a predetermined threshold (e.g., above 99.5%), the candidate region is determined to be a perfect match for the seed graphic. In some embodiments, in addition to area overlap, an edge-to-edge distance check can be added, that is, checking whether the distance between the edge of each metal line in the candidate region and the corresponding edge of the seed pattern is less than a predetermined tolerance (e.g., 1 nm). If both area overlap and edge distance meet the requirements, the match is considered successful.

[0053] Understandably, since this scheme does not involve feature extraction and similarity approximation calculation, but instead performs precise comparisons directly at the geometric level, the matching results have 100% accuracy and there are no false positives or false negatives.

[0054] The third approach is a reverse matching solution based on a manufacturing rule checking engine. This approach is suitable for scenarios where there is already a mature manufacturing rule checking toolchain, where existing electronic design automation infrastructure can be reused, and where it is not desired to introduce an additional matching engine.

[0055] In this solution, the "Find Specific Spacing Graphics" or "Find Specific Width Graphics" functions in the manufacturing rule checking tool can be used to transform the matching problem into a design rule checking problem. The specific process is as follows: First, based on the geometric parameters of the seed graphic, a set of design rule check commands are constructed. For example, if the spacing between adjacent metal lines in the seed graphic is S, a design rule check command is constructed to find all areas in the original layout where the spacing between adjacent metal lines is equal to S or within the S ± tolerance range. Then, this design rule check command is run to obtain a list of all locations that meet the spacing condition. Each location in this list records the coordinate information of a set of adjacent metal lines. Next, a window of the same size as the seed graphic's bounding box is expanded outward from each location in this list. The complete metal graphic within the window is extracted and compared a second time with the overall outline of the seed graphic. This second comparison can use area comparison or side count comparison to confirm whether the graphic within the window matches the seed graphic in its overall outline. Finally, the window that passes the second comparison is marked as the target area.

[0056] For example, a wafer fab uses Calibre as its manufacturing rule inspection tool. Based on the "find_spacing" command of this tool, an inspection script is constructed. First, all metal line pairs with a spacing of 76nm are searched to obtain about 500 candidate positions. Then, a second contour comparison is performed on these 500 candidate positions, and finally 480 are confirmed as target areas, while 20 areas with the same spacing but different overall contours are excluded.

[0057] In some embodiments, before performing pattern matching, the type of the original layout can be determined first, and then a corresponding scheme can be selected from the various pattern matching schemes mentioned above based on the type of the original layout for matching. This dynamic selection mechanism allows for the adoption of optimal matching strategies for layouts with different characteristics, thereby balancing matching speed and accuracy overall.

[0058] The type of the original layout can be classified according to at least one of the following dimensions: graphic regularity, layout data size, metal layer density, and polygon complexity in the graphic.

[0059] The regularity of the pattern is used to characterize the repetitiveness and regularity of metal patterns in the layout. It can be quantified and evaluated as follows: Divide the original layout into multiple grid cells, count the number of repeating patterns of metal patterns in each grid cell. If the proportion of repeating patterns to the total number of patterns exceeds a predetermined threshold (e.g., 80%), the layout is considered to have high regularity; otherwise, it is considered to have low regularity. When the original layout is determined to have high regularity, such as in the layout of a memory chip, its metal layer patterns are typically composed of a large number of repeating parallel metal line arrays, resulting in a very regular structure. In this case, the first scheme described above is chosen as the pattern matching scheme to leverage its fastest matching speed and complete the matching and positioning of the large-scale repeating array in the shortest possible time. When the original layout is determined to have low regularity, such as in the layout of random logic modules in high-performance computing chips or system-on-a-chip, its metal layer patterns are characterized by diverse shapes, varied orientations, and irregular sizes. In this case, the second scheme described above is preferred as the pattern matching scheme to ensure the accuracy of the matching results.

[0060] The data size of a map can be measured by the total number of metal graphics, the data file size, or the total area of ​​the map. When the total number of metal graphics in the original map is less than a first predetermined threshold (e.g., 100,000 polygons) or the data file size is less than a predetermined capacity threshold (e.g., 100MB), the map is considered a small-scale map. In this case, the absolute computation time of the three schemes is not significantly different, and the second scheme is preferred to obtain the most accurate matching result. When the total number of metal graphics in the original map is greater than or equal to the first predetermined threshold, the map is considered a large-scale map. In this case, computation speed becomes the primary consideration, and the first scheme is preferred to minimize the matching time.

[0061] When the hardware environment or software platform executing the embodiments of this application has integrated a manufacturing rule checking tool, and the manufacturing rule checking tool supports the function of "finding a specific spacing graphic", the third scheme described above can be selected as the pattern matching scheme. This selection strategy can make full use of existing tool capabilities and hardware licenses, without the need to deploy additional algorithm modules or apply for additional software licenses for the matching operation, thus reducing implementation costs and deployment complexity.

[0062] It should be noted that, regardless of which scheme is used, a matching result list will be output after the pattern matching operation is completed. Each record in the matching result list includes the coordinate range of the target region, the rotation angle of the target region relative to the seed graphic, and the matching confidence (the numerical value of the confidence in the first and second schemes, and a Boolean value of "match" or "not match" in the third scheme).

[0063] In this embodiment, the target area to be processed is located by pattern matching rather than by calculating each coordinate individually, fundamentally changing the implementation path of pitch relaxation and avoiding complex iterative calculations of displacement. The three schemes are suitable for different application scenarios, giving the technical solution of this embodiment good adaptability and flexibility. The dynamic selection mechanism further ensures that the optimal matching strategy is automatically selected under different map types without manual intervention. The tolerance mechanism and confidence output provide data support for subsequent manual review and process control.

[0064] 104. For each target area, replace the entire metal graphic within the target area with a seed graphic to increase the pitch of the metal graphic in the target area from the first pitch to the second pitch, thus obtaining the target layout.

[0065] In this embodiment, a complete replacement operation is performed for each target area. This complete replacement operation differs fundamentally from the traditional method of moving elements one by one or calculating displacements in batches. Specifically, the complete replacement operation can be as follows: First, based on the coordinates of the target area, delete all metal graphics within that target area from the original map. In other words, delete all existing metal line segments within the target area as a whole, rather than deleting them one by one.

[0066] Then, the entire seed graphic is placed into the target area at its coordinate position. Specifically, the anchor point of the seed graphic can be used as the insertion reference. The anchor point is aligned with the predetermined coordinate position of the target area (e.g., the lower left corner of the target area), and then all the metal lines of the seed graphic are placed into the target area at once.

[0067] It should be noted that for each target area, the above deletion and insertion operations constitute an atomic operation, meaning that the metal graphics within the target area are either completely replaced or not replaced at all; there is no intermediate state of partial replacement. This atomic characteristic ensures the consistency and integrity of the layout data, avoiding data corruption caused by partial replacement failure.

[0068] In some embodiments, after the overall replacement is completed, a boundary processing step is also included to ensure the cleanliness of the replaced layout in terms of design rules.

[0069] Specifically, the spacing between the boundary of each target area to be replaced and the adjacent unreplaced metal pattern can be detected first. Since the bounding box size of the seed pattern is larger than the outer envelope size of the core line group, a certain buffer space is reserved around the core line group. This buffer space is used for spacing detection and necessary fine-tuning with adjacent patterns after replacement. When the detected spacing is less than a predetermined minimum spacing threshold, the metal lines at the boundary of the seed pattern are fine-tuned to ensure the spacing meets manufacturing design rules. This fine-tuning can be achieved by slightly moving the boundary lines inward or slightly reducing the linewidth of the boundary lines. This predetermined minimum spacing threshold is derived from the design rule document of the target wafer fab. When the detected spacing is greater than or equal to this predetermined minimum spacing threshold, the current boundary state is maintained without any adjustment.

[0070] Since the replacement operations between each target region are independent and there is no data dependency, the embodiments of this application can use parallel computing to execute the replacement operations of all target regions. For example, multiple computing cores of a multi-core processor or a graphics processing unit (GPU) can be called to process different target regions simultaneously, thereby further accelerating the overall processing.

[0071] In practical applications, the original layout may contain dozens or even hundreds of matched target regions. In one specific embodiment, the layout of a memory chip contains approximately 200 target regions requiring pitch relaxation. Using parallel computing, the replacement operation is performed simultaneously on a 16-core processor, with the overall replacement time taking only a few hundred milliseconds. In contrast, in a comparative experiment using the traditional root-by-root moving method, the same layout would take several minutes to process.

[0072] In some embodiments, a replacement report can be output after all replacements are completed. This replacement report may include the total number of matched target areas, the number of successfully replaced areas, and a list of areas that were not successfully replaced and their reasons (e.g., skipped due to insufficient boundary spacing). Simultaneously, a target layout is output, in which the metal graphic pitch of all processed areas has been increased from the first pitch to the second pitch.

[0073] In this embodiment, the overall replacement method completes the pitch adjustment of all metal lines within the target area in one go, avoiding multiple iterative calculations caused by moving each line individually, resulting in a significant efficiency improvement. Atomicity operations ensure data consistency and avoid the risk of layout corruption. Boundary handling steps ensure that the replaced layout meets manufacturing design rules and does not introduce new design rule violations due to the replacement operation. The introduction of parallel computing further accelerates the processing, making this embodiment particularly suitable for large-scale, high-density integrated circuit layouts. Furthermore, since it is an overall replacement rather than displacement, the replaced metal pattern is a pre-verified "clean" pattern, avoiding spacing conflicts with adjacent patterns due to movement, fundamentally solving the manufacturing rule check violation problem that easily occurs in traditional solutions.

[0074] 105. Perform optical proximity correction on the target pattern to generate a mask pattern, and fabricate a mask based on the mask pattern.

[0075] In the embodiments of this application, the optical proximity effect correction can employ model-based optical proximity correction (MB-OPC) or rule-based optical proximity correction (RB-OPC). During the correction process, all metal patterns in the target layout are subjected to edge segmentation, edge movement, and the addition of auxiliary patterns (such as scattering bars and serifs) to compensate for the optical proximity effect during the photolithography process, so that the final image on the wafer is consistent with the design target.

[0076] Because the pitch of the metal patterns in the target layout has been significantly increased, the spacing between patterns is more ample, significantly reducing the difficulty of optical proximity correction. Specifically, during the correction process, there is sufficient space to insert sub-resolution auxiliary patterns (SRAF), the width of the process variation band (PV band) is significantly narrowed, and edge placement error (EPE) is easier to control within acceptable limits. Therefore, both the computation time for optical proximity correction and the quality of the corrected pattern are significantly improved.

[0077] After optical proximity correction is completed, a mask pattern (i.e., mask data stream, typically output in MEBES format) is generated. Then, based on this mask pattern, a physical mask is fabricated using an electron beam lithography machine or a laser lithography machine.

[0078] In actual testing, directly performing optical proximity correction on the original layout without pitch relaxation took approximately 120 minutes. Furthermore, the width of the process variation band in some areas exceeded the allowable range of the process window, requiring additional manual intervention and iterative correction. However, under the same process conditions, performing optical proximity correction on the target layout processed according to the embodiments of this application reduced the correction time to approximately 60 minutes, and the width of the process variation band in all areas remained within the allowable range of the design rules, requiring no additional manual intervention. This demonstrates that the mask manufacturing method provided by the embodiments of this application not only improves efficiency in the pitch relaxation stage but also has a positive impact on the subsequent optical proximity correction process, resulting in an overall efficiency gain.

[0079] In some embodiments, after obtaining the target layout and before performing optical proximity correction, this application embodiment further includes a verification step to ensure that the quality of the target layout meets the requirements of subsequent processes. Specifically, it may be as follows: First, a manufacturing rule check is performed on the target layout to verify whether the linewidth, spacing, area, density, and other parameters of all metal patterns in the target layout meet the design rules of the target wafer fab.

[0080] Then, an optical proximity effect correction compatibility assessment is performed on the target pattern, and evaluation metrics are output. These metrics include at least one of the following: minimum resolvable spacing (i.e., whether adjacent lines can be clearly distinguished after photolithography), sub-resolution auxiliary pattern insertion space (i.e., whether there is sufficient space to insert scattering strips next to the main pattern), process variation band width (i.e., the offset range of the pattern edge under dose and focal length variations), and edge placement error (i.e., the deviation between the edge and the designed target position after imaging). Embodiments of this application set corresponding preset conditions for these evaluation metrics, such as the process variation band width not exceeding the maximum value allowed by the design rules, and the edge placement error not exceeding the allowable range.

[0081] When the aforementioned evaluation metrics fail to meet the preset conditions, an alternative seed pattern with a larger pitch is selected from the seed pattern library (e.g., increasing the target pitch from 80nm to 90nm), and the pattern matching and overall replacement operations are re-executed until the evaluation metrics meet the preset conditions. This verification and iteration mechanism forms a complete quality assurance closed loop, ensuring that the final target layout input into the optical proximity effect correction process has good manufacturability and correction friendliness.

[0082] Understandably, due to the increased pitch of the target layout, the runtime of optical proximity correction is significantly shortened, the quality of the corrected pattern is significantly improved, and the process window is more ample. The verification step ensures that the target layout meets the requirements in both design rules and optical proximity correction compatibility, avoiding the problem being discovered only at the mask manufacturing stage and resulting in high rework costs. The automatic iteration mechanism further guarantees the quality of the final output target layout, making the mask manufacturing method provided in this application highly automated and robust.

[0083] In summary, the mask manufacturing method provided in this application includes obtaining an original layout, which includes a metal pattern with a first pitch; obtaining a seed pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; using the seed pattern as a matching template, performing a pattern matching operation on the original layout to locate at least one target region matching the seed pattern; for each target region, replacing the metal pattern within the target region entirely with the seed pattern to increase the pitch of the metal pattern in the target region from the first pitch to the second pitch, thereby obtaining a target layout; performing optical proximity correction on the target layout to generate a mask pattern, and performing mask manufacturing based on the mask pattern. This application embodiment can quickly locate small-pitch metal pattern regions through pattern matching and uses an overall replacement method to replace the small-pitch metal pattern with a seed pattern of the target pitch in one go, improving the processing efficiency of layout pitch relaxation while avoiding the introduction of new manufacturing rule violations due to moving metal lines one by one, thus ensuring layout quality.

[0084] To facilitate better implementation of the mask manufacturing method provided in this application, this application also provides a mask manufacturing apparatus. The meanings of the terms used are the same as in the mask manufacturing method described above, and specific implementation details can be found in the descriptions within the method embodiments.

[0085] Please see Figure 3 , Figure 3 This is a schematic diagram of the mask manufacturing apparatus provided in an embodiment of this application. The mask manufacturing apparatus may include a first acquisition unit 201, a second acquisition unit 202, a pattern matching unit 203, a pattern replacement unit 204, and a mask generation unit 205. The first acquisition unit 201 is used to acquire the original layout, which includes a metal graphic with a first pitch. The second acquisition unit 202 is used to acquire a sub-pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch is greater than the first pitch, and the seed pattern satisfies a preset manufacturing design rule. The pattern matching unit 203 is used to perform a pattern matching operation on the original layout using a seed graphic as a matching template in order to locate at least one target region that matches the seed graphic. The graphic replacement unit 204 is used to replace the metal graphic in each target area with the seed graphic, so as to increase the metal graphic pitch in the target area from the first pitch to the second pitch, thereby obtaining the target layout. The mask generation unit 205 is used to perform optical proximity correction on the target pattern, generate a mask pattern, and manufacture a mask based on the mask pattern.

[0086] For specific implementation methods of each of the above units, please refer to the embodiments of the mask manufacturing method described above, which will not be repeated here.

[0087] In summary, the mask manufacturing apparatus provided in this application embodiment can acquire an original layout by a first acquisition unit 201, the original layout including a metal pattern with a first pitch; acquire a sub-pattern by a second acquisition unit 202, the seed pattern being a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; use the seed pattern as a matching template by a pattern matching unit 203 to perform a pattern matching operation on the original layout to locate at least one target area that matches the seed pattern; replace the metal pattern in each target area with the seed pattern by a pattern replacement unit 204 to increase the pitch of the metal pattern in the target area from the first pitch to the second pitch, thereby obtaining a target layout; and perform optical proximity effect correction on the target layout by a mask generation unit 205 to generate a mask pattern, and perform mask manufacturing based on the mask pattern. This application embodiment can quickly locate small-pitch metal graphic areas through pattern matching, and use a whole-body replacement method to replace the small-pitch metal graphic with the seed graphic of the target pitch in one go, thereby improving the processing efficiency of layout pitch relaxation, while avoiding the introduction of new manufacturing rule violations due to moving metal lines one by one, thus ensuring layout quality.

[0088] This application also provides an electronic device that may integrate the mask manufacturing apparatus of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or the methods provided in this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0089] The memory 302 can be used to store software programs and the methods provided in this application. The processor 301 executes various functional applications and data processing by running the software programs stored in the memory 302 and the methods provided in this application. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0090] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows: Obtain the original layout, which includes a metal graphic with a first pitch; Obtain a sub-pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; Using the seed graphic as a matching template, perform pattern matching operations on the original layout to locate at least one target region that matches the seed graphic. For each target area, the metal pattern within the target area is replaced with a seed pattern to increase the pitch of the metal pattern in the target area from the first pitch to the second pitch, thus obtaining the target layout. Optical proximity correction is performed on the target pattern to generate a mask pattern, and mask fabrication is performed based on the mask pattern.

[0091] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0092] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps: Obtain the original layout, which includes a metal graphic with a first pitch; Obtain a sub-pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule; Using the seed graphic as a matching template, perform pattern matching operations on the original layout to locate at least one target region that matches the seed graphic. For each target area, the metal pattern within the target area is replaced with a seed pattern to increase the pitch of the metal pattern in the target area from the first pitch to the second pitch, thus obtaining the target layout. Optical proximity correction is performed on the target pattern to generate a mask pattern, and mask fabrication is performed based on the mask pattern.

[0093] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0094] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0095] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0096] The mask manufacturing method, apparatus, storage medium, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for manufacturing a mask, characterized in that, include: Obtain the original layout, which includes a metal graphic with a first pitch; Obtain a seed pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfies a preset manufacturing design rule; Using the seed graphic as a matching template, a pattern matching operation is performed on the original layout to locate at least one target region that matches the seed graphic. For each target region, the metal pattern within the target region is replaced entirely with the seed pattern to increase the pitch of the metal pattern in the target region from the first pitch to the second pitch, thereby obtaining the target layout. Optical proximity correction is performed on the target pattern to generate a mask pattern, and a mask is fabricated based on the mask pattern.

2. The mask manufacturing method as described in claim 1, characterized in that, The seed graphic includes: a core line group, which is composed of multiple parallel metal lines, each of which has the same line width and the same length; Wherein, the sum of the spacing between adjacent metal lines and the line width is equal to the second pitch.

3. The mask manufacturing method as described in claim 2, characterized in that, The seed graphic also includes: A bounding box is used to define the matching range of the seed graphic, and the size of the bounding box is larger than the outer envelope size of the core line group; the bounding box is used to limit the size of the scanning window in the pattern matching operation to locate the target area that matches the overall outline of the seed graphic. An anchor point, located at a predetermined position within the bounding box, is used to precisely place the seed graphic into the coordinate position of the target region using the anchor point as an insertion reference during the overall replacement.

4. The mask manufacturing method as described in claim 1, characterized in that, The step of using the seed graphic as a matching template to perform a pattern matching operation on the original layout to locate at least one target region that matches the seed graphic includes: Extract the first set of geometric features of the seed graphic; The original layout is traversed according to a predetermined scanning rule, and the second set of geometric features of the metal graphic within the current scanning window is extracted at each scanning position. Calculate the similarity between the first geometric feature set and the second geometric feature set; The similarity is compared with a preset threshold. When the similarity reaches the preset threshold, the region corresponding to the current scanning window is marked as the target region.

5. The mask manufacturing method as described in claim 1, characterized in that, The step of replacing the entire metal pattern within the target area with the seed pattern includes: Based on the coordinates of the target area, delete all metal graphics within the target area from the original map. Place the seed graphic entirely into the coordinates of the target region.

6. The mask manufacturing method as described in claim 1, characterized in that, After replacing the entire metal pattern within the target area with the seed pattern and before obtaining the target layout, the method further includes: Detect the distance between the boundary of each replaced target region and the adjacent unreplaced metal pattern; When the spacing is less than a predetermined minimum spacing threshold, the metal lines at the boundary of the seed pattern are finely adjusted so that the spacing meets the manufacturing design rules. When the spacing is greater than or equal to the predetermined minimum spacing threshold, the current boundary state is maintained.

7. The mask manufacturing method as described in claim 1, characterized in that, After obtaining the target layout but before performing the optical proximity correction, the method further includes: Perform manufacturing rule checks on the target layout; Perform an optical proximity effect correction compatibility assessment on the target layout and output the assessment index; When the evaluation index does not meet the preset conditions, a replacement seed graphic with a larger pitch is selected from the seed graphic library, and the pattern matching operation and the overall replacement are re-executed.

8. A mask manufacturing apparatus, characterized in that, include: The first acquisition unit is used to acquire the original layout, the original layout including a metal pattern with a first pitch; The second acquisition unit is used to acquire a seed pattern, wherein the seed pattern is a metal pattern with a second pitch, the second pitch being greater than the first pitch, and the seed pattern satisfying a preset manufacturing design rule. A pattern matching unit is used to perform a pattern matching operation on the original layout using the seed graphic as a matching template to locate at least one target region that matches the seed graphic. A graphic replacement unit is used to replace the metal graphic in each target area with the seed graphic, thereby increasing the metal graphic pitch in the target area from the first pitch to the second pitch, to obtain the target layout. The mask generation unit is used to perform optical proximity effect correction on the target pattern, generate a mask pattern, and manufacture a mask based on the mask pattern.

9. A storage medium, characterized in that, The storage medium stores a plurality of instructions, which are applicable to a processor for loading to execute the mask manufacturing method according to any one of claims 1-7.

10. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the mask manufacturing method as described in any one of claims 1-7.

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