An online monitoring method for the running state of a poultry slaughtering production line equipment

Abstract

The application provides an online monitoring method for the running state of poultry slaughtering production line equipment, which comprises the following steps: taking the reference clock count value corresponding to the scanning period of the controller as a reference, setting the basic clock count value which is co-prime to the reference clock count value, and generating periodic NMI pulses in combination with the frequency of hardware events; taking the equipment driving current, position feedback and temperature change rate as hardware events, and generating instant NMI pulses when the hardware events cross the adaptive nonlinear threshold boundary; after the NMI trigger, locking the hardware time stamp and reading the interrupt source identification, grabbing the corresponding original state data according to the identification, and writing the original state data into the dual-port RAM; and then completing the scrambling packet according to the address difference value and the time stamp characteristics, matching the CRC polynomial to generate the check code, and sending the check code to the data processing unit through DMA.

Description

Technical Field

[0001] This application belongs to the field of online monitoring, and in particular relates to a method for online monitoring of the operating status of poultry slaughtering production line equipment. Background Technology

[0002] Poultry slaughtering production lines typically operate in high-temperature, high-humidity, and easily contaminated environments. Under prolonged high-load operation, related equipment is prone to mechanical wear, physical jamming, or electrical failures. Without real-time online monitoring of the operating status of core equipment such as cutting, conveying, driving, and temperature control systems, sudden malfunctions can lead to production line shutdowns, reduced capacity, and economic losses. Furthermore, delayed handling of anomalies can compromise food hygiene and personnel safety. Current industrial automation monitoring methods largely rely on conventional polling scanning mechanisms or ordinary maskable interrupt mechanisms of the main controller. However, poultry slaughtering production lines are characterized by high equipment operation frequency, numerous concurrent states, and short-duration anomalies. Fixed-cycle polling is easily constrained by the main program's scanning cycle, resulting in delayed responses to transient anomalies. Ordinary interrupt mechanisms, under high-density concurrent events, may also miss critical underlying anomaly signals due to priority conflicts, excessive nesting, or system task blocking.

[0003] Furthermore, the process of uploading underlying equipment status data to the upper-level data processing system suffers from several issues, including insufficient synchronization of acquisition timing, impact of on-site electromagnetic interference on transmission reliability, low security of direct transmission of raw data, and high communication channel occupancy. These problems make it difficult to meet the requirements of industrial sites for real-time monitoring, completeness, and traceability of monitoring data. Therefore, there is an urgent need for an online monitoring method for the operating status of poultry slaughtering production line equipment that can reduce the impact of routine program execution cycles, promptly capture sudden equipment conditions, and balance timing consistency and transmission reliability during data acquisition, caching, verification, and transmission. Summary of the Invention

[0004] To address the problems in existing technologies where equipment status monitoring is constrained by polling cycles, prone to missing transient anomalies due to ordinary interruptions, poor timing synchronization of data acquisition, and insufficient transmission reliability, making it difficult to meet the real-time requirements of online monitoring in production lines, the present invention provides, in a first aspect, a method for online monitoring of the operating status of poultry slaughtering production line equipment, the method comprising:

[0005] The reference clock count value is determined based on the controller scan cycle and the master clock reference, and a basic interrupt cycle count value that is coprime to the reference clock count value is set. A dynamic cycle is generated based on the recent hardware event interrupt frequency and the basic interrupt cycle. A periodic NMI interrupt trigger pulse is generated according to the dynamic cycle. The drive current, position feedback signal and temperature change rate of the device execution component are set as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, an instantaneous NMI interrupt trigger pulse is generated. When the NMI interrupt trigger pulse is valid, the interrupt controller locks the current value of the high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine; selects one from the preset address pointer set according to the interrupt source identifier, retrieves the original state data from memory and registers according to the pointer, stores it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and triggers the data processing task. Read the buffer data. For each multi-byte data in the original status data, use the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with the preset base number, to determine the number of cyclic left shifts and perform scrambling. Concatenate the scrambled status data, timestamp, and interrupt source identifier into a status data packet. Select the CRC polynomial according to the interrupt source identifier to calculate a 32-bit check code and append it to the end. Send it to the data processing unit through the DMA channel.

[0006] On the other hand, the present invention also provides an online monitoring system for the operating status of poultry slaughtering production line equipment, the system comprising: The generation module is used to determine the reference clock count value based on the controller scan cycle and the master clock reference, and set the basic interrupt cycle count value that is coprime to the reference clock count value. It generates a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generates a periodic NMI interrupt trigger pulse according to the dynamic cycle. It sets the drive current, position feedback signal and temperature change rate of the device execution component as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, it generates an instantaneous NMI interrupt trigger pulse. The trigger module is used to lock the current value of the high-precision hardware timestamp counter synchronized with the master clock when the NMI interrupt trigger pulse is valid, obtain the interrupt source identifier, enter the interrupt service routine, select one from the preset address pointer set according to the interrupt source identifier, grab the original state data from memory and registers according to the pointer, store it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and trigger the data processing task. The sending module is used to read buffer data. For each multi-byte data in the original status data, it uses the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with a preset base number, to determine the number of cyclic left shifts and perform scrambling. The scrambled status data, timestamp, and interrupt source identifier are concatenated into a status data packet. Based on the interrupt source identifier, a 32-bit check code is calculated using a CRC polynomial and appended to the end. The data packet is then sent to the data processing unit through the DMA channel.

[0007] This invention converts the controller scan cycle into a reference clock count value and sets a base clock count value that is coprime to it. It then dynamically adjusts the periodic NMI trigger interval based on the frequency of recent hardware events. Simultaneously, it performs limit detection on drive current, position feedback, and temperature change rate based on floating nonlinear thresholds, triggering instantaneous NMI acquisition of device status. Hardware timestamp latching and dual-port RAM buffering improve the timing consistency and access efficiency of status data acquisition. Lightweight scrambling based on address difference and timestamp characteristics, along with CRC polynomial verification selected according to interrupt source, enhances data transmission reliability and anomaly tracing capabilities. Attached Figure Description

[0008] Figure 1 A flowchart illustrating a method for online monitoring of the operating status of equipment in a poultry slaughtering production line; Figure 2 For adaptive threshold monitoring graph; Figure 3 This is a comparison chart of processing time. Detailed Implementation

[0009] The terms "first," "second," and "third," etc., used in this application specification, claims, and the aforementioned drawings are used to distinguish different objects, not to define a specific order.

[0010] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0011] This invention proposes an online monitoring method for the operating status of poultry slaughtering production line equipment, such as... Figure 1 As shown, it includes: S1. Determine the reference clock count value based on the controller scan cycle and the master clock reference, and set the basic interrupt cycle count value that is coprime to the reference clock count value. Generate a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generate a periodic NMI interrupt trigger pulse according to the dynamic cycle. Set the drive current, position feedback signal and temperature change rate of the device execution component as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, generate an instantaneous NMI interrupt trigger pulse.

[0012] An STM32F4 series microcontroller is used as the main control chip. The controller's default scan cycle is obtained, and a reference clock count value is calculated based on the main clock frequency, serving as the counting reference for subsequent interrupt cycle configurations. Using the Euclidean algorithm, a base clock count value, coprime to the reference clock count value, is generated under the same main clock counting unit, and the base interrupt cycle is calculated accordingly.

[0013] Configure the prescaler and auto-reload register of the 32-bit general-purpose timer TIM5, write the target initial count value into the auto-reload register, and make TIM5 form a dynamic cycle according to this count value. When TIM5 experiences an update overflow event, a periodic NMI interrupt trigger pulse is generated through the associated signal output channel. The number of hardware event triggers in the past ten reference cycles is counted to calculate the recent hardware event interrupt frequency, and the target initial count value for the next cycle is calculated by combining the base clock count value and a preset adjustment coefficient. When the recent hardware event interrupt frequency increases, the count value corresponding to the periodic NMI is increased to reduce the risk of dense triggering of periodic and instantaneous NMIs.

[0014] The analog signal from the Hall current sensor is read by the internal analog-to-digital converter ADC1 and converted into a drive current. The photoelectric encoder pulse is read by the timer TIM2 of the quadrature encoder interface and the position feedback signal is calculated. The surface temperature is acquired by the DS18B20, and the temperature conversion result is read according to the single-bus communication timing and written into the internal SRAM temperature status buffer. The temperature change rate on the time axis is then obtained by least squares fitting.

[0015] For drive current, position feedback signal, and temperature change rate, the same adaptive threshold generation method is used to calculate the nonlinear threshold boundary: extract the five most recent independent sampled values ​​of the corresponding hardware event, calculate the arithmetic mean as the baseline reference point, and generate a threshold bias based on the fluctuation difference between the maximum and minimum values, forming a floating adaptive nonlinear threshold boundary. The current sampled value is continuously compared with the corresponding threshold boundary. When any current sampled value is higher than the upper threshold limit or lower than the lower threshold limit, the over-limit trigger signal is connected to the NMI input pin or NMI trigger logic through the hardware over-limit output circuit, generating an instantaneous NMI interrupt trigger pulse.

[0016] As an optional implementation, the step of generating a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generating periodic NMI interrupt trigger pulses according to the dynamic cycle, includes: The total number of hardware event interrupts over the past ten baseline periods is counted, and the recent hardware event interrupt frequency is obtained by dividing the total number of interrupts by the length of the ten baseline periods. Determine whether the recent hardware event interrupt frequency is zero. If it is zero, use the clock count value corresponding to the basic interrupt cycle as the target initial count value. If it is not zero, increase the clock count value corresponding to the basic interrupt cycle according to the total number of occurrences to obtain the target initial count value, and limit the target initial count value between a preset minimum count value and a preset maximum count value. The target initial count value is loaded into the auto-reload register of the control chip's built-in 32-bit general-purpose timer TIM5; When TIM5 counts up to the auto-reload value and generates an update overflow event, the external signal output pin is controlled to generate a pulse signal that lasts for a preset time, and a periodic NMI interrupt trigger pulse is issued.

[0017] During the operation of the poultry slaughtering production line, the scanning cycle of the controller is set to 1ms. Under the condition that the main clock frequency of the controller is 100MHz, the scanning cycle is converted into 100,000 clock counts. The basic clock count value is selected as 100,003 clock counts. The greatest common divisor of 100,003 and 100,000 is 1, and based on this, the basic interrupt cycle is approximately 1.00003ms.

[0018] Over the past 10 baseline cycles, the monitoring logic recorded the total number N of hardware event NMI interrupts, including 5 instances of blade motor current surge interrupts. At this point, a division operation determined the recent hardware event interrupt frequency to be 500Hz. Since this frequency is not zero, the base clock count is adjusted based on the total number of occurrences, for example, according to the target initial count value. Calculation, where The base clock count value is used, α is a preset adjustment coefficient, and the calculation result is limited to between a preset minimum count value and a preset maximum count value; when When N is 5 and α is 0.1, the initial count value of the target is approximately 150005.

[0019] The initial target count value of 150005 is loaded into the auto-reload register of the 32-bit general-purpose timer TIM5 inside the control chip via a write operation, and the counting is restarted. TIM5 is driven by a 100MHz clock source and increments every 10ns. When the count value reaches the auto-reload value and an update overflow event is generated, the pre-associated external signal output pin GPIO is pulled high, and a 100-cycle delay reset logic within the hardware ensures it remains high for 1μs before being pulled low. This 1μs pulse signal is connected to the NMI input pin via an external hardware connection or a hardware OR gate, and the periodic timer trigger status bit is set synchronously, issuing a periodic NMI interrupt trigger pulse with a dynamic period. This reduces the periodic NMI trigger density when instantaneous NMI triggers are frequent, thus reducing the risk of interrupt congestion.

[0020] As an optional implementation, generating an instantaneous NMI interrupt trigger pulse when any hardware event parameter value crosses a floating adaptive nonlinear threshold boundary includes: Extract the values ​​of the five most recent independent samples of the hardware event under test in chronological order, and calculate the arithmetic mean as the baseline reference point; The maximum and minimum values ​​are selected from the five independent samples, and the difference between the maximum and minimum values ​​is calculated as the fluctuation difference value. The upper limit of the nonlinear threshold is obtained by squaring the fluctuation difference value, multiplying it by a preset dimension conversion ratio coefficient corresponding to the hardware event type, and adding the baseline reference point. The lower limit of the nonlinear threshold is obtained by multiplying the square of the fluctuation difference value after subtracting the baseline reference point from the baseline reference point by a preset dimension conversion ratio coefficient corresponding to the hardware event type. The real-time collected hardware event parameter values ​​are compared with the upper and lower limits of the nonlinear threshold. When the real-time collected parameter value is greater than the upper limit of the nonlinear threshold or less than the lower limit of the nonlinear threshold, an instant NMI interrupt trigger pulse is sent through the hardware interrupt logic.

[0021] Taking the drive current state of the motor executing the poultry slaughtering line cutting as an example of the hardware event under test, the analog-to-digital converter (ADC) continuously acquires data at a rate of 10kHz. Within a sliding time window, the control algorithm extracts the five most recent independent current sampling values ​​in chronological order, which are 3.10A, 3.15A, 3.20A, 3.12A, and 3.18A, respectively. The arithmetic mean of these values ​​is calculated to obtain an average of 3.15A, which is then used as the baseline reference point.

[0022] Simultaneously, by scanning these five samples, the maximum value of 3.20A and the minimum value of 3.10A were selected, and the difference of 0.10A was obtained as the fluctuation difference value representing the fluctuation. For the hardware event type of motor current, the system presets a conversion ratio coefficient for dimension normalization and sensitivity adjustment. This conversion ratio coefficient matches the current dimension; in this embodiment, K=10A. - ¹.

[0023] Perform the calculation of the nonlinear adaptive interval. Square the obtained fluctuation difference value of 0.10A to obtain 0.01A², and multiply it by the conversion factor 10A. - ¹The threshold bias is then 0.10A. This bias is added to the baseline reference point to obtain an upper limit of 3.25A for the nonlinear threshold and a lower limit of 3.05A for the corresponding nonlinear threshold.

[0024] In the next ADC conversion cycle, the latest real-time current value of 3.35A is compared with the preset upper limit of 3.25A and lower limit of 3.05A. Since 3.35A exceeds the upper limit, the hardware comparator pulls its output pin high. This high-level over-limit trigger signal is input to the NMI pin via the external hardware connection, generating an instantaneous NMI interrupt trigger pulse within a preset propagation delay, and triggering the protective acquisition of status data. The correspondence between the motor drive current sampling sequence and the adaptive threshold boundary is as follows: Figure 2 As shown.

[0025] S2, when the NMI interrupt trigger pulse is valid, the interrupt controller locks the current value of the high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine; selects one from the preset address pointer set according to the interrupt source identifier, retrieves the original state data from the memory and registers according to the pointer, stores it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and triggers the data processing task.

[0026] Upon detecting the trigger edge signal of the non-maskable interrupt input pin, the current low-priority task is suspended. The hardware trigger time measurement module latches the current count value of the 32-bit unsigned hardware accumulator used as a high-precision hardware timestamp counter, reads the count value from the latch register, and obtains the high-precision hardware timestamp synchronized with the main frequency system clock. A bitwise AND operation is used to determine whether the trigger source is a timer overflow, current limit violation, position feedback limit violation, or temperature change rate limit violation. Based on this, a 16-bit unsigned integer interrupt source identifier is assigned, and execution jumps to the non-maskable interrupt service function (NMI) to execute the code.

[0027] Inside the interrupt service routine, a pointer variable pointing to the first address of a two-dimensional array is declared as a preset set of address pointers. Based on the obtained interrupt source identifier value as the array row index, the corresponding address pointer is selected. According to the selected address pointer, the static random access memory (SRAM) data area and peripheral data register area are traversed, and the corresponding length of raw status data is extracted according to the data block length recorded in the mapping lookup table.

[0028] The acquired raw state data, along with a 32-bit hardware timestamp and a 16-bit interrupt source identifier, are written into a designated shared memory area of ​​the external dual-port random access memory (DPRAM) chip via an asynchronous parallel bus, following a preset byte alignment order. The NMI interrupt service routine sets the background data processing flag; upon detecting that the background data processing flag is set, the background scheduling task releases the blocking state of the background data processing task and triggers subsequent data processing.

[0029] As an optional implementation, the interrupt controller locks the current value of a high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine, including: Within a preset number of clock cycle response delays from when the interrupt pin detects the trigger edge input event, the time measurement module and event source latch module in the processing system are activated. The instantaneous binary accumulated value of the 32-bit hardware accumulator, which is driven by the core main oscillator frequency and operates in incremental counting mode, is latched into the read-only event buffer register associated with the interrupt pin through hardware logic. The current trigger source status bit is recorded through the event source latch module; The interrupt service routine reads the value in the event buffer register to obtain the lock timestamp, reads the trigger source status bit in the event source latch module, generates an interrupt source identifier according to the preset mapping relationship, then clears the corresponding trigger source status bit, and enters the subsequent data capture process.

[0030] A time measurement module and an event source latch module are configured within the processor chip or its peripheral logic. The time measurement module includes a 32-bit unsigned hardware accumulator driven by the master clock, used as a high-precision hardware timestamp counter. The event source latch module includes a latch register for recording trigger source status bits. The 32-bit unsigned hardware accumulator operates in an incrementing counting mode. The clock input source is the chip's core master oscillation source, such as a 100MHz clock reference output after PLL frequency multiplication. Each step cycle is 10ns, and a full cycle takes approximately 42.95 seconds. When a rising edge occurs that triggers a sudden change in the NMI pin level from 0V to 3.3V (i.e., a trigger edge input event), the edge detection circuit responds. Within a preset response delay of 15 to 25ns, this edge signal is converted into a strobe pulse on the internal hardware trigger bus, activating the aforementioned time measurement module and event source latch module.

[0031] When the device function is activated, the instantaneous binary cumulative value in the aforementioned 32-bit hardware accumulator, which is 0x4B9E3A12, is latched in parallel by the hardware logic into the read-only event buffer register associated with the NMI pin, such as CAP_REG0. Simultaneously, the event source latch module writes the current trigger source state into the event source latch register, such as SRC_REG0; for example, when the current over-limit trigger signal is valid, the corresponding current over-limit status bit in SRC_REG0 is set. The CPU suspends the execution of the current task, saves the context, and jumps to execute the NMI interrupt service routine. In the service routine, the kernel reads the value 0x4B9E3A12 from the read-only event buffer register to obtain the latch timestamp representing the moment the event occurred.

[0032] The event source latch register SRC_REG0 is read. The interrupt service routine reads the trigger source status bits in the event source latch register and performs a bitwise AND operation with a preset valid bit mask to obtain a valid trigger source bitmap. According to the preset trigger source mapping table, the set trigger source status bits are converted into corresponding 16-bit unsigned integer interrupt source identifiers. The preset trigger source mapping table is written into the microcontroller's internal SRAM or non-volatile memory area during the system initialization phase to record the one-to-one correspondence between trigger source status bits and 16-bit unsigned integer interrupt source identifiers. For example, when bit 0 in the event source latch register is set, it indicates a current over-limit trigger, and the corresponding interrupt source identifier is 0x0001; when bit 2 in the event source latch register is set, it indicates a temperature change rate over-limit trigger, and the corresponding interrupt source identifier is 0x0003.

[0033] When multiple trigger source status bits are set simultaneously, the trigger source status bit with the highest priority is selected according to the preset priority order to generate the interrupt source identifier, and the remaining trigger source statuses are retained in the subsequent processing queue.

[0034] As an optional implementation, the step of retrieving raw state data from memory and registers according to the pointers therein, storing it together with the timestamp and interrupt source identifier in a dual-port RAM buffer, and triggering a data processing task includes: Obtain the first physical starting address and the corresponding data block length value from the selected preset address pointer set; Configure the source address register of the dedicated bus control and scheduling module to the first physical starting address; Set the size limit value of the target data block to be transported as the length value of the data block; The dedicated bus control and scheduling module is activated to transfer the binary raw state data read from the source address to a dedicated data pool in the dual-port RAM buffer.

[0035] A mapping lookup table is pre-built in the global storage area. This table records the data capture address and data block length corresponding to different interrupt sources through a preset set of address pointers. When the interrupt source identifier indicates a temperature change rate exceeding the limit interrupt, for example, when the identifier code is 0x0003, the NMI service routine locates the corresponding entry in the mapping lookup table based on the identifier code and reads the first physical starting address from that entry to extract the data. The first physical starting address points to the temperature status buffer in the internal SRAM, for example, 0x20002000. The temperature status buffer is used to store the temperature value, temperature difference between adjacent sampling times, temperature change rate, corresponding sampling timestamp, and status flag word obtained by the DS18B20 through single-bus timing acquisition and conversion. The NMI service routine also reads the corresponding data block length value in the entry. The data block length value is set to 64 bytes, i.e., 16 32-bit wide temperature status buffer data.

[0036] Select and configure a bus control scheduling module for memory access, such as stream channel 4 of DMA controller 1. Configure the source address register of this channel to the first physical start address 0x20002000 of the temperature status buffer. Simultaneously, configure the DMA data width to 32 bits and set the data transfer count register DMA_NDTR to 16, enabling the transfer of 16 32-bit data items, corresponding to a target transfer size of 64 bytes.

[0037] The starting absolute address of the dual-port RAM buffer, such as the dedicated data pool of DPRAM address 0x60010000 obtained through mapping via the external memory controller, is assigned to the DMA memory address register. The data width, address increment method, and transfer direction of the DMA channel are configured so that the DMA channel only performs data transfer from the source address to the dual-port RAM buffer. The DMA channel enable bit is set to activate the scheduling module. After the bus matrix takes over, the binary raw status data of the temperature status buffer in the internal SRAM is continuously read through the hardware burst transfer mechanism and transferred to the dedicated data pool of the dual-port RAM for use by diagnostic tasks.

[0038] S3 reads the buffer data. For each multi-byte data in the original status data, it uses the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with the preset base number, to determine the number of cyclic left shifts and perform scrambling. It concatenates the scrambled status data, timestamp, and interrupt source identifier into a status data packet, selects the CRC polynomial to calculate a 32-bit check code according to the interrupt source identifier, appends it to the tail, and sends it to the data processing unit through the DMA channel.

[0039] After the background scheduling task detects that the background data processing flag is set, it reads the data in the shared area of ​​the dual-port random access memory (DPRAM) and establishes an array of pending status data to complete the data reading.

[0040] The original state data array is traversed. For 16-bit and 32-bit multi-byte data of equal length, pointer arithmetic is used to calculate the integer difference between the physical memory address of the currently processed data and the physical address of the previously processed data. The lowest eight bits of the 32-bit hardware timestamp are extracted and XORed with a preset base number. The result of the XOR operation is used as a time perturbation value. This time perturbation value is added to the address difference between the physical address of the currently processed data and the physical address of the previously processed data to obtain a shift parameter. The shift parameter is then moduloed by the current data bit width to obtain the number of bits for the circular left shift.

[0041] By using the number of bits to be shifted left as the shift parameter of the left-shift function, a bit-by-bit left-shift operation is performed on the multi-byte data, thereby completing the lightweight scrambling process.

[0042] Set up a transmit buffer byte array, and sequentially write the scrambled status data byte stream, four-byte timestamp data, and two-byte interrupt source identifier into the transmit buffer to assemble a standard format status data packet.

[0043] If the interrupt source identifier is a periodic timed trigger, then the IEEE standard CRC-32 polynomial is loaded; if the interrupt source identifier is an immediate over-limit trigger, then the Castagnoli CRC-32C polynomial is loaded, a 32-bit checksum is calculated and appended to the end of the status data packet.

[0044] Configure the DMA controller's second data stream channel four, set the source address to the first address of the assembled status data packet byte array, and the destination address to the data transmission register address of the serial peripheral interface SPI. Send the status data packet to the host computer's data processing unit chip through the DMA channel.

[0045] As an optional implementation, the step of determining the cyclic left shift number and performing scrambling by using the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bits of the timestamp with a preset reference number, includes: Extract the last eight binary bits of the timestamp, perform a bitwise XOR operation with a preset base number, and use the result as the time perturbation value; The physical address of the current data is arithmetically subtracted from the physical address of the previous data to obtain the address difference in bytes. If the current data is the first data, the physical address of the previous data is taken as the default initial address. The shift parameter is obtained by adding the time perturbation value to the address difference. The shift parameter is moduloed by the current data bit width value to obtain the number of cyclic left shifts, and the current data is scrambled by cyclic left shift according to the number of cyclic left shifts.

[0046] When scrambling the raw state data in the dual-port RAM buffer, the previously recorded lock timestamp is read. The lock timestamp is set to a 32-bit value 0x4B9E3A7F, and its last eight bits are truncated to obtain 0x7F. The system uses an 8-bit fixed unsigned integer constant 0xA5 as a preset base value. A bitwise XOR operation is performed between 0x7F and 0xA5 to obtain 0xDA, which is decimal 2^18. This 2^18 is then used as the time perturbation value for the current data block to introduce time characteristics.

[0047] Scrambling is performed sequentially on each multi-byte status data. Taking the third status data as an example, this status data is a 32-bit variable with a data width of 32 bits, stored at physical address 0x60010008, and the physical address of the previous status data is 0x60010004. If the current data is the first data, the previous physical address is taken as the default initial address 0x60010000. Subtracting the current physical address 0x60010008 from the previous physical address 0x60010004 yields an address difference of 4.

[0048] Add the time perturbation value 218 to the address difference value 4 to obtain the shift parameter 222. Take the shift parameter 222 modulo the current state data bit width 32, i.e., 222 mod 32, to obtain the cyclic left shift number 30. Then, perform a cyclic left shift operation on the original content, such as 0x12345678, by 30 bits, so that the bit order within the 32-bit state data is cyclically rearranged, reducing the risk of exposing the fixed pattern of the original state data, and providing perturbed data content for subsequent transmission verification.

[0049] As an optional implementation, the step of selecting a CRC polynomial to calculate a 32-bit checksum based on the interrupt source identifier includes: Based on the interruption source identifier, a corresponding CRC polynomial is selected from the preset CRC polynomial set, and a CRC static lookup table containing 256 32-bit constants corresponding to the selected CRC polynomial is loaded into the system's computation acceleration memory. Initialize a 32-bit parity register and set all valid data bits to 1; Read the complete status data packet byte by byte in sequence, and perform a bitwise XOR operation between the read byte and the lowest eight bits of the verification operation register to obtain the table index value used for mapping. The corresponding 32-bit mapping value is retrieved from the CRC static lookup table based on the index value of the table. The value of the check operation register is shifted eight bits to the right and then XORed with the retrieved 32-bit mapping value to update the check operation register. Repeatedly read bytes and update the checksum register until all bytes in the complete state data packet have been processed. Then, invert the bits in the checksum register to obtain the 32-bit checksum of the data packet. A comparison of processing time between the lookup table method and the calculation method under different data packet sizes is provided. Figure 3 As shown.

[0050] During the boot phase, the firmware pre-generates and loads multiple CRC static lookup tables based on a preset set of CRC polynomials. Before sending status data packets, it selects the corresponding CRC polynomial and its CRC static lookup table based on the interrupt source identifier carried in the current status data packet. The CRC static lookup table is pre-generated according to the selected CRC polynomial and its corresponding reflection parameters to match the right-shift lookup table update method. For example, when the interrupt source identifier corresponds to the Ethernet CRC-32 polynomial 0x04C11DB7, the system selects the CRC static lookup table corresponding to this polynomial and its reflection parameters. This lookup table is 1KB in size and contains 256 32-bit mapping constants. Before sending status data packets, the firmware internally defines a 32-bit checksum register and assigns it an initial value of 0xFFFFFFFF, setting all 32 valid data bits to logic one.

[0051] At the start of the operation, single-byte data from the status data packet to be sent is extracted one by one in ascending address order. The first data byte read is hexadecimal 0xC3. At this time, the lowest eight bits (0xFF) of the current content (0xFFFFFFFF) of the checksum register are extracted, and the read data byte 0xC3 is XORed with these lowest eight bits (0xFF) to produce an eight-bit data 0x3C, which is decimal 60, as the table index value for this round.

[0052] The corresponding 32-bit mapping constant is retrieved from the CRC static lookup table using the index value. Simultaneously, the checksum register is logically shifted eight bits to the right, and the shifted register value is XORed with the 32-bit mapping constant to obtain the updated checksum register value. This process is repeated until the end of the data packet, and the final register value is inverted bit by bit to obtain the 32-bit CRC checksum appended to the end of the status data packet.

[0053] This invention also proposes an online monitoring system for the operating status of poultry slaughtering production line equipment, comprising the following modules: The generation module is used to determine the reference clock count value based on the controller scan cycle and the master clock reference, and set the basic interrupt cycle count value that is coprime to the reference clock count value. It generates a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generates a periodic NMI interrupt trigger pulse according to the dynamic cycle. It sets the drive current, position feedback signal and temperature change rate of the device execution component as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, it generates an instantaneous NMI interrupt trigger pulse. The trigger module is used to lock the current value of the high-precision hardware timestamp counter synchronized with the master clock when the NMI interrupt trigger pulse is valid, obtain the interrupt source identifier, enter the interrupt service routine, select one from the preset address pointer set according to the interrupt source identifier, grab the original state data from memory and registers according to the pointer, store it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and trigger the data processing task. The sending module is used to read buffer data. For each multi-byte data in the original status data, it uses the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with a preset base number, to determine the number of cyclic left shifts and perform scrambling. The scrambled status data, timestamp, and interrupt source identifier are concatenated into a status data packet. Based on the interrupt source identifier, a 32-bit check code is calculated using a CRC polynomial and appended to the end. The data packet is then sent to the data processing unit through the DMA channel.

[0054] As an optional implementation, the step of generating a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generating periodic NMI interrupt trigger pulses according to the dynamic cycle, includes: The total number of hardware event interrupts over the past ten baseline periods is counted, and the recent hardware event interrupt frequency is obtained by dividing the total number of interrupts by the length of the ten baseline periods. Determine whether the recent hardware event interrupt frequency is zero. If it is zero, use the clock count value corresponding to the basic interrupt cycle as the target initial count value. If it is not zero, increase the clock count value corresponding to the basic interrupt cycle according to the total number of occurrences to obtain the target initial count value, and limit the target initial count value between a preset minimum count value and a preset maximum count value. The target initial count value is loaded into the auto-reload register of the control chip's built-in 32-bit general-purpose timer TIM5; When TIM5 counts up to the auto-reload value and generates an update overflow event, the external signal output pin is controlled to generate a pulse signal that lasts for a preset time, and a periodic NMI interrupt trigger pulse is issued.

[0055] As an optional implementation, generating an instantaneous NMI interrupt trigger pulse when any hardware event parameter value crosses a floating adaptive nonlinear threshold boundary includes: Extract the values ​​of the five most recent independent samples of the hardware event under test in chronological order, and calculate the arithmetic mean as the baseline reference point; The maximum and minimum values ​​are selected from the five independent samples, and the difference between the maximum and minimum values ​​is calculated as the fluctuation difference value. The upper limit of the nonlinear threshold is obtained by squaring the fluctuation difference value, multiplying it by a preset dimension conversion ratio coefficient corresponding to the hardware event type, and adding the baseline reference point. The lower limit of the nonlinear threshold is obtained by multiplying the square of the fluctuation difference value after subtracting the baseline reference point from the baseline reference point by a preset dimension conversion ratio coefficient corresponding to the hardware event type. The real-time collected hardware event parameter values ​​are compared with the upper and lower limits of the nonlinear threshold. When the real-time collected parameter value is greater than the upper limit of the nonlinear threshold or less than the lower limit of the nonlinear threshold, an instant NMI interrupt trigger pulse is sent through the hardware interrupt logic.

[0056] As an optional implementation, the interrupt controller locks the current value of a high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine, including: Within a preset number of clock cycle response delays from when the interrupt pin detects the trigger edge input event, the time measurement module and event source latch module in the processing system are activated. The instantaneous binary accumulated value of the 32-bit hardware accumulator, which is driven by the core main oscillator frequency and operates in incremental counting mode, is latched into the read-only event buffer register associated with the interrupt pin through hardware logic. The current trigger source status bit is recorded through the event source latch module; The interrupt service routine reads the value in the event buffer register to obtain the lock timestamp, reads the trigger source status bit in the event source latch module, generates an interrupt source identifier according to the preset mapping relationship, then clears the corresponding trigger source status bit, and enters the subsequent data capture process.

[0057] As an optional implementation, the step of retrieving raw state data from memory and registers according to the pointers therein, storing it together with the timestamp and interrupt source identifier in a dual-port RAM buffer, and triggering a data processing task includes: Obtain the first physical starting address and the corresponding data block length value from the selected preset address pointer set; Configure the source address register of the dedicated bus control and scheduling module to the first physical starting address; Set the size limit value of the target data block to be transported as the length value of the data block; The dedicated bus control and scheduling module is activated to transfer the binary raw state data read from the source address to a dedicated data pool in the dual-port RAM buffer.

[0058] As an optional implementation, the step of determining the cyclic left shift number and performing scrambling by using the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bits of the timestamp with a preset reference number, includes: Extract the last eight binary bits of the timestamp, perform a bitwise XOR operation with a preset base number, and use the result as the time perturbation value; The physical address of the current data is arithmetically subtracted from the physical address of the previous data to obtain the address difference in bytes. If the current data is the first data, the physical address of the previous data is taken as the default initial address. The shift parameter is obtained by adding the time perturbation value to the address difference. The shift parameter is moduloed by the current data bit width value to obtain the number of cyclic left shifts, and the current data is scrambled by cyclic left shift according to the number of cyclic left shifts.

[0059] As an optional implementation, the step of selecting a CRC polynomial to calculate a 32-bit checksum based on the interrupt source identifier includes: Based on the interruption source identifier, a corresponding CRC polynomial is selected from the preset CRC polynomial set, and a CRC static lookup table containing 256 32-bit constants corresponding to the selected CRC polynomial is loaded into the system's computation acceleration memory. Initialize a 32-bit parity register and set all valid data bits to 1; Read the complete status data packet byte by byte in sequence, and perform a bitwise XOR operation between the read byte and the lowest eight bits of the verification operation register to obtain the table index value used for mapping. The corresponding 32-bit mapping value is retrieved from the CRC static lookup table based on the index value of the table. The value of the check operation register is shifted eight bits to the right and then XORed with the retrieved 32-bit mapping value to update the check operation register. Repeatedly read bytes and update the check operation register until all bytes in the complete status data packet have been processed. Then, invert the values ​​in the check operation register bit by bit to obtain the 32-bit check code of the data packet.

[0060] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. A method for online monitoring of the operating status of poultry slaughtering production line equipment, characterized in that, include: The reference clock count value is determined based on the controller scan cycle and the master clock reference, and a basic interrupt cycle count value that is coprime to the reference clock count value is set. A dynamic cycle is generated based on the recent hardware event interrupt frequency and the basic interrupt cycle, and a periodic NMI interrupt trigger pulse is generated according to the dynamic cycle. The drive current, position feedback signal, and temperature change rate of the device's actuators are set as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, an instantaneous NMI interrupt trigger pulse is generated. When the NMI interrupt trigger pulse is valid, the interrupt controller locks the current value of the high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine; selects one from the preset address pointer set according to the interrupt source identifier, retrieves the original state data from memory and registers according to the pointer, stores it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and triggers the data processing task. Read the buffer data. For each multi-byte data in the original state data, use the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with the preset base number, to determine the number of cyclic left shifts and perform scrambling. The scrambled status data, timestamp, and interrupt source identifier are concatenated into a status data packet. A 32-bit checksum is calculated using a CRC polynomial based on the interrupt source identifier and appended to the end of the packet. The packet is then sent to the data processing unit via the DMA channel.

2. The method according to claim 1, characterized in that, The process of generating a dynamic cycle based on recent hardware event interrupt frequency and basic interrupt cycle, and generating periodic NMI interrupt trigger pulses according to the dynamic cycle, includes: The total number of hardware event interrupts over the past ten baseline periods is counted, and the recent hardware event interrupt frequency is obtained by dividing the total number of interrupts by the length of the ten baseline periods. Determine whether the recent hardware event interrupt frequency is zero. If it is zero, use the clock count value corresponding to the basic interrupt cycle as the target initial count value. If it is not zero, increase the clock count value corresponding to the basic interrupt cycle according to the total number of occurrences to obtain the target initial count value, and limit the target initial count value between a preset minimum count value and a preset maximum count value. The target initial count value is loaded into the auto-reload register of the control chip's built-in 32-bit general-purpose timer TIM5; When TIM5 counts up to the auto-reload value and generates an update overflow event, the external signal output pin is controlled to generate a pulse signal that lasts for a preset time, and a periodic NMI interrupt trigger pulse is issued.

3. The method according to claim 1, characterized in that, When any hardware event parameter value crosses a floating adaptive nonlinear threshold boundary, an instantaneous NMI interrupt trigger pulse is generated, including: Extract the values ​​of the five most recent independent samples of the hardware event under test in chronological order, and calculate the arithmetic mean as the baseline reference point; The maximum and minimum values ​​are selected from the five independent samples, and the difference between the maximum and minimum values ​​is calculated as the fluctuation difference value. The upper limit of the nonlinear threshold is obtained by squaring the fluctuation difference value, multiplying it by a preset dimension conversion ratio coefficient corresponding to the hardware event type, and adding the baseline reference point. The lower limit of the nonlinear threshold is obtained by multiplying the square of the fluctuation difference value after subtracting the baseline reference point from the baseline reference point by a preset dimension conversion ratio coefficient corresponding to the hardware event type. The real-time collected hardware event parameter values ​​are compared with the upper and lower limits of the nonlinear threshold. When the real-time collected parameter value is greater than the upper limit of the nonlinear threshold or less than the lower limit of the nonlinear threshold, an instant NMI interrupt trigger pulse is sent through the hardware interrupt logic.

4. The method according to claim 2, characterized in that, The interrupt controller locks the current value of a high-precision hardware timestamp counter synchronized with the master clock, obtains the interrupt source identifier, and enters the interrupt service routine, including: Within a preset number of clock cycle response delays from when the interrupt pin detects the trigger edge input event, the time measurement module and event source latch module in the processing system are activated. The instantaneous binary accumulated value of the 32-bit hardware accumulator, which is driven by the core main oscillator frequency and operates in incremental counting mode, is latched into the read-only event buffer register associated with the interrupt pin through hardware logic. The current trigger source status bit is recorded through the event source latch module; The interrupt service routine reads the value in the event buffer register to obtain the lock timestamp, reads the trigger source status bit in the event source latch module, generates an interrupt source identifier according to the preset mapping relationship, then clears the corresponding trigger source status bit, and enters the subsequent data capture process.

5. The method according to claim 1, characterized in that, The process of retrieving raw state data from memory and registers based on pointers, storing it along with a timestamp and interrupt source identifier in a dual-port RAM buffer, and triggering a data processing task includes: Obtain the first physical starting address and the corresponding data block length value from the selected preset address pointer set; Configure the source address register of the dedicated bus control and scheduling module to the first physical starting address; Set the size limit value of the target data block to be transported as the length value of the data block; The dedicated bus control and scheduling module is activated to transfer the binary raw state data read from the source address to a dedicated data pool in the dual-port RAM buffer.

6. The method according to claim 1, characterized in that, The step of determining the number of bits for cyclic left shift and performing scrambling by using the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bits of the timestamp with a preset reference number, includes: Extract the last eight binary bits of the timestamp, perform a bitwise XOR operation with a preset base number, and use the result as the time perturbation value; The physical address of the current data is arithmetically subtracted from the physical address of the previous data to obtain the address difference in bytes. If the current data is the first data, the physical address of the previous data is taken as the default initial address. The shift parameter is obtained by adding the time perturbation value to the address difference. The shift parameter is moduloed by the current data bit width value to obtain the number of cyclic left shifts, and the current data is scrambled by cyclic left shift according to the number of cyclic left shifts.

7. The method according to claim 1, characterized in that, The step of selecting a CRC polynomial to calculate a 32-bit checksum based on the interruption source identifier includes: Based on the interruption source identifier, a corresponding CRC polynomial is selected from the preset CRC polynomial set, and a CRC static lookup table containing 256 32-bit constants corresponding to the selected CRC polynomial is loaded into the system's computation acceleration memory. Initialize a 32-bit parity register and set all valid data bits to 1; Read the complete status data packet byte by byte in sequence, and perform a bitwise XOR operation between the read byte and the lowest eight bits of the verification operation register to obtain the table index value used for mapping. The corresponding 32-bit mapping value is retrieved from the CRC static lookup table based on the index value of the table. The value of the check operation register is shifted eight bits to the right and then XORed with the retrieved 32-bit mapping value to update the check operation register. Repeatedly read bytes and update the check operation register until all bytes in the complete status data packet have been processed. Then, invert the values ​​in the check operation register bit by bit to obtain the 32-bit check code of the data packet.

8. An online monitoring system for the operating status of poultry slaughtering production line equipment, characterized in that, include: The generation module is used to determine the reference clock count value based on the controller scan cycle and the master clock reference, set the basic interrupt cycle count value that is coprime to the reference clock count value, generate a dynamic cycle based on the recent hardware event interrupt frequency and the basic interrupt cycle, and generate periodic NMI interrupt trigger pulses according to the dynamic cycle. The drive current, position feedback signal, and temperature change rate of the device's actuators are set as hardware events. When any hardware event parameter value crosses the floating adaptive nonlinear threshold boundary, an instantaneous NMI interrupt trigger pulse is generated. The trigger module is used to lock the current value of the high-precision hardware timestamp counter synchronized with the master clock when the NMI interrupt trigger pulse is valid, obtain the interrupt source identifier, enter the interrupt service routine, select one from the preset address pointer set according to the interrupt source identifier, grab the original state data from memory and registers according to the pointer, store it together with the timestamp and interrupt source identifier into the dual-port RAM buffer, and trigger the data processing task. The sending module is used to read buffer data. For each multi-byte data in the original state data, it uses the difference between the address pointer and the previous data address pointer, combined with the time perturbation value generated by XORing the low-order bit sequence of the timestamp with a preset base number, to determine the number of cyclic left shifts and perform scrambling. The scrambled status data, timestamp, and interrupt source identifier are concatenated into a status data packet. A 32-bit checksum is calculated using a CRC polynomial based on the interrupt source identifier and appended to the end of the packet. The packet is then sent to the data processing unit via the DMA channel.

9. The system according to claim 8, characterized in that, The process of generating a dynamic cycle based on recent hardware event interrupt frequency and basic interrupt cycle, and generating periodic NMI interrupt trigger pulses according to the dynamic cycle, includes: The total number of hardware event interrupts over the past ten baseline periods is counted, and the recent hardware event interrupt frequency is obtained by dividing the total number of interrupts by the length of the ten baseline periods. Determine whether the recent hardware event interrupt frequency is zero. If it is zero, use the clock count value corresponding to the basic interrupt cycle as the target initial count value. If it is not zero, increase the clock count value corresponding to the basic interrupt cycle according to the total number of occurrences to obtain the target initial count value, and limit the target initial count value between a preset minimum count value and a preset maximum count value. The target initial count value is loaded into the auto-reload register of the control chip's built-in 32-bit general-purpose timer TIM5; When TIM5 counts up to the auto-reload value and generates an update overflow event, the external signal output pin is controlled to generate a pulse signal that lasts for a preset time, and a periodic NMI interrupt trigger pulse is issued.

10. The system according to claim 8, characterized in that, When any hardware event parameter value crosses a floating adaptive nonlinear threshold boundary, an instantaneous NMI interrupt trigger pulse is generated, including: Extract the values ​​of the five most recent independent samples of the hardware event under test in chronological order, and calculate the arithmetic mean as the baseline reference point; The maximum and minimum values ​​are selected from the five independent samples, and the difference between the maximum and minimum values ​​is calculated as the fluctuation difference value. The upper limit of the nonlinear threshold is obtained by squaring the fluctuation difference value, multiplying it by a preset dimension conversion ratio coefficient corresponding to the hardware event type, and adding the baseline reference point. The lower limit of the nonlinear threshold is obtained by multiplying the square of the fluctuation difference value after subtracting the baseline reference point from the baseline reference point by a preset dimension conversion ratio coefficient corresponding to the hardware event type. The real-time collected hardware event parameter values ​​are compared with the upper and lower limits of the nonlinear threshold. When the real-time collected parameter value is greater than the upper limit of the nonlinear threshold or less than the lower limit of the nonlinear threshold, an instant NMI interrupt trigger pulse is sent through the hardware interrupt logic.

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