A protection circuit for high-voltage LDO frequency compensation capacitor

Abstract

The application discloses a protection circuit for high-voltage LDO frequency compensation capacitor, which comprises a voltage division protection module, a pull-up enable module and a pull-down enable module; the voltage division protection module is connected in parallel with the Miller compensation capacitor; the pull-up enable module is connected to an error amplifier output node; the pull-down enable module is connected to an LDO output node; when the LDO normally works, the three modules are all turned off, and the circuit stability is not affected; when the LDO is turned off, the three enable voltages synchronously turn on the modules, and the Miller compensation capacitor is protected; the circuit has a protection method: when the LDO is turned off, the voltage division protection module connects the fourth resistor into the circuit, and the Miller compensation capacitor is protected by the series connection of the third resistor and the fourth resistor; the pull-up enable module pulls up the output node potential to 10V; and the pull-down enable module pulls down the LDO output node potential to zero potential. The application effectively protects the Miller compensation capacitor, prevents high-voltage breakdown, and does not affect the loop stability when the LDO normally works.

Description

Technical Field

[0001] This invention relates to the field of power management chip technology, specifically to a protection circuit for the frequency compensation capacitor of a high-voltage LDO. Background Technology

[0002] Low dropout regulators (LDOs), as linear modulation integrated circuits in power management chips, occupy an important position in the power management chip market due to their advantages in noise, power consumption, response speed, and ease of integration. An LDO is essentially a negative feedback system, which requires the addition of a frequency compensation module to ensure system stability. The most common compensation method is Miller compensation, which uses a small capacitor to push the poles of the preamplifier to a lower frequency, causing pole splitting and effectively improving loop stability.

[0003] However, in high-voltage LDO circuits, a significant voltage drop occurs across the frequency compensation capacitor when the circuit is turned off. This voltage drop exceeds the capacitor's rated voltage, leading to a series of serious consequences:

[0004] First, dielectric breakdown: When the applied voltage exceeds the dielectric strength of the dielectric, the dielectric will break down, causing permanent damage and leading to capacitor failure.

[0005] Second, parameter degradation: Long-term operation at voltages close to or slightly exceeding the rated voltage will accelerate dielectric aging, leading to a reduction in effective capacity, an increase in leakage current, an increase in power consumption, and a significant shortening of capacitor life.

[0006] Third, circuit overheating: Short circuits or parameter degradation can cause internal heating in capacitors, leading to cracking of ceramic capacitors and deformation and melting of film capacitors. These problems ultimately cause the frequency compensation capacitor to fail, resulting in system instability.

[0007] For example, patent CN120406645A discloses an LDO frequency compensation circuit based on a voltage-controlled current source. This circuit uses a multi-stage current mirror and a Miller compensation network to ensure loop phase margin, resulting in a stable output voltage without fluctuations. However, this frequency compensation module does not protect the Miller compensation capacitor. When the circuit is turned off, a significant voltage drop may still occur across the capacitor, damaging it, affecting frequency compensation, and further causing circuit instability.

[0008] Therefore, there is an urgent need for a protection circuit that can effectively protect the frequency compensation capacitor of the high-voltage LDO without affecting the normal operation and stability of the circuit, so as to solve the shortcomings of the existing technology. Summary of the Invention

[0009] To address the problem mentioned in the background art regarding the instability of high-voltage LDO circuits when the circuit is turned off, this invention provides a protection circuit for the frequency compensation capacitor of a high-voltage LDO.

[0010] The above-mentioned objective of this application is achieved through the following technical solution:

[0011] A protection circuit for the frequency compensation capacitor of a high-voltage LDO includes:

[0012] The voltage divider protection module is connected in parallel with the Miller compensation capacitor to provide voltage divider protection for the Miller compensation capacitor when the LDO circuit is turned off, thereby limiting the voltage across the Miller compensation capacitor to not exceed its rated operating voltage.

[0013] A pull-up enable module is used to connect to the output node of the error amplifier in the LDO circuit and pull up the potential of the output node to a preset voltage when the LDO circuit is turned off.

[0014] A pull-down enable module is used to connect to the LDO output node and pull the potential of the LDO output node down to zero when the LDO circuit is turned off.

[0015] By adopting the above technical solution, the protection circuit for the high-voltage LDO frequency compensation capacitor includes a voltage divider protection module, a pull-up enable module, and a pull-down enable module. The voltage divider protection module is connected in parallel with the Miller compensation capacitor, and performs voltage divider protection on the Miller compensation capacitor when the LDO circuit is turned off, limiting the voltage across its terminals to not exceed the rated operating voltage. The pull-up enable module is connected to the output node of the error amplifier, and pulls the output node potential up to the preset voltage when the LDO circuit is turned off. The pull-down enable module is connected to the LDO output node, and pulls the LDO output node potential down to zero potential when the LDO circuit is turned off. The three modules work together and are synchronously turned on when the LDO circuit is turned off, effectively protecting the Miller compensation capacitor from high-voltage breakdown. At the same time, when the LDO is working normally, each module is in the off state, which does not affect the normal operating performance of the circuit.

[0016] In a preferred embodiment, the voltage divider protection module may be further configured to include a third resistor, a fourth resistor, and a fifth switching transistor.

[0017] The third resistor and the fourth resistor are connected in series and then connected in parallel with the Miller compensation capacitor; the fifth switching transistor is connected in series with the fourth resistor.

[0018] The gate of the fifth switching transistor is connected to a first enable voltage. When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off. When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on.

[0019] By adopting the above technical solution, the voltage divider protection module includes a third resistor, a fourth resistor, and a fifth switching transistor. The third resistor, the fourth resistor, the fifth switching transistor, and the Miller compensation capacitor together form a compensation network. The third resistor and the fourth resistor are connected in series and then connected in parallel with the Miller compensation capacitor. The fifth switching transistor is connected in series with the fourth resistor. The gate of the fifth switching transistor is connected to a first enable voltage. When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off. At this time, the fourth resistor is open, and the third resistor is connected in series with the Miller compensation capacitor, which does not affect the normal compensation function of the capacitor. When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on, connecting the fourth resistor to the circuit. At this time, the third resistor and the fourth resistor are connected in series. Through the voltage divider formed by the third resistor and the fourth resistor, the voltage across the capacitor is limited to not exceed the rated value, thereby achieving effective protection for the Miller compensation capacitor.

[0020] In a preferred embodiment, this application may be further configured such that the pull-up enable module includes a third switching transistor and a fourth switching transistor;

[0021] The control terminals of the third and fourth switching transistors are both connected to the second enable voltage, their sources are both connected to the pull-up voltage, and their drains are respectively connected to different output nodes of the error amplifier.

[0022] When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off. When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling up the output node potential of the error amplifier to the pull-up voltage.

[0023] By adopting the above technical solution, the pull-up enable module includes a third switching transistor and a fourth switching transistor; the gates of both the third and fourth switching transistors are connected to a second enable voltage, the sources are connected to a pull-up voltage, and the drains are respectively connected to different output nodes of the error amplifier; when the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off, without affecting the normal operation of the error amplifier; when the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling the output node potential of the error amplifier up to the pull-up voltage (such as 10V), preventing the output node from being in a floating or uncertain state, and avoiding the generation of additional leakage paths when the circuit is turned off.

[0024] In a preferred embodiment, this application may be further configured such that the pull-down enable module includes a sixth switching transistor;

[0025] The gate of the sixth switching transistor is connected to the third enable voltage, its source is grounded, and its drain is connected to the LDO output node.

[0026] When the LDO circuit is working normally, the third enable voltage controls the sixth switching transistor to turn off. When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential.

[0027] By adopting the above technical solution, the gate of the sixth switching transistor is connected to the third enable voltage, the source is grounded, and the drain is connected to the LDO output node. When the LDO circuit is working normally, the third enable voltage controls the sixth switching transistor to turn off, without affecting the normal operation of the error amplifier. When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential, ensuring that the potential of each node is determined in the off state, and preventing leakage and false triggering.

[0028] In a preferred embodiment, this application can be further configured such that the first enable voltage, the second enable voltage, and the third enable voltage operate simultaneously, synchronously enabling the voltage divider protection module, the pull-up enable module, and the pull-down enable module when the LDO circuit is turned off, and synchronously turning off each module when the LDO circuit is operating normally.

[0029] By adopting the above technical solution, the first enable voltage, the second enable voltage, and the third enable voltage work simultaneously. When the LDO circuit is turned off, the voltage divider protection module, the pull-up enable module, and the pull-down enable module are turned on synchronously. When the LDO circuit is working normally, each module is turned off synchronously. The three enable voltages work together to control the circuit, and none of them can be missing. This ensures that the protection circuit can fully and effectively protect the Miller compensation capacitor when the LDO is turned off, and that each module is completely turned off when the LDO is working normally, without affecting the loop stability and normal operating performance of the LDO.

[0030] The second objective of this invention is achieved through the following technical solution:

[0031] A protection method for the frequency compensation capacitor of a high-voltage LDO includes the following steps:

[0032] When the LDO circuit is working normally, the voltage divider protection module, pull-up enable module, and pull-down enable module are turned off to prevent the protection circuit from interfering with the normal operation of the LDO circuit.

[0033] When the LDO circuit is turned off, the voltage divider protection module, pull-up enable module, and pull-down enable module are simultaneously turned on.

[0034] The voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, limiting the voltage across the Miller compensation capacitor to not exceed its rated operating voltage.

[0035] The pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage.

[0036] The pull-down enable module pulls the LDO output node potential down to zero.

[0037] By adopting the above technical solution, the protection method for the high-voltage LDO frequency compensation capacitor firstly controls the voltage divider protection module, pull-up enable module, and pull-down enable module to be turned off when the LDO circuit is working normally, so that the protection circuit does not interfere with the normal operation of the LDO circuit; then, when the LDO circuit is turned off, the voltage divider protection module, pull-up enable module, and pull-down enable module are simultaneously turned on; the voltage divider protection module performs voltage divider protection on the Miller compensation capacitor, limiting the voltage across its terminals to not exceed the rated operating voltage; the pull-up enable module pulls up the output node potential of the error amplifier to the preset voltage; the pull-down enable module pulls down the LDO output node potential to zero potential; this method achieves comprehensive protection for the Miller compensation capacitor through synchronous control of the enable voltage.

[0038] In a preferred embodiment, this application can be further configured such that: the voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, specifically including:

[0039] The gate of the fifth switching transistor is controlled by the first enable voltage;

[0040] When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off and the fourth resistor to open.

[0041] When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on, so that the fourth resistor is connected to the circuit and connected in series with the third resistor. The third resistor and the fourth resistor provide voltage division protection for the Miller compensation capacitor.

[0042] By adopting the above technical solution, the voltage divider protection method controls the gate of the fifth switching transistor through the first enabling voltage. When the LDO circuit is working normally, the first enabling voltage controls the fifth switching transistor to turn off, the fourth resistor to open, and the third resistor to be connected in series with the Miller compensation capacitor. At this time, the voltage divider protection module is in a high-impedance state, which does not affect the normal frequency compensation function of the capacitor. When the LDO circuit is turned off, the first enabling voltage controls the fifth switching transistor to turn on, and the fourth resistor is connected to the circuit. At this time, the third resistor and the fourth resistor are connected in series, and voltage is divided through the third resistor and the fourth resistor to limit the voltage across the capacitor to not exceed the rated value. This method automatically activates the voltage divider protection when the LDO is turned off and automatically closes the voltage divider path when the LDO is working normally, realizing intelligent switching between protection and function.

[0043] In a preferred embodiment, this application can be further configured such that the pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage, specifically including:

[0044] The gates of the third and fourth switching transistors are controlled by the second enable voltage;

[0045] When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off;

[0046] When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling the output node potential of the error amplifier up to the power supply voltage.

[0047] By adopting the above technical solution, the pull-up enable method controls the gates of the third and fourth switching transistors through the second enable voltage. When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off, without affecting the normal operation of the error amplifier. When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling the output node potential of the error amplifier up to the pull-up voltage (e.g., 10V). This method ensures that the output node potential of the error amplifier is pulled up to the preset voltage when the circuit is turned off, avoiding uncertain states and leakage problems caused by floating nodes.

[0048] In a preferred embodiment, this application can be further configured such that the pull-down enable module pulls the LDO output node potential down to zero potential, specifically including:

[0049] The gate of the sixth switching transistor is controlled by the third enable voltage;

[0050] When the LDO circuit is operating normally, the third enable voltage controls the sixth switching transistor to turn off;

[0051] When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero.

[0052] By adopting the above technical solution, the pull-down enable method controls the gate of the sixth switching transistor through the third enable voltage. When the LDO circuit is working normally, the third enable voltage controls the sixth switching transistor to turn off, without affecting the normal operation of the error amplifier. When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential. This method ensures that the LDO output node potential is pulled down to ground potential when the circuit is turned off. Combined with the pull-up enable module, the error amplifier is in a defined potential state when it is turned off, effectively preventing additional leakage current.

[0053] In summary, this application includes at least one of the following beneficial technical effects:

[0054] 1. When the LDO circuit is turned off, the voltage divider protection module controls the fifth switching transistor to turn on by the enable voltage, the fourth resistor is connected to the circuit, and the third resistor and the fourth resistor are connected in series. The voltage is divided by the third resistor and the fourth resistor to limit the voltage across the capacitor to not exceed the rated operating voltage.

[0055] 2. When the LDO is working normally, the protection circuit controls the switching transistors to turn off through the enable voltage. The voltage divider protection module is in a high-impedance state, and the pull-up enable module and pull-down enable module are also in the off state, which does not affect the normal operation of the LDO at all.

[0056] 3. The first enable voltage, the second enable voltage, and the third enable voltage work simultaneously to synchronously activate the voltage divider protection module, the pull-up enable module, and the pull-down enable module when the LDO circuit is turned off. None of them can be omitted. The three work together to ensure that the potential of each node is determined when the LDO is turned off, prevent additional leakage current, and achieve comprehensive protection for the frequency compensation capacitor and related circuits.

[0057] 4. The protection circuit consists of only a small number of resistors and switching transistors, with a simple structure that does not occupy too much chip area. It is easy to integrate into existing LDO power management chips without requiring major modifications to the original LDO main circuit, and has high practical value. Attached Figure Description

[0058] Figure 1 This is a general circuit diagram of an embodiment of a protection circuit for a high-voltage LDO frequency compensation capacitor according to this application;

[0059] Figure 2 This is a simulation curve of the loop gain of an LDO in an embodiment of a protection circuit for a high-voltage LDO frequency compensation capacitor according to this application.

[0060] Figure 3 This is a loop phase simulation curve of an LDO according to an embodiment of a protection circuit for a high-voltage LDO frequency compensation capacitor in this application.

[0061] Figure 4 This is a waveform diagram of the voltage drop across the Miller compensation capacitor when the circuit of a protection circuit embodiment for a high-voltage LDO frequency compensation capacitor is turned off.

[0062] Figure 5 This is a flowchart of an embodiment of a protection method for a high-voltage LDO frequency compensation capacitor according to this application;

[0063] Figure 6 This is a flowchart illustrating the implementation of step S30 in an embodiment of a protection method for a high-voltage LDO frequency compensation capacitor according to this application.

[0064] Figure 7 This is a flowchart illustrating the implementation of step S40 in an embodiment of a protection method for a high-voltage LDO frequency compensation capacitor according to this application.

[0065] Figure 8 This is a flowchart illustrating the implementation of step S50 in an embodiment of a protection method for a high-voltage LDO frequency compensation capacitor according to this application.

[0066] The components include: 1. Voltage divider protection module; 2. Pull-up enable module; 3. Pull-down enable module; 4. Error amplifier; and 5. Miller compensation capacitor. Detailed Implementation

[0067] The following is in conjunction with the appendix Figure 1-8 This application will be described in further detail.

[0068] In one embodiment, such as Figure 1 As shown, this application discloses a protection circuit for the frequency compensation capacitor of a high-voltage LDO, comprising:

[0069] The voltage divider protection module 1 is connected in parallel with the Miller compensation capacitor 5 and is used to perform voltage divider protection on the Miller compensation capacitor 5 when the LDO circuit is turned off, limiting the voltage across the Miller compensation capacitor 5 to not exceed its rated operating voltage.

[0070] Pull-up enable module 2 is used to connect to the output node of error amplifier 4 in LDO circuit, and pull up the potential of the output node to a preset voltage when LDO circuit is turned off;

[0071] Pull-down enable module 3 is used to connect to the LDO output node and pull down the potential of the LDO output node to zero when the LDO circuit is turned off.

[0072] In this embodiment, the main circuit of the LDO includes an error amplifier 4, a power transistor, a feedback network, and a Miller compensation capacitor 5. The error amplifier 4 adopts a single-stage common-source common-gate structure, consisting of Mn1-Mn4 and Mp1-Mp2. The power transistor is Mp5. The feedback network consists of a first resistor R1 and a second resistor R2. The Miller compensation capacitor 5 is Cc. The voltage divider protection module 1 is connected in parallel with the Miller compensation capacitor 5Cc to provide voltage divider protection for the Miller compensation capacitor 5Cc when the LDO circuit is turned off. The pull-up enable module 2 is connected to the output nodes A and B of the error amplifier 4. The pull-down enable module 3 is connected to the output node C of the LDO.

[0073] The voltage divider protection module 1 consists of a third resistor R3, a fourth resistor R4, and a fifth switching transistor Mn5. R3 and R4 are connected in series and then in parallel with Cc. Mn5 is connected in series with R4, and the gate of Mn5 is connected to the first enable voltage VENC. The pull-up enable module 2 consists of a third switching transistor Mp3 and a fourth switching transistor Mp4, both of which are PMOS transistors. Their gates are connected to the second enable voltage VENP, their sources are connected to a pull-up voltage of 10V, and their drains are connected to points A and B, respectively. The sixth switching transistor Mn6 of the pull-down enable module 3 is an NMOS transistor. Its gate is connected to the third enable voltage VENN, its source is grounded, and its drain is connected to point C. The three enable voltages VENP, VENN, and VENC work simultaneously and none of them can be omitted. When the LDO circuit is operating normally, VENC is low, controlling Mn5 to turn off; VENP is high, controlling Mp3 and Mp4 to turn off; and VENN is low, controlling Mn6 to turn off. The protection circuit is in a high-impedance state and does not affect the normal operation of the LDO. When the LDO circuit is off, VENC becomes high, controlling Mn5 to turn on and connecting R4 to the circuit. R3 and R4 are connected in series to divide the voltage, limiting the voltage across Cc. VENP becomes low, controlling Mp3 and Mp4 to turn on, pulling the potentials at points A and B up to 10V. VENN becomes high, controlling Mn6 to turn on, pulling the potential at point C down to zero. Figure 2 and Figure 3 As shown, after adding the capacitor protection module, the loop gain and loop phase of the LDO loop are consistent with the simulation results without the capacitor protection module, indicating that the protection module has no impact on circuit stability; Figure 4 As shown, when the voltage divider module and the enable module are off, there is a 10V voltage drop across the capacitor. When they are on, the voltage drop across the capacitor remains around 5V, effectively protecting the capacitor.

[0074] In one embodiment, the voltage divider protection module 1 includes a third resistor, a fourth resistor, and a fifth switching transistor;

[0075] The third resistor and the fourth resistor are connected in series and then connected in parallel with the Miller compensation capacitor 5; the fifth switching transistor is connected in series with the fourth resistor.

[0076] The gate of the fifth switching transistor is connected to a first enable voltage. When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off. When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on.

[0077] In this embodiment, the third resistor R3 and the fourth resistor R4 form a series voltage divider branch, connected in parallel with the Miller compensation capacitor 5Cc; the fifth switching transistor Mn5 is connected in series with the fourth resistor R4. Mn5 is an NMOS transistor, its gate is connected to the first enable voltage VENC, its drain is connected to one end of R4, and its source is grounded. When the LDO circuit is working normally, VENC is low, Mn5 is off, R3 is connected in series with Cc, R4 is not connected to the circuit, Mn5 is off, its resistance is large, it consumes almost no extra current, and does not affect the normal frequency compensation function of Cc; when the LDO circuit is off, VENC becomes high, Mn5 conducts, connecting R4 to the circuit, R3 and R4 are connected in series to divide the voltage, limiting the voltage across Cc to not exceed its rated operating voltage (e.g., 5V); by reasonably selecting the resistance value of R3, the voltage across Cc can be limited to a safe range, effectively preventing the capacitor from undergoing dielectric breakdown, parameter degradation, or overheating damage due to excessive voltage. Figure 2 As shown, when the voltage divider module is turned on, the voltage drop across the capacitor remains around 5V, while when the voltage divider module is turned off, a voltage drop of 10V appears across the capacitor, proving that this voltage divider protection module 1 can effectively protect the Miller compensation capacitor 5.

[0078] In one embodiment, the pull-up enable module 2 includes a third switching transistor and a fourth switching transistor;

[0079] The control terminals of the third and fourth switching transistors are both connected to the second enable voltage, their sources are both connected to the pull-up voltage, and their drains are respectively connected to different output nodes of the error amplifier 4.

[0080] When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off. When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling up the output node potential of the error amplifier 4 to the pull-up voltage.

[0081] In this embodiment, both the third switching transistor Mp3 and the fourth switching transistor Mp4 are PMOS transistors. Their gates are connected to the second enable voltage VENP, and their sources are connected to a pull-up voltage (e.g., 10V). Their drains are connected to output nodes A and B of the error amplifier 4, respectively. When the LDO circuit is working normally, VENP is high, and Mp3 and Mp4 are off, not affecting the normal operation of the error amplifier 4. The potentials of output nodes A and B of the error amplifier 4 are determined by the error amplifier 4 itself. When the LDO circuit is off, VENP becomes low, and Mp3 and Mp4 are turned on, connecting points A and B to the 10V pull-up voltage through Mp3 and Mp4. This pulls the potentials of points A and B to a high level (10V), preventing the output nodes from being in a floating or uncertain state and preventing additional leakage paths caused by uncertain node potentials when the circuit is off. Combined with the pull-down enable module 3, which pulls down the LDO output node C to zero potential, the error amplifier 4 is in a definite potential state when off, effectively protecting the stability of the circuit.

[0082] In one embodiment, the pull-down enable module 3 includes a sixth switching transistor;

[0083] The gate of the sixth switching transistor is connected to the third enable voltage, its source is grounded, and its drain is connected to the LDO output node.

[0084] When the LDO circuit is working normally, the third enable voltage controls the sixth switching transistor to turn off. When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential.

[0085] In this embodiment, the sixth switching transistor Mn6 is an NMOS transistor, with its gate connected to the third enable voltage VENN, its source grounded, and its drain connected to the LDO output node C. When the LDO circuit is working normally, VENN is low, Mn6 is off, and the normal operation of the error amplifier 4 is not affected. The potential of the LDO output node C is determined by the preceding circuit. When the LDO circuit is off, VENN becomes high, Mn6 conducts, and the C point is connected to ground through Mn6, pulling the potential of the C point down to zero potential (GND). This ensures that the potential of the LDO output node is pulled down to ground potential in the off state. Combined with the pull-up enable module 2, the output nodes A and B are pulled up to 10V, so that the error amplifier 4 is in a defined potential state in the off state (the LDO output node is low, and the error amplifier output node is high). This effectively prevents additional leakage paths and false triggering risks caused by floating nodes or uncertain potentials when the circuit is off.

[0086] In one embodiment, the first enabling voltage, the second enabling voltage, and the third enabling voltage operate simultaneously, synchronously enabling the voltage divider protection module 1, the pull-up enabling module 2, and the pull-down enabling module 3 when the LDO circuit is turned off, and synchronously turning off each module when the LDO circuit is operating normally.

[0087] In this embodiment, the first enable voltage VENC, the second enable voltage VENP, and the third enable voltage VENN are three synchronously operating logic control signals, which work together to control the circuit. When the LDO circuit is operating normally, VENC is at a low level to control the voltage divider protection module 1 to turn off, VENP is at a high level to control the pull-up enable module 2 to turn off, and VENN is at a low level to control the pull-down enable module 3 to turn off. The entire protection circuit is in a high-impedance state, consuming no additional current and not affecting the loop stability and normal operating performance of the LDO. When the LDO circuit is turned off, VENC becomes high to control the voltage divider protection module 1 to turn on, VENP becomes low to control the pull-up enable module 2 to turn on, and VENN becomes high to control the pull-down enable module 3 to turn on. The three modules are activated synchronously, providing comprehensive protection for the Miller compensation capacitor 5 and the error amplifier 4. Figure 2 and Figure 3 As shown, loop stability simulation of the circuit was performed. After adding the capacitor protection module, the loop gain and loop phase of the LDO loop were consistent with the simulation results without the capacitor protection module, indicating that the protection module has no impact on the stability of the circuit. Figure 4 As shown, when the voltage divider module and the enable module are off, a 10V voltage drop will occur across the capacitor between 5μs and 10μs, and between 50μs and 60μs, exceeding the capacitor's rated voltage. This causes increased leakage current, capacitance drift, and even breakdown. When the voltage divider module and the enable module are on, the voltage drop across the capacitor remains around 5V, effectively protecting the capacitor. Therefore, the protection circuit with synchronous control of the three enable voltages effectively protects the frequency compensation capacitor without affecting the normal operation of the LDO.

[0088] In one embodiment, a protection circuit for a high-voltage LDO frequency compensation capacitor applies a protection method for the high-voltage LDO frequency compensation capacitor, which corresponds one-to-one with the protection circuit for the high-voltage LDO frequency compensation capacitor in the above embodiments. For example... Figure 5 As shown, the protection method for the frequency compensation capacitor of the high-voltage LDO includes:

[0089] S10: When the LDO circuit is working normally, the voltage divider protection module, pull-up enable module, and pull-down enable module are turned off to prevent the protection circuit from interfering with the normal operation of the LDO circuit.

[0090] In this embodiment, normal operation of the LDO circuit means that the power management chip is in a normal power supply state, the core modules such as the error amplifier and power transistor are working normally, and the output voltage is stable at the preset value; the voltage divider protection module is turned off when the fifth switching transistor Mn5 is in the off state, the fourth resistor R4 is open, and the third resistor R3 is connected in series with the Miller compensation capacitor Cc; the pull-up enable module is turned off when the third switching transistor Mp3 and the fourth switching transistor Mp4 are in the off state; the pull-down enable module is turned off when the sixth switching transistor Mn6 is in the off state.

[0091] Specifically, when the LDO is operating normally, the first enable voltage VENC is low, controlling Mn5 to turn off, the fourth resistor R4 is open, and the third resistor R3 is connected in series with the Miller compensation capacitor Cc, resulting in a high-impedance voltage divider branch that consumes almost no additional current. The second enable voltage VENP is high, controlling Mp3 and Mp4 to turn off, without affecting the normal operation of the error amplifier. The third enable voltage VENN is low, controlling Mn6 to turn off, without affecting the normal operation of the error amplifier. The entire protection circuit is in a high-impedance state, having no impact on the loop stability and normal operating performance of the LDO.

[0092] S20: When the LDO circuit is turned off, the voltage divider protection module, pull-up enable module, and pull-down enable module are simultaneously turned on.

[0093] In this embodiment, LDO circuit shutdown means that the power management chip stops supplying power or enters standby mode, at which time the core modules such as error amplifier and power transistor stop working; synchronous startup means that the switching transistors of the three modules are turned on at the same time by the enable voltage, and the voltage divider protection module, pull-up enable module and pull-down enable module enter the working state at the same time.

[0094] Specifically, when the LDO is off, VENC goes high, controlling Mn5 to turn on; VENP goes low, controlling Mp3 and Mp4 to turn on; VENN goes high, controlling Mn6 to turn on; the three modules turn on synchronously, achieving comprehensive protection for the LDO circuit when it is off. For example... Figure 2 and Figure 3 As shown, after adding the capacitor protection module, the loop gain and loop phase of the LDO loop are consistent with the simulation results without the capacitor protection module, indicating that the activation of the protection module does not affect the stability of the circuit.

[0095] S30: The voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, limiting the voltage across the Miller compensation capacitor to not exceed its rated operating voltage.

[0096] In this embodiment, voltage divider protection refers to reducing the voltage across the Miller compensation capacitor by using a resistor to divide the voltage. The rated operating voltage of the Miller compensation capacitor is usually 5V. Exceeding this voltage may cause dielectric breakdown, parameter degradation, or overheating damage to the capacitor.

[0097] Specifically, when Mn5 is turned on, the fourth resistor R4 is open-circuited, and the third resistor R3 is connected in series with the Miller compensation capacitor Cc; by properly selecting the resistance values ​​of R3 and R4, the voltage drop across Cc is limited to within the rated operating voltage. For example... Figure 4 As shown, when the voltage divider module and the enable module are off, a voltage drop of 10V will fall on the capacitor between 5μs and 10μs and between 50μs and 60μs, exceeding the capacitor's rated voltage. When the voltage divider module and the enable module are on, the voltage drop across the capacitor remains around 5V, effectively protecting the capacitor.

[0098] S40: The pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage.

[0099] In this embodiment, the preset voltage is a pull-up voltage of 10V, which is used to pull the output nodes A and B of the error amplifier to a high level. The pull-up operation can prevent the output nodes from being in a floating or uncertain state when the circuit is turned off, thus preventing the generation of additional leakage paths.

[0100] Specifically, when Mp3 and Mp4 are turned on, points A and B are connected to a 10V pull-up voltage through Mp3 and Mp4, raising the potential of points A and B to 10V; combined with the pull-down enable module, the LDO output node is pulled low, so that the LDO is in a defined potential state when it is off (the LDO output node is low and the error amplifier output node is high), effectively preventing leakage and false triggering.

[0101] S50: The pull-down enable module pulls down the LDO output node potential to zero potential.

[0102] In this embodiment, zero potential refers to ground potential (GND), which is used to pull the LDO output node C low. The pull-down operation ensures that the LDO output node has a defined low level state when the circuit is turned off, and works with the pull-up enable module to keep the error amplifier in a defined off state.

[0103] Specifically, when Mn6 is turned on, point C is connected to ground through Mn6, pulling the potential of point C down to zero. For example... Figure 3 As shown, point C is the LDO output node. After being pulled down to zero potential, the LDO output node is turned off to prevent additional leakage current paths caused by the uncertainty of node potential when the circuit is turned off, thus protecting the stability and reliability of the circuit.

[0104] In one embodiment, such as Figure 6 As shown, in step S30, the voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, including:

[0105] S31: The gate of the fifth switching transistor is controlled by the first enable voltage.

[0106] In this embodiment, the first enable voltage VENC is a logic control signal, which is active high and is used to control the conduction and turn-off of the fifth switching transistor Mn5. The fifth switching transistor Mn5 is an NMOS transistor, whose gate is connected to VENC, its drain is connected to one end of R4, and its source is grounded.

[0107] Specifically, when VENC is low, the gate-source voltage of Mn5 is less than the threshold voltage, and Mn5 is in the off state; when VENC is high, the gate-source voltage of Mn5 is greater than the threshold voltage, and Mn5 is turned on, connecting R4 to the circuit and performing a series voltage divider with R3; by switching between high and low levels of VENC, precise control of the working state of the voltage divider protection module can be achieved.

[0108] S32: When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off and the fourth resistor to open.

[0109] In this embodiment, when the LDO circuit is working normally, VENC is at a low level and Mn5 is turned off; the fourth resistor R4 is open, and the third resistor R3 is connected in series with the Miller compensation capacitor Cc.

[0110] Specifically, when Mn5 is turned off, R3 is connected to the circuit. Mn5 has a large resistance value when turned off, so it consumes almost no extra current. R3 is connected in series with Cc. The open circuit of R4 has minimal impact on the frequency compensation function of Miller compensation capacitor Cc and does not affect the normal operation performance and loop stability of LDO.

[0111] S33: When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on, so that the fourth resistor is connected to the circuit and connected in series with the third resistor. The third resistor and the fourth resistor provide voltage division protection for the Miller compensation capacitor.

[0112] In this embodiment, when the LDO circuit is turned off, VENC becomes high, Mn5 is turned on, and the fourth resistor R4 is connected to the circuit; at this time, only the third resistor R3 and the fourth resistor R4 are connected in series, and the series voltage division of R3 and R4 provides voltage division protection for the Miller compensation capacitor Cc.

[0113] Specifically, when Mn5 is turned on, R4 is connected to the circuit, and current flows through R3+R4. The voltage divider branch resistors become R3 and R4. By properly selecting the resistance values ​​of R3 and R4, the voltage across the Miller compensation capacitor Cc is limited to within the rated operating voltage (e.g., 5V). Figure 4 As shown, when the voltage divider module and the enable module are off, there is a 10V voltage drop across the capacitor; when the voltage divider module and the enable module are on, the voltage drop across the capacitor remains around 5V, effectively preventing dielectric breakdown, parameter degradation, and overheating damage to the capacitor due to excessive voltage. This method automatically activates the voltage divider protection when the LDO is off and automatically shuts down the voltage divider path when the LDO is working normally, realizing intelligent switching between protection and function.

[0114] In one embodiment, such as Figure 7 As shown, in step S40, the pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage, including:

[0115] S41: The gates of the third and fourth switching transistors are controlled by the second enable voltage.

[0116] In this embodiment, the second enable voltage VENP is a logic control signal, active low, used to control the turn-on and turn-off of the third switching transistor Mp3 and the fourth switching transistor Mp4; Mp3 and Mp4 are both PMOS transistors, with their gates connected to VENP, their sources connected to a pull-up voltage (10V), and their drains connected to the output nodes A and B of the error amplifier, respectively.

[0117] Specifically, when VENP is high, the gate-source voltages of Mp3 and Mp4 are greater than the threshold voltage (the PMOS transistor conducts when the gate-source voltage is less than the threshold voltage), and Mp3 and Mp4 are in the off state; when VENP is low, the gate-source voltages of Mp3 and Mp4 are less than the threshold voltage, and Mp3 and Mp4 are turned on, pulling points A and B up to the pull-up voltage; by switching between high and low levels of VENP, precise control of the pull-up enable function of the error amplifier output node is achieved.

[0118] S42: When the LDO circuit is operating normally, the second enable voltage controls the third and fourth switching transistors to turn off.

[0119] In this embodiment, when the LDO circuit is working normally, VENP is at a high level, and Mp3 and Mp4 are turned off. At this time, the potentials of points A and B are determined by the error amplifier itself and are not affected by the pull-up enable module.

[0120] Specifically, when Mp3 and Mp4 are turned off, the pull-up enable module is completely disconnected from the output node of the error amplifier, which does not affect the normal operation of the error amplifier, and the voltage signal output by the error amplifier is normally transmitted to the subsequent circuits.

[0121] S43: When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling the output node potential of the error amplifier up to the power supply voltage.

[0122] In this embodiment, when the LDO circuit is turned off, VENP becomes low, and Mp3 and Mp4 are turned on. At this time, points A and B are connected to the pull-up voltage of 10V through Mp3 and Mp4, and their potentials are pulled up to 10V.

[0123] Specifically, when Mp3 and Mp4 are turned on, the potentials of points A and B are forcibly pulled up to 10V to prevent the output nodes from being in a floating or uncertain state. Combined with the pull-down enable module, the output node C of the LDO is pulled down to zero potential, so that the LDO is in a definite potential state when it is off (the LDO output node is at a low level and the error amplifier output node is at a high level), which effectively prevents additional leakage paths and false triggering risks caused by uncertain node potentials when the circuit is turned off.

[0124] In one embodiment, such as Figure 8 As shown, in step S50, the pull-down enable module pulls the LDO output node potential down to zero, including:

[0125] S51: The gate of the sixth switching transistor is controlled by the third enable voltage.

[0126] In this embodiment, the third enable voltage VENN is a logic control signal, which is active high and is used to control the conduction and turn-off of the sixth switching transistor Mn6. Mn6 is an NMOS transistor, whose gate is connected to VENN, its source is grounded, and its drain is connected to the LDO output node C.

[0127] Specifically, when VENN is low, the gate-source voltage of Mn6 is less than the threshold voltage, and Mn6 is in the off state; when VENN is high, the gate-source voltage of Mn6 is greater than the threshold voltage, and Mn6 is turned on, pulling point C down to ground potential; by switching between high and low levels of VENN, precise control of the pull-down enable function of the LDO output node is achieved.

[0128] S52: When the LDO circuit is operating normally, the third enable voltage controls the sixth switching transistor to turn off.

[0129] In this embodiment, when the LDO circuit is working normally, VENN is at a low level and Mn6 is turned off. At this time, the potential at point C is determined by the preceding circuit and is not affected by the pull-down enable module.

[0130] Specifically, when Mn6 is turned off, the pull-down enable module is completely disconnected from the LDO output node, which does not affect the normal operation of the LDO. The LDO can still receive the signal input from the front-end circuit and amplify it normally.

[0131] S53: When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential.

[0132] In this embodiment, when the LDO circuit is turned off, VENN becomes high and Mn6 is turned on; at this time, point C is connected to ground through Mn6, and the potential is pulled down to zero.

[0133] Specifically, when Mn6 is enabled, the potential at point C is forcibly pulled down to zero, ensuring that the LDO output node is in a defined low-level state when the circuit is off. Combined with the pull-up enable module, the output nodes A and B are pulled up to 10V, ensuring that the error amplifier is in a defined potential state when the circuit is off (LDO output node is low level, error amplifier output node is high level). This effectively prevents additional leakage paths and false triggering risks caused by floating nodes or uncertain potentials when the circuit is off, protecting the stability of the circuit. The three enable voltages VENC, VENP, and VENN work synchronously and are indispensable, working together to provide comprehensive protection for the Miller compensation capacitor and the error amplifier.

[0134] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0135] The present invention and its embodiments have been described above. This description is not restrictive. The accompanying drawings are only one embodiment of the present invention. The actual structure is not limited to this. In short, if a person skilled in the art is inspired by this description and designs a similar structure and embodiment without departing from the spirit of the present invention, such design should fall within the protection scope of the present invention.

Claims

1. A protection circuit for the frequency compensation capacitor of a high-voltage LDO, characterized in that, include: The voltage divider protection module (1) is connected in parallel with the Miller compensation capacitor (5) to perform voltage divider protection on the Miller compensation capacitor (5) when the LDO circuit is turned off, and to limit the voltage across the Miller compensation capacitor (5) to not exceed its rated operating voltage. Pull-up enable module (2) is used to connect to the output node of error amplifier (4) in LDO circuit and pull up the potential of the output node to a preset voltage when LDO circuit is turned off; The pull-down enable module (3) is used to connect to the LDO output node and pull down the potential of the LDO output node to zero potential when the LDO circuit is turned off.

2. The protection circuit for the frequency compensation capacitor of a high-voltage LDO according to claim 1, characterized in that: The voltage divider protection module (1) includes a third resistor, a fourth resistor, and a fifth switching transistor; The third resistor and the fourth resistor are connected in series and then connected in parallel with the Miller compensation capacitor (5); the fifth switching transistor is connected in series with the fourth resistor. The gate of the fifth switching transistor is connected to a first enable voltage. When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off. When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on.

3. The protection circuit for the frequency compensation capacitor of a high-voltage LDO according to claim 1, characterized in that: The pull-up enable module (2) includes a third switching transistor and a fourth switching transistor; The control terminals of the third and fourth switching transistors are both connected to the second enable voltage, their sources are both connected to the pull-up voltage, and their drains are respectively connected to different output nodes of the error amplifier (4). When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off. When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling up the output node potential of the error amplifier (4) to the pull-up voltage.

4. The protection circuit for the frequency compensation capacitor of a high-voltage LDO according to claim 1, characterized in that: The pull-down enable module (3) includes a sixth switching transistor; The gate of the sixth switching transistor is connected to the third enable voltage, its source is grounded, and its drain is connected to the LDO output node. When the LDO circuit is working normally, the third enable voltage controls the sixth switching transistor to turn off. When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero potential.

5. The protection circuit for the frequency compensation capacitor of a high-voltage LDO according to claim 1, characterized in that: The first enabling voltage, the second enabling voltage, and the third enabling voltage work simultaneously. When the LDO circuit is turned off, the voltage divider protection module (1), the pull-up enabling module (2), and the pull-down enabling module (3) are turned on synchronously. When the LDO circuit is working normally, each module is turned off synchronously.

6. A protection circuit for a high-voltage LDO frequency compensation capacitor according to claim 1, wherein the protection circuit for the high-voltage LDO frequency compensation capacitor applies a protection method for the high-voltage LDO frequency compensation capacitor, the protection method for the high-voltage LDO frequency compensation capacitor comprising the steps of: When the LDO circuit is working normally, the voltage divider protection module, pull-up enable module, and pull-down enable module are turned off to prevent the protection circuit from interfering with the normal operation of the LDO circuit. When the LDO circuit is turned off, the voltage divider protection module, pull-up enable module, and pull-down enable module are simultaneously turned on. The voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, limiting the voltage across the Miller compensation capacitor to not exceed its rated operating voltage. The pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage. The pull-down enable module pulls the LDO output node potential down to zero.

7. A protection method for a high-voltage LDO frequency compensation capacitor according to claim 6, characterized in that, The voltage divider protection module provides voltage divider protection for the Miller compensation capacitor, specifically including: The gate of the fifth switching transistor is controlled by the first enable voltage; When the LDO circuit is working normally, the first enable voltage controls the fifth switching transistor to turn off and the fourth resistor to open. When the LDO circuit is turned off, the first enable voltage controls the fifth switching transistor to turn on, so that the fourth resistor is connected to the circuit and connected in series with the third resistor. The third resistor and the fourth resistor provide voltage division protection for the Miller compensation capacitor.

8. A protection method for a high-voltage LDO frequency compensation capacitor according to claim 6, characterized in that, The pull-up enable module pulls up the output node potential of the error amplifier to a preset voltage, specifically including: The gates of the third and fourth switching transistors are controlled by the second enable voltage; When the LDO circuit is working normally, the second enable voltage controls the third and fourth switching transistors to turn off; When the LDO circuit is turned off, the second enable voltage controls the third and fourth switching transistors to turn on, pulling the output node potential of the error amplifier up to the power supply voltage.

9. A protection method for a high-voltage LDO frequency compensation capacitor according to claim 6, characterized in that, The pull-down enable module pulls the LDO output node potential down to zero potential, specifically including: The gate of the sixth switching transistor is controlled by the third enable voltage; When the LDO circuit is operating normally, the third enable voltage controls the sixth switching transistor to turn off; When the LDO circuit is turned off, the third enable voltage controls the sixth switching transistor to turn on, pulling the LDO output node potential down to zero.

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