Intelligent fusion terminal multi-stage high-precision time keeping and time keeping method

Abstract

The application discloses a kind of intelligent fusion terminal multistage high-precision time keeping and time keeping method, comprising: establishing soft clock reference in first processor;Data interaction is carried out between second processor and the first processor via asynchronous serial interface, and the time data corresponding to the data interaction process is obtained;Based on the time data, the asymmetric delay of physical communication link is compensated, and the random scheduling jitter on the second processor side is filtered out, and the clock deviation amount of the second processor relative to the soft clock reference is calculated;Based on the clock deviation amount, the system clock of the second processor is smoothly corrected.The application reduces the physical asymmetric error of cross-chip serial communication and random system scheduling interference, and realizes the monotone increasing and high-precision synchronization of terminal system clock under the premise of reducing underlying event omission.

Description

Technical Field

[0001] This invention relates to the field of power distribution network automation terminal technology, specifically to a multi-level high-precision time synchronization and timekeeping method for intelligent fusion terminals. Background Technology

[0002] Intelligent converged terminals are widely used in core business scenarios such as distribution network operation monitoring, electricity consumption information collection, and fault event recording. Because they often contain multiple physically isolated processing units, including underlying acquisition units, a core main control system, and various peripheral communication modules, these units need to maintain strict, high-precision clock synchronization to ensure the absolute accuracy and consistency of time-series data in services such as Sequence of Events (SOE), fault waveform sampling, and full-domain data tracing. The reliability and accuracy of the time reference determine the validity of the terminal's underlying protection actions' logical judgments and the scientific nature of the network-wide distributed state assessment.

[0003] Current time synchronization solutions for such multi-processor converged terminals typically rely on a single real-time clock chip in the underlying hardware as a global reference. This is achieved through a standard asynchronous serial interface and a basic symmetric time synchronization protocol model, periodically distributing timestamps to the main control system for time synchronization. When updating the local system time, the industry-standard underlying logic involves globally or broadly disabling system interrupts at the physical instant of modifying the time register to prevent timing conflicts during data writing. However, due to differences in hardware architecture between the underlying microcontroller and the main control system, cross-chip serial interaction is susceptible to asymmetric communication overhead and random scheduling congestion in the main control system kernel, resulting in significant discrete-time errors in the synchronization process.

[0004] In summary, existing methods struggle to effectively address the dual timing disturbances caused by physical link latency asymmetry and random scheduling in complex scenarios involving multi-processor cross-chip interactions. Furthermore, the coarse-grained underlying clock overwriting mechanism can easily disrupt the monotonically increasing properties of the timeline, and may even lead to interruptions in high-real-time acquisition services and the omission of critical short-state events.

[0005] Therefore, there is an urgent need to study a method that can improve the time synchronization accuracy and runtime robustness of complex multi-unit terminal architectures. Summary of the Invention

[0006] Purpose of the invention: To provide a multi-level high-precision time synchronization and timekeeping method for intelligent fusion terminals, in order to solve the above-mentioned problems existing in the prior art.

[0007] Technical solution: A multi-level high-precision time synchronization and timekeeping method for intelligent fusion terminals, comprising: Establish a soft clock reference in the first processor; Data interaction is performed between the second processor and the first processor via an asynchronous serial interface to obtain time data corresponding to the data interaction process; The clock deviation of the second processor relative to the soft clock reference is calculated by compensating for the asymmetric delay of the physical communication link based on time data and filtering out random scheduling jitter on the second processor side. The system clock of the second processor is smoothly corrected based on the clock skew.

[0008] According to one aspect of this application, an anomaly recovery step in redundant source switching mode is also included, specifically comprising: When the monitoring determines that the main clock source of the first processor has recovered from the abnormal state and is available again, the real-time system deviation value between the first processor and the second processor is calculated and extracted. Extract the pre-configured first deviation threshold and compare the real-time system deviation value with the first deviation threshold; If the real-time system deviation value is determined not to exceed the first deviation threshold, then the proportional frequency modulation method is directly used to perform closed-loop smooth convergence of the system clock of the second processor.

[0009] In one embodiment, the anomaly recovery step further includes: If the real-time system deviation value is determined to exceed the first deviation threshold, the current timestamp and time step are extracted to construct a clock discontinuity feature marker. Insert clock discontinuity feature markers into the terminal's underlying event sequence record; After completing the recording operation of clock discontinuity feature marking, a clock step correction operation based on time step amount is performed, and the proportional frequency modulation mode is switched to suppress residual time deviation.

[0010] In one embodiment, the method further includes a clock health determination step for the first processor, specifically including: Extract the absolute value of the clock skew, the rate of change of the clock skew per unit time, and the communication quality characteristics of the data interaction process; The extracted features are compared with the pre-configured multi-dimensional health thresholds. If the number of consecutive exceedances of any one-dimensional feature reaches a preset value, an alarm message is output, and the current clock source of the first processor is determined to be in an abnormal state, triggering a switching operation of the backup redundant clock source.

[0011] In one embodiment, the switching operation to trigger the backup redundant clock source specifically includes: The availability status of each clock source is detected sequentially according to the priority sequence of the pre-configured hardware real-time clock, satellite second pulse clock, network time protocol clock, and local operating system backup clock. Extract the clock source with the highest priority that is available as the current time base after the switch to maintain global clock synchronization of the terminal.

[0012] In one embodiment, a cascading synchronization step for external modules is further included, specifically comprising: After the system clock of the second processor completes smooth correction, extract the current timestamp data and the current clock synchronization status; The corresponding time quality bits are constructed based on the clock synchronization state. The time quality bits are used to characterize whether the current time base is in an externally locked state or a local timekeeping state. The timestamp data and time quality bits are encapsulated into an extended time synchronization command, which is then sent to cascaded external modules via an industrial serial bus to drive the external modules to perform local clock synchronization with status indicators. Beneficial effects: This invention can effectively reduce the physical asymmetry error and random system scheduling interference in cross-chip serial communication, and achieve strict monotonically increasing and high-precision synchronization of the terminal system clock while ensuring that no underlying events are missed. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the steps of the intelligent fusion terminal multi-level high-precision time synchronization and timekeeping method of the present invention.

[0014] Figure 2 This is a schematic diagram illustrating the steps of obtaining time data via an asynchronous serial interface according to the present invention.

[0015] Figure 3 This is a schematic diagram illustrating the steps of the present invention to compensate for asymmetric delays and filter out random scheduling jitter based on time data to calculate clock deviation.

[0016] Figure 4 This is a schematic diagram illustrating the steps of the present invention to extract round-trip transmission residuals and filter out random scheduling jitter using a sliding median filter. Detailed Implementation

[0017] Example 1: This example provides a multi-level high-precision time synchronization and timekeeping method for intelligent fusion terminals, mainly including the following steps: like Figure 1 As shown, in step 101, a soft clock reference is established in the first processor.

[0018] The hardware architecture of intelligent converged terminal devices typically includes a low-level controller responsible for high real-time data acquisition and a main control unit responsible for complex business processing.

[0019] The first processor is specifically deployed as a microcontroller responsible for AC sampling and low-level protection actions. To provide a stable time source unaffected by external interference, a soft clock reference independent of the external network status is built inside the first processor.

[0020] The soft clock reference is driven periodically by the timer inside the first processor in conjunction with the hardware interrupt mechanism, forming a continuously increasing local time measurement system.

[0021] Establishing this benchmark reduces the absolute dependence on a single external clock source, enabling the terminal to maintain the temporal continuity of local event occurrence sequence recording even when encountering external communication link failures.

[0022] Step 102: Data interaction is performed between the second processor and the first processor via an asynchronous serial interface to obtain the time data corresponding to the data interaction process.

[0023] The second processor can be specifically deployed as a core control unit carrying an operating system.

[0024] Since the first processor and the second processor are physically independent and operate at different frequencies, there is an unavoidable transmission delay in the asynchronous serial interface through which they communicate.

[0025] When the second processor needs to align its system time with the first processor's soft clock reference, the second processor will proactively initiate a time alignment request.

[0026] During this data interaction process, a complete set of time data is obtained by capturing timestamps at four physical moments: request sending, request arrival, response sending, and response receiving.

[0027] The time data provides a basis for subsequent calculations to separate various delay components in the communication link, avoiding time synchronization errors caused by the uncertainty of asynchronous serial communication.

[0028] Step 103: Based on time data, compensate for the asymmetric delay of the physical communication link and filter out random scheduling jitter on the second processor side, and calculate the clock deviation of the second processor relative to the soft clock reference.

[0029] When data is exchanged through an asynchronous serial interface, in addition to the fixed asymmetric delay caused by the difference in physical transmission baud rate and data frame length, the kernel task scheduling mechanism of the operating system on the second processor side will also introduce random scheduling jitter.

[0030] By performing feature extraction and filtering on the acquired time data, the fixed physical transmission delay is removed, and the influence of random jitter is suppressed by the filtering algorithm. The actual difference between the current system time of the second processor and the soft clock reference of the first processor, i.e., the clock deviation, is calculated.

[0031] The purpose of filtering out scheduling jitter is to prevent momentary lag in the operating system from being mistakenly regarded as clock drift, so that the calculated clock deviation can truly reflect the inherent deviation between the physical crystal oscillators of the two independent processors.

[0032] Step 104: Perform smooth correction on the system clock of the second processor based on the clock skew amount.

[0033] After calculating the actual clock skew, the second processor adjusts the system clock it maintains internally based on the skew.

[0034] Specifically, the correction process does not use a step-by-step approach that directly overwrites the current system time. Instead, it fine-tunes the clock frequency parameters of the second processor's operating system kernel, allowing the system clock to slowly converge to a state synchronized with the soft clock reference over a certain evolution period.

[0035] The smoothing correction mechanism ensures that the system clock timeline increases monotonically, preventing the inversion of timestamps in the terminal's underlying event records due to time callbacks or jumps.

[0036] In addition, it should be noted that there are two different scenarios for setting the timeliness indicator in this system.

[0037] When the first processor fails or only the first processor operates independently for a short time, its offline timekeeping accuracy mainly relies on its internal crystal oscillator. However, when the entire intelligent fusion terminal disconnects from the external synchronization source and enters a long-term timekeeping state, since the second processor is usually equipped with a high-precision temperature-compensated crystal oscillator, the global system timekeeping will use the system clock of the second processor as the baseline, thereby meeting the system-level error requirements for long-term operation of the terminal.

[0038] Example 2: Further explanation of the lock-free update mechanism of the soft clock inside the first processor and the hardware timestamp acquisition process.

[0039] In one possible implementation, establishing a soft clock reference in the first processor includes the following steps: Step 201: Configure the first clock buffer and the second clock buffer in the first processor, and set the active index to indicate the currently valid buffer.

[0040] The first and second clock buffers are specifically two independent data storage areas allocated in memory, a mechanism known in engineering as the ping-pong buffering mechanism. Each buffer area contains second, millisecond, and sequence number fields.

[0041] The active index is a single-byte variable used to indicate the buffer block currently in a readable state. By configuring double buffering and a separate indicator variable, data write operations and data read operations are isolated in physical memory space, aiming to solve data inconsistency problems that may occur during concurrent access.

[0042] Specifically, the time value to be updated is obtained by reading back the time value to be updated at a preset period through a hardware real-time clock connected to the first processor.

[0043] The first processor masks interrupts only during bus operations that write timing data to the multi-byte register of the hardware real-time clock, and the duration window for masking interrupts is configured to be less than the minimum time resolution of the event sequence record.

[0044] The hardware real-time clock is a physical clock chip that operates independently of the first processor core. The software clock inside the first processor mainly relies on timer interrupts to run, but long-term operation will accumulate crystal oscillator errors.

[0045] Specifically, the first processor actively initiates a bus read request to the hardware real-time clock every 1 second physical time interval to extract absolute time data as the time value to be updated.

[0046] In some optional implementations, to prevent transient failures in the hardware real-time clock itself, the first processor performs three readback verification operations after reading. If the three consecutive extracted time values ​​are inconsistent, the hardware real-time clock is determined to be faulty. At this time, the first processor stops the readback operation, downgrades the soft clock to a pure internal timer interrupt counting self-running mode, and triggers an abnormal alarm command.

[0047] When the physical clock chip needs to be synchronized, there is a risk that the bus timing may be disrupted by a high-priority interrupt when writing multi-byte data to the bus. Therefore, the first processor only disables the global interrupt response at the moment the bus write operation is triggered.

[0048] Specifically, the physical time consumed by the bus write process is limited to within 15 microseconds. In power system terminals, the minimum time resolution for sequential event recording is typically calibrated to 1 millisecond. Since 15 microseconds is less than 1 millisecond, the short shielding time window will not lead to the loss of millisecond-level service events, thus maintaining the integrity of the underlying acquisition services while ensuring the safety of hardware register writes.

[0049] Step 202: Obtain the time value to be updated from an external clock source, identify the inactive buffer that is different from the active index, and write the time value to be updated into the inactive buffer.

[0050] When performing a data update, the first processor extracts the current active index value, performs mathematical operations on the active index value, calculates the memory index of the inactive buffer, and locks the background buffer area that is not currently occupied by the business reading module.

[0051] The time value to be updated is overwritten into the second and millisecond component fields of the inactive buffer, and the sequence number field is incremented.

[0052] Furthermore, after the data writing is completed, the first processor executes a data memory barrier instruction once to force the buffered data located in the cache to be flushed to the main memory, ensuring that the newly written time value has deterministic global visibility to all interrupt contexts.

[0053] Step 203: After the write is completed, a single-byte atomic flip operation is performed on the active index to switch the inactive buffer to the new active buffer, thereby completing the lock-free update of the soft clock reference without masking interrupts.

[0054] The single-byte atomic flip operation is implemented through an assembly-level assignment instruction that cannot be interrupted, changing the value of the active index from its current value to the index value of the aforementioned inactive buffer.

[0055] In microcontroller architectures, write operations on a single byte are inherently atomic. The moment the active index completes its flip, the foreground read operation is immediately redirected to the buffer block containing the latest time data. This reduces the drawback of embedded systems needing to execute global interrupt disable instructions when updating the clock, achieving zero blocking on the read path.

[0056] In some optional implementations, the reading business module reads the active index once before obtaining the time, and reads the active index again after obtaining the time data. If the index values ​​read twice are equal to the initial read value, the obtained time data is considered complete and valid; otherwise, the reading process is re-executed.

[0057] According to one aspect of this application, data interaction is performed between a second processor and a first processor via an asynchronous serial interface to obtain time data corresponding to the data interaction process, including: like Figure 2 As shown, in step 21, the serial receiving channel of the first processor is configured to direct memory access mode to automatically receive time request frames sent by the second processor.

[0058] Direct memory access (DMI) is a hardware-level data transfer mechanism independent of the central processing unit (CPU). A time request frame is a high-precision time synchronization instruction message issued by a secondary processor.

[0059] By establishing a hardware mapping channel between the serial peripheral's receive register and the system's static random access memory, the hardware controller automatically moves each byte received by the peripheral interface into memory without triggering any byte-by-byte receive interrupts, thus eliminating the tens of microseconds of response jitter caused by software interrupt handling.

[0060] Step 22: When the serial receive line idle flag is detected and an idle interrupt is triggered, the count value of the hardware timer built into the first processor is read at the first instruction of the idle interrupt service routine to obtain the receive timestamp.

[0061] After the last stop bit of the time request frame is transmitted, the serial physical line remains high for a duration greater than one character transmission cycle. Based on this, the serial peripheral hardware automatically sets the idle line detection flag and submits an idle interrupt request with the highest preemption priority to the kernel.

[0062] The hardware timer is specifically configured as a 32-bit high-frequency counter in a continuously free-running state. After the kernel responds to an idle interrupt and enters the service routine, it immediately reads the current count value of the hardware timer at the first assembly instruction.

[0063] Since the hardware pipeline delay between interrupt triggering and the execution of the first instruction is a fixed number of processor clock cycles, the extracted receive timestamp accurately anchors the physical boundary of the arrival of the request message, suppressing random software latency.

[0064] Step 23: Assemble a time response frame based on the received timestamp and the current soft clock reference value of the first processor, and read the count value of the hardware timer to obtain the transmission timestamp when writing the first byte of the time response frame to the serial transmission data register of the first processor.

[0065] After the first processor completes the encapsulation of local time data, it prepares to return a time acknowledgment frame to the second processor. Within the same clock cycle that triggers the physical transmission action by filling the first physical byte of this acknowledgment frame into the serial peripheral's transmit data register, the processor core synchronously reads the aforementioned continuously running hardware timer; this count value serves as the transmission timestamp.

[0066] By extracting timer values ​​under the same benchmark at two strict hardware boundary points—the end of reception and the start of transmission—objective data support is provided for calculating the actual program execution time inside the first processor.

[0067] Step 24: After filling the sending timestamp into the specified payload field of the time response frame, the time response frame containing the receiving timestamp and the sending timestamp is sent to the second processor as time data.

[0068] The first processor directly writes the captured receive timestamp and send timestamp into a specific payload field of the response message for external transmission. Based on the two values ​​captured by the hardware timer, the precise processing delay of the first processor can be extracted, and the operational relationship between its physical quantities satisfies the following extraction equation: MCU =T3-T2; in, MCU T3 is the extracted sending timestamp, and T2 is the extracted receiving timestamp, representing the precise processing delay of the first processor.

[0069] In some alternative implementations, if the first processor needs to output a synchronous physical pulse signal to the outside, it is preferable to use the output compare channel of a hardware timer to directly drive the pin level to flip. If the hardware timer channel resources of the first processor are limited, the second carry event of the soft clock can also be bound to a conventional general-purpose input / output pin, and the pin level can be driven by software instructions to simulate the output of a second pulse signal. However, this alternative method will reintroduce microsecond-level execution jitter, and the system selection should be based on the accuracy target during actual deployment.

[0070] This embodiment constructs a lock-free update mechanism based on ping-pong buffering and single-byte index atomic flipping, which compresses the interrupt masking time caused by writing to the clock register to an extremely short window that is much shorter than the minimum resolution of the event sequence record, thereby reducing the underlying protection actions and loss of critical events caused by time synchronization operations.

[0071] Example 3: Based on Example 2 above, this example provides a further explanation.

[0072] In one possible implementation, before calculating the clock offset of the second processor relative to the soft clock reference by compensating for the asymmetric delay of the physical communication link based on time data and filtering out random scheduling jitter on the second processor side, the following steps are further included: Step 301: Extract the length of the first byte of the time request frame and the length of the second byte of the time response frame.

[0073] Data transmission in an asynchronous serial interface relies on the serial transmission of physical voltage levels. The transmission time at the physical layer is strictly linearly positively correlated with the number of physical bytes occupied by the data packet. The length of the first byte represents the total number of physical bytes consumed when the second processor issues instructions, and the length of the second byte represents the total number of physical bytes occupied when the first processor sends back a data packet containing dual hardware timestamps.

[0074] Step 302: Obtain the pre-configured communication baud rate of the asynchronous serial interface.

[0075] Communication baud rate characterizes the number of bits that a physical communication link can transmit per second. The technical motivation for extracting this configuration parameter is to establish a mathematical benchmark that maps differences in byte length in the spatial dimension to differences in physical transmission time in the temporal dimension.

[0076] Step 303: Based on the difference between the length of the first byte and the length of the second byte, and the communication baud rate, calculate and extract the fixed delay correction amount introduced by the asymmetry of the serial physical communication frame length.

[0077] Traditional symmetric time synchronization algorithms assume consistent round-trip transmission delays. However, structural differences between request and response frames in intelligent fusion terminals lead to asymmetric physical transmission times. By establishing a conversion model for physical transmission timing, this asymmetric deviation can be accurately extracted. The calculation relationship is as follows: uart =(N resp -N req )*10 / f baud ; in, uart To calculate the extracted fixed delay correction, N resp The length of the second byte, N req The length of the first byte is given by f, and the constant 10 represents the total number of bits in a single byte, including the start and stop bits. baud This is the communication baud rate.

[0078] Step 304: In the subsequent step of calculating and extracting the clock deviation, the fixed delay correction amount is used as the benchmark for compensating for the asymmetric delay of the physical communication link.

[0079] After pre-stripping the fixed physical delay deviation calculated through the communication protocol frame structure, the subsequent core filtering algorithm can focus on processing and suppressing unpredictable random jitter caused by the operating system kernel task scheduling.

[0080] In another embodiment, based on time data compensation for asymmetric delays in the physical communication link and filtering out random scheduling jitter on the second processor side, the clock deviation of the second processor relative to the soft clock reference is calculated, specifically including: like Figure 3 As shown, in step 31, the time deviation and frequency drift to be solved are constructed into a two-dimensional state vector.

[0081] Given the inherent characteristics of physical crystal oscillator aging and temperature drift, the actual clock error between two processors is not a static scalar, but rather includes the absolute phase difference at the current moment and the frequency difference that evolves over time. Therefore, a two-dimensional state space is established to jointly track these two physical characteristics: x k =[θ k ,ρ k ] T ; Where, x k Let θ be the two-dimensional state vector corresponding to the discrete time period. k Let ρ be the time deviation of the system to be solved. k The frequency shift to be solved for in the system is represented by the superscript T, which indicates the transpose of the matrix.

[0082] Step 32: Extract the round-trip transmission residual and single-time deviation observation value of a single interaction based on time data and in combination with a fixed delay correction amount.

[0083] The round-trip transmission residual represents the total uncertain time consumed during the lifetime of the data exchanged between the two ends, after removing the fixed processing time of the first processor and the physical link transmission time, caused by the random task scheduling of the operating system on the second processor side. The single-shot bias observation represents the instantaneous time difference calculation result without filtering and model smoothing.

[0084] Specifically, when the second processor sends a time request frame to the first processor, it reads the local operating system clock to obtain the request transmission time T1; after receiving the time response frame, it reads the local operating system clock to obtain the response reception time T4. Combining the reception timestamp T2 and transmission timestamp T3 carried in the response frame, the extraction equations for the round-trip transmission residual and single-shot deviation observations are as follows: RTT var =(T4-T1)-(T3-T2)-(N req +N resp )*10 / f baud ; θ raw =((T2-T1)-(T4-T3)) / 2+Δ uart / 2; Among them, RTT var For the round-trip transmission residual, θ raw For a single deviation observation, T1 is the request sending time recorded by the second processor, T4 is the response receiving time recorded by the second processor, T2 is the receiving timestamp, T3 is the sending timestamp, and N is the receiving timestamp. req N is the length of the first byte. resp The length of the second byte, f baud For the communication baud rate, Δ uartThis is a fixed delay correction amount. The physical meaning of the round-trip transmission residual is that, after removing the deterministic processing time and the theoretically shortest physical transmission time from the first processor's internal processing lifecycle, the remaining part reflects the uncertain delay introduced by the operating system scheduling on the second processor side.

[0085] Step 33: Use the process noise covariance matrix, which includes pre-configured white frequency noise parameters and frequency random walk parameters, to predict the state evolution of the two-dimensional state vector.

[0086] In the physical model of crystal oscillator drift, the white frequency noise parameter characterizes the severity of short-term random phase jitter, while the frequency random walk parameter characterizes the long-term slow frequency drift caused by the influence of external thermodynamic environment. Introducing these physical parameters to construct the process noise covariance matrix drives the filter to proactively predict the evolution trend of clock error based on physical principles during the data interaction window. The prediction process of time deviation follows a linear operation law: multiplying the frequency drift of the previous cycle by the evolution duration and then superimposing it onto the time deviation of the previous cycle.

[0087] Specifically, the state evolution equation is: x{k|k-1}=F*x{k-1|k-1}, where F=[[1,τ],[0,1]] is the state transition matrix, and τ is the actual evolution time between two adjacent data interactions. The corresponding observation equation is: zk=H*xk+vk, where H=[1,0] characterizes the dimension of the system's direct observation time deviation, and vk is the measurement noise.

[0088] In one alternative implementation, the white frequency noise and frequency random walk parameters can be set by those skilled in the art by performing Allan variance analysis on the crystal oscillator configured in the first processor to extract the corresponding noise figure for adaptive configuration.

[0089] Step 34: Based on the single deviation observation and the measurement noise covariance determined based on the round-trip transmission residual, the predicted two-dimensional state vector is recursively updated, and the final time deviation and frequency drift after filtering out random scheduling jitter are calculated and extracted as clock deviation.

[0090] By combining the predicted prior state caused by process noise with the current dynamically weighted observation data, a Kalman state gain matrix is ​​calculated and generated. This gain matrix is ​​then used to perform closed-loop correction on the initial predicted two-dimensional state vector, ultimately outputting a smooth two-dimensional error feature that is immune to sudden scheduling jitter.

[0091] It should be noted that existing formulas, such as state transition equations, observation equations, and Kalman gain calculation equations, will not be elaborated upon here.

[0092] According to another aspect of this application, before recursively updating the predicted two-dimensional state vector based on single-blindness observations and measurement noise covariance, a step of dynamically constructing the measurement noise covariance is included, specifically including: Step 3a: Within a sliding window of a preset length, extract the specified percentile value of the historical round-trip transmission residual sequence to construct the historical minimum round-trip basis.

[0093] To accurately assess the smoothness of current instantaneous communication scheduling, a dynamic comparison benchmark is established. This is achieved by storing recent round-trip transmission residual data in a fixed-capacity FIFO queue and sorting the sequence to extract the lowest percentile value. This value objectively represents the communication time boundary where, under the current overall system load, the operating system scheduling execution is most efficient and interruption suspension time is minimized.

[0094] Step 3b: Calculate the deviation between the currently extracted round-trip transport residual and the historical minimum round-trip basis.

[0095] Calculate the ratio of the difference between the currently observed residual value and the aforementioned ideal basis. This deviation serves as an evaluation metric, objectively reflecting the severity of the blocking interference encountered in the operating system kernel during this time data interaction process.

[0096] Step 3c: Dynamically determine and output the measurement noise covariance based on the degree of deviation, so that during the recursive update process, adaptive weighting is performed on low-quality single deviation observations with a deviation degree higher than a set threshold.

[0097] Traditional recursive estimators typically use a fixed constant as measurement noise. This step dynamically transforms the operating system's scheduling quality into the confidence weights of the filter. Specifically, when the deviation is large, the measurement noise covariance is actively amplified, forcing the filter to reject the current low-quality observation data. The numerical relationship is as follows: R k = *(1+κ*MAX(0,RTT var / RTT base -1)); Among them, R k The dynamic output measurement noise covariance, σ0 is the pre-configured baseline measurement standard deviation, κ is the quality attenuation coefficient characterizing the severity of attenuation, MAX is the clipping operator extracting the maximum value from the input set, and RTT is the dynamic output measurement noise covariance. var RTT is the currently extracted round-trip transport residual. baseTo construct the historical minimum round-trip baseline, it is assumed that after parameter normalization, the baseline measurement standard deviation is configured to be 0.05 and the quality attenuation coefficient is configured to be 20. The specific values ​​of the above parameters can be adaptively adjusted according to the statistical characteristics of the operating system scheduling jitter in the actual system. Those skilled in the art can determine the appropriate values ​​by observing the statistical distribution of the round-trip transmission residuals without creative effort.

[0098] If the calculated current round-trip residual is equal to the historical baseline, the computational term is set to zero, the output measurement noise covariance maintains the baseline minimum, and the confidence weight assigned to the current high-precision observation is increased.

[0099] According to one aspect of this application, after extracting the final time deviation and frequency drift after filtering out random scheduling jitter, the method further includes: Step 3d: Extract the state uncertainty covariance matrix corresponding to the two-dimensional state vector that is synchronously maintained during the recursive update process.

[0100] The state uncertainty covariance matrix is ​​a core associated matrix that the recursive estimator maintains simultaneously when updating the state vector. The characteristics of its elements quantitatively characterize the statistical confidence interval of the current system's joint estimation results of time deviation and frequency drift.

[0101] Step 3e: Based on the internal parameters of the state uncertainty covariance matrix, calculate the predicted standard deviation of time uncertainty over the future evolution duration.

[0102] As time progresses in the unaligned interaction state, the unknown uncertainty of the physical crystal oscillator frequency will continue to amplify through integration, causing the uncertainty of the time deviation to exhibit a nonlinear surge trend. By extracting the time deviation variance, frequency deviation variance, and their cross-covariance components from this associated matrix, and combining them with process noise parameters, the theoretical extreme standard deviation of the system clock deviation from the true reference at any future time can be calculated through rigorous mathematical deduction.

[0103] Specifically, let the updated form of the state uncertainty covariance matrix be P = [[P 11 ,P 12 ],[P 12 ,P 22 If the white frequency noise parameter in the process noise covariance matrix is ​​q1 and the frequency random walk parameter is q2, then the predicted standard deviation of the time uncertainty after a future evolution time τ satisfies the following relationship: σ predict (τ)=sqrt(P 11 +2τP 12 +τ 2 *P 22 +q1*τ+q2*τ 3 / 3 ).

[0104] In step 3f, constraint σ predict (τ)<=A target ;where A target To determine the pre-configured target accuracy tolerance, the adaptive synchronization period can be obtained by inversely solving for the maximum τ value that satisfies the inequality. Those skilled in the art can determine this maximum τ value using a numerical bisection search method or an analytical root-finding method.

[0105] Step 3f: Under the condition that the standard deviation of the time uncertainty prediction does not exceed the pre-configured target accuracy tolerance, dynamically reverse the solution to find the maximum evolution time that meets the conditions, and determine it as the adaptive synchronization period for the next data interaction.

[0106] To balance low occupancy of underlying communication bus resources with high clock synchronization accuracy, the fixed-period forced polling mechanism is replaced with an error uncertainty-driven adaptive polling mechanism. When frequency offset tracking is stable and the value of the state uncertainty covariance matrix is ​​extremely small, the maximum evolution time obtained by inverse calculation can be dynamically extended to 300 seconds; while when the system encounters a sudden change in ambient temperature that causes the frequency offset confidence to diverge, the calculated evolution time will automatically shrink to 3 seconds, thereby automatically triggering high-frequency intensive time synchronization to quickly relock the crystal oscillator frequency.

[0107] In some alternative implementations, in addition to the preferred scheme of using the extracted state uncertainty covariance matrix to drive the adaptive cycle, an exponential smoothing algorithm with a forgetting factor can be used to independently estimate the long-term average drift rate, and the extracted absolute value of the average drift rate can be mapped to multiple preset threshold intervals. The duration of the next round of data interaction is then hard-matched according to the specific level of the current drift rate.

[0108] According to one aspect of this application, smoothing correction of the system clock of the second processor based on clock skew specifically includes: Step 30a: Extract the first error feature for the time dimension and the second error feature for the frequency dimension from the clock skew.

[0109] The final time deviation output by the above high-order filtering algorithm is defined as the first error feature, and the calculated crystal oscillator frequency drift is defined as the second error feature.

[0110] Step 30b: Extract absolute correction parameters for the system clock based on the first error feature, and extract fine-tuning correction parameters for the system clock based on the second error feature.

[0111] To meet the security interface specifications of the second processor's operating system kernel system calls, it is necessary to scale and transform the physical characteristic parameters. Specifically, the base unit of the first error characteristic is converted into an absolute correction parameter at the microsecond level, and the dimensionless second error characteristic is exponentially amplified and converted into a fine-tuning correction parameter at the parts-per-million level.

[0112] In step 30c, absolute calibration parameters and fine-tuning calibration parameters are injected into the operating system kernel of the second processor simultaneously through the system call interface, so as to drive the system clock to achieve closed-loop smooth convergence under the constraint of strict monotonically increasing.

[0113] Traditional network time synchronization application layer software typically only reports the absolute time difference to the system kernel and performs a forced reset, which can cause dangerous negative jumps in the operating system's system clock. This embodiment injects both absolute displacement control instructions and frequency fine-tuning control instructions simultaneously through an interface call, prompting the kernel clock subsystem to gradually offset the existing two-dimensional error by smoothly fine-tuning the oscillator step.

[0114] During this process, the system clock value maintains a monotonically increasing unidirectional extension property, avoiding deadlock crashes caused by time axis backtracking in all upper-level industrial control applications that rely on system time.

[0115] In one optional implementation, when the second processor's operating system is a Linux kernel, the system call interface is specifically the adjtimex() system call, which achieves two-parameter atomic injection by simultaneously setting its offset field and frequency field. Those skilled in the art will understand that for other operating system kernels, the equivalent clock adjustment interface provided by that operating system can be used to achieve the same function.

[0116] Example 4: This example provides an alternative implementation for compensating for asymmetric delays in the physical communication link based on time data and filtering out random scheduling jitter on the second processor side, calculating the clock deviation of the second processor relative to the soft clock reference. The specific difference lies in the following: for second processors without dedicated hardware floating-point units or with limited system computing power, the matrix multiplication and high-order state-space estimation models, which consume significant memory and execution cycles, are abandoned. Instead, a data window statistical filtering strategy with extremely low basic execution overhead is adopted. The remaining data acquisition and compensation logic is the same as in Example 3, and can be referred to the foregoing description; it will not be repeated here.

[0117] In one possible implementation, the following steps are included: like Figure 4 As shown, in step 401, based on the accumulated time data from multiple historical periods and combined with a fixed delay correction amount, the round-trip transmission residuals from multiple interactions and the single deviation observation value are extracted.

[0118] Because the task scheduling of the operating system exhibits a highly random distribution in the time domain, data samples extracted in a single instance lack statistical persuasiveness. The second processor, over a continuous physical time period, repeatedly initiates time-synchronization communication interactions, accumulating multiple sets of time data containing four basic timestamps. Based on this, the round-trip transmission residuals corresponding to each independent interaction process and the unfiltered, unsmoothed single-instance deviation observations are calculated and extracted, thereby constructing two parallel discrete time series in system memory.

[0119] Step 402: Extract the specified percentile value of the round-trip transmission residual sequence within a sliding window of a set length, and determine it as the scheduling delay basis.

[0120] After constructing the round-trip residual sequence, the second processor establishes a first-in, first-out (FIFO) data sliding window. When new residual data is pushed into the window, the oldest historical residual data is removed.

[0121] The second processor sorts all round-trip residual values ​​within the current sliding window in ascending order and directly extracts the value corresponding to the preset low percentile index. This percentile value represents the baseline communication time least affected by random scheduling congestion during recent communication. The preset sliding window length can be set to 16 samples, and the specified percentile can be set to the 10th percentile. By extracting the low percentile value, occasional delay spikes are effectively shielded, establishing a stable and reliable scheduling delay baseline.

[0122] Step 403: Based on the scheduling delay basis and the pre-configured acceptance tolerance, abnormal single deviation observations caused by scheduling jitter exceeding the limit are removed, and the valid sample set is retained.

[0123] After obtaining the above scheduling delay base, a pre-configured scalar time value is added to it as a hard threshold boundary.

[0124] The second processor evaluates the round-trip residual corresponding to each acquired single deviation observation. If the residual value is greater than the boundary, it determines that the current interaction process has encountered a serious kernel scheduling blockage, and directly marks the corresponding single deviation observation as invalid data in memory and removes it.

[0125] Only when the residual value is less than or equal to the boundary will the corresponding single bias observation be judged as a high-confidence sample, and thus retained and combined to construct a valid sample set. This step, from the perspective of hard physical truncation, isolates the serious asymmetric latency risk caused by operating system scheduling from the subsequent core computation closed loop.

[0126] Step 404: Perform a sliding median filtering operation on the single deviation observations within a continuously preset number of valid sample sets to calculate and extract the clock deviation amount after filtering out random scheduling jitter.

[0127] After the aforementioned hard truncation screening, slight random fluctuations will still remain within the effective sample set. The second processor further establishes a median extraction window for the effective samples. When the accumulated number of effective samples reaches a preset standard, the values ​​within the window are sorted by size, and the sample value at the absolute middle position is extracted and output.

[0128] Through this statistical extraction mechanism, a smoothed estimate that filters out the effects of various random scheduling jitters is calculated, and this output value is determined as the final clock skew amount output in this embodiment.

[0129] By configuring direct memory access and idle interrupt mechanisms at the hardware level to capture high-precision timestamps, and combining physical frame length difference compensation and two-dimensional state space recursive estimation on the main control system side, asymmetric transmission time and random scheduling jitter are filtered out, reducing the cross-chip synchronization error from milliseconds to microseconds and improving clock synchronization accuracy.

[0130] In a typical deployment scenario, the first processor uses an ARM Cortex-M4 microcontroller with a main frequency of 72MHz, the second processor uses an ARM Cortex-A7 processor with a Linux operating system, and the communication baud rate of the asynchronous serial interface is configured to 115200bps.

[0131] Under a test environment that runs continuously for 24 hours, after adopting the above Kalman filtering scheme, the steady-state value of the time deviation of the second processor system clock relative to the soft clock reference is maintained within ±100 microseconds. Compared with the direct time synchronization method without filtering (the deviation fluctuation range is about ±2 milliseconds), the synchronization accuracy is improved by about an order of magnitude.

[0132] Those skilled in the art will understand that specific accuracy indicators may vary depending on the processor model, operating system kernel version, communication baud rate configuration, and ambient temperature conditions.

[0133] Example 5: Further explanation is given of the clock health determination steps for the first processor, the switching operation of triggering the backup redundant clock source, and the abnormal recovery steps in the redundant source switching mode.

[0134] In one possible implementation, a clock health determination step for the first processor is also included, specifically comprising the following steps: Step 501: Extract the absolute value of the clock skew, the rate of change of the clock skew per unit time, and the communication quality characteristics of the time data interaction process.

[0135] To accurately assess the reliability of the current time synchronization link, operational characteristics are extracted from three dimensions. The absolute value of the clock skew is used to characterize the instantaneous phase difference range of the current physical crystal oscillator. The rate of change of the clock skew per unit time is used to characterize the severity of drift caused by sudden changes in ambient temperature or aging of the physical crystal oscillator. Communication quality characteristics are specifically reflected by extracting the standard deviation of the round-trip transmission residuals during multiple interactions, which is used to characterize the stability and anti-interference capability of the underlying asynchronous serial interface physical channel.

[0136] Step 502: Compare the extracted features with the pre-configured multi-dimensional health thresholds, and continuously count the number of times each dimension exceeds the limit.

[0137] For the features in the three dimensions mentioned above, corresponding hard constraint boundaries are pre-configured for each.

[0138] Specifically, an absolute deviation threshold is configured for the absolute value of the clock deviation, which can be set to 5 milliseconds. A drift rate threshold is configured for the rate of change of the clock deviation per unit time, which can be set to 0.5 milliseconds per minute. A communication jitter threshold is configured for the communication quality characteristics, which can be set to 1 millisecond. The extracted real-time features are input one by one into the comparison module to determine whether they exceed the preset values ​​of the corresponding dimensions.

[0139] Step 503: If the number of consecutive overruns of any one-dimensional feature reaches a preset value, an alarm message is output, and the current clock source of the first processor is determined to be in an abnormal state, triggering the switching operation of the backup redundant clock source.

[0140] Because physical equipment may encounter transient electromagnetic interference during operation, causing abrupt changes in single data acquisition, a continuous failure detection logic is introduced to prevent erroneous triggering of the switching mechanism. The preset value can be set to 3 times. When a feature in a certain dimension exceeds its corresponding multi-dimensional health threshold for three consecutive detection cycles, the system confirms that the degradation is not due to transient interference, but rather a substantial failure of the clock source or a link disconnection. At this point, an alarm log is generated for recording, the failure clock source is blocked from further participation, and the switching control process of the multi-source redundancy architecture is initiated.

[0141] Step 504: Probe the availability status of each clock source in sequence according to the priority sequence of the pre-configured hardware real-time clock, satellite second pulse clock, network time protocol clock, and backup clock of the local operating system.

[0142] In a multi-source redundancy architecture, there are multiple alternative time providers. The hardware real-time clock of the first processor has the highest local physical accuracy and is set as the highest priority. The satellite second pulse clock relies on the Global Navigation Satellite System to provide an absolute time reference and is set as the second highest priority. The network time protocol clock relies on Ethernet to provide wide-area synchronization services and is the third highest priority.

[0143] The backup clock of the local operating system, relying on an internal temperature-compensated crystal oscillator for free operation, is set to the lowest priority as a last resort. Following this strict priority order, the system reads the status registers of each interface to sequentially determine whether each clock source is currently in a reliable and usable state with a connected link.

[0144] Step 505: Extract the clock source with the highest priority and in an available state as the current time base after the switch, so as to maintain the global clock synchronization of the terminal.

[0145] By traversing the above priority sequence, the system automatically locks the currently surviving time source module with the highest priority and reroutes its time output signal to the input of the core clock filtering algorithm.

[0146] This operation completes a seamless handover within milliseconds of physical time, ensuring that even if the entire intelligent converged terminal suffers from local hardware failure or network disconnection, it can still maintain the operation of global timing logic by relying on the optimal residual time source.

[0147] According to one aspect of this application, an anomaly recovery step in redundant source switching mode is also included, specifically comprising: Step 50a: When the monitoring determines that the main clock source of the first processor has recovered from the abnormal state and is available again, calculate and extract the real-time system deviation value between the first processor and the second processor.

[0148] Once the real-time clock of the first processor hardware, which was previously identified as abnormal, is repaired or the external connection is restored to stability, the system needs to switch back to the main clock source.

[0149] Before performing the actual system clock parameter modification, the second processor initiates an instantaneous data interaction with the first processor to calculate and extract the instantaneous time difference accumulated during the period of abnormal isolation when the two processors run independently, i.e., the real-time system deviation value.

[0150] Step 50b: Extract the pre-configured first deviation threshold and compare the real-time system deviation value with the first deviation threshold.

[0151] The first deviation threshold is the physical boundary between a small, easily smoothed range of clock errors and a large, step-wise range of errors. This value is configured based on the operating system's maximum allowable frequency adjustment capability and the service's tolerance for time convergence timeliness; specifically, it can be set to 200 milliseconds. The system inputs the acquired real-time system deviation value into a comparator to determine whether it has exceeded this boundary.

[0152] Step 50c: If the real-time system deviation value is determined not to exceed the first deviation threshold, the proportional frequency modulation method is directly used to perform closed-loop smooth convergence of the system clock of the second processor; if the real-time system deviation value is determined to exceed the first deviation threshold, the clock step correction operation is performed and then switched to the proportional frequency modulation method.

[0153] When the accumulated deviation is less than or equal to 200 milliseconds, the system determines that the error can be absorbed without the business being aware of it through gradual frequency fine-tuning.

[0154] At this point, the operating system kernel's clock frequency adjustment interface is invoked, setting the maximum proportional frequency adjustment to 500 parts per million. The clock gradually approximates the actual time by slightly speeding up or slowing down its own ticking. This not only maintains the strict monotonically increasing timeline but also does not interfere with upper-layer protection and control tasks that rely on continuous time.

[0155] According to one aspect of this application, the anomaly recovery step further includes: Step 5i: If the real-time system deviation value exceeds the first deviation threshold, extract the current timestamp, determine the corresponding time step based on the real-time system deviation value, and construct a clock discontinuity feature marker.

[0156] When the abnormal isolation time is too long and the cumulative deviation is greater than 200 milliseconds, if the proportional frequency modulation method is continued, the convergence process will take several hours or even days, which will seriously affect the accuracy requirements of power incident tracing.

[0157] Therefore, the system adopts a forced time-step transition. In order to legitimize the physical transition in business logic, the system actively extracts the absolute timestamp of the moment the transition occurs and the specific time difference of the transition to be executed, and concatenates it with a hardware switchback feature code to construct a structured anomaly traceability message, namely a clock discontinuity feature marker.

[0158] Step 5ii: Insert the clock discontinuity feature marker into the event sequence record at the terminal's underlying layer.

[0159] The clock discontinuity feature constructed above is marked as a low-level system event with the highest write privileges and forcibly written into the event sequence record database in the persistent storage module.

[0160] This action physically occurs just before the time step jump, ensuring that when the master station retrieves fault recordings or event logs, it can clearly know that a legitimate time jump has occurred at this moment by parsing this marker, thereby avoiding misjudgments about the order of events.

[0161] Step 5iii: After completing the recording operation of the clock discontinuity feature mark, perform a clock step correction operation based on the time step amount, and switch to the proportional frequency modulation mode to suppress the residual time deviation.

[0162] After confirming that the log writing is correct, the system calls the kernel absolute time setting interface to adjust the system clock significantly to near the time scale currently indicated by the master clock source.

[0163] Since the stepping operation itself cannot achieve absolute alignment at the microsecond level, after completing the coarse adjustment stepping, the system control logic immediately switches back to the aforementioned proportional frequency modulation mode. By extracting the residual minute deviation a second time for closed-loop frequency fine-tuning, high-precision steady-state synchronization is finally achieved in the large deviation fault-tolerant switchback scenario.

[0164] A two-way fine-tuning correction parameter targeting the time and frequency dimensions is introduced to drive the operating system kernel to achieve smooth closed-loop convergence. At the same time, when facing a large-span clock deviation switching scenario, the clock discontinuity feature mark of the forced insertion is further processed step by step, which not only maintains the strict monotonic increase of the time axis under normal steady-state operation, but also ensures the legality and timing robustness of global business time traceability under jump conditions.

[0165] Example 6 further explains the cascading synchronization steps for external modules.

[0166] In one possible implementation, a cascading synchronization step for external modules is also included, specifically comprising the following steps: Step 601: After the system clock of the second processor completes the smooth correction, extract the current timestamp data and determine the current clock synchronization state based on the execution state of the smooth correction.

[0167] Intelligent converged terminals typically function as data aggregation nodes, cascading multiple business data acquisition and control modules downwards in their physical structure. To ensure the timing consistency of events generated by devices within the entire terminal network, the second processor, after completing its own frequency fine-tuning and clock convergence, needs to provide a time reference output to the outside.

[0168] Specifically, the second processor extracts the current timestamp data, which includes physical components of year, month, day, hour, minute, second, and millisecond, from the operating system kernel. At the same time, the system extracts the current clock synchronization status from the background daemon process. This status parameter objectively reflects whether the terminal is currently in a high-precision synchronization mode physically locked with the upper-level master station or satellite second pulse signal, or in a local timekeeping mode where the external synchronization communication link is broken and it is forced to rely on the internal crystal oscillator for maintenance.

[0169] Step 602: Construct the corresponding time quality bit based on the clock synchronization state. The time quality bit is used to characterize whether the current time reference is in an externally locked state or a local timekeeping state.

[0170] Conventional one-way time synchronization protocols only include a time value vector in the sent message, making it impossible for the downstream receiving module to assess the confidence level of the acquired time data. This embodiment directly maps the synchronization state by allocating a specific physical space of binary status bits in the message structure.

[0171] Specifically, a separate byte is allocated in the data field as the time quality bit, with its highest bit defined as a synchronization or timekeeping flag. A value of 1 indicates a locked synchronization state, while a value of 0 indicates an offline timekeeping state. The second highest bit is defined as a hardware fault flag. This state feature mapping mechanism adds quantifiable quality evaluation attributes to the output timestamp data.

[0172] Step 603: Encapsulate the timestamp data and time quality bits into an extended time synchronization command and send it to the cascaded external modules via the industrial serial bus to drive the external modules to perform local clock synchronization with status indicators.

[0173] Based on the basic communication frame format standard, timestamp data with millisecond precision is combined with the aforementioned constructed time quality bits and filled into the data payload area. Specifically, a hexadecimal extended instruction structure with a data identifier field of F100H is used for encapsulation, and a frame sequence number and cyclic redundancy check code are added to the frame structure to ensure the integrity of the transmitted data.

[0174] After encapsulation and compilation, the message instruction is sent to each cascaded external service module via the terminal's RS-485. Upon receiving the instruction message, the external module parses and extracts the time quality bits to assess the available level of the received time reference. If it determines that the access conditions of the local service control logic are met, it then extracts the timestamp data to overwrite or adjust the clock register of its local controller.

[0175] In some alternative implementations, in addition to employing an extended instruction encapsulation protocol based on an industrial serial communication bus, the intelligent converged terminal can also instantiate a network time protocol server process for the Ethernet physical interface in parallel, or instantiate a time status topic publishing mechanism for the IoT application layer protocol. All of these external synchronization interface processes with different physical forms share the system clock reference and time quality parameters uniformly maintained by the second processor, thus ensuring compatibility with and meeting the high-precision clock alignment requirements of cascaded devices with different hardware access forms under a unified spatiotemporal reference.

Claims

1. A multi-level high-precision time synchronization and timekeeping method for intelligent fusion terminals, characterized in that, include: Establish a soft clock reference in the first processor; Data interaction is performed between the second processor and the first processor via an asynchronous serial interface to obtain time data corresponding to the data interaction process; The clock deviation of the second processor relative to the soft clock reference is calculated by compensating for the asymmetric delay of the physical communication link based on time data and filtering out random scheduling jitter on the second processor side. The system clock of the second processor is smoothly corrected based on the clock skew.

2. The method according to claim 1, characterized in that, Establishing a soft clock reference in the first processor includes: Configure a first clock buffer and a second clock buffer in the first processor, and set an active index to indicate the currently valid buffer; Get the time value to be updated, identify the inactive buffer that is different from the active index, and write the time value to be updated into the inactive buffer; After the write is completed, a single-byte atomic flip operation is performed on the active index to switch the inactive buffer to the new active buffer, thereby completing the lock-free update of the soft clock reference without masking interrupts.

3. The method according to claim 2, characterized in that, Retrieve the time value to be updated, including: The time value to be updated is read back at a preset period using a hardware real-time clock connected to the first processor. The first processor masks interrupts only during bus operations that write data to the multi-byte register of the hardware real-time clock, and the duration window for masking interrupts is configured to be less than the minimum time resolution of the event sequence record.

4. The method according to claim 1, characterized in that, Data interaction is performed between the second processor and the first processor via an asynchronous serial interface to obtain time data corresponding to the data interaction process, including: Configure the serial receive channel of the first processor to direct memory access mode to automatically receive time request frames sent by the second processor; When the serial receive line idle flag is detected and an idle interrupt is triggered, the count value of the hardware timer built into the first processor is read at the first instruction of the idle interrupt service routine to obtain the receive timestamp. When writing the first byte of the time acknowledgment frame to the serial data register of the first processor, the count value of the hardware timer is read to obtain the transmission timestamp; A time response frame containing the receive timestamp and the send timestamp is sent to the second processor as time data.

5. The method according to claim 4, characterized in that, Before calculating the clock offset of the second processor relative to the soft clock reference by compensating for asymmetric delay in the physical communication link based on time data and filtering out random scheduling jitter on the second processor side, the process also includes: Extract the length of the first byte of the time request frame and the length of the second byte of the time response frame; Obtain the pre-configured communication baud rate of the asynchronous serial interface; Based on the difference between the length of the first byte and the length of the second byte, and the communication baud rate, the fixed delay correction amount introduced by the asymmetry of the serial physical communication frame length is calculated and extracted. In the subsequent step of calculating and extracting the clock deviation, the fixed delay correction amount is used as the benchmark for compensating for the asymmetric delay of the physical communication link.

6. The method according to claim 5, characterized in that, Based on time data compensation for asymmetric delays in the physical communication link and filtering out random scheduling jitter on the second processor side, the clock deviation of the second processor relative to the soft clock reference is calculated, specifically including: The time deviation and frequency drift to be solved are constructed as a two-dimensional state vector; Extract round-trip transmission residuals and single-period deviation observations for a single interaction based on time data; Using the process noise covariance matrix containing pre-configured white frequency noise parameters and frequency random walk parameters, state evolution prediction is performed on a two-dimensional state vector. Based on the single deviation observation and the measurement noise covariance, the predicted two-dimensional state vector is recursively updated, and the final time deviation and frequency drift after filtering out random scheduling jitter are calculated and extracted as clock deviation.

7. The method according to claim 6, characterized in that, Before recursively updating the predicted two-dimensional state vector based on single-blindness observations and measurement noise covariance, the process also includes a step of dynamically constructing the measurement noise covariance, specifically including: Within a sliding window of a preset length, extract the specified percentile value of the historical round-trip transmission residual sequence to construct the historical minimum round-trip basis. Calculate the deviation of the currently extracted round-trip transport residual from the historical minimum round-trip basis; The measurement noise covariance is dynamically determined and output based on the degree of deviation, so that in the recursive update process, low-quality single deviation observations with a deviation degree higher than a set threshold are subject to adaptive weight reduction.

8. The method according to claim 6, characterized in that, After extracting the final time deviation and frequency drift after filtering out random scheduling jitter, the following is also included: Extract the state uncertainty covariance matrix corresponding to the updated two-dimensional state vector; Based on the internal parameters of the state uncertainty covariance matrix, the predicted standard deviation of time uncertainty over the future evolution duration is calculated; Under the condition that the standard deviation of the time uncertainty prediction does not exceed the pre-configured target accuracy tolerance, the maximum evolution time that meets the conditions is dynamically reversed and determined as the adaptive synchronization period for the next data interaction.

9. The method according to claim 1, characterized in that, The clock deviation of the second processor relative to the soft clock reference, calculated by compensating for asymmetric delay in the physical communication link based on time data and filtering out random scheduling jitter on the second processor side, is specifically achieved through the following method: Extract round-trip transmission residuals and single bias observations from multiple sets of historical time data. Extract the specified percentile value of the round-trip transmission residual sequence within a sliding window of a set length, and determine it as the scheduling delay basis; Based on the scheduling delay basis and the pre-configured acceptance tolerance, abnormal single deviation observations caused by scheduling jitter exceeding the limit are removed, and the valid sample set is retained. Perform a sliding median filtering operation on the single deviation observations within a continuously preset number of valid sample sets to calculate and extract the clock deviation after filtering out random scheduling jitter.

10. The method according to claim 1, characterized in that, The system clock of the second processor is smoothed based on the clock skew, specifically including: Extract the first error feature for the time dimension and the second error feature for the frequency dimension from the clock skew. The absolute correction parameters for the system clock are extracted based on the first error feature, and the fine-tuning correction parameters for the system clock are extracted based on the second error feature. Through the system call interface, absolute calibration parameters and fine-tuning calibration parameters are simultaneously injected into the operating system kernel of the second processor to drive the system clock to achieve closed-loop smooth convergence under the constraint of strict monotonically increasing.

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