GPU board system and electronic device

Abstract

The application provides a GPU board system and an electronic device. The GPU board system comprises a GPU module, an MCU management module and a CPLD module, and the GPU module, the MCU management module and the CPLD module are in communication connection. The GPU module is used for data processing tasks. The CPLD module is used for providing level conversion transmission and latching for the MCU management module and the GPU module. The CPLD module is used for monitoring the working state of the MCU management module. When the running state of the MCU management module is monitored to be abnormal, the preset level state of the key signal output by the MCU management module is maintained immediately to make the GPU module continue to work normally, and the MCU management module is triggered to restart and recover without induction. The application can support fault level maintenance and induction-free recovery.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a GPU board system and electronic device. Background Technology

[0002] With the rapid development of Artificial Intelligence (AI) technology, Graphics Processing Units (GPUs) have risen rapidly in the AI ​​wave, becoming the most widely used and cost-effective heterogeneous accelerated computing solution in the AI ​​field, leading to a surge in market demand. For end customers, building a hardware environment that meets AI computing needs is costly, and GPU instability or frequent failures can cause irreparable losses. Therefore, many downstream AI and internet companies are placing stringent demands on the performance and stability of GPUs. Meanwhile, for designers, the increasing integration of current GPUs has led to more complex and numerous onboard interfaces. These new application requirements present new challenges for GPU system design. Ensuring stable and reliable operation while meeting the multifaceted performance requirements of GPUs has become a critical issue that urgently needs to be addressed in this field. Summary of the Invention

[0003] The purpose of this application is to provide a GPU board system and electronic device that can solve at least one of the technical problems mentioned in the prior art.

[0004] One aspect of this application provides a GPU board system. The GPU board system includes a GPU module, an MCU management module, and a CPLD module, all of which are communicatively connected. The GPU module is responsible for data processing tasks; the CPLD module provides level conversion transmission and latching for the MCU management module and the GPU module; the CPLD module monitors the operating status of the MCU management module; and when an abnormality is detected in the operating status of the MCU management module, it immediately maintains a preset level for key signals output by the MCU management module to ensure the GPU module continues to operate normally, and triggers a seamless restart of the MCU management module for recovery.

[0005] Furthermore, the GPU module has a first master I2C interface, and the CPLD module has a first slave I2C interface. The first master I2C interface and the first slave I2C interface are communicatively connected to enable bidirectional data interaction between the GPU module and the CPLD module. The MCU management module has a second master I2C interface, and the CPLD module has a second slave I2C interface. The second master I2C interface and the second slave I2C interface are communicatively connected to enable bidirectional data interaction between the MCU management module and the CPLD module.

[0006] Furthermore, the MCU management module has multiple first GPIO interfaces, the GPU module has multiple second GPIO interfaces, and the CPLD module has multiple third GPIO interfaces and multiple fourth GPIO interfaces. The multiple third GPIO interfaces in the CPLD module are communicatively connected to the first GPIO interfaces in the MCU management module; the multiple fourth GPIO interfaces in the CPLD module are communicatively connected to the second GPIO interfaces in the GPU module and peripheral modules. The CPLD module is used to implement the mutual conversion of different voltage levels between the third GPIO interfaces and the fourth GPIO interfaces and to latch the signals of the multiple first GPIO interfaces of the MCU management module.

[0007] Furthermore, the MCU management module is used to periodically upload a PWM heartbeat signal to the CPLD module through a first GPIO interface. When the PWM heartbeat signal is normal, the CPLD module is used to perform signal pass-through and latching between the MCU management module, the GPU module, and the peripheral module. When the PWM heartbeat signal is abnormal, the CPLD module is used to immediately maintain the key level signal of some interfaces of the MCU management module and provide the key level signal to the corresponding interface. In addition, the CPLD module is used to send a reset signal to the MCU management module through a third GPIO interface.

[0008] Furthermore, the GPU board system also includes a power clock module, which is used to stably supply the power and clock signals required for the operation of the GPU module; the GPU module has a third main I2C interface, which is used to collect power data and clock chip data of the power clock module through the third main I2C interface, and to control the output voltage and output mode of each power supply in the power clock module through the third main I2C interface.

[0009] Furthermore, the CPLD module is also used to centrally manage the signals of each power supply and clock control chip in the power clock module through the fourth GPIO interface. Each power supply is configured with an enable signal, a power good signal, and an alarm signal. The CPLD module is used to directly control the power-on process of the enable signal of each power supply, and to uniformly collect and process the power good signal and the alarm signal, and then only feed back the final result signal to the MCU management module.

[0010] Furthermore, the GPU board system also includes a monitoring module, which is used to monitor the key operating status of the GPU board system in real time. The monitoring module includes a current monitoring circuit, a voltage monitoring circuit, and a temperature monitoring circuit. The key operating status of the GPU board system includes current information, voltage information, and temperature data at multiple points of the GPU board system. The MCU management module has a fourth main I2C interface and a fifth GPIO interface. The MCU management module is used to manage the data of the current monitoring circuit, the voltage monitoring circuit, and the temperature monitoring circuit through the fourth main I2C interface. The MCU management module is used to control the GPIO signals of the current monitoring circuit, the voltage monitoring circuit, and the temperature monitoring circuit in the monitoring module through the fifth GPIO interface.

[0011] Furthermore, the MCU management module has a fifth master I2C interface, and the GPU module has a fifth slave I2C interface. The fifth master I2C interface and the fifth slave I2C interface are communicatively connected to realize data interaction between the MCU management module and the GPU module.

[0012] Furthermore, the GPU board system also includes a gold finger, which has a system management bus interface. The MCU management module has a sixth slave I2C interface, and the system management bus interface is communicatively connected to the sixth slave I2C interface. All data stored in the registers inside the MCU management module can be accessed through the system management bus interface on the gold finger. In addition, the system management bus interface on the gold finger is also used to support online upgrades of the MCU management module. The gold finger has a sixth GPIO interface, and the MCU management module has a seventh GPIO interface. The sixth GPIO interface is communicatively connected to the seventh GPIO interface. The MCU management module is used to process external GPIO signals accessed through the sixth GPIO interface on the gold finger and then distribute them to the corresponding modules.

[0013] Another aspect of this application provides an electronic device. The electronic device includes a GPU board system as described above.

[0014] The GPU board system and electronic device of one or more embodiments of this application can achieve at least one of the following beneficial technical effects: (1) Significantly reduce the selection threshold and hardware cost of MCU management module. The CPLD module completes the conversion of different I / O levels and the expansion of MCU management module interface. There is no need to configure an independent level conversion chip and watchdog chip. It effectively solves the technical pain points of insufficient interface types and limited resources of low-end MCU management module. While controlling hardware costs, it ensures the integrity of system functions. (2) Significantly improve the stability and continuity of system operation. When the internal program of the MCU management module is abnormal, the CPLD module can maintain the preset level of key signals to ensure that the GPU module is not affected and continues to work normally. At the same time, it triggers the MCU's seamless restart recovery process to avoid system shutdown or functional interruption and achieve a smooth transition in abnormal conditions. (3) Enhance the safety and reliability of system operation. The monitoring module provides comprehensive real-time monitoring of the voltage, current and system temperature of the onboard power supply, and timely feedback of operating status information. This provides data support for system fault warning and abnormal handling, and reduces the risk of hardware damage or functional failure caused by abnormal power supply or excessive temperature. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the framework of a GPU board system according to an embodiment of this application.

[0016] Figure 2 This is a schematic diagram of the I2C topology framework in a GPU board system according to an embodiment of this application.

[0017] Figure 3 This is a schematic diagram of the GPIO topology framework in a GPU board system according to an embodiment of this application.

[0018] Figure 4 This is a logical diagram illustrating the logical processing state of a CPLD module according to an embodiment of this application.

[0019] Figure 5 This is a flowchart illustrating the working mode determination process of a CPLD module according to an embodiment of this application. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0021] The GPU board system and electronic device of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0022] This application provides a GPU board system. Figure 1 A schematic diagram of the framework of a GPU board system 100 according to one embodiment of this application is shown. Figure 1 As shown, one embodiment of this application includes a GPU module 110, an MCU (Microcontroller Unit) management module 120, and a CPLD (Complex Programmable Logic Device) module 130.

[0023] The MCU management module 120 provides communication interfaces such as I2C (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface) to support external register access and software upgrades. On the other hand, it undertakes the communication scheduling of various modules within the GPU board and realizes signal control of the entire module.

[0024] The GPU module is the core processing unit of the GPU board system 100 and can be used to handle data processing tasks.

[0025] The GPU module 110, MCU management module 120, and CPLD module 130 are all connected. The CPLD module 130 can provide level conversion transmission and latching for the MCU management module 120 and GPU module 110. The CPLD module 130 can monitor the working status of the MCU management module 120. When an abnormality is detected in the operating status of the MCU management module 120, it immediately maintains the preset level of the key signals output by the MCU management module 120 to ensure that the GPU module 110 continues to work normally, and triggers the MCU management module 120 to restart and recover without being detected. This realizes functions such as level maintenance and restarting and recovering the MCU management module 120.

[0026] In some embodiments, the CPLD module 130 of this application can also expand the limited GPIO (General Purpose Input Output) interface resources of the MCU management module 120, and can also complete the conversion of different GPIO levels between modules, which can meet the increasing number of GPIO interfaces required on the GPU board system 100.

[0027] In some embodiments, the GPU board system 100 of this application may further include a power clock module 140 and a monitoring module 150.

[0028] The power clock module 140 can stably supply the power and clock signals required for the operation of the GPU module 110. The power clock module 140 includes multiple (e.g., N) power supplies 141 and a clock control chip 142. The power supplies 141 may include, but are not limited to, digital POL (Digital Point-of-Load) power supplies.

[0029] The monitoring module 150 can monitor the key operating status of the GPU board system 100 in real time. Optionally, the monitoring module 150 may include, but is not limited to, a current monitoring circuit 151, a voltage monitoring circuit 152, and a temperature monitoring circuit 153. The key operating status of the GPU board system 100 may include, but is not limited to, current information, voltage information, and temperature data at multiple points of the GPU board system 100.

[0030] Figure 2 A schematic diagram of the I2C topology framework in a GPU board system 100 according to an embodiment of this application is disclosed. Figure 2 As shown, the modules in the GPU board system 100 can achieve data interaction and function control through the I2C interface.

[0031] The GPU module 110 has a first master I2C interface 211, and the CPLD module 130 has a first slave I2C interface 212. The first master I2C interface 211 of the GPU module 110 and the first slave I2C interface 212 of the CPLD module 130 are communicatively connected, thereby enabling bidirectional data interaction between the GPU module 110 and the CPLD module 130.

[0032] The MCU management module 120 has a second master I2C interface 221, and the CPLD module 130 has a second slave I2C interface 222. The second master I2C interface 221 of the MCU management module 120 and the second slave I2C interface 222 of the CPLD module 130 are connected for communication, thereby enabling bidirectional data interaction between the MCU management module 120 and the CPLD module 130.

[0033] The GPU module 110 can write data into the registers configured inside the CPLD module 130 through the first main I2C interface 211. The MCU management module 120 can access and read all the data stored in the registers inside the CPLD module 130 through the second main I2C interface 221.

[0034] In some embodiments, the GPU module 110 has a third main I2C interface 231. The GPU module 110 can acquire power data and clock chip data from the power clock module 140 through the third main I2C interface 231, and can control the output voltage and output mode of each power supply 141 in the power clock module 140 to precisely match its operating requirements. The clock control chip 142 supports switching signal sources and reading the clock's LOCK function. The GPU module 110 can also obtain the current operating status of the clock control chip 142 in real time through this third main I2C interface 231.

[0035] In some embodiments, the MCU management module 120 has a fourth main I2C interface 241, through which the MCU management module 120 can manage data from the current monitoring circuit 151, voltage monitoring circuit 152, and temperature monitoring circuit 153. The current monitoring circuit 151 can calculate current information by collecting the voltage across a precision resistor, and this current information can be stored in a register configured within the MCU management module 120. The voltage monitoring circuit 152 can collect voltage signals from all critical power supplies on the GPU board system 100 using an ADC (Analog-to-Digital Converter) and store them in a register configured within the MCU management module 120. The temperature monitoring circuit 153 can employ a temperature sensor chip to collect temperature data from multiple points on the GPU board system 100, such as the air inlet, air outlet, and the area surrounding high-temperature components, and then store the temperature data in a register configured within the MCU management module 120.

[0036] In some embodiments, the MCU management module 120 has a fifth master I2C interface 251, and the GPU module 110 has a fifth slave I2C interface 252. The fifth master I2C interface 251 and the fifth slave I2C interface 252 are connected in communication, thereby enabling data interaction between the MCU management module 120 and the GPU module 110.

[0037] The GPU board system 100 of this application also includes a gold finger 160, which has a System Management Bus (SMBUS) interface 261, and the MCU management module 120 has a sixth slave I2C interface 262.

[0038] The system management bus interface 261 on the gold finger 160 is connected to the sixth slave I2C interface 262 of the MCU management module 120. Through the system management bus interface 261 on the gold finger 160, all data stored in the registers inside the MCU management module 120 can be accessed. In addition, the system management bus interface 261 on the gold finger 160 can also support the online upgrade function of the MCU management module 120.

[0039] Figure 3 A schematic diagram of the GPIO topology framework in a GPU board system 100 according to an embodiment of this application is disclosed. Figure 3 As shown, the CPLD module 130 has a level conversion function. Since the MCU management module 120 operates at 3.3V, while some circuits operate at different voltages such as 1.8V or 1.2V, the GPIO signal lines between the MCU management module 120 and modules with different voltage levels need to be level-converted by the CPLD module 130 to achieve stable communication between them. Therefore, in some embodiments, the MCU management module 120 has multiple first GPIO interfaces 311, the GPU module 110 has multiple second GPIO interfaces 312, and the CPLD module 130 has multiple third GPIO interfaces 313 and multiple fourth GPIO interfaces 314.

[0040] In this module, multiple third GPIO interfaces 313 in the CPLD module 130 are communicatively connected to the first GPIO interface 311 in the MCU management module 120; multiple fourth GPIO interfaces 314 in the CPLD module 130 are communicatively connected to the second GPIO interface 312 in the GPU module 110 and peripheral modules, such as a power clock module 140. The CPLD module 130 can be used to convert between different voltage levels of the third GPIO interfaces 313 and the fourth GPIO interfaces 314 and latch the signals of the multiple first GPIO interfaces 311 of the MCU management module 120. For example, when the operating level of the MCU management module 120 is 3.3V and the operating level of the GPU module 110 is 1.2V, the level of the third GPIO interface 313, which is connected to the MCU management module 120, is 3.3V, and the level of the fourth GPIO interface 314, which is connected to the GPU module 110, is 1.2V. In order to achieve stable communication between the MCU management module 120 and the GPU module 110, the CPLD module 130 can perform different voltage level conversion between the third GPIO interface 313 and the fourth GPIO interface 314.

[0041] Figure 4 This document presents a logic diagram illustrating the logic processing state of a CPLD module 130 according to an embodiment of this application. Figure 5A flowchart illustrating the operating mode determination of a CPLD module 130 according to an embodiment of this application is disclosed. (Refer to...) Figure 4 and Figure 5 As shown, the MCU management module 120 can utilize the CPLD module 130 as a watchdog timer. The MCU management module 120 can periodically upload a fixed PWM heartbeat signal to the CPLD module 130 as a watchdog signal through one of its first GPIO interfaces 311, allowing the CPLD module 130 to monitor the operating status of the MCU management module 120 in real time. When the PWM heartbeat signal is normal (i.e., the MCU management module 120 is working normally), the CPLD module 130 can perform signal pass-through, latching, and level conversion between the MCU management module 120, the GPU module 110, and peripheral modules, assisting the MCU management module 120 in completing signal transmission and level adaptation. When the PWM heartbeat signal is abnormal, such as when the PWM heartbeat signal is interrupted (i.e., no valid heartbeat signal is received within a preset time), the CPLD module 130 can determine that the MCU management module 120 program is abnormal. In this case, the CPLD module 130 can immediately maintain the last state of the key level signals of some interfaces of the MCU management module 120 and provide the key level signals to all corresponding interfaces. The key level signals of some interfaces of the MCU management module 120 can be preset level states of some GPIO signals that affect the operation of the GPU module 110, thereby realizing the level signal holding function, ensuring normal power output, and allowing the GPU module 110 to continue to operate stably.

[0042] Furthermore, when an abnormal operation of the MCU management module 120 is detected, the CPLD module 130 can send a RESET signal to the MCU management module 120 through one of the third GPIO interfaces 313 without affecting the operation of the GPU module 110, supporting the seamless recovery and restart of the MCU management module 120 and ensuring the overall continuity of system operation.

[0043] In some embodiments, the CPLD module 130 of this application can also realize GPIO resource expansion and centralized signal management. For example, the CPLD module 130 can also centrally manage the signals of each power supply and clock control chip in the power clock module 140 through the fourth GPIO interface 314. Since the GPU module 110 requires more than a dozen different types of power supplies, each power supply is configured with an EN (enable) signal, a PG (power good) signal, and some ALERT (alarm) signals. If the above signals are directly processed by the MCU management module 120 alone, it will occupy a large amount of its I / O resources. By centrally managing such signals through the CPLD module 130, dozens of I / O resources can be saved for the MCU management module 120, reducing the resource load of the MCU management module 120.

[0044] In addition, the power control and signal acquisition process can be optimized through the CPLD module 130. Specifically, the power-on process of the EN (enable) signal of each power supply can be directly controlled by the CPLD module 130, and the PG (power good) signal and ALERT (alarm) signal are uniformly acquired and processed by the CPLD module 130, and the final result signal is fed back only to the MCU management module 110, thereby greatly simplifying the signal processing process of the MCU management module 120.

[0045] Continue to refer to Figure 3 In some embodiments, the MCU management module 120 has a fifth GPIO interface 315, through which the MCU management module 120 can control the RESET and other GPIO signals of the current monitoring circuit 151, voltage monitoring circuit 152 and temperature monitoring circuit 153 in the monitoring module 150.

[0046] In some embodiments, the gold finger 160 has a sixth GPIO interface 316, and the MCU management module 120 has a seventh GPIO interface 31. The sixth GPIO interface 316 and the seventh GPIO interface 31 are communicatively connected. External GPIO signals such as RESET transmitted by the server through the sixth GPIO interface 316 on the gold finger 160 need to be processed by the MCU management module 120 before being distributed to the corresponding modules.

[0047] The GPU board system 100 of this application supports fault level maintenance and seamless recovery. It employs a separate architecture for the MCU management module 120 and the CPLD module 130, respectively implementing I2C interface management and GPIO control functions. The GPU board system 100 also includes multiple modules such as power supply, clock, and monitoring. All voltage, current, and temperature data on the card are synchronized via I2C. The MCU management module 120 and the GPU module 110 can precisely adjust the operating status of each module through the I2C interface. All GPIO signals on the GPU board system 100 can be controlled by the MCU management module 120 and processed by the CPLD module 130, reducing the resource requirements of the MCU management module 120. Furthermore, the CPLD module 130 can monitor the operating status of the MCU management module 120 in real time. When the MCU management module 120 malfunctions, the CPLD module 130 can immediately trigger a fault protection mechanism to maintain the stability of critical signals, ensuring the continuous normal operation of the GPU module 110, and simultaneously completing the seamless recovery of the MCU management module 120.

[0048] The GPU board system 100 of this application can achieve at least the following beneficial technical effects: (1) Significantly reduce the selection threshold and hardware cost of MCU management module 120. The CPLD module 130 completes the conversion of different I / O levels and the interface expansion function of MCU management module 120. There is no need to configure an independent level conversion chip and watchdog chip. It effectively solves the technical pain points of insufficient interface types and limited resources of low-end MCU management module 120, and ensures the integrity of system functions while controlling hardware costs. (2) Significantly improve the stability and continuity of system operation. When the internal program of the MCU management module 120 is abnormal, the CPLD module 130 can maintain the preset level of key signals to ensure that the GPU module 110 is not affected and continues to work normally. At the same time, it triggers the MCU's seamless restart recovery process to avoid system shutdown or functional interruption and achieve a smooth transition in abnormal conditions. (3) Enhance the safety and reliability of system operation. The monitoring module 150 monitors the voltage, current and system temperature of the onboard power supply in all aspects in real time, and provides timely feedback on the operating status information. This provides data support for system fault warning and abnormal handling, and reduces the risk of hardware damage or functional failure caused by abnormal power supply or excessive temperature.

[0049] This application also provides an electronic device. This electronic device may include the GPU board system 100 as described above.

[0050] The electronic devices covered by this application may include, but are not limited to, desktop computers, graphics workstations, industrial servers, artificial intelligence computing devices, edge computing terminals, industrial control hosts, data center computing devices, and high-performance graphics processing devices.

[0051] The electronic device of this application has beneficial technical effects that are substantially similar to those of the GPU board system 100 described above, therefore, it will not be described in detail here.

[0052] The GPU board system and electronic device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the GPU board system and electronic device of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A GPU board system, characterized in that, It includes a GPU module, an MCU management module, and a CPLD module. The GPU module, the MCU management module, and the CPLD module are all communication-connected. The GPU module is responsible for data processing tasks; The CPLD module is used to provide level conversion transmission and latching for the MCU management module and the GPU module. The CPLD module is used to monitor the working status of the MCU management module. When an abnormality is detected in the operating status of the MCU management module, the CPLD module immediately maintains the preset level of the key signals output by the MCU management module to ensure that the GPU module continues to work normally and triggers the MCU management module to restart and recover without being noticed.

2. The GPU board system as described in claim 1, characterized in that, The GPU module has a first master I2C interface, and the CPLD module has a first slave I2C interface. The first master I2C interface and the first slave I2C interface are communicatively connected to realize bidirectional data interaction between the GPU module and the CPLD module. The MCU management module has a second master I2C interface, and the CPLD module has a second slave I2C interface. The second master I2C interface and the second slave I2C interface are communicatively connected to realize bidirectional data interaction between the MCU management module and the CPLD module.

3. The GPU board system as described in claim 2, characterized in that, The MCU management module has multiple first GPIO interfaces, the GPU module has multiple second GPIO interfaces, and the CPLD module has multiple third GPIO interfaces and multiple fourth GPIO interfaces. The multiple third GPIO interfaces in the CPLD module are communicatively connected to the first GPIO interfaces in the MCU management module; the multiple fourth GPIO interfaces in the CPLD module are communicatively connected to the second GPIO interfaces in the GPU module and the peripheral module. The CPLD module is used to realize the mutual conversion of different voltage levels between the third GPIO interfaces and the fourth GPIO interfaces and to latch the signals of the multiple first GPIO interfaces of the MCU management module.

4. The GPU board system as described in claim 3, characterized in that, The MCU management module is used to periodically upload PWM heartbeat signals to the CPLD module through a first GPIO interface. When the PWM heartbeat signal is normal, the CPLD module is used to perform signal pass-through and latching between the MCU management module, the GPU module, and the peripheral module; When the PWM heartbeat signal is abnormal, the CPLD module is used to immediately maintain the critical level signal of some interfaces of the MCU management module and provide the critical level signal to the corresponding interface. In addition, the CPLD module is used to send a reset signal to the MCU management module through a third GPIO interface.

5. The GPU board system as described in claim 3, characterized in that, The GPU board system also includes a power clock module, which is used to stably supply the power and clock signals required for the operation of the GPU module. The GPU module has a third main I2C interface, which is used to collect power data and clock chip data from the power clock module through the third main I2C interface, and to control the output voltage and output mode of each power supply in the power clock module through the third main I2C interface.

6. The GPU board system as described in claim 5, characterized in that, The CPLD module is also used to centrally manage the signals of each power supply and clock control chip in the power clock module through the fourth GPIO interface. Each power supply is equipped with an enable signal, a power good signal, and an alarm signal. The CPLD module is used to directly control the power-on process of the enable signal of each power supply, and to collect and process the power good signal and the alarm signal in a unified manner, and then feed back the final result signal only to the MCU management module.

7. The GPU board system as described in claim 1, characterized in that, The GPU board system also includes a monitoring module, which is used to monitor the key operating status of the GPU board system in real time. The monitoring module includes a current monitoring circuit, a voltage monitoring circuit, and a temperature monitoring circuit. The key operating status of the GPU board system includes current information, voltage information, and temperature data at multiple points of the GPU board system. The MCU management module has a fourth main I2C interface and a fifth GPIO interface. The MCU management module is used to manage the data of the current monitoring circuit, the voltage monitoring circuit and the temperature monitoring circuit through the fourth main I2C interface. The MCU management module is used to control the GPIO signals of the current monitoring circuit, the voltage monitoring circuit and the temperature monitoring circuit in the monitoring module through the fifth GPIO interface.

8. The GPU board system as described in claim 1, characterized in that, The MCU management module has a fifth master I2C interface, and the GPU module has a fifth slave I2C interface. The fifth master I2C interface and the fifth slave I2C interface are communicatively connected to realize data interaction between the MCU management module and the GPU module.

9. The GPU board system as described in any one of claims 1 to 8, characterized in that, The GPU board system also includes a gold finger, which has a system management bus interface. The MCU management module has a sixth slave I2C interface. The system management bus interface is communicatively connected to the sixth slave I2C interface. All data stored in the registers inside the MCU management module can be accessed through the system management bus interface on the gold finger. Furthermore, the system management bus interface on the gold finger is also used to support online upgrades of the MCU management module. The gold finger has a sixth GPIO interface, and the MCU management module has a seventh GPIO interface. The sixth GPIO interface and the seventh GPIO interface are communicatively connected. The MCU management module is used to process the external GPIO signals accessed through the sixth GPIO interface on the gold finger and then distribute them to the corresponding modules.

10. An electronic device, characterized in that, Including the GPU board system as described in any one of claims 1 to 9.

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