Server cooling fan board compatible with multiple specifications of fans and fan switching method

Abstract

This invention pertains to the field of server cooling, specifically a server cooling fan board compatible with multiple fan specifications and a fan switching method. The server cooling fan board includes a board body, a composite fan interface area, a unified fan control unit, a power circuit, an in-situ detection module, a specification identification module, and a drive output module. The board body features six sets of small fan interfaces and four sets of large fan interfaces arranged in a staggered manner, compatible with PWM 4-pin / 8-pin interfaces. The unified fan control unit uses a CPLD chip to automatically identify fan specifications by reading ID resistor values ​​or speed feedback signals, enabling intelligent switching between 6-channel and 4-channel drive outputs. It also features mixed access detection, tiered fault handling, and closed-loop monitoring functions. This invention allows for flexible switching between multiple fan specifications simply by replacing the fan, without requiring board replacement, significantly reducing hardware costs and maintenance difficulty. It is highly adaptable and suitable for various server cooling systems.

Description

Technical Field

[0001] This invention relates to a server cooling fan board compatible with multiple fan specifications and a fan switching method, belonging to the field of server cooling technology. Background Technology

[0002] Servers generate a lot of heat during operation, and fan cooling is a key structure for ensuring stable server operation. To facilitate quick maintenance in case of fan failure, current servers typically design the fan control and interface as a separate fan board, which is separate from the motherboard. This allows for replacement of faulty fans simply by removing and installing the fan, without having to disassemble the entire motherboard module.

[0003] In standard-sized server chassis, the mainstream fan cards currently fall into two categories:

[0004] One type is a fan board that is compatible with 6038 / 6060 fans (referred to as small fans), which supports up to 6 6038 fans; the other type is a fan board that is compatible with 8038 / 8060 fans (referred to as large fans), which supports up to 4 8038 / 8060 fans.

[0005] Due to significant differences in the external dimensions, installation spacing, and terminal positions between the 6038 / 6060 and 8038 / 8060 fan specifications, the interface terminals corresponding to the six small fans are incompatible with the four large fans, resulting in the two fan boards being incompatible.

[0006] When servers change their fan configurations based on different power consumption and heat dissipation requirements, the corresponding fan cards must be replaced. The existing solution has the following obvious drawbacks:

[0007] 1) High design and production costs: It is necessary to design, verify and produce two specifications of fan boards at the same time, which not only increases hardware design costs and PCB mold opening costs, but also increases material procurement and inventory management costs, which is not conducive to large-scale production.

[0008] 2) High assembly and maintenance difficulty: When switching fan configurations, the entire board module, including the fan board, needs to be disassembled and replaced. The fan board disassembly and assembly process is complicated, which increases the difficulty of operation for assembly personnel and takes a long time, affecting the efficiency of server maintenance.

[0009] 3) Poor compatibility and flexibility: The two types of board structures are not standardized, making it impossible to freely switch between multiple fan specifications, which is not conducive to the standardized deployment of servers and cannot meet the flexible heat dissipation configuration requirements in different scenarios.

[0010] 4) Limited interface compatibility: Existing boards typically only support a single type of interface and cannot be compatible with both PWM 4-pin and 8-pin mainstream fan interfaces at the same time. The compatibility range is narrow and it is difficult to meet the control requirements of fans of different specifications.

[0011] Among existing patented technologies, there are several solutions related to fan control. Publication number CN115718531A discloses a "method, apparatus, device, and storage medium for decoupling a fan backplane from its BMC," which achieves decoupling of the BMC code and the fan backplane type by communicating between the BMC on the motherboard and the CPLD on the fan backplane. This solution addresses the communication decoupling problem between the BMC and the CPLD; however, its fan backplane still uses a single-specification fan interface design and does not involve an interface layout compatible with multiple physical size fans on the same board.

[0012] Publication number CN222300018U discloses a "fan compatibility control circuit, motherboard, and storage system," which uses a CPLD to generate voltage control signals or PWM control signals based on fan type detection signals to adjust the speed of voltage fans or PWM fans respectively. This solution addresses the compatibility issue between voltage fans and PWM fans, rather than the compatibility of fans with different physical sizes.

[0013] CN223728206U discloses a "fan board and heat dissipation device with multi-compatible redundancy control", which includes multiple sets of fans, each set of fans including multiple pluggable fans and non-pluggable fans. The "multi-compatible" in this solution refers to the compatibility between pluggable and non-pluggable fans, solving the problem of maintenance convenience, rather than the compatibility of fans with different physical specifications.

[0014] Publication number CN122170081A discloses a "fan control method, apparatus, CPLD, and storage medium" that identifies the target device category by acquiring the presence signal of the mounting plate, and the target device category is associated with the number of output channels. In this scheme, the number of output channels is determined based on the number of mounting plates, rather than based on the physical specifications of the connected fans for identification and switching.

[0015] CN121254995A discloses "A Server Backplane Fan Control System and Method Based on CPLD", which switches between BMC control mode and CPLD autonomous control mode via a DIP switch. This solution addresses the switching of control modes, rather than the switching between different fan specifications.

[0016] In summary, existing technologies lack a server cooling fan board solution that is fully compatible with fans of different physical specifications, from hardware layout to control logic. Therefore, there is an urgent need for a server cooling fan board and corresponding control method that is compatible with multiple fan specifications, supports free fan switching, and adapts to multiple interface types. Summary of the Invention

[0017] To address the problems of existing server fan boards being incompatible with multiple fan specifications, requiring the design of multiple boards, complex disassembly and assembly, high cost, and inability to simultaneously adapt to both PWM 4-pin and 8-pin fan interfaces, this invention provides a server cooling fan board compatible with multiple fan specifications and a fan switching method. This allows for free switching between multiple fan specifications on the same board, requiring only the fan to be replaced without replacing the fan board. It is also compatible with multiple interface types, improving compatibility and flexibility, and reducing costs and maintenance difficulty.

[0018] Specifically, the technical solution of the present invention is as follows:

[0019] Firstly, server cooling fan boards compatible with multiple fan sizes, including:

[0020] The board body is set up independently of the server motherboard and is used to realize the installation, control and heat dissipation of the fan; the board body adopts a multi-layer PCB design, and the overall size is adapted to the standard server chassis. It achieves electrical connection and signal transmission with the chassis back panel and server motherboard through connectors.

[0021] The composite fan interface area is located on the board body and includes M sets of first-specification fan interfaces and N sets of second-specification fan interfaces, where M>N. The first-specification fan interfaces are used to connect to first-specification fans, and the second-specification fan interfaces are used to connect to second-specification fans. The size of the first-specification fan is smaller than that of the second-specification fan. The first-specification fan interfaces and the second-specification fan interfaces are arranged in a staggered and partitioned manner on the board body. The spacing between adjacent fan interfaces is determined according to the installation size of the corresponding fan, so that the first-specification fan and the second-specification fan do not interfere with each other when installed separately.

[0022] A unified fan control unit is located on the main body of the board and is electrically connected to each first-specification fan interface and each second-specification fan interface respectively.

[0023] The power supply circuit is located on the main body of the board and is electrically connected to the unified fan control unit and all fan interfaces to supply power to the connected fans.

[0024] The in-situ detection module is located on the main body of the board and is electrically connected to each fan interface. It is used to detect whether a fan is connected to each fan interface and transmit the detection results to the unified fan control unit.

[0025] The specification identification module is located on the main body of the board and is electrically connected to each fan interface. It is used to read the ID resistance value or feedback resistance value of the connected fan to identify the fan specification type and transmit the identified specification type to the unified fan control unit.

[0026] The drive output module is located on the board body and is electrically connected to the unified fan control unit and each fan interface. It is used to output drive according to the control signal of the unified fan control unit.

[0027] The unified fan control unit is used to receive the detection results of the in-situ detection module and the specification type identified by the specification identification module. According to the detection results and specification type, the unified fan control unit switches to the first working mode and enables M drive outputs when it detects M first specification fans connected, switches to the second working mode and enables N drive outputs when it detects N second specification fans connected, and triggers an alarm signal when it detects that first specification fans and second specification fans are connected in a mixed manner.

[0028] It should be noted that the composite interface layout of this invention is not a simple physical superposition. Unlike existing technologies that adapt to different fan sizes by replacing the mechanical back frame, this invention simultaneously lays out two physical interface specifications on the electrical layer of the same PCB board, and combines them with corresponding electrical identification and control logic to form a complete system solution. The mounting hole positions, spacing, and terminal positions of the two fan specifications (6038 and 8038 specifications) differ significantly, requiring careful staggered layout design within the limited board space; it cannot be simply placed.

[0029] In this invention, the terms fan interface or interface socket are used to refer to the physical connector soldered on the fan board, and fan plug or fan connector are used to refer to the lead plug that comes with the fan itself.

[0030] Preferably, the unified fan control unit is a CPLD chip, which integrates a PWM output interface and a serial communication interface (such as I...). 2 (C interface or SGPIO interface), and is compatible with both PWM 4-pin and PWM 8-pin fans; the CPLD chip connects via I... 2 The C interface or SGPIO interface is used to communicate with the server's BMC, and is used to report fan configuration information, speed information, and operating status information to the BMC, and to receive speed control commands issued by the BMC.

[0031] In existing technologies, fan control schemes using CPLD chips mainly fall into three categories: ① Transparent forwarding type – forwarding the TACH signal (speed feedback signal or speed measurement signal) to the BMC and the PWM signal to the fan; ② BMC failure takeover type – forcibly running at full speed when the BMC is detected to be stuck; ③ Link fault detection type – detecting inconsistencies in PWM information. The core breakthrough of the CPLD chip in this invention lies in its ability to perform proactive decision-making across the entire chain, including specification determination, drive path switching, speed curve matching, and mixed access detection.

[0032] Unlike the CPLD chip in patent document CN122170081A, which identifies device type and determines output channel number based on the number of board mounting plates, the CPLD chip in this invention identifies the physical specifications of the fan (small fan / large fan) rather than the device type. Existing fan boards have a fixed number of drive channels (if designed to control 6 channels, they will always control 6 channels), requiring no switching. However, the CPLD chip in this invention faces a binary choice between 6 small fans and 4 large fans, requiring a comprehensive scan of 10 interfaces to make a judgment and physically switch the drive configuration. This represents a completely new decision-making logic.

[0033] Preferably, both the first-specification fan interface and the second-specification fan interface are universal interfaces compatible with both PWM 4-pin and PWM 8-pin interfaces. The pin definitions of each universal interface include power pin, ground pin, PWM speed control pin, and speed feedback pin. The PWM 8-pin interface type fan interface also includes dual rotor signal pins. The specification identification module determines the specification type of the connected fan by reading the fan's ID resistance value or feedback resistance value and combining it with the pin definition information of the universal interface.

[0034] The interface pin definitions are matched to the control requirements of both types of fans, and can automatically adapt according to the fan interface type of the connected fan. Taking the 8-pin female interface as an example, in its pin layout, pin 1 is the positive power supply, pin 2 is ground, pin 3 is the PWM speed control signal input, pin 4 is the speed feedback signal output, and pins 5-8 are reserved for extended signals (such as the second speed feedback for dual-rotor fans, fan presence detection, fault alarms, etc.). When a fan with a 4-pin PWM interface is inserted, the 4 pins of the fan are inserted into pins 1-4, and pins 5-8 are left floating; when a fan with an 8-pin PWM interface is inserted, all 8 pins are connected accordingly.

[0035] Preferably, the board body is further provided with a board identification module, which stores a board type identifier and a version identifier. The unified fan control unit confirms the board configuration parameters by reading the board type identifier and version identifier, and determines the supported fan specification combinations based on the board configuration parameters. The board identification module is implemented using a resistor divider network or a memory chip. The board configuration parameters can be changed by replacing different resistor values ​​or burning different identifier codes, without modifying the CPLD program. This design allows the board to be compatible with more fan specifications by changing the Board ID (board identifier or motherboard identification code), without modifying the board or CPLD.

[0036] Furthermore, there are 6 sets of the first-specification fan interfaces arranged linearly for connecting 6038 or 6060 specification fans; there are 4 sets of the second-specification fan interfaces arranged linearly for connecting 8038 or 8060 specification fans; the 6 sets of the first-specification fan interfaces and the 4 sets of the second-specification fan interfaces are staggered on the board, and the center lines of the two sets of interface areas are parallel to each other and have a preset offset distance, so that the 6 6038 / 6060 fans and the 4 8038 / 8060 fans will not interfere with each other when installed separately.

[0037] Preferably, the presence detection module is implemented using a voltage divider resistor circuit, which determines whether the fan is in position by detecting the pin level of each fan interface; for the PWM 4-pin interface, the presence status of the fan is determined by detecting the DC level of the speed feedback pin or the presence signal pin level; for the PWM 8-pin interface, the presence status of the fan is determined by detecting the level of the dedicated presence signal pin.

[0038] Preferably, the unified fan control unit has built-in speed control curve parameters and speed detection logic parameters for various fan specifications;

[0039] When switching to the first working mode, the first speed control curve is determined according to the speed control curve parameters matched with the first specification fan, and the first speed control curve is called to control the speed. At the same time, the first speed detection logic is determined according to the speed detection logic parameters matched with the first specification fan, and the first speed detection logic is called to detect the speed status.

[0040] When switching to the second working mode, the second speed control curve is determined according to the speed control curve parameters matched with the second specification fan, and the second speed control curve is called to control the speed. At the same time, the second speed detection logic is determined according to the speed detection logic parameters matched with the second specification fan, and the second speed detection logic is called to detect the speed status.

[0041] The speed regulation curve parameters include the PWM duty cycle mapping relationship corresponding to different temperature ranges, and the speed detection logic parameters include the speed pulse count threshold and the speed abnormality judgment threshold.

[0042] Preferably, the fan board further includes an overcurrent protection module, which is disposed on the board body and includes multiple overcurrent protection sub-modules. Each overcurrent protection sub-module is connected in series between the power supply circuit and the corresponding fan interface. Each overcurrent protection sub-module includes a fuse and an overcurrent detection chip, which are used to automatically cut off the power supply to the fan interface when a short circuit occurs or the current exceeds a preset threshold, and report the overcurrent status to the unified fan control unit. Each overcurrent protection sub-module works independently, and when an overcurrent occurs at any fan interface, only the power supply to that fan interface is cut off without affecting the normal operation of other fan interfaces.

[0043] The server cooling fan board, which is compatible with multiple fan specifications, achieves automatic fan specification identification and operating mode switching through a unified fan control unit. The specific mechanism is as follows:

[0044] After the fan is connected, the presence detection module detects whether each fan interface is in the presence state through the interface pins and transmits the presence signal to the unified fan control unit.

[0045] The specification identification module determines the specifications and quantity of connected fans by reading the fan's ID resistor value or feedback resistor value and combining it with the communication protocol information of the PWM 4-pin / 8-pin interface.

[0046] When M first-specification fans are detected to be connected (e.g., 6 6038 / 6060 specification fans), the unified fan control unit control board switches to the first working mode (small fan mode), starts the M-channel drive output module, and adopts the PWM speed regulation curve and speed detection logic corresponding to the first-specification fans to realize independent control and status monitoring of the M fans.

[0047] When N second-specification fans are detected to be connected (such as four 8038 / 8060 specification fans), the unified fan control unit control board switches to the second working mode (large fan mode), starts the N-channel drive output module, and adopts the PWM speed regulation curve and speed detection logic corresponding to the second-specification fans to realize independent control and status monitoring of the N fans.

[0048] If mixed access (simultaneous access of the first-specification fan and the second-specification fan) is detected, the board will automatically trigger an alarm signal and report it to the system through the BMC, indicating that the fan configuration is abnormal, thus ensuring the server's heat dissipation safety.

[0049] It is important to note that mixed access detection is a unique abnormal scenario definition proposed in this invention. Given the current technological context of single-specification fan boards (as seen in existing patent documents such as CN115718531A, CN222300018U, and CN223728206U, where fan boards are designed for a single specification), the abnormal scenario of simultaneous access for both small and large fans simply does not exist. Existing technologies only detect whether a fan is inserted, without considering the possibility of inserting an incorrectly sized fan. This invention is the first in the field of server fan boards to define the abnormal scenario of mixed access and provide a corresponding electrical detection solution.

[0050] If the number of fans of the same specification is less than the rated number but greater than zero, it is determined to be a partial access mode. The unified fan control unit still switches to the corresponding working mode, but reports a partial access alarm through the BMC and adjusts the number of drive output channels according to the actual number of fans accessed.

[0051] Secondly, this invention also provides a fan switching method for server cooling fan boards compatible with multiple fan specifications, enabling free switching between different specifications and numbers of fans without replacing the fan board. The specific steps are as follows:

[0052] Step S1: Power off the server or enter a safe shutdown state, so that the fan and the server cooling fan board compatible with multiple fan specifications are both in a power-off state; avoid damaging the equipment by operating it while it is powered on.

[0053] Step S2: Remove the first or second specification fan currently installed on the server cooling fan board compatible with multiple specifications of fans from the corresponding interface, without disassembling the fan board body.

[0054] Step S3: Based on the server's heat dissipation requirements, select to install M first-specification fans or N second-specification fans, and insert the selected fans into the corresponding first-specification fan interface or second-specification fan interface on the board body; ensure that the fans are securely installed and the interfaces make good contact;

[0055] Step S4: The server powers on and starts up, and the unified fan control unit initializes and performs a self-test;

[0056] Step S5: The unified fan control unit performs an in-situ scan of all fan interfaces by the in-situ detection module to detect whether a fan is connected to each fan interface, and records the location and number of fan interfaces with fans connected, thereby obtaining the detection results of the in-situ detection module.

[0057] Step S6: The unified fan control unit reads the ID resistance value or feedback resistance value of each connected fan through the specification identification module to identify the specification type of each connected fan.

[0058] Step S7: The unified fan control unit, based on the detection results of the in-situ detection module and the specification type identified by the specification identification module, counts the total number of connected fans and the number of fans of each specification, and performs mode determination.

[0059] If the detection result shows that M first-specification fans are connected and no second-specification fans are connected, then it is determined to be the first working mode, and step S8a is executed;

[0060] If the detection result shows that N second-specification fans are connected and no first-specification fans are connected, then it is determined to be the second working mode, and step S8b is executed;

[0061] If the test result shows that the first specification fan and the second specification fan are mixed and connected, or the number of connected fans does not match the expected number, it is determined to be a configuration abnormality and step S9 is executed;

[0062] Step S8a: Switch to the first working mode, enable the M-channel drive output module, call the first speed control curve and the first speed detection logic that match the first specification fan, and control the speed and monitor the status of each fan through the PWM signal;

[0063] Step S8b: Switch to the second working mode, enable the N-channel drive output module, call the second speed control curve and the second speed detection logic that match the second specification fan, and control the speed and monitor the status of each fan through the PWM signal;

[0064] Step S9: Trigger an alarm signal and report it to the server BMC via the communication interface, indicating that the fan configuration is abnormal and awaiting manual handling;

[0065] Step S10: During normal operation of the fan, the unified fan control unit collects the speed signal and operating status of each fan in real time, performs closed-loop speed control, and continuously monitors the fan operating status. If an abnormality is detected, a graded fault handling process is executed.

[0066] Furthermore, the method for reading the ID resistor value or feedback resistor value in step S6 includes: for fans with an 8-pin PWM interface, the fan specification is determined by reading the resistance value of the built-in ID resistor and comparing it with a preset ID resistor-specification mapping table; for fans with a 4-pin PWM interface, the fan specification is determined by sending a preset PWM test signal to the fan and measuring the fan speed feedback signal, and comparing the measured speed-duty cycle response curve with the standard response curves of fans of various specifications.

[0067] Furthermore, the mode determination in step S7 also includes:

[0068] When the number of fans of the same specification detected is less than the rated number but greater than zero, it is determined to be a partial access mode; the unified fan control unit switches to the working mode corresponding to the specifications of the accessed fans, and enables the corresponding number of drive outputs according to the actual number of accessed fans. At the same time, a partial access alarm is reported through the BMC (the partial access alarm is a prompt alarm, used to inform the BMC that the actual number of fans of the same specification in the current fan interface is less than the rated number but greater than zero).

[0069] When a fan interface is detected to be empty and the configuration information issued by the BMC requires that the fan interface should have a fan, a missing alarm is reported through the BMC (the missing alarm is used to inform the BMC that a certain fan interface is currently empty but the system configuration requires that the interface should have a fan).

[0070] The BMC defines the following configuration information: The BMC stores standard fan configuration information for the server. This information specifies the fan specifications that should be installed on each fan interface. The BMC communicates with these fan interfaces via I / O.2 The C interface sends configuration information to the unified fan control unit.

[0071] Preferably, the closed-loop speed control in step S10 includes: the unified fan control unit collects the actual speed signal of each fan in real time through the PWM interface, compares the actual speed with the target speed, and calculates the speed deviation value; based on the speed deviation value, the PWM output duty cycle is dynamically adjusted using a PID control algorithm or a fuzzy control algorithm to make the actual speed approach the target speed; the target speed is determined by the BMC based on the speed adjustment command issued by the server temperature sensor data, or by the unified fan control unit autonomously based on the detection results of the onboard temperature sensor.

[0072] This invention achieves integrated closed-loop control encompassing monitoring, identification, configuration, and speed adjustment, unlike existing BMC scheduling schemes where the monitoring-decision-control link requires passing through the BMC (resulting in polling delays of hundreds of milliseconds to several seconds). This integrated closed-loop system achieves microsecond / millisecond-level rapid response, substantially contributing to the stability and temperature control accuracy of server cooling systems.

[0073] Furthermore, the speed closed-loop control in step S10 also includes:

[0074] The unified fan control unit uses an ADC (analog-to-digital converter) module to detect the power supply voltage of each fan interface in real time and converts the analog voltage value into a digital value; different voltage thresholds and detection accuracies are set for different power rails;

[0075] The unified fan control unit detects the voltage drop by connecting a precision resistor in series in the power supply circuit of each fan interface, and calculates the actual operating current of each fan after ADC conversion, thereby realizing independent current monitoring of each fan interface.

[0076] The unified fan control unit continuously stores the real-time detected voltage and current values ​​in its internal register and compares them with preset voltage and current thresholds.

[0077] When the voltage or current value exceeds the preset threshold, the corresponding protection logic is triggered; if the abnormal state cannot be recovered, the power supply to the fan interface is cut off.

[0078] Furthermore, during the self-test process in step S4, the unified fan control unit also detects the power supply circuit, overcurrent protection module, and communication interface. If an abnormality is detected in the power supply circuit, it attempts to switch to the redundant power supply branch and reports a power abnormality alarm. If an overcurrent protection module is detected to be triggered, it cuts off the power supply to the corresponding interface and reports an overcurrent alarm. If an abnormality is detected in the communication interface, it switches to independent operation mode, and the unified fan control unit independently controls the fan speed based on the onboard temperature sensor.

[0079] Furthermore, the fan switching method for the server cooling fan board compatible with multiple fan specifications also includes a fan hot-swap switching step: during server operation, when it is detected that an existing fan has been unplugged and a new fan has been plugged in, the unified fan control unit re-executes the process from step S5 to step S8 to achieve online fan specification switching; during the fan hot-swap switching process, the unified fan control unit keeps other running fans working normally and only re-detects and reconfigures the newly connected fan interface.

[0080] Furthermore, the method for detecting an anomaly and executing the graded fault handling process in step S10 includes:

[0081] The unified fan control unit integrates in-situ detection signals, power supply status detection signals, speed feedback signals, and current detection signals to form a comprehensive detection result;

[0082] Status assessment based on comprehensive test results:

[0083] When the system is determined to be in a normal state, it accepts the PWM / speed command issued by the BMC, outputs the drive level / PWM wave, maintains the normal operation of the fan, and reports the normal state to the BMC.

[0084] When an abnormal state is identified, the fault type is distinguished:

[0085] If the fault is a power supply abnormality, the corresponding fan drive will be cut off and a power alarm will be triggered.

[0086] If the fault is a short circuit or overcurrent, an emergency shutdown driver will be executed and hardware protection will be triggered.

[0087] If the fault is low speed or stall, increase the PWM duty cycle and try again. If the retry is successful, normal operation will be restored. If the retry fails, proceed to fault handling.

[0088] If the fault is a disconnection or absence, the corresponding fan driver will be shut down and an offline alarm will be triggered.

[0089] The power supply status detection signal is obtained by detecting the power supply voltage of each fan interface through ADC analog-to-digital conversion; the current detection signal is obtained by detecting the voltage drop through a precision resistor connected in series in the power supply circuit of each fan interface and then calculating it through ADC conversion, thereby realizing independent current monitoring of each fan interface.

[0090] When the speed deviation is too low or the speed deviation of a stall fault is within the preset first threshold range, the unified fan control unit executes a speed regulation strategy that increases the PWM duty cycle; when the speed deviation is within the preset second threshold range, it executes a speed regulation strategy that decreases the PWM duty cycle.

[0091] For disconnection or absence-related faults, the unified fan control unit first performs a retry drive operation. If the fan resumes operation after the retry, the system returns to normal and reports to the BMC. If the fan still fails to resume operation after the retry, the corresponding fan drive is shut down and an offline alarm is triggered. At the same time, the speed of other normally operating fans is adjusted according to the server's heat dissipation requirements to compensate for the lack of heat dissipation capacity.

[0092] After the fault is resolved, the fault code is latched and the fault indicator light is illuminated. The unified fan control unit stops the output of the corresponding channel and enters standby mode, while all fault information is reported to the BMC.

[0093] After the fault is handled, the severity of the fault is judged: if the fault has been resolved or can be recovered, the fault status is cleared, normal operation is restored and testing continues; if the fault is a serious fault and cannot be recovered, the fault code is latched and the fault indicator light is lit, the corresponding channel output is stopped and the system enters standby mode, and the fault information is reported to the BMC.

[0094] Preferably, after the fault handling is completed, the process also includes a status reporting and standby determination step:

[0095] The unified fan control unit decides whether to continue inspection and operation or shut down and standby based on the severity of the fault:

[0096] When the fault has been resolved or can be recovered, the unified fan control unit clears the fault status, resumes normal operation, and continues to perform fan hardware status information detection, forming a closed-loop monitoring;

[0097] When the fault is a serious and unrecoverable fault, the unified fan control unit latches the fault code, illuminates the corresponding fault indicator light, stops the output of the corresponding fan channel and enters standby mode, and at the same time reports all fault information to the BMC, which records the system log.

[0098] The serious faults include abnormal power supply, short circuit / overcurrent, open circuit / no position, and low speed / blocked transition faults that cannot be recovered after retrying.

[0099] Thirdly, the present invention also provides a server heat dissipation system, comprising:

[0100] Server chassis;

[0101] The server motherboard is located inside the server chassis and contains the BMC;

[0102] The server cooling fan board compatible with multiple fan specifications is installed inside the server chassis, independent of the server motherboard, and electrically connected to the server motherboard and / or chassis backplane via a connector.

[0103] The unified fan control unit communicates with the BMC via a communication interface to report fan configuration information, speed information, operating status information and alarm information to the BMC, and to receive speed control commands issued by the BMC.

[0104] The BMC generates speed control commands based on temperature data from various temperature sensors on the server and sends them to the unified fan control unit. When the BMC malfunctions or communication is interrupted, the unified fan control unit switches to independent operation mode and autonomously controls the fan speed based on the detection results of the onboard temperature sensors.

[0105] The independent operation mode refers to a state where, when the BMC malfunctions or communication is interrupted, the unified fan control unit no longer relies on the speed control commands issued by the BMC, but instead autonomously calculates the target speed and outputs a PWM control signal based on the detection results of the onboard temperature sensor. In independent operation mode, the CPLD chip independently completes the entire control chain of temperature acquisition, speed decision, and PWM output.

[0106] Furthermore, the server chassis is equipped with multiple temperature sensors distributed in the heat-generating areas of the server motherboard, CPU, memory, and hard drive. Each temperature sensor is electrically connected to the BMC. Based on the temperature data from each temperature sensor and a preset temperature-speed mapping table, the BMC calculates the target speed of each fan and sends it to the unified fan control unit. The temperature-speed mapping table dynamically selects the corresponding mapping relationship according to the specifications of the currently connected fan.

[0107] The BMC has a pre-set temperature-speed mapping table, which is a dataset of the correspondence between temperature values ​​and target speed values; the temperature-speed mapping table includes a first temperature-speed mapping table corresponding to a first specification fan and a second temperature-speed mapping table corresponding to a second specification fan.

[0108] Based on the temperature data from each temperature sensor and the specifications of the currently connected fans reported by the unified fan control unit, the BMC selects the temperature-speed mapping table corresponding to the specifications (if it is a first specification fan, the first temperature-speed mapping table is selected; if it is a second specification fan, the second temperature-speed mapping table is selected), calculates the target speed of each fan, and sends it to the unified fan control unit.

[0109] The server cooling fan board and fan switching method compatible with multiple fan specifications provided by this invention can be widely used in various servers, storage devices, and other electronic devices that require fan cooling. This invention integrates the interfaces of multiple fan specifications onto the same board, and with the automatic identification and switching control of the CPLD chip, it achieves flexible switching of fan configurations and a universal design for the board, resulting in significant economic benefits and practical value, making it suitable for large-scale industrial application.

[0110] The beneficial effects of this invention are:

[0111] 1) This invention integrates two or more independent fan boards into a single type of fan board, reducing the design, verification, production and inventory costs of the board, while also reducing the types of materials, which facilitates large-scale production and material management.

[0112] 2) The same board of this invention supports multiple fan specifications simultaneously (such as 6 6038 / 6060 fans or 4 8038 / 8060 fans), and all are compatible with PWM 4-pin / 8-pin interfaces. It can be freely configured according to server power consumption and heat dissipation requirements, offering wide compatibility. Through the configuration of the board's identification module, it can be expanded to more specifications such as 8 small fans or 6 large fans. The unique control of the CPLD code can be compatible with more and more sophisticated systems.

[0113] 3) When switching fan specifications, this invention only requires replacing the fan body, without disassembling the fan board module, which simplifies the operation process, reduces the difficulty of assembly and maintenance, shortens the maintenance and assembly time, and improves the efficiency of server maintenance.

[0114] 4) By integrating overcurrent protection module, in-situ detection module, specification identification module, etc., this invention can automatically identify fan configuration, switch working modes, monitor fan operating status in real time, and trigger alarms in a timely manner to ensure server heat dissipation safety and stable operation.

[0115] 5) The CPLD chip of the present invention transforms from a traditional passive executor into an active decision-making center, completing the entire chain of active decision-making, including specification determination, drive path switching, speed regulation curve matching, and hybrid access detection, achieving a fast response at the microsecond / millisecond level, which is superior to the second-level response of the traditional BMC scheduling scheme.

[0116] 6) This invention defines the abnormal scenario of mixed access for the first time in the field of server fan boards: when large and small fans are connected simultaneously, due to the differences in their heat dissipation capacity (airflow) and airflow characteristics, it may lead to turbulent airflow inside the server, insufficient heat dissipation in local areas, or even overheating and damage. The mixed access detection mechanism of this invention replaces the traditional mechanical foolproof structure with an electrical method. On the one hand, it simplifies the design complexity of connectors, and on the other hand, it can realize more flexible alarms and responses at the system level (such as reporting through BMC, logging, etc.), which is an effect that mechanical foolproofing cannot achieve.

[0117] 7) The monitoring process of this invention realizes the differentiation and graded processing of various fault types such as power supply abnormality, short circuit / overcurrent, low speed / locked rotor, disconnection / no position, and executes differentiated protection strategies (retry, power failure, alarm, standby) for different fault types, and latches fault codes and illuminates fault indicator lights, forming a complete system protection mechanism, which further improves the reliability and maintainability of the server heat dissipation system.

[0118] 8) This invention achieves universal compatibility of fans of various specifications through a unified board structure design, which facilitates the standardized design and large-scale deployment of servers and improves production line and assembly efficiency. Attached Figure Description

[0119] Figure 1 A schematic diagram of the assembly state of the circuit board body of the present invention when six small fans are installed;

[0120] Figure 2 This is a schematic diagram of the assembly state of the circuit board body of the present invention when four large fans are installed.

[0121] Figure 3 This is a flowchart of the main loop control of the server cooling fan board compatible with multiple fan specifications as described in this invention;

[0122] Figure 4 This is a flowchart illustrating the monitoring and hierarchical fault handling process for the server cooling fan board compatible with multiple fan specifications as described in this invention. Detailed Implementation

[0123] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0124] Definitions of abbreviations and key terms:

[0125] PCB: Printed Circuit Board.

[0126] PWM: Pulse Width Modulation is a digital encoding method for analog signal levels that controls average power or achieves other control objectives by changing the pulse width (duty cycle).

[0127] 4 / 8 pin: Short for 4-pin or 8-pin fan interface, which are two mainstream PWM fan interfaces.

[0128] CPLD: Complex Programmable Logic Device.

[0129] I2 C: Inter-Integrated Circuit, the interconnect bus for integrated circuits.

[0130] BMC: Baseboard Management Controller; a commonly used remote management chip for servers.

[0131] SGPIO: Serial General Purpose Input / Output, is a protocol used for serial communication.

[0132] ID: Identification or identifier.

[0133] N-channel MOSFET: refers to a MOSFET whose conductive channel is an N-type semiconductor; MOSFET: metal-oxide-semiconductor field-effect transistor; N-type semiconductor refers to a semiconductor material in which pentavalent impurity elements are doped into intrinsic semiconductors, making the electron concentration much greater than the hole concentration, and its conduction mainly relies on electrons as charge carriers.

[0134] PID stands for Proportional-Integral-Derivative. It is a widely used feedback control algorithm in industrial control, automation, and electronic systems.

[0135] CPU: Central Processing Unit.

[0136] Comprehensive test results: refers to the comprehensive judgment criteria formed by the CPLD chip after integrating multi-dimensional information such as in-situ detection signals, power supply status detection signals, speed feedback signals and current detection signals, which are used to determine the working status of the fan.

[0137] Example 1

[0138] The server cooling fan board compatible with multiple fan sizes in this embodiment includes the following components:

[0139] The board itself adopts a multi-layer PCB design, and its overall size is compatible with standard server chassis, operating independently of the server motherboard. Connectors are provided on the board for electrical connection and signal transmission with the backplane and / or motherboard of the standard server chassis.

[0140] The composite fan interface area is located on one side of the board body, including 6 sets of first-specification fan interfaces and 4 sets of second-specification fan interfaces. The 6 sets of first-specification fan interfaces are arranged linearly for connecting 6038 / 6060 fans; the 4 sets of second-specification fan interfaces are arranged linearly for connecting 8038 / 8060 fans. The first-specification and second-specification fan interfaces are staggered, and the spacing between the first-specification and second-specification fan interfaces is designed according to the size of the two fan sizes to ensure that they do not interfere with each other during installation. The 6 sets of first-specification fan interfaces and 4 sets of second-specification fan interfaces are staggered on the board body, and the center lines of the areas where the first-specification fan interfaces are located are parallel to each other and have a preset offset distance.

[0141] In this example, for a clearer distinction, we define the first specification fan as the small fan, and the first specification fan interface corresponds to the small fan interface; the second specification fan is the large fan, and the second specification fan interface corresponds to the large fan interface.

[0142] Both the first-specification fan interface and the second-specification fan interface are universal interfaces compatible with PWM 4-pin and 8-pin interfaces. The pin definitions include power pin, ground pin, PWM speed control pin, and speed feedback pin (the 8-pin interface additionally includes dual rotor signal pins).

[0143] The control and drive circuitry is located on the main board and integrates a unified fan control unit (CPLD chip), power supply circuit, presence detection module, specification identification module, and drive output module. The CPLD chip, as the unified fan control unit, is responsible for fan presence detection, specification identification, mode switching, speed control, and signal reporting. The CPLD chip integrates a PWM output interface and an 8-pin communication interface, allowing it to adapt to both first-specification and second-specification fan interfaces.

[0144] The power supply circuit adopts a shared power supply design to convert the server's standard 12V power supply voltage into the operating voltage required by the fan. The power supply circuit includes a power input interface, a main power supply branch, and a redundant power supply branch. The main power supply branch includes a power conversion chip, filter capacitors, and a voltage regulator circuit, used to convert the 12V input into the operating voltage required by the fan and output it to the fan power supply bus. The redundant power supply branch is connected in parallel with the main power supply branch, and both are connected to the fan power supply bus via a diode OR logic circuit. The output terminals of the main power supply branch and the redundant power supply branch are each connected to a common power supply node through an isolation diode. During normal operation, the main power supply branch outputs a normal voltage, and its corresponding isolation diode is turned on, supplying power to the fan. The output voltage of the redundant power supply branch is slightly lower than that of the main power supply branch, and its corresponding isolation diode is in the off state. When the output voltage of the main power supply branch is lower than that of the redundant power supply branch due to a power conversion chip failure, a voltage regulator circuit malfunction, or a power outage, the corresponding isolation diode of the redundant power supply branch automatically turns on, taking over the fan power supply from the main power supply branch. The switching time is in the microsecond range, and the fan power supply is uninterrupted. Whether you connect 6 small fans or 4 large fans, you can get a stable power supply through the same power circuit.

[0145] In some other embodiments, the power supply circuit integrates an ADC module, which uses ADC conversion to detect the voltage values ​​of each power supply in real time, converting analog power supply voltages into digital values, and setting different voltage thresholds and detection accuracies for different power rails. Simultaneously, an external precision resistor connected in series in the power supply circuit of each fan interface is used to detect the voltage drop across the precision resistor, and the actual operating current of each fan is calculated after ADC conversion. These voltage and current values ​​are uploaded in real time to the internal register of the CPLD chip, enabling independent monitoring of the power supply status of each fan interface. When the detected current value exceeds a preset threshold, overcurrent protection logic is triggered, executing the corresponding protection action of the overcurrent protection module; if the overcurrent state cannot be recovered, an attempt is made to shut down the power supply to that fan interface.

[0146] The presence detection module is implemented using a voltage divider resistor circuit to detect whether a fan is connected to each fan interface. Specifically, the presence detection pin of each fan interface is connected to a reference voltage (e.g., 3.3V) through a pull-up resistor. The fan has an internal presence identification circuit. When the fan connector plug is physically connected to the fan interface female on the board (i.e., the fan is inserted into the fan interface), the corresponding pin inside the fan is pulled low to a low level or directly grounded, causing the voltage of the presence detection pin to be pulled low from a high level. When no fan is connected to the fan interface, the presence detection pin is kept high through the pull-up resistor.

[0147] The CPLD chip determines whether a fan interface is in the fan-in-place state (i.e., the fan is physically inserted and the electrical connection is normal) by reading the voltage level of the presence detection pins of each fan interface. Specifically, for a 4-pin PWM interface, the CPLD chip determines the fan-in-place state by detecting the DC level of the speed feedback pin or the level of the dedicated presence signal pin; for an 8-pin PWM interface, the CPLD chip determines the fan-in-place state by detecting the level of the dedicated presence signal pin.

[0148] The specification identification module is used to read the specification identification signal of the connected fan (i.e., the signal used to identify the fan specification type, including ID resistor value or speed feedback signal, etc.) to determine the specification type and interface type of the connected fan. For fans with an 8-pin PWM interface, the fan has a built-in ID identification resistor connected to a specific pin of the interface. The specification identification module reads the resistance value of the ID resistor through this specific pin and compares this resistance value with a preset ID resistor-specification mapping table (essentially a lookup table, a key database used by the CPLD chip to "decode" the fan's identity, essentially a dataset of correspondences between ID resistor values ​​and fan specifications) to determine the fan specification. For fans with a 4-pin PWM interface, since there is no pin corresponding to the ID identification resistor, the specification identification module indirectly determines the specification through the following methods:

[0149] The CPLD chip sends a preset test PWM signal to the fan, and at the same time measures the fan speed feedback signal through the speed feedback pin. The measured speed-duty cycle response curve is compared with the preset standard response curves of various fan specifications to determine the fan specification.

[0150] The measured speed-duty cycle response curve refers to the characteristic curve formed by the unified fan control unit sending a set of preset PWM test signals with different duty cycles to the fan under test during the specification identification process, and measuring the actual speed value fed back by the fan under each duty cycle. The curve is plotted or fitted by the above-mentioned paired duty cycle-speed data points.

[0151] The standard response curves for fans of various specifications refer to the standard duty cycle-speed response characteristic data for different specifications of fans (such as 6038 / 6060 specification fans, 8038 / 8060 specification fans, etc.) that are pre-installed in a unified fan control unit. Each specification of fan corresponds to a standard curve, which serves as a comparison benchmark for specification identification.

[0152] The combination of these two identification methods allows the same fan interface to adapt to fans with different pin counts and specifications.

[0153] This invention employs a static identification path (reading the ID to identify the resistor / speed feedback signal), which differs from the dynamic testing path in existing technologies (identifying by measuring the speed under two duty cycles). It eliminates the need for two tests, resulting in faster and more reliable response, and less disturbance to the system. This identification method is a specialized solution designed specifically for the hardware characteristics of this invention (multiple interfaces coexist).

[0154] The drive output module is mounted on the board body and electrically connected to the unified fan control unit and each fan interface. The drive output module provides drive output to each fan interface based on the control signals from the CPLD chip. The drive output module includes multiple independent drive channels corresponding to each fan interface (in this embodiment, there are 10 drive channels, i.e., one drive channel for each of the 6 first-specification fan interfaces and 4 second-specification fan interfaces). Each drive channel includes a drive transistor (preferably an N-channel MOSFET, connected in the power supply circuit of the corresponding fan interface as a low-side switch) and a corresponding drive control circuit.

[0155] The CPLD chip determines the current operating mode based on the identification results: if it identifies six 6038 / 6060 specification fans (small fans), it is determined to be in small fan mode; if it identifies four 8038 / 8060 specification fans (large fans), it is determined to be in large fan mode. The CPLD chip sends channel enable signals to the drive output module based on the current operating mode: in small fan mode, it enables six drive channels corresponding to the six first-specification fan interfaces; in large fan mode, it enables four drive channels corresponding to the four second-specification fan interfaces; and the inactive drive channels remain off.

[0156] After the corresponding drive channel is activated, the drive output module receives the PWM speed control signal (i.e., pulse width modulation signal) sent by the CPLD chip. The drive control circuit controls the conduction and cutoff of the drive transistor according to the duty cycle of the PWM speed control signal. By controlling the high-speed switching action of the drive transistor, the average current flowing through the fan is controlled, thereby achieving precise adjustment of the fan speed. Since the drive control circuits of each drive channel are independent of each other, and each drive transistor is connected in series in the power supply circuit of its corresponding fan interface, the change of the conduction / cutoff state of any drive channel will not affect the output of other drive channels, realizing independent speed control of each fan.

[0157] In some other embodiments, after the drive output module outputs a PWM speed control signal to the fan, the CPLD chip acquires the fan speed feedback signal (TACH signal) in real time through the speed feedback pins of each fan interface. The system uses a fan speed sampling circuit to convert the sampled speed pulse signal into a duty cycle value. The CPLD chip compares the duty cycle of the currently output PWM speed control signal with the measured speed feedback signal using an algorithm to calculate the speed deviation value and deviation rate, and obtain abnormal parameters (including speed deviation percentage, deviation duration, etc.). These abnormal parameters serve as the basis for status judgment and are used for subsequent normal / abnormal branch processing and graded fault determination.

[0158] The overcurrent protection module is located on the main board and includes 10 overcurrent protection sub-modules corresponding to 6 sets of first-specification fan interfaces and 4 sets of second-specification fan interfaces. Each overcurrent protection sub-module is connected in series between the power supply circuit and the corresponding fan interface (either a first-specification fan interface or a second-specification fan interface). Each overcurrent protection sub-module contains a fuse and an overcurrent detection chip. When a short circuit occurs at a fan interface or the current exceeds a preset threshold, the corresponding overcurrent detection chip triggers the protection action, blowing the fuse of that fan interface or cutting off the power supply to that fan interface through an electronic switch, and simultaneously reporting the overcurrent status through the unified fan control unit. Because each overcurrent protection sub-module is independent of each other, an overcurrent fault in one fan interface will not affect the normal power supply and operation of other fan interfaces.

[0159] The communication interface is located on the board itself, and is accessed via I... 2 The C interface connects to the server BMC and is used to report information such as fan configuration, speed, and operating status to the BMC, while also receiving speed control commands issued by the BMC.

[0160] The board itself also features a board identification module, which stores the board type and version identifiers. The CPLD chip reads the information from the board identification module to confirm the board configuration parameters and determines the supported fan specifications based on these parameters. The board identification module is implemented using a resistor divider network; by changing different resistor values, the board configuration parameters can be altered without modifying the CPLD program.

[0161] Example 2

[0162] like Figure 1 As shown, when installing 6 6038 / 6060 specification fans (small fans); Figure 1When the board uses "60 fan" to represent the small fans, each small fan is inserted into the first-specification fan interface (corresponding to numbers 60F1, 60F2, 60F3, 60F4, 60F5, 60F6), while the second-specification fan interfaces (corresponding to numbers 80FAN1, 80FAN2, 80FAN3, 80FAN4) are left unused. At this time, the board is in small fan mode, configured with 6 fans.

[0163] like Figure 2 As shown, when installing four 8038 / 8060 specification fans (large fans); Figure 2 When the "80 fan" designation is used to represent the large fan, all large fans are inserted into the second-specification fan connectors (corresponding to numbers 80FAN1, 80FAN2, 80FAN3, and 80FAN4), while the first-specification fan connectors (corresponding to numbers 60F1, 60F2, 60F3, 60F4, 60F5, and 60F6) remain unused. At this time, the board is in large fan mode, configured with four fans.

[0164] In both installation states, the fan maintains stable contact with the corresponding fan interface, and fans of different specifications do not interfere with each other.

[0165] in, Figure 1 and Figure 2 The “connector” refers to the fan interface, which is a physical connector soldered onto the board body; “overcurrent protection” refers to the overcurrent protection module; and “CPLD” refers to the CPLD chip.

[0166] Example 3

[0167] like Figure 3 As shown, the main loop control flow of the server cooling fan board compatible with multiple fan specifications described in this invention is as follows:

[0168] After the system starts up, the server is powered on, and the CPLD chip is reset, the CPLD chip first initializes each functional module.

[0169] After entering the main loop, the CPLD chip performs polling. During the polling process, the CPLD chip performs multiple hardware checks simultaneously, including: board ID reading, power supply and individual fan overcurrent detection, full interface fan presence scan, fan specification identification, and BMC communication link self-test. At the same time, it collects data from the onboard temperature sensor to provide a basis for subsequent speed control.

[0170] During the CPLD polling process, the in-situ detection module scans each fan interface to check for the presence of a fan (i.e., the fan's in-situ status). Simultaneously, the specification identification module reads the specification information of each connected fan (i.e., the fan's type, such as a 6038 / 6060 or 8038 / 8060 fan). This in-situ and specification information together constitute the fan hardware status information, which the CPLD chip uses to obtain the detection results for each fan interface.

[0171] The CPLD chip determines its status based on the detection results:

[0172] If the status is normal, i.e., the detection result shows that M first-specification fans (small fans) are connected and no second-specification fans are connected, or N second-specification fans (large fans) are connected and no first-specification fans are connected, then it is determined to be a normal working state. The CPLD chip calls the corresponding speed control curve according to the current working mode (small fan mode or large fan mode), executes standard temperature control speed control output, and outputs PWM speed control signal to control the fan operation.

[0173] Among them, the standard temperature-controlled speed output is achieved by the CPLD chip identifying a compliant single fan configuration, calling the corresponding specification-specific speed control curve, and dynamically adjusting the PWM duty cycle based on the overall machine temperature data through a PID algorithm to achieve a conventional fan drive output that ensures long-term stable and constant temperature for the server.

[0174] If the status is abnormal / faulty, a fault protection output will be executed. The fault protection output here refers to the complete set of protective control actions executed by the CPLD chip when it detects abnormal states such as mixed fan connection (large and small fans connected simultaneously), mismatched number of fans (including partial connection of a single-specification fan and no fan connection at all fan interfaces), abnormal power supply / short circuit / locked rotor / open wire, etc. This differs from standard temperature-controlled speed regulation that matches a dedicated speed control curve under normal operating conditions. It is only triggered when the status is determined to be an abnormal branch, and specifically includes two types of execution logic:

[0175] 1) Recoverable fault scenarios: In the case of recoverable faults such as low speed, slight stall, or only part of a single type of fan being connected, increase the PWM duty cycle to retry at full speed, and adjust the speed of the remaining normally operating fans to compensate for the lack of heat dissipation capacity;

[0176] 2) Unrecoverable severe fault scenarios: Under severe faults such as overcurrent, short circuit, absence of position, and mixed access, the corresponding channel drive output is cut off, the BMC fault alarm is reported, the fault code is latched, and the fault indicator light is lit.

[0177] If the detection result is mixed access, mismatch in the number of accesses, or other abnormal normal configuration, it is judged as an abnormal state. The CPLD chip further distinguishes the specific fault type (including power supply abnormality, short circuit / overcurrent, low speed / locked rotor, open circuit / no position, etc., see Example 4 below for details), and executes the corresponding processing strategy according to the fault type, and also outputs the corresponding PWM speed control signal (such as full speed operation, stop output or retry, etc., depending on the fault type).

[0178] Normal and abnormal state branch processing logic: The CPLD chip judges the state based on the comprehensive detection results. The entire logic is divided into two major branches: normal operation and abnormal fault processing.

[0179] If the abnormal parameters meet the normal operating threshold range (such as speed deviation within ±5% and current within the rated range), the normal judgment and operation logic will be executed to maintain the current PWM speed control output, and the fan will continue to operate normally.

[0180] If the abnormal parameter reaches the abnormal level, a differentiated speed adjustment strategy will be implemented according to the degree of deviation of the parameter: when the abnormal parameter shows that the speed is slightly low (such as the deviation is between 5% and 15%), the PWM duty cycle will be increased appropriately to increase the speed; when the abnormal parameter shows that the speed is high, the PWM duty cycle will be decreased appropriately to reduce the speed, so that the fan speed approaches the target value.

[0181] Regardless of whether the status is normal or abnormal, the CPLD chip will transmit real-time status information (including the presence status, specifications, current speed, operating mode, and fault codes of each fan interface) through the communication interface (I... 2 The C interface feeds back to the BMC and loops back to the CPLD chip polling step, re-judging the status based on the latest result to achieve closed-loop monitoring.

[0182] The core feature of this main loop process is that the CPLD chip does not simply transmit the detection results to the BMC, but actively completes the complete closed-loop link of detection, judgment, control and feedback. The status judgment link includes a variety of specific judgment logics such as fan specification identification (a binary decision between 6 small fans and 4 large fans), mixed access detection, and quantity matching, rather than a general normal / abnormal binary judgment.

[0183] Example 4

[0184] Regarding the method for distinguishing specific fault types in Example 3, such as Figure 4 As shown, the monitoring and hierarchical fault handling process for the server cooling fan board compatible with multiple fan specifications of this invention is as follows:

[0185] The system starts up and performs fan hardware status information detection. The CPLD chip continuously scans and identifies the specifications of each fan interface, acquiring the fan's presence status and specification information (i.e., the fan hardware status information described in Example 3). Simultaneously, it integrates multi-dimensional information such as presence detection signals, power supply status detection signals, speed feedback signals, and current detection signals to form a comprehensive detection result. All the multi-source hardware signals corresponding to the above comprehensive detection result are... Figure 3 The hardware signals collected by the CPLD chip, including those related to position, power supply, overcurrent, and speed, are the same set of detection data. Figure 3 Main loop process and Figure 4 The fault classification process uses the same underlying hardware data acquisition data source.

[0186] Status assessment based on comprehensive test results:

[0187] 1) Normal state (no fault):

[0188] The CPLD chip receives PWM / speed commands from the BMC, outputs drive levels / PWM waves according to the speed control curve of the current operating mode to maintain normal fan operation, and reports normal status information (including the presence status, specifications, current speed, and operating mode of each fan interface) to the BMC. It then returns to the beginning of the process to restart fan hardware status information detection, forming a closed-loop monitoring system.

[0189] 2) Abnormal state (fault exists):

[0190] CPLD chips differentiate between fault types, specifically including the following fault types and their corresponding handling strategies:

[0191] Fault Type 1 – Power Supply Abnormality: When a deviation of the fan power supply voltage from the normal range is detected (such as excessively low voltage, excessive voltage fluctuations, or no voltage output), it is determined to be a power supply abnormality. The CPLD chip immediately cuts off the drive output of the corresponding fan and triggers a power alarm to be reported to the BMC.

[0192] Fault Type 2 – Short Circuit / Overcurrent: When the overcurrent protection module detects that the fan current exceeds the preset threshold, it determines it as a short circuit / overcurrent fault. The CPLD chip performs an emergency shutdown operation and triggers hardware protection mechanisms (such as latching the overcurrent state and preventing the fan interface from being powered on again) to prevent the fault from escalating and damaging the board.

[0193] Fault Type 3 – Low Fan Speed / Stalled: When the actual fan speed is detected to be consistently lower than a preset percentage of the target speed (e.g., lower than 70% of the target speed for more than 3 seconds) or the speed feedback signal disappears, it is determined to be low fan speed or stalled. The CPLD chip first attempts to increase the PWM duty cycle to 100% for a retry. If the speed returns to normal, operation continues; if the speed still cannot be restored after the retry, the following post-fault handling procedure is initiated.

[0194] Fault Type 4 – Disconnection / No Fan in Position: When the fan in position detection module detects no in position signal at the fan interface, but the system expects a fan to be present at that location, it is determined to be a disconnection or no fan in position fault. The CPLD chip shuts down the corresponding fan drive output and triggers an offline alarm to be reported to the BMC.

[0195] Of the four fault types mentioned above, after fault types 1, 2, and 4 are determined and confirmed, the CPLD chip executes the corresponding protection action (cuts off the drive, shuts off the output, or shuts down in an emergency), and then enters the post-fault processing flow.

[0196] For fault type 3, the CPLD chip first attempts to restore the PWM duty cycle to 100% by retrying. If the retry is successful, it maintains normal operation and reports the restored normal state. If the retry fails, it proceeds to the post-fault processing flow.

[0197] Post-fault handling procedures:

[0198] The CPLD chip makes the final determination of the fault type:

[0199] 1) If the fault has been resolved or can be recovered (e.g., the low speed / blocked turnaround fault is restored to normal after retry), the CPLD chip clears the fault state, resumes normal operation, and returns to the process start point to continue to perform fan hardware status information detection, thereby realizing closed-loop monitoring.

[0200] 2) If the fault is severe and unrecoverable (such as abnormal power supply, short circuit / overcurrent, open wire / no position, or low speed / blocked fan failure that cannot be recovered after retry), the CPLD chip latches the fault code (for subsequent fault tracing), illuminates the corresponding fault indicator light (for on-site maintenance personnel to quickly locate the faulty fan), stops the output of the corresponding fan channel, and enters standby mode, awaiting manual intervention. Simultaneously, all fault information is reported to the BMC via the communication interface, and the BMC records it in the system log.

[0201] Status Reporting and Standby Determination: The CPLD chip determines whether to continue continuous inspection or shut down for standby based on the severity of the fault. For recovered faults or minor anomalies, the CPLD chip clears the fault status, maintains normal fan operation, and continuously performs fan hardware status information detection, forming a closed-loop monitoring system. For severe and unrecoverable faults, the CPLD chip latches the fault code, illuminates the fault indicator light, stops the output of the corresponding fan channel, and enters standby mode. Simultaneously, it reports all fault information to the BMC, which records the system log. The specific logic for determining whether to continue continuous inspection or shut down for standby based on fault severity is as follows: When fault types 1, 2, and 4 (power supply abnormality, short circuit / overcurrent, open wire / no position) cannot be recovered after retry or protection action, they are determined to be severe faults, and shutdown for standby is executed. When fault type 3 (low speed / locked rotor) is successfully retried by increasing the PWM duty cycle, it is determined to be recovered, and continuous inspection is executed. If fault type 3 still cannot be recovered after retry, it is determined to be a severe fault, and shutdown for standby is executed.

[0202] The core feature of this graded fault handling process is:

[0203] ① The CPLD chip has multi-dimensional comprehensive detection capabilities, and can simultaneously detect multiple parameters such as presence signal, power supply status, speed feedback, and current, rather than simply detecting whether the fan is rotating.

[0204] ② The CPLD chip has the ability to distinguish fault types. It can accurately distinguish four different fault types: abnormal power supply, short circuit / overcurrent, low speed / stalled rotor, and open circuit / no position, rather than reporting a general fan fault.

[0205] ③ The CPLD chip has hierarchical processing capabilities and executes differentiated protection strategies for different fault types. For recoverable faults (low speed / locked rotor), it first attempts to retry recovery, while for unrecoverable serious faults (short circuit / overcurrent), it directly executes emergency shutdown, which reflects intelligent fault management.

[0206] ④ The CPLD chip has the ability to persist fault information. By latching fault codes and illuminating indicator lights, it provides on-site maintenance personnel with an intuitive means of fault location, thereby improving the maintainability of the system.

[0207] Example 5

[0208] This example demonstrates how to switch fans. Specifically, it shows how to switch from six 6038 fans (small fans) to four 8038 fans (large fans). The specific steps are as follows:

[0209] Preparation before operation: Ensure the server is properly shut down and the power is disconnected. After the fan has completely stopped spinning, open the side panel of the server chassis to expose the fan board.

[0210] To remove the existing small fans: Hold the housings of the six 6038 fans and pull them vertically upwards to separate them from the first-specification fan connectors (60F1~60F6) on the board. Remove the 6038 fans and store them properly. There is no need to disassemble the fan board itself.

[0211] Install the large fans: Align the four 8038 standard fans with the second standard fan interface (80FAN1~80FAN4) on the board, insert them vertically downwards, and ensure that the fan interface is in full contact with the board interface. The fans are installed firmly and without any looseness.

[0212] Power-on verification: Close the server chassis side panel, connect the power supply, and start the server. The CPLD chip on the fan board automatically completes self-test, in-situ scanning, and specification identification.

[0213] Mode switching: After the CPLD chip detects the connection of four 8038 specification fans, it automatically switches to the second working mode (large fan mode), configures four PWM drives, and the fans start and run normally.

[0214] Status Confirmation: Check fan configuration, speed, and other information through the server BMC management interface to confirm that the fan is running normally, there are no alarm signals, and the switchover is complete.

[0215] The process of switching from four 8038 / 8060 fans to six 6038 fans is the same as the steps above. You only need to replace the fans with the corresponding specifications. No adjustments to the board are required.

[0216] Example 6

[0217] This example demonstrates the hot-swap switching method.

[0218] During server operation, when an existing fan is detected to have been unplugged and a new fan is inserted, the CPLD chip re-executes the in-situ scanning and specification identification process to achieve online fan specification switching. During hot-swapping, the CPLD chip keeps other running fans operating normally, only re-detecting and reconfiguring the interface of the newly connected fan.

[0219] For example, when an 8038 fan fails and needs to be replaced during server operation, the operator can directly unplug the faulty fan and insert a new 8038 fan (or replace it with a 6038 fan as needed, but note that different fan specifications cannot be mixed on the same board). The CPLD chip automatically detects the new fan connection and completes identification and configuration. The entire process does not require downtime, realizing hot-swappable fan replacement.

[0220] Example 7

[0221] In mass production scenarios, the same PCB board may need to be adapted to different server models, and different models may need to support different fan configurations. By setting a board identification module, the board type can be set during the production process simply by mounting resistors with different resistance values ​​or burning different identification codes. The CPLD chip reads this identification code during power-on initialization and automatically adapts to the corresponding fan configuration. For example, for a model that needs to support a configuration of 6 small fans / 4 large fans, the board identification module is set to the first configuration value; for a model that needs to support a configuration of 8 small fans / 6 large fans, the board identification module is set to the second configuration value—while the PCB design and CPLD program are completely identical, requiring no modification. This greatly improves the reusability of the boards and reduces production and management costs.

[0222] Example 8

[0223] During server operation, if, due to operational error, both small and large fans (e.g., three 6038 fans and two 8038 fans) are simultaneously inserted onto the same board, the CPLD chip's presence detection module and specification recognition module will detect this mixed connection. The CPLD chip will immediately trigger an alarm signal via I... 2 The C interface reported to the BMC that a fan configuration error (hybrid access alarm) occurred, and the board did not start any fan drivers, requiring manual intervention.

[0224] The necessity of the aforementioned hybrid access detection lies in the fact that if large and small fans operate simultaneously, their different heat dissipation capacities (airflow) and airflow characteristics may lead to turbulent airflow inside the server, resulting in insufficient heat dissipation or even overheating and damage in localized areas. The hybrid access detection mechanism of this invention prevents mis-insertion through electrical means. Compared to traditional mechanical foolproof structures (such as different connector shapes or guide keys), it simplifies connector design complexity (the two interfaces can use the same or similar shapes and be distinguished electrically), and allows for more flexible alarms and responses at the system level (such as reporting via BMC and logging), effects that mechanical foolproofing cannot achieve.

[0225] Example 9

[0226] The server cooling fan board compatible with multiple fan specifications described in this invention executes the following automated closed-loop detection and graded fault handling logic during operation:

[0227] (1) Hardware status acquisition and comprehensive judgment:

[0228] The system continuously collects various hardware operating parameters of the fan, specifically including:

[0229] Power Supply Voltage and Current Detection: The system employs an ADC (Analog-to-Digital Converter) to convert the power supply voltage of the detection system from analog to digital. Different voltage thresholds and detection accuracies are set for different power rails, and the internally integrated ADC module monitors the power supply voltage of each fan interface in real time. Simultaneously, an external precision resistor connected in series in the power supply circuit of each fan interface detects the voltage drop, and the actual operating current of each fan is calculated after ADC conversion, enabling independent current monitoring for each fan. The real-time detected and converted voltage and current values ​​are continuously uploaded to the internal registers of the unified fan control unit (CPLD chip).

[0230] Feedback speed detection: The actual fan speed feedback signal is detected through the fan speed feedback pin (TACH signal). The system uses a high-precision fan speed sampling circuit to convert the sampled speed pulse signal into a duty cycle value. The CPLD chip compares the duty cycle of the currently output PWM speed control signal with the measured speed feedback signal using an algorithm to calculate the speed deviation value and deviation rate, and obtain abnormal parameters (such as speed deviation percentage, deviation duration, etc.).

[0231] (2) Branch processing for normal and abnormal states:

[0232] The CPLD chip determines its status based on comprehensive detection results, and the entire logic is divided into two main branches: normal operation and abnormal fault processing.

[0233] If the abnormal parameters meet the normal operating threshold range (such as speed deviation within ±5% and current within the rated range), the normal judgment and operation logic will be executed to maintain the current PWM speed control output, and the fan will continue to operate normally.

[0234] If the abnormal parameter reaches the abnormal level, a differentiated speed adjustment strategy will be implemented according to the degree of deviation of the parameter: when the abnormal parameter shows that the speed is slightly low (such as the deviation is between 5% and 15%), the PWM duty cycle will be increased appropriately to increase the speed; when the abnormal parameter shows that the speed is high, the PWM duty cycle will be decreased appropriately to reduce the speed, so that the fan speed approaches the target value.

[0235] (3) Segmentation and differentiated protection of fault scenarios:

[0236] When abnormal parameters indicate that the fan is not rotating (the speed feedback signal disappears for more than a preset time) or the fan is offline (the presence detection signal is lost), the system drives different speeds according to the preset fan redundancy scheme:

[0237] First, try to re-drive the offline fan (e.g., resend the start PWM signal). If the fan is detected to have resumed operation, report the return to normal status to the BMC and restore normal speed control.

[0238] If the fan still fails to resume operation after retrying, the redundant control logic will be followed according to the offline state, the drive output of the corresponding fan channel will be turned off, an offline alarm will be triggered and reported to the BMC, and the speed of other normally operating fans will be adjusted according to the server's heat dissipation requirements to compensate for the lack of heat dissipation capacity of the offline fan.

[0239] The fault scenarios are further subdivided into multiple types of faults (including power supply abnormality, short circuit / overcurrent, low speed / locked rotor, open circuit / no position, etc.), and different protection and alarm strategies are implemented for each type of fault: for recoverable faults (low speed / locked rotor), a retry recovery is first attempted; for unrecoverable severe faults (power supply abnormality, short circuit / overcurrent, open circuit / no position), an emergency shutdown or drive disconnection is directly executed.

[0240] (4) Status reporting and standby determination:

[0241] The CPLD chip determines whether to continue inspection or shut down for standby based on the severity of the fault.

[0242] For recovered faults or minor anomalies, the CPLD chip clears the fault state, maintains normal fan operation, and continuously performs fan hardware status information detection to form a closed-loop monitoring.

[0243] For serious and unrecoverable faults, the CPLD chip latches the fault code, illuminates the fault indicator light, stops the output of the corresponding fan channel and enters standby mode, and simultaneously reports all fault information to the BMC, which records the system log.

[0244] Unlike existing technologies that simply detect power supply voltage without current detection and corresponding protection strategies, or those that only detect and report fan status without comprehensive redundant control logic and anomaly handling strategies, this invention achieves comprehensive monitoring, intelligent speed adjustment, hierarchical fault handling, and redundant control of fan operating status through the aforementioned automated closed-loop detection and graded fault handling logic, significantly improving the reliability and maintainability of the server cooling system.

[0245] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Server cooling fan cards compatible with multiple fan sizes, including: The board itself is separate from the server motherboard and is used for fan installation, control, and heat dissipation; Its characteristic is that it further includes: The composite fan interface area is located on the board body and includes M sets of first-specification fan interfaces and N sets of second-specification fan interfaces, where M>N. The first-specification fan interfaces are used to connect to first-specification fans, and the second-specification fan interfaces are used to connect to second-specification fans. The size of the first-specification fan is smaller than that of the second-specification fan. The first-specification fan interfaces and the second-specification fan interfaces are arranged in a staggered and partitioned manner on the board body. The spacing between adjacent fan interfaces is determined according to the installation size of the corresponding fan, so that the first-specification fan and the second-specification fan do not interfere with each other when installed separately. A unified fan control unit is located on the main body of the board and is electrically connected to each first-specification fan interface and each second-specification fan interface respectively. The power supply circuit is located on the main body of the board and is electrically connected to the unified fan control unit and all fan interfaces to supply power to the connected fans. The in-situ detection module is located on the main body of the board and is electrically connected to each fan interface. It is used to detect whether a fan is connected to each fan interface and transmit the detection results to the unified fan control unit. The specification identification module is located on the main board and is electrically connected to each fan interface. It is used to read the ID resistance value or feedback resistance value of the connected fan to identify the fan specification type and transmit the identified specification type to the unified fan control unit. The drive output module is located on the board body and is electrically connected to the unified fan control unit and each fan interface. It is used to output drive according to the control signal of the unified fan control unit. The unified fan control unit is used to receive the detection results of the in-situ detection module and the specification type identified by the specification identification module. According to the detection results and specification type, the unified fan control unit switches to the first working mode and enables M drive outputs when it detects M first specification fans connected, switches to the second working mode and enables N drive outputs when it detects N second specification fans connected, and triggers an alarm signal when it detects that first specification fans and second specification fans are connected in a mixed manner.

2. The server cooling fan board compatible with multiple fan specifications according to claim 1, characterized in that: The unified fan control unit is a CPLD chip, which integrates a PWM output interface and a serial communication interface, and is compatible with both PWM 4-pin and PWM 8-pin fans; the CPLD chip connects via I... 2 The C interface or SGPIO interface is used to communicate with the server's BMC, and is used to report fan configuration information, speed information, and operating status information to the BMC, and to receive speed control commands issued by the BMC.

3. The server cooling fan board compatible with multiple fan specifications according to claim 1, characterized in that: Both the first and second specification fan interfaces are universal interfaces compatible with PWM 4-pin and PWM 8-pin interfaces. The pin definitions of each universal interface include power pin, ground pin, PWM speed control pin, and speed feedback pin. The PWM 8-pin interface type fan interface also includes dual rotor signal pins. The specification identification module determines the specification type of the connected fan by reading the fan's ID resistance value or feedback resistance value and combining it with the pin definition information of the universal interface.

4. The server cooling fan board compatible with multiple fan specifications according to claim 1, characterized in that: The board body is also equipped with a board identification module, which stores the board type identifier and version identifier. The unified fan control unit confirms the board configuration parameters by reading the board type identifier and version identifier, and determines the supported fan specification combination based on the board configuration parameters. The board identification module is implemented using a resistor voltage divider network or a storage chip. The board configuration parameters can be changed by changing different resistor values ​​or burning different identifier codes, without modifying the CPLD program.

5. The server cooling fan board compatible with multiple fan specifications according to claim 1, characterized in that: The presence detection module is implemented using a voltage divider resistor circuit. It determines whether the fan is in position by detecting the pin level of each fan interface. For the PWM 4-pin interface, it determines the fan's presence status by detecting the DC level of the speed feedback pin or the presence signal pin level. For the PWM 8-pin interface, it determines the fan's presence status by detecting the level of the dedicated presence signal pin.

6. The server cooling fan board compatible with multiple fan specifications according to claim 1, characterized in that: The unified fan control unit has built-in speed control curve parameters and speed detection logic parameters for various fan specifications; When switching to the first working mode, the first speed control curve is determined according to the speed control curve parameters matched with the first specification fan, and the first speed control curve is called to control the speed. At the same time, the first speed detection logic is determined according to the speed detection logic parameters matched with the first specification fan, and the first speed detection logic is called to detect the speed status. When switching to the second working mode, the second speed control curve is determined according to the speed control curve parameters matched with the second specification fan, and the second speed control curve is called to control the speed. At the same time, the second speed detection logic is determined according to the speed detection logic parameters matched with the second specification fan, and the second speed detection logic is called to detect the speed status. The speed regulation curve parameters include the PWM duty cycle mapping relationship corresponding to different temperature ranges, and the speed detection logic parameters include the speed pulse count threshold and the speed abnormality judgment threshold.

7. A fan switching method for a server cooling fan board compatible with multiple fan specifications, applied to the server cooling fan board compatible with multiple fan specifications as described in claim 6, characterized in that, Includes the following steps: Step S1: Power off the server or enter a safe shutdown state, so that the fan and the server cooling fan board that is compatible with multiple fan specifications are both in a power-off state. Step S2: Remove the first or second specification fan currently installed on the server cooling fan board compatible with multiple specifications of fans from the corresponding interface, without disassembling the fan board body. Step S3: Based on the server's heat dissipation requirements, select to install M first-specification fans or N second-specification fans, and insert the selected fans into the corresponding first-specification fan interface or second-specification fan interface on the board body. Step S4: The server powers on and starts up, and the unified fan control unit initializes and performs a self-test; Step S5: The unified fan control unit performs an in-situ scan of all fan interfaces by the in-situ detection module to detect whether a fan is connected to each fan interface, and records the location and number of fan interfaces with fans connected, thereby obtaining the detection results of the in-situ detection module. Step S6: The unified fan control unit reads the ID resistance value or feedback resistance value of each connected fan through the specification identification module to identify the specification type of each connected fan. Step S7: The unified fan control unit, based on the detection results of the in-situ detection module and the specification type identified by the specification identification module, counts the total number of connected fans and the number of fans of each specification, and performs mode determination. If the detection result shows that M first-specification fans are connected and no second-specification fans are connected, then it is determined to be the first working mode, and step S8a is executed; If the detection result shows that N second-specification fans are connected and no first-specification fans are connected, then it is determined to be the second working mode, and step S8b is executed; If the test result shows that the first specification fan and the second specification fan are mixed and connected, or the number of connected fans does not match the expected number, it is determined to be a configuration abnormality and step S9 is executed; Step S8a: Switch to the first working mode, enable the M-channel drive output module, call the first speed control curve and the first speed detection logic that match the first specification fan, and control the speed and monitor the status of each fan through the PWM signal. Step S8b: Switch to the second working mode, enable the N-channel drive output module, call the second speed control curve and the second speed detection logic that match the second specification fan, and control the speed and monitor the status of each fan through the PWM signal; Step S9: Trigger an alarm signal and report it to the server BMC via the communication interface, indicating that the fan configuration is abnormal and awaiting manual handling; Step S10: During normal fan operation, the unified fan control unit collects the speed signal and operating status of each fan in real time, performs closed-loop speed control, and continuously monitors the fan operating status. If an abnormality is detected, a graded fault handling process is executed.

8. The fan switching method for a server cooling fan board compatible with multiple fan specifications according to claim 7, characterized in that, The method for reading the ID resistor value or feedback resistor value in step S6 includes: for fans with an 8-pin PWM interface, the fan specification is determined by reading the resistance value of the built-in ID resistor and comparing it with a preset ID resistor-specification mapping table; for fans with a 4-pin PWM interface, the fan specification is determined by sending a preset PWM test signal to the fan and measuring the fan speed feedback signal, comparing the measured speed-duty cycle response curve with the standard response curves of various fan specifications.

9. The fan switching method for a server cooling fan board compatible with multiple fan specifications according to claim 7, characterized in that, The mode determination in step S7 also includes: When the number of fans of the same specification is less than the rated number but greater than zero, it is determined to be a partial access mode; the unified fan control unit switches to the working mode corresponding to the specifications of the accessed fans, and enables the corresponding number of drive outputs according to the actual number of accessed fans, while reporting the partial access alarm through the BMC. When a fan interface is detected to be empty and the configuration information issued by the BMC requires that the fan interface should have a fan, a missing alarm is reported through the BMC.

10. The fan switching method for a server cooling fan board compatible with multiple fan specifications according to claim 7, characterized in that, Step S10, the closed-loop speed control, includes: the unified fan control unit collects the actual speed signal of each fan in real time through the PWM interface, compares the actual speed with the target speed, and calculates the speed deviation value; based on the speed deviation value, the PWM output duty cycle is dynamically adjusted using a PID control algorithm or a fuzzy control algorithm to make the actual speed approach the target speed; the target speed is determined by the BMC based on the speed adjustment command issued by the server temperature sensor data, or by the unified fan control unit autonomously based on the detection results of the onboard temperature sensor.

11. The fan switching method for a server cooling fan board compatible with multiple fan specifications according to claim 7, characterized in that, It also includes a fan hot-swap switching step: During server operation, when it is detected that an existing fan has been unplugged and a new fan has been plugged in, the unified fan control unit re-executes the process from step S5 to step S8 to achieve online fan specification switching; during the fan hot-swap switching process, the unified fan control unit keeps other running fans working normally and only re-detects and reconfigures the newly connected fan interface.

12. The fan switching method for a server cooling fan board compatible with multiple fan specifications according to claim 7, characterized in that, The method for detecting an anomaly and executing the graded fault handling process in step S10 includes: The unified fan control unit integrates in-situ detection signals, power supply status detection signals, speed feedback signals, and current detection signals to form a comprehensive detection result; Status assessment based on comprehensive test results: When the system is determined to be in a normal state, it accepts the PWM / speed command issued by the BMC, outputs the drive level / PWM wave, maintains the normal operation of the fan, and reports the normal state to the BMC. When an abnormal state is identified, the fault type is distinguished: If the fault is a power supply abnormality, the corresponding fan drive will be cut off and a power alarm will be triggered. If the fault is a short circuit or overcurrent, an emergency shutdown driver will be executed and hardware protection will be triggered. If the fault is low speed or stall, increase the PWM duty cycle and try again. If the retry is successful, normal operation will be restored. If the retry fails, proceed to fault handling. If the fault is a disconnection or absence, the corresponding fan driver will be shut down and an offline alarm will be triggered. After the fault is resolved, the fault code is latched and the fault indicator light is illuminated. The unified fan control unit stops the output of the corresponding channel and enters standby mode, while all fault information is reported to the BMC.

13. A server cooling system, characterized in that, include: Server chassis; The server motherboard is located inside the server chassis and contains the BMC; The server cooling fan board compatible with multiple fan specifications as described in any one of claims 1-6 is disposed inside the server chassis, independently of the server motherboard, and electrically connected to the server motherboard and / or chassis backplane via a connector; The unified fan control unit communicates with the BMC via a communication interface to report fan configuration information, speed information, operating status information and alarm information to the BMC, and to receive speed control commands issued by the BMC. The BMC generates speed control commands based on temperature data from various temperature sensors on the server and sends them to the unified fan control unit. When the BMC malfunctions or communication is interrupted, the unified fan control unit autonomously controls the fan speed based on the detection results of the onboard temperature sensors.

14. A server cooling system according to claim 13, characterized in that, The server chassis is equipped with multiple temperature sensors, distributed in the heat-generating areas of the server motherboard, CPU, memory, and hard drive. Each temperature sensor is electrically connected to the BMC. The BMC calculates the target speed of each fan based on the temperature data from each temperature sensor and a preset temperature-speed mapping table, and sends the result to the unified fan control unit. The temperature-speed mapping table dynamically selects the corresponding mapping relationship based on the specifications of the currently connected fan. The BMC has a pre-set temperature-speed mapping table, which is a dataset of the correspondence between temperature values ​​and target speed values; the temperature-speed mapping table includes a first temperature-speed mapping table corresponding to a first specification fan and a second temperature-speed mapping table corresponding to a second specification fan. Based on the temperature data from each temperature sensor and the specifications of the currently connected fans reported by the unified fan control unit, the BMC selects the temperature-speed mapping table corresponding to the specifications, calculates the target speed of each fan, and sends it to the unified fan control unit.

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