Hybrid data storage method for flash memory and memory device using the same
Patent Information
- Application Number
- CN202510312480.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-09-18
AI Technical Summary
然而，随着SSD器件中的存储器经过不断重复的写入操作或抹除操作后，可能造成数据保存能力下降，甚至发生存储数据发生错误的状况
[0012]In summary, the hybrid data storage method for flash memory and the storage device employing the hybrid data storage method of this application check and convert data storage methods on a word-line basis, thereby improving the storage space utilization of each storage block in the data storage device. Furthermore, this application uses the hybrid data storage method to dynamically manage the flash memory in the data storage device, achieving the goals of flexibly improving the data access speed of some word lines (i.e., after being converted to single-level memory cell mode), improving the durability of some word lines, and extending the lifespan of the data storage device.
Smart Images
Figure CN122777043A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a flash memory data storage method, and more particularly to a hybrid flash memory data storage method and a storage device employing the hybrid data storage method. Background Technology
[0002] Solid-state drive (SSD) devices are data storage devices made with integrated circuits. Common SSD devices use non-volatile memory as the main data storage element.
[0003] In recent years, SSDs have become increasingly popular among users due to their advantages over traditional hard drives, including smaller size, greater durability, lighter weight, greater portability, noiseless operation, and faster access speeds. However, repeated write and erase operations on the memory in an SSD can lead to a decrease in data retention capacity and even data corruption.
[0004] Therefore, blocks with poor data retention capabilities are usually marked as "bad blocks" through storage block management to avoid storing data in the aforementioned "bad blocks," which could lead to errors in read, write, or erase operations. Summary of the Invention
[0005] Because the memory management method described above marks an entire block of data in the SSD's memory with problematic data retention capabilities as a "bad block," the SSD will not use these "bad blocks" to store data. This means that the entire block marked as a "bad block" can no longer be used. However, there is still other usable storage space (e.g., pages) within the "bad block." Therefore, the memory management method described above wastes usable storage space.
[0006] To address the aforementioned problems, the purpose of this application is to provide a hybrid data storage method for flash memory, comprising the following steps: storing data in at least one memory block of flash memory using an X-level cell method; executing automatic error correction code (ECC) on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, converting the data storage method corresponding to the at least one word line in the at least one memory block that meets the condition of exceeding the critical value from the X-level cell method to the single-level cell (SLC) method; and when the error bit rate is confirmed not to exceed the critical value, maintaining the data storage method corresponding to the at least one word line in the at least one memory block as the X-level cell method.
[0007] In one embodiment, after the step of converting the data storage mode corresponding to at least one word line in at least one storage block that meets the error bit rate exceeding the critical value from the X-level storage cell mode to the single-level storage cell mode when it is confirmed that the error bit rate exceeds the critical value, the method further includes the step of recording the word line corresponding to the single-level storage cell mode in the word line management table.
[0008] In one embodiment, after the step of converting the data storage mode corresponding to at least one word line in at least one storage block that meets the condition of exceeding the critical value from the X-level storage cell mode to the single-level storage cell mode when it is confirmed that the error bit rate exceeds the critical value, the at least one storage block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.
[0009] In one embodiment, the threshold value can be adjusted.
[0010] In one embodiment, the X-level storage cell method is a two-level storage cell (MLC), a three-level storage cell (TLC), a four-level storage cell (QLC), or a five-level storage cell (PLC).
[0011] To address the aforementioned problems, another objective of this application is to provide a data storage device employing a hybrid data storage method, comprising: a controller; a memory electrically coupled to the controller and configured to store firmware code; and multiple flash memory modules electrically coupled to and communicating with the controller; wherein, after the firmware code is executed by the controller, the following steps are performed: data is stored in at least one storage block of the multiple flash memory modules using an X-level memory cell method; automatic error correction code is executed on the at least one storage block to confirm whether the error bit rate of at least one word line in the at least one storage block exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, the data storage method corresponding to the at least one word line in the at least one storage block that meets the condition of the error bit rate exceeding the critical value is converted from the X-level memory cell method to the single-level memory cell method; and when the error bit rate is confirmed not to exceed the critical value, the data storage method corresponding to the at least one word line in the at least one storage block is maintained as the X-level memory cell method.
[0012] In summary, the hybrid data storage method for flash memory and the storage device employing the hybrid data storage method of this application check and convert data storage methods on a word-line basis, thereby improving the storage space utilization of each storage block in the data storage device. Furthermore, this application uses the hybrid data storage method to dynamically manage the flash memory in the data storage device, achieving the goals of flexibly improving the data access speed of some word lines (i.e., after being converted to single-level memory cell mode), improving the durability of some word lines, and extending the lifespan of the data storage device. Attached Figure Description
[0013] Figure 1 This is a system block diagram showing the data storage device according to an embodiment of this application.
[0014] Figure 2 This is a schematic diagram of a storage block according to an embodiment of this application.
[0015] Figure 3 This is a schematic diagram showing the word line when the bit rate of a conformation error in a memory block exceeds a critical value, according to an embodiment of this application.
[0016] Figure 4 This is another schematic diagram illustrating the word line when the bit rate of a conformation error in a memory block exceeds a critical value, according to an embodiment of this application.
[0017] Figure 5 This is a schematic diagram showing the character line management table according to an embodiment of this application.
[0018] Figure 6 This is a flowchart illustrating a hybrid data storage method according to an embodiment of this application.
[0019] Figure 7 This is a flowchart illustrating another embodiment of the hybrid data storage method of this application.
[0020] Figure Labels
[0021] 10 Controllers
[0022] 20. Memory
[0023] 22 Firmware Code
[0024] 30-line management table
[0025] 100 Data storage devices
[0026] BL0 bit line
[0027] BL1 bit line
[0028] BL2 bit line
[0029] BL3 bit line
[0030] BLn bitline
[0031] BLK0 storage block
[0032] BLK1 storage block
[0033] BLKn storage block
[0034] FL0 flash memory
[0035] FLn flash memory
[0036] SL0 High Error Rate Word Line
[0037] SL1 High Error Rate Word Line
[0038] WL0 letter line
[0039] WL1 letter line
[0040] WL2 letter line
[0041] WL3 letter line
[0042] WL4 letter line
[0043] WL5 letter line
[0044] WL6 letter line
[0045] WL7 letter line
[0046] WL8 letter line
[0047] WLn letter line
[0048] S600, S602 Steps
[0049] S604, S606 Steps
[0050] S608, S610 Steps Detailed Implementation
[0051] Please refer to Figure 1 This is a system block diagram showing the data storage device 100 according to an embodiment of this application. Figure 1 As shown, the data storage device 100 may include a controller 10, a memory 20, and n flash memory modules FL0 to FLn, where n is a natural number greater than or equal to 1.
[0052] The controller 10 is configured to be electrically coupled to and communicate with the flash memory FL0 to FLn. The controller 10 can control the read, write, and erase operations of the flash memory FL0 to FLn.
[0053] The memory 20 is electrically coupled to the controller 10. The memory 20 is configured to store firmware code 22. The memory 20 may be composed of non-volatile memory.
[0054] Firmware code 22 can be stored in memory 20. In other embodiments, firmware code 22 can also be stored in the memory (not shown) of controller 10. After firmware code 22 is executed by controller 10, the following steps can be performed: data is stored in one of the memory blocks BLK0 to BLKn of flash memory FL0 to FLn using an X-level memory cell method; automatic error correction code is executed on memory blocks BLK0 to BLKn to confirm whether the error bit rate of word lines in memory blocks BLK0 to BLKn exceeds a critical value; when the error bit rate is confirmed to exceed the critical value, the data storage method corresponding to the word lines in memory blocks BLK0 to BLKn that meet the error bit rate exceeding the critical value is changed from X-level memory cell method to single-level memory cell method; and when the error bit rate is confirmed not to exceed the critical value, the data storage method corresponding to the word lines in memory blocks BLK0 to BLKn is maintained as X-level memory cell method.
[0055] Furthermore, in this embodiment, the X-level storage cell method can be, for example, a two-level, three-level, four-level, or five-level storage cell method, or other higher-level data storage cell methods in NAND technology. The aforementioned two-level storage cell method has a higher data access speed than the three-level storage cell method, and a lower data storage capacity than the three-level storage cell method. The aforementioned three-level storage cell method has a higher data access speed than the four-level storage cell method, and a lower data storage capacity than the four-level storage cell method. The aforementioned four-level storage cell method has a higher data access speed than the five-level storage cell method, and a lower data storage capacity than the five-level storage cell method, and so on. In other words, the X-level storage cell method has a higher data access speed than the X+1-level storage cell method, and a lower data storage capacity than the X+1-level storage cell method. Furthermore, the X-level storage cell method described above has a lower data access speed than the single-level storage cell method, and the X-level storage cell method described above has a higher data storage capacity than the single-level storage cell method.
[0056] In other words, the single-level storage cell method offers the fastest data access speed compared to the X-level storage cell method. Furthermore, the single-level storage cell method provides approximately 100,000 P / E cycles, the double-level storage cell method provides approximately 10,000 P / E cycles, the triple-level storage cell method provides approximately 3,000 P / E cycles, and the quadruple-level storage cell method provides approximately 1,000 P / E cycles. Here, P refers to programming and E refers to erasure. Therefore, the single-level storage cell method has superior endurance compared to the X-level storage cell method; that is, the single-level storage cell method has the highest endurance.
[0057] Flash memory FL0 to FLn are electrically coupled to controller 10. Flash memory FL0 to FLn can communicate with controller 10. Flash memory FL0 to FLn are configured to be controlled by controller 10 to perform data read, write, and erase operations. Flash memory FL0 has multiple storage blocks BLK0 to BLKn, and so on, each of flash memory FL0 to FLn has multiple storage blocks BLK0 to BLKn.
[0058] In other embodiments, the data storage device 100 further includes a word line management table 30. The word line management table 30 is connected to the controller 10. The word line management table 30 is configured to record information related to word lines using an X-level memory cell configuration and word lines using a single-level memory cell configuration. The controller 10 can use the aforementioned information provided by the word line management table 30 to control the flash memory FL0 to FLn to perform read, write, and erase operations in a specific data storage mode.
[0059] In other embodiments, the word line management table 30 can be stored in the memory 20 and connected to the controller 10 to provide the aforementioned related information to the controller 10. Furthermore, after the step of converting the data storage mode corresponding to the word lines in storage blocks BLK0 to BLKn that meet the error bit rate exceeding the threshold from X-level storage cell mode to single-level storage cell mode when the error bit rate is confirmed to exceed the threshold, the storage blocks BLK0 to BLKn include word lines using X-level storage cell mode and word lines using single-level storage cell mode, i.e., a hybrid data storage mode.
[0060] Please refer to Figure 2 This is a schematic diagram showing storage blocks BLK0 to BLKn in an embodiment of this application. Figure 2As shown, each of the memory blocks BLK0 to BLKn in the data storage device 100 includes multiple word lines WL0 to WLn and multiple bit lines BL0 to BLn. Regions where the multiple word lines WL0 to WLn and the multiple bit lines BL0 to BLn intersect each other perpendicularly can form multiple memory cells (not labeled in the figure). The aforementioned memory cell refers to the smallest structure used to access data.
[0061] In the preset data storage mode of the data storage device 100, storage blocks BLK0 to BLKn can be configured to provide storage capacity with the same capacity as each other. For example, storage block BLK0 can provide storage capacity Y0, storage block BLK1 can provide storage capacity Y0, ..., storage block BLKn can provide storage capacity Y0.
[0062] Please refer to Figure 3 This is a schematic diagram illustrating the word lines in an embodiment of this application when the coincidence error bit rate in memory blocks BLK0 to BLKn exceeds a critical value. For example... Figure 3 As shown, after executing the automatic error correction code, if the error bit rate (e.g., 50.1%) of word line WL5 in memory block BLK0 exceeds a threshold value (e.g., 50%), the controller 10 can convert the data storage mode corresponding to word line WL5 in memory block BLK0 that meets the error bit rate exceeding the threshold value from X-level memory cell mode to single-level memory cell mode. The aforementioned word line WL5 can be labeled as a high error bit rate word line SL0. In other embodiments, the threshold value can be set and adjusted by the user; that is, the threshold value is adjustable, and the threshold value can be between 20% and 80% of the error correction bit count, but is not limited to this.
[0063] After word line WL5 in memory block BLK0 is marked as word line SL0 with a high error rate, the storage capacity that memory block BLK0 can provide changes from storage capacity Y0 to storage capacity Y1, where storage capacity Y1 is less than storage capacity Y0. Since no word lines in memory blocks BLK1 to BLKn have an error rate exceeding the critical value, memory blocks BLK1 continue to provide storage capacity Y0, ..., and memory blocks BLKn continue to provide storage capacity Y0.
[0064] It is worth noting that since some memory cells can still be used in word lines SL0 with high error rates, the embodiments of this application can continue to use word lines SL0 with high error rates in memory block BLK0 to access data. Compared with the memory management method of the prior art, which marks the entire block with data retention capability problems in the memory of the SSD device as a "bad block" and then the SSD device will not use the aforementioned "bad block" to store data, the embodiments of this application have a higher storage space utilization.
[0065] In addition, when the high error rate word line SL0 is converted from the X-level storage cell mode to the single-level storage cell mode, although the overall data storage capacity of the high error rate word line SL0 decreases, the data access speed is significantly improved, and the durability is also improved.
[0066] In other words, the embodiments of this application perform inspection and conversion on a word line basis to improve the storage space utilization of storage blocks BLK0 to BLKn in the data storage device 100, and can flexibly improve the data access speed of some word lines (i.e., after being converted to single-level storage cell mode), as well as improve the durability of some word lines and extend the service life of the data storage device 100.
[0067] Please refer to Figure 4 This is another schematic diagram illustrating the word line when the conformation error bit rate in memory blocks BLK0 to BLKn exceeds a critical value, according to an embodiment of this application. Figure 4 As shown, after executing the automatic error correction code, and confirming that the error bit rate of word line WL5 (e.g., 50.1%) and the error bit rate of word line WL0 (e.g., 53%) in memory blocks BLK0 to BLKn both exceed the threshold value (e.g., 50%), the controller 10 can change the data storage mode of word line WL5 and word line WL0 in memory block BLK0 that meet the error bit rate exceeding the threshold value from the X-level memory cell mode to the single-level memory cell mode. The aforementioned word line WL5 can be labeled as a high error bit rate word line SL0, and the aforementioned word line WL0 can be labeled as a high error bit rate word line SL1.
[0068] After word line WL5 in memory block BLK0 is marked as a high error rate word line SL0, and word line WL0 is marked as a high error rate word line SL1, memory block BLK0 can provide storage capacity Y0 to storage capacity Y2, where storage capacity Y2 is less than storage capacity Y0. Since no word lines in memory blocks BLK1 to BLKn have errors exceeding the critical value, memory blocks BLK1 continue to provide storage capacity Y0, ..., and BLKn continue to provide storage capacity Y0.
[0069] Please refer to Figure 5 This is a schematic diagram showing the word line management table 30 of an embodiment of this application. Figure 5As shown, the word line management table 30 can record the data storage mode used by word lines WL0 to WLn in memory blocks BLK0 to BLKn. When the data storage mode corresponding to a word line in memory blocks BLK0 to BLKn that has exceeded the critical value is changed from X-level memory cell mode to single-level memory cell mode, the controller 10 can update the word line management table 30 and control the data storage device 100 to operate with the updated word line management table 30.
[0070] Please refer to Figure 6 This is a flowchart illustrating a hybrid data storage method according to an embodiment of this application. For example... Figure 6 As shown, in step S600, the controller 10 uses an X-level storage cell method to store data in the storage blocks BLK0 to BLKn of the flash memory FL0 to FLn.
[0071] In step S602, the controller 10 executes automatic error correction code on the storage blocks BLK0 to BLKn.
[0072] Step S604: Confirm whether the error bit rate of word lines WL0 to WLn in storage blocks BLK0 to BLKn exceeds the critical value. If the determination is "no", proceed to step S608. If the determination is "yes", proceed to step S606.
[0073] Step S606: When it is confirmed that the error bit rate exceeds the critical value, the data storage mode corresponding to word lines WL0 to WLn in storage blocks BLK0 to BLKn that meet the error bit rate exceeding the critical value is changed from X-level storage cell mode to single-level storage cell mode.
[0074] Step S608: When it is confirmed that the error bit rate has not exceeded the critical value, the data storage mode corresponding to word lines WL0 to WLn in the storage blocks BLK0 to BLKn is maintained as X-level storage cell mode, and the process returns to step S600.
[0075] Please refer to Figure 7 This is a flowchart illustrating a hybrid data storage method according to another embodiment of this application. Figure 7 Examples and Figure 6 The difference between the embodiments is: Figure 7 After step S606, step S610 is also included, and the remaining steps are the same as... Figure 6 Similar or identical items will not be elaborated upon here.
[0076] In step S610, the controller 10 records the word lines corresponding to the single-level storage unit method in the word line management table 30. Therefore, the controller 10 can control the data storage device 100 to perform data read, write, or erase operations by updating the word line management table 30.
[0077] In summary, the hybrid data storage method for flash memory and the storage device employing the hybrid data storage method of this application check and convert data storage methods on a word-line basis, thereby improving the storage space utilization of each storage block in the data storage device. Furthermore, this application uses the hybrid data storage method to dynamically manage the flash memory in the data storage device, achieving the goals of flexibly improving the data access speed of some word lines (i.e., after being converted to single-level memory cell mode), improving the durability of some word lines, and extending the lifespan of the data storage device.
Claims
1. A hybrid data storage method for flash memory, characterized in that, Includes the following steps: The data is stored in at least one storage block of the flash memory using an X-level storage cell method; Automatic error correction code is executed on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a critical value; When it is confirmed that the error bit rate exceeds the critical value, the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition that the error bit rate exceeds the critical value is changed from the X-level storage cell mode to the single-level storage cell mode. and When it is confirmed that the error bit rate has not exceeded the critical value, the data storage mode corresponding to the at least one word line in the at least one storage block is maintained as the X-level storage cell mode.
2. The hybrid data storage method for flash memory according to claim 1, characterized in that, When it is confirmed that the error bit rate exceeds the threshold, after the step of changing the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to the single-level storage cell mode, the method further includes the step of recording the word line corresponding to the single-level storage cell mode in the word line management table.
3. The hybrid data storage method for flash memory according to claim 1, characterized in that, When it is confirmed that the error bit rate exceeds the threshold, after the step of converting the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to the single-level storage cell mode, the at least one storage block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.
4. The hybrid data storage method for flash memory according to claim 1, characterized in that, The threshold value can be adjusted.
5. The hybrid data storage method for flash memory according to claim 1, characterized in that, The X-level storage unit method can be a two-level storage unit method, a three-level storage unit method, a four-level storage unit method, or a five-level storage unit method.
6. A data storage device employing a hybrid data storage method, characterized in that, include: Controller; The memory, electrically coupled to the controller, is configured to store firmware code; Multiple flash memory modules are electrically coupled to and communicate with the controller; After the firmware code is executed by the controller, the following steps are performed: The data is stored in at least one storage block of the plurality of flash memory using an X-level storage cell method; Automatic error correction code is executed on the at least one memory block to confirm whether the error bit rate of at least one word line in the at least one memory block exceeds a critical value; and When it is confirmed that the error bit rate exceeds the critical value, the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition that the error bit rate exceeds the critical value is changed from the X-level storage cell mode to the single-level storage cell mode. When it is confirmed that the error bit rate has not exceeded the critical value, the data storage mode corresponding to the at least one word line in the at least one storage block is maintained as the X-level storage cell mode.
7. The data storage device employing a hybrid data storage method according to claim 6, characterized in that, When it is confirmed that the error bit rate exceeds the threshold, after the step of changing the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to the single-level storage cell mode, the method further includes the step of recording the word line corresponding to the single-level storage cell mode in the word line management table.
8. The data storage device employing a hybrid data storage method according to claim 6, characterized in that, When it is confirmed that the error bit rate exceeds the threshold, after the step of converting the data storage mode corresponding to the at least one word line in the at least one storage block that meets the condition of the error bit rate exceeding the threshold from the X-level storage cell mode to the single-level storage cell mode, the at least one storage block includes word lines using the X-level storage cell mode and word lines using the single-level storage cell mode.
9. The data storage device employing a hybrid data storage method according to claim 6, characterized in that, The threshold value can be adjusted.
10. The data storage device employing a hybrid data storage method according to claim 6, characterized in that, The X-level storage unit method can be a two-level storage unit method, a three-level storage unit method, a four-level storage unit method, or a five-level storage unit method.