Conversion and storage data unit and storage device of flag set and operating method thereof

Abstract

The disclosure provides a storage device and an operating method thereof. The storage device can generate a conversion flag based on a first flag set including N first flags respectively corresponding to N data units and a second flag set including N second flags respectively corresponding to the N data units, store at least one of a) one or more target data units among the N data units, b) the first flag set, and c) the second flag set in a data area, and store the conversion flag in a flag area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0034324, filed on March 18, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a storage device for converting and storing data units and flag sets, and a method of operating the same. Background Technology

[0004] A storage device is a device that stores data in response to requests from external devices such as computers, mobile terminals (e.g., smartphones or tablets).

[0005] A storage device may include a memory for storing data and a controller for controlling the memory. The memory may be volatile or non-volatile. The controller may receive commands from an external device (i.e., a host) and execute or control operations according to the received commands to read, write, or erase data in the memory contained in the storage device.

[0006] Storage devices can write data to memory in units of a preset page size (e.g., 4KB). However, external devices may send read and write requests to the storage device for data units smaller than the page size (e.g., 512 bytes).

[0007] Therefore, in order to handle read and write requests for data units, storage devices need to manage information about the data units contained in a page separately through additional data. Summary of the Invention

[0008] The embodiments of this disclosure are intended to provide a storage device and a method of operation thereof, which can efficiently store additional data for managing information related to data units requested to be written by a host.

[0009] The advantages of the embodiments disclosed herein are not limited to those described herein, and those skilled in the art will understand other unmentioned advantages from the following description.

[0010] In embodiments of this disclosure, a storage device may include: a memory including a data region and a flag region corresponding to the data region; and a controller configured to generate a transition flag based on a first flag set and a second flag set, the first flag set including N first flags respectively corresponding to N data units, the second flag set including N second flags respectively corresponding to N data units, where N is a natural number of 2 or greater; storing at least one of the following in the data region: a) one or more target data units among the N data units, b) the first flag set, and c) the second flag set; and storing the transition flag in the flag region.

[0011] In embodiments of this disclosure, a method of operating a storage device may include: generating a first set of flags and a second set of flags, the first set of flags including N first flags corresponding to N data units, and the second set of flags including N second flags corresponding to N data units, where N is a natural number of 2 or greater; generating a conversion flag based on the first set of flags and the second set of flags; storing at least one of the following in a data area: a) one or more target data units among the N data units, b) the first set of flags, and c) the second set of flags; and storing the conversion flag in a flag area corresponding to the data area.

[0012] In embodiments of this disclosure, a storage device may include: a data region; and a flag region configured to store metadata corresponding to data stored in the data region. The storage device is configured to: generate a first flag set and a second flag set, the first flag set including N first flags corresponding to N data units, and the second flag set including N second flags corresponding to N data units, where N is a natural number of 2 or greater; generate a conversion flag based on the first flag set and the second flag set; store at least one of the following in the data region: a) one or more target data units among the N data units, b) the first flag set, and c) the second flag set; and store the conversion flag in the flag region corresponding to the data region.

[0013] According to embodiments of this disclosure, the storage device can efficiently store additional data for managing information related to data units requested to be written by the host.

[0014] The advantages of the embodiments disclosed herein are not limited to those described above, and other advantages will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0015] The embodiments of this disclosure will be more fully understood through the following detailed description and accompanying drawings, which are for illustrative purposes only and are not intended to limit the embodiments.

[0016] Figure 1This is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0017] Figure 2 It is shown schematically. Figure 1 A block diagram of the memory in the memory.

[0018] Figure 3 This is a diagram illustrating the schematic operation of a storage device according to an embodiment of the present disclosure.

[0019] Figure 4 This is a diagram illustrating the operation of a storage device determining a first set of flags according to an embodiment of the present disclosure.

[0020] Figure 5 This is a diagram illustrating the operation of a storage device determining a second set of flags according to an embodiment of the present disclosure.

[0021] Figure 6 This is a flowchart describing the operation of a storage device determining the value of a conversion flag according to an embodiment of the present disclosure.

[0022] Figure 7 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure storing a first set of flags and a second set of flags in a data area.

[0023] Figure 8 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure storing a target data unit in a data area.

[0024] Figure 9 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure storing N data units in a data area.

[0025] Figure 10 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure to restore a first set of flags, a second set of flags, and N data units.

[0026] Figure 11 This is a diagram illustrating another operation of a storage device according to an embodiment of the present disclosure to restore a first set of flags, a second set of flags, and N data units.

[0027] Figure 12 This is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0028] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, the same reference numerals may be assigned even if the same component appears in different drawings. Details of known techniques or functions may be omitted when it is determined that the subject matter of the disclosure will be unclear. As used herein, when a component “comprises,” “has,” or “consistes of another component,” the component may include other components unless the word “only” is used before “comprises,” “has,” or “consistes of.” As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0029] Labels such as “first”, “second”, “A”, “B”, “(a)”, and “(b)” may be used to describe components of this disclosure. These labels are only used to distinguish one component from another, and the nature, order, or number of components is not limited by the labels.

[0030] When describing the positional relationship between components, when two or more components are described as “connected,” “linked,” or “linked,” these two or more components can be directly “connected,” “linked,” or “linked,” or another component can be situated between them. Here, the other component can be included in one or more of the two or more components that are “connected,” “linked,” or “linked” to each other.

[0031] When using terms such as “afterward,” “next,” “after,” and “before” to describe time flow relationships related to components, operating methods, and manufacturing methods, this may include discontinuous relationships unless the terms “immediately” or “directly” are also used.

[0032] When a component is specified with a value or its corresponding information (e.g., level), the value or corresponding information can be interpreted as including tolerances due to various factors (e.g., process factors, internal or external influences, or noise).

[0033] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0035] Reference Figure 1 The storage device 100 may include a memory 110 for storing data and a controller 120 for controlling the memory 110.

[0036] The memory 110 may include multiple memory blocks and operates under the control of the controller 120. The operation of the memory 110 may include, for example, read operations, programming operations (also known as write operations), and erase operations.

[0037] The memory 110 may include a memory cell array that includes a plurality of memory cells (also simply referred to as "cells") for storing data.

[0038] For example, memory 110 can be implemented in various types of memory such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, 3D NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), and Spin-Transfer Torque Random Access Memory (STT-RAM).

[0039] The memory 110 can be implemented as a three-dimensional array structure. For example, embodiments of this disclosure can be applied to charge-trapped flash memory (CTF) in which the charge storage layer is composed of a dielectric layer and to flash memory in which the charge storage layer is composed of a conductive floating gate.

[0040] The memory 110 can receive commands and addresses from the controller 120 and can access the region in the memory cell array selected by the address. The memory 110 can perform operations instructed by commands on the region selected by the address.

[0041] The memory 110 can perform programming, reading, or erasing operations. For example, when performing a programming operation, the memory 110 can program data into a region selected by an address. When performing a reading operation, the memory 110 can read data from the region selected by an address. In an erasing operation, the memory 110 can erase the data stored in the region selected by an address.

[0042] The controller 120 can control write (programming) operations, read operations, erase operations, and background operations on the memory 110. For example, background operations may include at least one of garbage collection (GC) operations, wear leveling (WL) operations, read reclamation (RR) operations, bad block management (BBM) operations, etc.

[0043] The controller 120 may control the operation of the memory 110 based on requests from a device located outside the storage device 100 (e.g., a host). However, the controller 120 may also control the operation of the memory 110 regardless of requests from the host.

[0044] As a non-limiting example, the host can be a computer, a supermobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device constituting a data center, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, and a mobile device capable of being driven or autonomously controlled by a human (e.g., a vehicle, robot, or drone). Optionally, the host can be a virtual reality (VR) device that provides 2D or 3D virtual reality images, or an augmented reality (AR) device that provides augmented reality images. The host can be any of the various electronic devices that require a storage device 100 capable of storing data.

[0045] The host may include at least one operating system (OS). The operating system typically manages and controls the host's functions and operations, and controls the interoperability between the host and storage device 100. Based on the host's mobility, operating systems can be categorized into general-purpose operating systems and mobile operating systems.

[0046] The controller 120 and the host can be separate devices, or they can be integrated into a single device. For convenience, the following description will treat the controller 120 and the host as separate devices.

[0047] Reference Figure 1 The controller 120 may include a memory interface 122 and a control circuit 123, and may further include a host interface 121.

[0048] Host interface 121 may provide an interface for communicating with a host. For example, host interface 121 may provide an interface using at least one of the following communication standards or interfaces: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Electronic Integrated Drive (IDE) protocol, and proprietary protocols.

[0049] When receiving a command from the host, the control circuit 123 can receive the command through the host interface 121 and perform operations to process the received command.

[0050] The memory interface 122 can be connected to the memory 110 to provide an interface for communication with the memory 110. That is, the memory interface 122 can provide an interface between the memory 110 and the controller 120 under the control of the control circuit 123.

[0051] The control circuit 123 can perform general control operations of the controller 120 to control the operation of the memory 110. For this purpose, for example, the control circuit 123 may include at least one of a processor 124 and a working memory 125, and may optionally include an error detection and correction circuit (ECC circuit) 126.

[0052] The processor 124 can control the general operation of the controller 120 and can perform logical calculations. The processor 124 can communicate with the host through the host interface 121 and with the memory 110 through the memory interface 122.

[0053] Processor 124 can perform the logical operations required to execute the Flash Translation Layer (FTL) function. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the Flash Translation Layer. The Flash Translation Layer can receive logical block addresses and translate them into physical block addresses using a mapping table.

[0054] Depending on the mapping unit, there are various address mapping methods for the flash translation layer. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0055] Processor 124 can randomize data received from the host. For example, processor 124 can randomize data received from the host using a set randomization seed. The randomized data can be provided to memory 110 and programmed into the memory cell array of memory 110.

[0056] During a read operation, processor 124 can derandomize the data received from memory 110. For example, processor 124 can derandomize the data received from memory 110 using a derandomization seed. The derandomized data can then be output to the host.

[0057] Processor 124 can run firmware to control the operation of controller 120. That is, in order to control the general operation of controller 120 and perform logical calculations, processor 124 can run (drive) firmware loaded into working memory 125 at startup. Hereinafter, the operation of storage device 100 according to embodiments of the present disclosure will be described as implementing processor 124, which runs firmware in which the corresponding operations are defined.

[0058] Firmware is a program stored in storage device 100 that is to be run to drive storage device 100, and may include various functional layers. For example, firmware may include binary data in which code is defined for running the functional layers respectively.

[0059] For example, the firmware may include at least one of the following: a flash translation layer that performs the translation function between the logical address requested by the host to the storage device 100 and the physical address of the memory 110; a host interface layer (HIL) for analyzing the command requested by the host to the storage device 100 and transmitting the command to the flash translation layer; and a flash interface layer (FIL) for transmitting the command issued by the flash translation layer to the memory 110.

[0060] Such firmware can be loaded into working memory 125 from, for example, memory 110 or a separate non-volatile memory (e.g., ROM or NOR flash memory) located outside memory 110. Processor 124 may load all or part of the firmware into working memory 125 first when performing a boot operation after power-on.

[0061] Processor 124 can execute logical calculations defined in firmware loaded in working memory 125 to control the general operation of controller 120. Processor 124 can store the results of executing the logical calculations defined in the firmware in working memory 125. Processor 124 can control controller 120 based on the results of executing the logical calculations defined in the firmware, causing controller 120 to generate commands or signals. When a portion of the firmware defining the logical calculation to be executed is stored in memory 110 but not loaded into working memory 125, processor 124 can generate an event (e.g., an interrupt) to load the corresponding portion of the firmware from memory 110 into working memory 125.

[0062] The processor 124 can load the metadata required for the driver firmware from the memory 110. Metadata is data used to manage the memory 110, and may include, for example, management information about user data stored in the memory 110.

[0063] The firmware can be updated during the manufacture of storage device 100 or during operation of storage device 100. Controller 120 can download new firmware from outside storage device 100 and update existing firmware using the new firmware.

[0064] To drive controller 120, working memory 125 can store necessary firmware, program code, commands, and data. Working memory 125 can be volatile memory, for example, including at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). In addition to working memory 125, controller 120 can also use separate volatile memory (e.g., SRAM, DRAM) located outside controller 120.

[0065] The error detection and correction circuit 126 can detect error bits in the target data and correct the detected error bits using an error correction code. The target data can be, for example, data stored in the working memory 125 or data read from the memory 110.

[0066] The error detection and correction circuit 126 can decode data using error correction codes. The error detection and correction circuit 126 can be implemented using various code decoders. For example, a decoder that performs non-system code decoding or a decoder that performs system code decoding can be used.

[0067] For example, when each read data consists of multiple sectors, the error detection and correction circuit 126 can detect error bits in each of the read data on a sector-by-sector basis. A sector can refer to a data unit smaller than a page, which is the read unit of flash memory. The sectors that make up each read data can be matched with each other using addresses.

[0068] The error detection and correction circuit 126 can calculate the bit error rate (BER) on a sector-by-sector basis and determine whether an error is correctable. For example, when the bit error rate is higher than a reference value, the error detection and correction circuit 126 can determine that the corresponding sector is uncorrectable or has failed. On the other hand, when the bit error rate is lower than the reference value, the error detection and correction circuit 126 can determine that the corresponding sector is correctable or has passed.

[0069] Error detection and correction circuit 126 can sequentially perform error detection and correction operations on all read data. If a sector in the read data is correctable, error detection and correction circuit 126 can omit error detection and correction operations for the corresponding sector in the next read data. When error detection and correction operations for all read data are completed in this manner, error detection and correction circuit 126 can detect uncorrectable sectors in the last read data. There may be one or more sectors determined to be uncorrectable. Error detection and correction circuit 126 can transmit information about the determined uncorrectable sectors (e.g., address information) to processor 124.

[0070] Bus 127 can provide a channel between components 121, 122, 124, 125, and 126 of controller 120. Bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., and a data bus for transmitting various data.

[0071] Some of the components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into one component. In addition to the components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0072] In the following text, reference will be made to Figure 2 The memory 110 is described in more detail.

[0073] Figure 2 It is shown schematically. Figure 1 Block diagram of memory 110 in the memory.

[0074] Reference Figure 2 According to embodiments of the present disclosure, the memory 110 may include a memory cell array 210, an address decoder 220, a read and write circuit 230, control logic 240, and a voltage generation circuit 250.

[0075] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number of 2 or greater.

[0076] Multiple word lines WL and multiple bit lines BL can be set in multiple memory blocks BLK1 to BLKz, and multiple memory cells can be arranged.

[0077] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 230 via multiple bit lines BL.

[0078] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be configured with non-volatile memory cells having a vertical channel structure.

[0079] The memory cell array 210 can be configured as a two-dimensional memory cell array or a three-dimensional memory cell array.

[0080] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) storing one bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) storing two bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) storing three bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) storing four bits of data. In yet another example, the memory cell array 210 may include a plurality of memory cells, each storing five or more bits of data.

[0081] The number of bits of data stored in each of multiple memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a three-level cell storing 3 bits of data.

[0082] Reference Figure 2 The address decoder 220, read and write circuit 230, control logic 240 and voltage generation circuit 250 can be operated as peripheral circuits to drive the memory cell array 210.

[0083] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0084] The address decoder 220 can operate under the control of the control logic 240.

[0085] Address decoder 220 can receive addresses through input / output buffers in memory 110. Address decoder 220 can decode the block address in the received address. Address decoder 220 can select at least one memory block based on the decoded block address.

[0086] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0087] During a read operation, the address decoder 220 can apply a read voltage Vread to a selected word line WL in a selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0088] In the programming verification operation, the address decoder 220 can apply the verification voltage generated in the voltage generation circuit 250 to the selected word line WL in the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0089] Address decoder 220 can decode the column address in the received address. Address decoder 220 can transmit the decoded column address to read and write circuit 230.

[0090] Read and programming operations on memory 110 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include at least one of a block address, a row address, and a column address.

[0091] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read and write circuitry 230.

[0092] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0093] The read and write circuitry 230 may include multiple page buffers PB. The read and write circuitry 230 may operate as a read circuit in the read operation of the memory cell array 210 and as a write circuit in the write operation of the memory cell array 210.

[0094] The aforementioned read and write circuit 230 can also be referred to as a page buffer circuit or a data register circuit that includes multiple page buffers PB. The read and write circuit 230 may include a data buffer responsible for data processing functions, and may also include a cache buffer responsible for caching functions.

[0095] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. During read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cells according to the programming state of the corresponding memory cells, so as to sense the threshold voltage (Vth) of the memory cells, and can latch the sensed data by sensing the change in the current flow of the sensing nodes.

[0096] The read and write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0097] During a read operation, the read and write circuit 230 temporarily stores the read data by sensing data in the memory cell, and then outputs the data DATA to the input / output buffer of the memory 110. In an embodiment, in addition to the page buffer PB or the page register, the read and write circuit 230 may also include a column select circuit.

[0098] Control logic 240 can be connected to address decoder 220, read and write circuitry 230, and voltage generation circuitry 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory 110.

[0099] Control logic 240 can respond to the control signal CTRL to control the general operation of memory 110. Control logic 240 can output control signals to adjust the precharge potential level of the sensing nodes of multiple page buffers PB.

[0100] Control logic 240 can control read and write circuit 230 to perform read operations on memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass for read operations in response to voltage generation circuit control signals output from control logic 240.

[0101] Each memory block of the aforementioned memory 110 may consist of multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0102] In a memory block BLK, multiple word lines (WL) and multiple bit lines (BL) can be arranged intersecting each other. For example, each of the multiple word lines (WL) can be arranged along the row direction, and each of the multiple bit lines (BL) can be arranged along the column direction. In another embodiment, each of the multiple word lines (WL) can be arranged along the column direction, and each of the multiple bit lines (BL) can be arranged along the row direction.

[0103] A memory cell can be connected to one of multiple word lines (WL) and multiple bit lines (BL). Each memory cell can contain a transistor.

[0104] For example, the transistor disposed in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected to the corresponding bit line BL directly or via another transistor. The source (or drain) of the transistor may be connected to the source line (which may be ground) directly or via another transistor. The gate of the transistor may include a floating gate and a control gate, the floating gate being surrounded by a dielectric, and a gate voltage being applied from the word line WL to the control gate.

[0105] In each memory block, a first select line (also referred to as a source select line or drain select line) may be additionally provided outside the first outermost word line closer to the read and write circuit 230 between the two outermost word lines, and a second select line (also referred to as a drain select line or source select line) may be additionally provided outside the second outermost word line between the two outermost word lines.

[0106] At least one dummy word line may be additionally provided between the first outermost word line and the first selection line. At least one dummy word line may also be additionally provided between the second outermost word line and the second selection line.

[0107] The read and program (write) operations of the aforementioned storage blocks can be performed on a page-by-page basis, and the erase operation can be performed on a block-by-block basis.

[0108] Figure 3 This is a diagram illustrating the schematic operation of a storage device 100 according to an embodiment of the present disclosure.

[0109] Reference Figure 3 The storage device 100 may include a memory 110 and a controller 120.

[0110] The memory 110 may include a data area DATA_AREA and a flag area FLG_AREA corresponding to the data area DATA_AREA.

[0111] A data area (DATA_AREA) is a region capable of storing data. For example, a data area (DATA_AREA) may include one or more storage blocks. Alternatively, a data area (DATA_AREA) may include one or more pages. A data area (DATA_AREA) can store a preset size of data (e.g., 4KB).

[0112] The flag region FLG_AREA is a region capable of storing flags corresponding to the data stored in the data region DATA_AREA. For example, the flag region FLG_AREA can be a region storing metadata corresponding to the data stored in the data region DATA_AREA. As another example, the flag region FLG_AREA can be a dedicated storage block allocated among the multiple storage blocks included in the memory 110 for storing flags.

[0113] The controller 120 can determine the data to be stored in the data area DATA_AREA and the flag area FLG_AREA based on N data units DU, the first flag set FLG1_SET and the second flag set FLG2_SET, where N is a natural number of 2 or greater.

[0114] Each of the N data units DU can be data with a preset size (e.g., 512 bytes). A data unit can be the smallest unit of data requested to be read or written from outside the storage device 100 (e.g., a host). A data unit can also be referred to by terms such as sector or segment.

[0115] At least one of the N data units DU can be included in a data block. The unit size of the data to be written to the data area DATA_AREA can be the size of the data block. The data units included in a data block can be written to the data area DATA_AREA at once and can be read from the data area DATA_AREA at once.

[0116] For example, eight data units (DUs) of size 512 bytes each can form a 4KB data block. A 4KB data block can be written to the data area DATA_AREA in one go, and the 4KB data block stored in the data area DATA_AREA can be read in one go.

[0117] The first flag set FLG1_SET may include N first flags FLG1 corresponding to N data units DU respectively. For example, each first flag FLG1 may be 1 bit data (1 or 0), and the first flag set FLG1_SET may be an N-bit bitmap (e.g., 0b11111111).

[0118] For example, the value of the first flag FLG1 can be a first value (e.g., 1) or a second value (e.g., 0). The first value and the second value are different from each other.

[0119] The second flag set FLG2_SET can include N second flags FLG2, each corresponding to one of the N data units DU. For example, each second flag FLG2 can be a 1-bit data (1 or 0), and the second flag set FLG2_SET can be an N-bit bitmap (e.g., 0b11111111).

[0120] For example, the value of the second flag FLG2 can be a third value (e.g., 1) or a fourth value (e.g., 0). The third and fourth values ​​are different from each other. The third value can be the same as one of the first and second values, and the fourth value can be the same as the other of the first and second values.

[0121] The controller 120 can determine the transition flag CONV_FLG based on the first flag set FLG1_SET and the second flag set FLG2_SET. The size of the transition flag CONV_FLG can be less than the sum of the sizes of the first flag set FLG1_SET and the second flag set FLG2_SET.

[0122] For example, controller 120 can generate a 1-bit transition flag CONV_FLG based on an 8-bit first flag set FLG1_SET and an 8-bit second flag set FLG2_SET. For example, when the result of performing an AND operation between the 8-bit first flag set FLG1_SET and the 8-bit second flag set FLG2_SET is the same as a reference value (e.g., 0xFF), controller 120 can determine that the transition flag CONV_FLG is 1, and when the result is different from the reference value, controller 120 can determine that the transition flag CONV_FLG is 0.

[0123] The controller 120 may store at least one of the following in the data area DATA_AREA: 1) one or more target data units TGT_DU among N data units DU; 2) a first flag set FLG1_SET; 3) a second flag set FLG2_SET.

[0124] Controller 120 can store the conversion flag CONV_FLG in the flag area FLG_AREA.

[0125] In embodiments of this disclosure, a first flag set FLG1_SET and a second flag set FLG2_SET can be determined based on the characteristics of N data units DU. Referring below... Figure 4 and Figure 5 Provide a detailed description.

[0126] Figure 4 This is a diagram illustrating the operation of a storage device 100 determining a first flag set FLG1_SET according to an embodiment of the present disclosure.

[0127] In embodiments of this disclosure, the controller 120 of the storage device 100 may set the value of a first flag FLG1 corresponding to a data unit among N data units DU that is requested to be written from outside the storage device 100 (e.g., a host) to a first value VAL_1. The data unit requested to be written from outside the storage device 100 may be read from outside the storage device 100. The data unit requested to be written from outside the storage device 100 may be referred to as a valid data unit.

[0128] The controller 120 can set the value of the first flag FLG1 corresponding to a data unit among the N data units DU that is not requested to be written from outside the storage device 100 to the second value VAL_2. Data units not requested to be written from outside the storage device 100 will not subsequently be read from outside the storage device 100 and therefore do not need to be stored in the data area DATA_AREA. Data units not requested to be written from outside the storage device 100 can also be referred to as dummy data units or invalid data units.

[0129] exist Figure 4 In this context, the values ​​of the first flags FLG1#1 and FLG1#N-1, which correspond to the data units DU#1 and DU#N-1 requested to be written from outside the storage device 100, are respectively the first value VAL_1.

[0130] The values ​​of the first flags FLG1#2 and FLG1#N, which are respectively associated with data units DU#2 and DU#N that are not requested to be written from outside the storage device 100, are the second value VAL_2.

[0131] Figure 5 This is a diagram illustrating the operation of a storage device 100 determining a second flag set FLG2_SET according to an embodiment of the present disclosure.

[0132] In embodiments of this disclosure, the controller 120 of the storage device 100 may set the value of the second flag FLG2 corresponding to a data unit among N data units DU that does not require a failed response to a read request from outside the storage device 100 (e.g., a host) to a third value VAL_3. In this case, the storage device 100 should store the corresponding data unit in the data area DATA_AREA, and when a read operation on the corresponding data unit is performed normally, it should send a successful read response to the outside of the storage device 100.

[0133] Data units that do not require a failed response to read requests from outside the storage device 100 can be referred to as correctable data units.

[0134] The controller 120 can set the value of the second flag FLG2, corresponding to the data unit among the N data units DU that must respond to a failed read request from outside the storage device 100, to the fourth value VAL_4. In this case, regardless of the read operation on the corresponding data unit, the storage device 100 should respond to the outside of the storage device 100. Therefore, the storage device 100 does not need to store the corresponding data unit in the data area DATA_AREA.

[0135] Data units that must respond to read requests from outside the storage device 100 in a failed manner can be referred to as uncorrectable data units.

[0136] exist Figure 5 In this context, the values ​​of the second flags FLG2#1 and FLG2#N-1, which correspond to data units DU#1 and DU#N-1 respectively, are the third value VAL_3. For data units DU#1 and DU#N-1, there is no need to respond to read requests from outside the storage device 100 with failure.

[0137] The values ​​of the second flags FLG2#2 and FLG2#N, which correspond to data units DU#2 and DU#N respectively, are the fourth value VAL_4. For data units DU#2 and DU#N, a failure response must be made for read requests from outside the storage device 100.

[0138] Figure 6 This is a flowchart describing the operation of a storage device 100 determining the value of the conversion flag CONV_FLG according to an embodiment of the present disclosure.

[0139] exist Figure 6 In the process, the controller 120 of the storage device 100 determines whether there is a first flag among the N first flags FLG1 that is set to the second value VAL_2 (operation S610).

[0140] When a first flag is set to the second value VAL_2 (i.e., "yes" in operation S610), the controller 120 can determine that the value of the transition flag CONV_FLG is the first transition flag value (operation S620).

[0141] On the other hand, when there is no first flag set to the second value VAL_2 (i.e., "No" in operation S610), the controller 120 determines whether there is a second flag set to the fourth value VAL_4 among the N second flags FLG2 (operation S630).

[0142] When a second flag is set to the fourth value VAL_4 (i.e., "yes" in operation S630), the controller 120 can determine that the value of the transition flag CONV_FLG is the first transition flag value (S620).

[0143] On the other hand, when there is no second flag set to the fourth value VAL_4 (i.e., "No" in operation S630), the controller 120 can determine that the value of the conversion flag CONV_FLG is the second conversion flag value (operation S640).

[0144] In other words, when there is at least one of the N first flags FLG1 that is set to the second value VAL_2 and the N second flags FLG2 that is set to the fourth value VAL_4, the controller 120 can determine that the value of the transition flag CONV_FLG is the first transition flag value.

[0145] When at least one of the first flags set to the second value VAL_2 and the second flag set to the fourth value VAL_4 exists, there are data units among the N data units DU that do not need to be stored in the data area DATA_AREA. Therefore, a portion of the data area DATA_AREA can be used to store other information instead of the corresponding data units.

[0146] When all N first flags FLG1 are equal to the first value VAL_1, and all N second flags FLG2 are equal to the third value VAL_3, the controller 120 can determine that the value of the transition flag CONV_FLG is the second transition flag value.

[0147] In this case, the first flag set FLG1_SET and the second flag set FLG2_SET can be restored based on the conversion flag CONV_FLG. This is because the values ​​of the N first flags FLG1 included in the first flag set FLG1_SET are all fixed to the first value VAL_1, and the values ​​of the N second flags FLG2 included in the second flag set FLG2_SET are all fixed to the third value VAL_3.

[0148] The size of the transition flag CONV_FLG is less than the sum of the sizes of the first flag set FLG1_SET and the second flag set FLG2_SET. Therefore, by storing the transition flag CONV_FLG instead of storing the first flag set FLG1_SET and the second flag set FLG2_SET, the controller 120 can save storage space in the memory 110.

[0149] For example, when the size of the first flag set FLG1_SET is 8 bits and the size of the second flag set FLG2_SET is 8 bits, the controller 120 can reduce the size of the storage space to be used from 16 bits to 1 bit by storing a 1-bit conversion flag CONV_FLG in memory 110.

[0150] In the following description, storage device 100 will store at least one of the following into data area DATA_AREA according to the value of conversion flag CONV_FLG: a) one or more target data units TGT_DU among N data units DU; b) a first flag set FLG1_SET; c) a second flag set FLG2_SET.

[0151] Figure 7 This is a diagram illustrating the operation of a storage device 100 according to an embodiment of the present disclosure storing a first flag set FLG1_SET and a second flag set FLG2_SET in a data area DATA_AREA.

[0152] Reference Figure 7 The data area DATA_AREA can include N sub-areas SUB_AREA. The size of each sub-area can be the same as the size of the data unit DU (e.g., 512 bytes).

[0153] When the value of the transition flag CONV_FLG is the first transition flag value CONV_FLG_VAL1, the controller 120 of the storage device 100 can store the first flag set FLG1_SET and the second flag set FLG2_SET in one of the N sub-regions SUB_AREA.

[0154] As described above, when the value of the transition flag CONV_FLG is the first transition flag value CONV_FLG_VAL1, a portion of the data area DATA_AREA can be used to store other information. Therefore, the controller 120 can use a sub-area that is part of the data area DATA_AREA to store the first flag set FLG1_SET and the second flag set FLG2_SET.

[0155] Therefore, the controller 120 does not need to use an area other than the data area DATA_AREA to store the first flag set FLG1_SET and the second flag set FLG2_SET. Therefore, since no separate storage space is needed to store the first flag set FLG1_SET and the second flag set FLG2_SET, storage space in the memory 110 can be saved.

[0156] The controller 120 may additionally store other information in the sub-regions storing the first flag set FLG1_SET and the second flag set FLG2_SET. For example, the controller 120 may additionally store parity information related to the data units to be stored in the data area DATA_AREA in the corresponding sub-regions. As another example, the controller 120 may additionally store the number of data units to be stored in the data area DATA_AREA in the corresponding sub-regions.

[0157] For example, controller 120 can store the first flag set FLG1_SET and the second flag set FLG2_SET in the first sub-region of N sub-regions SUB_AREA.

[0158] Figure 8 This is a diagram illustrating the operation of a storage device 100 according to an embodiment of the present disclosure storing a target data unit TGT_DU in a data area DATA_AREA.

[0159] Reference Figure 8When the conversion flag CONV_FLG is set to the first conversion flag value CONV_FLG_VAL1, the controller 120 of the storage device 100 can store the target data unit TGT_DU in the Kth sub-region and subsequent sub-regions of the data area DATA_AREA, where K is a natural number less than or equal to N and greater than or equal to 2. This is because, as described above, the first sub-region SUB_AREA among the N sub-regions is used to store the first flag set FLG1_SET and the second flag set FLG2_SET.

[0160] At this time, the value of the first flag FLG1 corresponding to each of the target data units TGT_DUs is the first value VAL_1, and the value of the second flag FLG2 corresponding to each of the target data units TGT_DUs is the third value VAL_3. The target data unit TGT_DU is the data unit that needs to be responded to normally in response to read requests from outside the storage device 100.

[0161] Figure 9 This is a diagram illustrating the operation of a storage device 100 according to an embodiment of the present disclosure storing N data units DU in a data area DATA_AREA.

[0162] Reference Figure 9 When the conversion flag CONV_FLG is set to the second conversion flag value CONV_FLG_VAL2, the controller 120 of the storage device 100 can store all N data units DU in the data area DATA_AREA. This is because, in response to a read request from outside the storage device 100, all N data units DU should be processed normally.

[0163] At this time, the aforementioned first flag set FLG1_SET and second flag set FLG2_SET are not stored in the data area DATA_AREA. This is because, as described above, based on the fact that the value of the transition flag CONV_FLG is the second transition flag value CONV_FLG_VAL2, the controller 120 can recognize that the values ​​of the N first flags FLG1 included in the first flag set FLG1_SET are all fixed to the first value VAL_1, and the values ​​of the N second flags FLG2 included in the second flag set FLG2_SET are all fixed to the third value VAL_3.

[0164] The above describes the storage device 100 storing at least one of the following in the data area DATA_AREA: a) one or more target data units TGT_DU among N data units DU, b) a first flag set FLG1_SET, and c) a second flag set FLG2_SET.

[0165] Figures 7 to 9The operations disclosed herein can be performed by a hardware accelerator contained in the storage device 100 instead of the controller 120.

[0166] The following describes the operation of the storage device 100 in restoring the first flag set FLG1_SET, the second flag set FLG2_SET, and N data units DU based on the data stored in the data area DATA_AREA and the flag area FLG_AREA.

[0167] Figure 10 This is a diagram illustrating the operation of a storage device 100 according to an embodiment of the present disclosure to restore a first flag set FLG1_SET, a second flag set FLG2_SET, and N data units DU.

[0168] Reference Figure 10 When the value of the transition flag CONV_FLG stored in the flag region FLG_AREA is the first transition flag value CONV_FLG_VAL1, the controller 120 of the storage device 100 can read the first flag set FLG1_SET and the second flag set FLG2_SET from a specific sub-region (e.g., the first sub-region) of the N sub-regions SUB_AREA included in the data region DATA_AREA. The corresponding sub-region stores the first flag set FLG1_SET and the second flag set FLG2_SET, instead of storing data units.

[0169] Based on the first flag set FLG1_SET and the second flag set FLG2_SET, the controller 120 can read the target data unit TGT_DU stored in the data area DATA_AREA. The number of target data units TGT_DU stored in the data area DATA_AREA can be determined based on the first flag set FLG1_SET and the second flag set FLG2_SET.

[0170] For example, the value of the first flag FLG1 corresponding to each of the target data units TGT_DU stored in the data area DATA_AREA is the first value VAL_1, and the value of the second flag FLG2 corresponding to each of the target data units TGT_DU stored in the data area DATA_AREA is the third value VAL_3.

[0171] Therefore, for a natural number I from 1 to N, the controller 120 can determine whether the condition that the value of the first flag is the first value VAL_1 and the value of the second flag is the third value VAL_3 is met. The controller 120 can determine that the number of natural numbers from 1 to N that meet the corresponding condition is the number of target data units TGT_DU stored in the data area DATA_AREA.

[0172] The controller 120 can generate N data units DU based on the first flag set FLG1_SET, the second flag set FLG2_SET, and the target data unit TGT_DU. Each of the N data units DU can be a target data unit read from the data area DATA_AREA or a dummy data unit.

[0173] The i-th data unit among N data units DU can be determined as a target data unit or a dummy data unit based on the first flag set FLG1_SET and the second flag set FLG2_SET, where i is a natural number of N or smaller.

[0174] When the value of the first flag is the first value VAL_1 and the value of the second flag is the third value VAL_3, the first data unit among the N data units DU is determined as the target data unit. On the other hand, when the value of the first flag is the second value VAL_2 and / or the value of the second flag is the fourth value VAL_4, the first data unit among the N data units DU is determined as a dummy data unit.

[0175] Figure 11 This is a diagram illustrating another operation of a storage device 100 according to an embodiment of the present disclosure to restore a first flag set FLG1_SET, a second flag set FLG2_SET, and N data units DU.

[0176] Reference Figure 11 When the value of the conversion flag CONV_FLG stored in the flag area FLG_AREA is the second conversion flag value CONV_FLG_VAL2, the controller 120 of the storage device 100 can read N data units DU from the data area DATA_AREA.

[0177] The controller 120 can generate a first flag set FLG1_SET and a second flag set FLG2_SET. The first flag set FLG1_SET contains the first flag FLG1 with the value of the first value VAL_1, and the second flag set FLG2_SET contains the second flag FLG2 with the value of the third value VAL_3.

[0178] Figure 11 and Figure 12 The operations disclosed in the storage device 100 can also be performed by a hardware accelerator included in the storage device 100 instead of the controller 120.

[0179] Figure 12 This is a diagram illustrating an operation method of a storage device 100 according to an embodiment of the present disclosure.

[0180] Reference Figure 12The method 1200 for operating the storage device 100 may include operation S1210, generating: a first flag set FLG1_SET, which includes N first flags FLG1, each corresponding to N data units DU, where N is a natural number of 2 or greater; and a second flag set FLG2_SET, which includes N second flags FLG2, each corresponding to N data units DU.

[0181] The value of each first flag FLG1 can be either the first value VAL_1 or the second value VAL_2. The value of each second flag FLG2 can be either the third value VAL_3 or the fourth value VAL_4.

[0182] For example, operation S1210 can set the value of the first flag FLG1 corresponding to the data unit among the N data units DU that is requested to be written from the outside of the storage device 100 to the first value VAL_1, and can set the value of the first flag FLG1 corresponding to the data unit among the N data units DU that is not requested to be written from the outside of the storage device 100 to the second value VAL_2.

[0183] For example, operation S1210 can set the value of the second flag FLG2 corresponding to the data unit among the N data units DU that does not need to fail to respond to read requests from outside the storage device 100 to the third value VAL_3, and can set the value of the second flag FLG2 corresponding to the data unit among the N data units DU that must fail to respond to read requests from outside the storage device 100 to the fourth value VAL_4.

[0184] The method 1200 for operating the storage device 100 may include operation S1220, generating a transition flag CONV_FLG based on a first flag set FLG1_SET and a second flag set FLG2_SET.

[0185] For example, when there is at least one of the N first flags FLG1 that is set to the second value VAL_2 and the N second flags FLG2 that is set to the fourth value VAL_4, operation S1220 can determine the value of the conversion flag CONV_FLG as the first conversion flag value CONV_FLG_VAL1; and when the values ​​of all N first flags FLG1 are the first value VAL_1 and the values ​​of all N second flags FLG2 are the third value VAL_3, operation S1220 can determine the value of the conversion flag CONV_FLG as the second conversion flag value CONV_FLG_VAL2.

[0186] The method 1200 of operating the storage device 100 may include operation S1230, storing at least one of the following in the data area DATA_AREA: a) one or more target data units TGT_DU of N data units DU, b) a first flag set FLG1_SET and c) a second flag set FLG2_SET.

[0187] For example, the data area DATA_AREA may include N sub-areas SUB_AREA. When the value of the conversion flag CONV_FLG is the first conversion flag value CONV_FLG_VAL1, operation S1230 can store the first flag set FLG1_SET and the second flag set FLG2_SET in one of the N sub-areas SUB_AREA. The first flag set FLG1_SET and the second flag set FLG2_SET can be stored in the first sub-area among the N sub-areas SUB_AREA.

[0188] The target data unit TGT_DU can be stored in the Kth sub-region and subsequent sub-regions of the data area DATA_AREA, where K is a natural number N or smaller. In this case, the value of the first flag FLG1 corresponding to each target data unit TGT_DU can be the first value VAL_1, and the value of the second flag FLG2 corresponding to each target data unit TGT_DU can be the third value VAL_3.

[0189] For example, when the value of the conversion flag CONV_FLG is the second conversion flag value CONV_FLG_VAL2, operation S1230 can store all N data units DU in the data area DATA_AREA.

[0190] The method 1200 of operating the storage device 100 may include operation S1240, storing the conversion flag CONV_FLG in the flag area FLG_AREA corresponding to the data area DATA_AREA.

[0191] For example, the flag region FLG_AREA can be a region that stores metadata corresponding to the data stored in the data region DATA_AREA.

[0192] Although embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not intended to limit the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted in conjunction with the appended claims and cover all equivalents within the scope of the appended claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: The memory includes a data area and a flag area corresponding to the data area; as well as Controller: A conversion flag is generated based on a first flag set and a second flag set. The first flag set includes N first flags corresponding to N data units respectively, and the second flag set includes N second flags corresponding to the N data units respectively, where N is a natural number of 2 or greater. Store one or more target data units from the N data units, b) the first flag set, and c) at least one item from the second flag set in the data area; as well as The conversion flag is stored in the flag area.

2. The storage device according to claim 1, wherein, When each of the N first flags has a first value or a second value, the controller: Set the value of the first flag corresponding to the data unit among the N data units that is requested to be written from outside the storage device to the first value; and The value of the first flag corresponding to the data unit among the N data units that is not requested to be written from outside the storage device is set to the second value.

3. The storage device according to claim 1, wherein, When each of the N second flags has a third or fourth value, the controller: The value of the second flag corresponding to the data unit among the N data units that does not require a failure response to a read request from outside the storage device is set to the third value, and The value of the second flag corresponding to the data unit among the N data units that needs to fail to respond to a read request from outside the storage device is set to the fourth value.

4. The storage device according to claim 1, wherein, When each of the N first flags has a first value or a second value, and each of the N second flags has a third value or a fourth value, the controller: In response to determining that at least one of the N first flags is set to the second value and the N second flags is set to the fourth value, the value of the transition flag is determined as a first transition flag value; as well as In response to determining that all N first flags have the first value and all N second flags have the third value, the value of the conversion flag is determined as the second conversion flag value.

5. The storage device according to claim 4, in, The data area comprises N sub-regions, and Wherein, when the conversion flag has the first conversion flag value, the controller stores the first flag set and the second flag set in one of the N sub-regions.

6. The storage device according to claim 5, wherein, The controller stores the first flag set and the second flag set in the first sub-region of the N sub-regions.

7. The storage device according to claim 6, wherein, The controller stores the target data unit in the Kth sub-region and subsequent sub-regions of the data region, where K is a natural number of N or less, and K is greater than or equal to 2. The first flag corresponding to each target data unit has the first value, and The second flag corresponding to each target data unit has the third value.

8. The storage device according to claim 4, wherein, When the conversion flag has the second conversion flag value, the controller stores all N data units in the data area.

9. The storage device according to claim 1, wherein, The flag area stores metadata corresponding to the data stored in the data area.

10. A method of operating a storage device, the method comprising: Generate a first flag set and a second flag set. The first flag set includes N first flags corresponding to N data units, and the second flag set includes N second flags corresponding to the N data units, where N is a natural number of 2 or greater. Generate a transition flag based on the first flag set and the second flag set; Store one or more target data units from the N data units, b) the first flag set, and c) at least one item from the second flag set in the data area; as well as The conversion flag is stored in the flag area corresponding to the data area.

11. The operating method according to claim 10, wherein, Each of the N first flags has a first value or a second value, and Generating the first flag set and the second flag set includes: Set the value of the first flag corresponding to the data unit among the N data units that is requested to be written from outside the storage device to the first value; and The value of the first flag corresponding to the data unit among the N data units that is not requested to be written from outside the storage device is set to the second value.

12. The operating method according to claim 10, wherein, Each of the N second flags has a third or fourth value, and Generating the first flag set and the second flag set includes: Set the value of the second flag corresponding to the data unit among the N data units that does not require a failure response to read requests from outside the storage device to the third value; and The value of the second flag corresponding to the data unit among the N data units that needs to fail to respond to a read request from outside the storage device is set to the fourth value.

13. The operating method according to claim 10, wherein, Each of the N first flags has a first value or a second value, and each of the N second flags has a third value or a fourth value. Generating the conversion flag includes: In response to determining that at least one of the N first flags is set to the second value and the N second flags is set to the fourth value, the value of the transition flag is determined as a first transition flag value; and In response to determining that all N first flags have the first value and all N second flags have the third value, the value of the conversion flag is determined as the second conversion flag value.

14. The operating method according to claim 13, wherein, The data area comprises N sub-regions, and Storing one or more target data units among the N data units, b) the first flag set, and c) at least one item of the second flag set in the data region includes: storing the first flag set and the second flag set in one of the N sub-regions according to the conversion flag having the first conversion flag value.

15. The operating method according to claim 14, wherein, The first set of flags and the second set of flags are stored in the first sub-region of the N sub-regions.

16. The operating method according to claim 15, wherein, The target data unit is stored in the Kth sub-region and subsequent sub-regions of the data region, where K is a natural number of N or less, and K is greater than or equal to 2. Wherein, the first flag corresponding to each target data unit has the first value, and The second flag corresponding to each target data unit has the third value.

17. The operating method according to claim 13, wherein, Storing one or more target data units from the N data units, b) the first flag set, and c) at least one item from the second flag set in the data area includes: storing all the N data units in the data area in response to determining that the transition flag has the second transition flag value.

18. The operating method according to claim 10, wherein, The flag area stores metadata corresponding to the data stored in the data area.

19. A storage device, comprising: Data area; as well as The flag area stores metadata corresponding to the data stored in the data area. Wherein, the storage device: Generate a first flag set and a second flag set. The first flag set includes N first flags corresponding to N data units, and the second flag set includes N second flags corresponding to the N data units, where N is a natural number of 2 or greater. Generate a transition flag based on the first flag set and the second flag set; Store one or more target data units from the N data units, b) the first flag set, and c) at least one item from the second flag set in the data area; and The conversion flag is stored in the flag area corresponding to the data area.

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