A life-aware thermal management method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a kind of life perception type thermal management method, device, electronic equipment and storage medium, involve solid state disk firmware temperature control technical field, wherein the method comprises: reading each Die real-time temperature data and statistics erase times, with Channel as unit to calculate average Die temperature and average erase times, utilize TLC block maximum erase times to set wear gradient, divide into low wear area, medium wear area and high wear area for whole life cycle, construct dynamic temperature threshold mathematical model, according to the model, with the basic frequency reduction temperature determined when opening card as starting point, the average erase times of each Channel is calculated in negative correlation and decreases, obtains the frequency reduction trigger temperature of each Channel special, compares the frequency reduction trigger temperature with average Die temperature in real time, only to the single Channel of temperature over standard executes frequency reduction, and restore high frequency operation after temperature falls to less than frequency reduction trigger temperature 5 DEG C.This application solves the problem that global temperature control of prior art seriously drags performance, lack of foresight.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive firmware temperature control technology, and in particular to a lifespan-aware thermal management method, device, electronic device, and storage medium. Background Technology

[0002] With the widespread adoption of solid-state drives (SSDs) in data centers, enterprise storage, and consumer electronics, NAND flash lifespan management and data reliability have become key factors affecting product performance. Die temperature can be obtained by reading the internal temperature register of the NAND flash, and the erase / write cycles (PE) value is calculated from firmware statistics, allowing for the calculation of the average die temperature and average erase / write cycles for each channel.

[0003] However, traditional SSD temperature control strategies typically employ a one-size-fits-all global threshold, such as throttling the entire drive when the temperature exceeds 85 degrees Celsius. This approach faces numerous challenges in practical applications. Traditional temperature control does not consider the non-linear characteristics of NAND Flash lifespan decay: the higher the number of erase / write cycles, the thinner the die oxide layer and the weaker the charge retention. Under the same high temperature, the probability of data flipping increases exponentially, and the global threshold cannot provide early protection for high PE dies. Furthermore, the workload of each channel within an SSD is often uneven, with dies closer to the controller generating more heat. If the overall drive frequency is reduced due to overheating of individual high PE dies, it will severely impact the overall I / O performance of the drive.

[0004] Furthermore, replacement of single or partial chips during after-sales repairs can cause significant gaps in the number of write cycles on the disk, and traditional temperature control cannot distinguish between the heat resistance differences between new and old dies. Moreover, traditional temperature control is a reactive measure and lacks the ability to proactively adjust based on the lifespan of the dies.

[0005] Therefore, there is an urgent need for a lifespan-aware thermal management method that can dynamically adjust temperature tolerance based on die health and achieve differentiated temperature control, maximizing performance while ensuring data reliability. Summary of the Invention

[0006] The present invention provides a lifetime-aware thermal management method to address the problems of existing technologies that employ global temperature control, fail to consider the nonlinear decay of NAND flash memory lifetimes, severely impact I / O performance, cannot distinguish between heat resistance differences, and lack forward-looking lifetime-aware control capabilities. The technical solution is as follows: According to one aspect of the present invention, a lifespan-aware thermal management method includes: reading the die temperature and erase / write cycles of a NAND flash memory; collecting and averaging the die temperature and erase / write cycles of each channel to obtain the average die temperature and average erase / write cycles of each channel; setting a wear gradient based on the maximum erase / write cycles of the TLC blocks in the NAND flash memory; constructing a dynamic temperature threshold mathematical model based on the wear gradient, the base frequency reduction temperature determined at the time of card opening, and the average erase / write cycles; performing a negative correlation decreasing calculation on the base frequency reduction temperature of each channel based on the dynamic temperature threshold mathematical model to obtain the corresponding frequency reduction trigger temperature; comparing the frequency reduction trigger temperature with the average die temperature and then performing individual frequency reduction on the channel; continuously monitoring the temperature of the channel; and resuming the original high-frequency operation when the temperature drops below the set temperature of the frequency reduction trigger temperature.

[0007] In one embodiment, the die temperature and erase / write count of the NAND are read, and the die temperature and erase / write count of each channel are collected and averaged to obtain the average die temperature and average erase / write count of each channel. This is achieved through the following steps: real-time temperature data of each die is read from the internal temperature register of the NAND, and the erase / write count of each die is counted. The average temperature of all dies under each channel and the average erase / write count of all dies under each channel are calculated separately, on a channel-by-channel basis, to obtain the average die temperature and average erase / write count of each channel.

[0008] In one embodiment, the wear gradient is set according to the maximum number of erase / write cycles of the TLC block in the NAND by the following steps: based on the maximum number of erase / write cycles of the TLC block, the entire life cycle is divided into multiple wear levels, the wear gradient step size M is set, and the erase / write cycles less than M are set as low wear zone, the erase / write cycles between M and 2M are set as medium wear zone, and the erase / write cycles greater than 2M are set as high wear zone.

[0009] In one embodiment, a dynamic temperature threshold mathematical model is constructed based on the wear gradient, the baseline frequency reduction temperature determined at the time of card opening, and the average number of erase / write cycles through the following steps: .

[0010] In one embodiment, the base frequency reduction temperature of each channel is negatively correlated and decreased according to the dynamic temperature threshold mathematical model to obtain the corresponding frequency reduction trigger temperature. This is achieved through the following steps: Based on the dynamic temperature threshold mathematical model, starting from the base frequency reduction temperature, and combined with the average number of erase / write cycles of each channel, a negative correlation decrease calculation is performed according to the wear gradient. This results in a greater decrease in the frequency reduction trigger temperature for channels with higher erase / write cycles, and a lower frequency reduction trigger temperature for channels with lower erase / write cycles.

[0011] In one embodiment, the process of comparing the frequency reduction trigger temperature with the average die temperature and then performing individual frequency reduction on the Channel is achieved through the following steps: the average die temperature of each Channel is compared with the frequency reduction trigger temperature in real time, and when the average die temperature is greater than or equal to the frequency reduction trigger temperature, frequency reduction is performed only on the Channel.

[0012] In one embodiment, the continuous monitoring of the Channel's temperature and the restoration of the original high-frequency operation after the temperature drops below the set temperature for frequency reduction triggering are achieved through the following steps: after frequency reduction triggering, the real-time temperature of the Channel is continuously monitored, and the Channel is restored to its original high-frequency operation state after the temperature drops below the Channel's frequency reduction triggering temperature by 5 degrees Celsius; the 5-degree Celsius hysteresis design is used to prevent frequent frequency changes when the temperature fluctuates slightly at the threshold edge.

[0013] According to one aspect of the present invention, a lifespan-aware thermal management device includes: a thermal data acquisition module for reading the die temperature and erase / write cycles of a NAND flash memory, acquiring and averaging the die temperature and erase / write cycles of each channel to obtain the average die temperature and average erase / write cycles of each channel; a dynamic threshold model construction module for setting a wear gradient based on the maximum erase / write cycles of the TLC block in the NAND flash memory, and constructing a dynamic temperature threshold mathematical model based on the wear gradient, the base frequency reduction temperature determined at the time of card opening, and the average erase / write cycles; a frequency reduction temperature calculation module for performing a negative correlation decreasing calculation on the base frequency reduction temperature of each channel according to the dynamic temperature threshold mathematical model to obtain the corresponding frequency reduction trigger temperature; and a separate frequency reduction thermal management module for comparing the frequency reduction trigger temperature with the average die temperature and performing separate frequency reduction on the channel, continuously monitoring the temperature of the channel, and restoring the original high-frequency operation when the temperature drops below the set temperature of the frequency reduction trigger temperature.

[0014] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein computer-readable instructions are stored on the memory; the computer-readable instructions are executed by one or more of the processors to cause the electronic device to implement the lifetime-aware thermal management method as described above.

[0015] According to one aspect of the invention, a storage medium has computer-readable instructions stored thereon, which are executed by one or more processors to implement the lifetime-aware thermal management method as described above.

[0016] The beneficial effects of the technical solution provided by this invention are: In the above technical solution, this invention first reads the real-time temperature data of each die in the NAND internal temperature register and counts the number of erase / write cycles. It then calculates the average die temperature and average number of erase / write cycles per channel to accurately obtain the lifespan health status of each channel. Based on this, it uses the maximum number of erase / write cycles of the TLC block to set a wear gradient, dividing the entire lifespan into low-wear, medium-wear, and high-wear zones, and constructs a dynamic temperature threshold mathematical model. Then, based on this model and starting from the base down-frequency temperature determined at the time of card activation, it performs a negative correlation decreasing calculation on the average number of erase / write cycles for each channel to obtain a dedicated down-frequency trigger temperature for each channel. Simultaneously, it compares the down-frequency trigger temperature with the average die temperature in real time, performing down-frequency reduction only on individual channels with excessive temperatures instead of full-disk down-frequency reduction. High-frequency operation resumes after the temperature drops below the down-frequency trigger temperature by 5°C, thus achieving differentiated temperature control based on NAND lifespan. This not only ensures the data reliability of high-erased-write-cycle dies but also reduces error rates. The bit is kept at a low level, and the performance of the entire disk is not dragged down by the overheating of individual dies. This significantly improves the IO performance of SSDs in PE failure scenarios such as repair and chip replacement. It effectively solves the problems of existing technologies that use a one-size-fits-all global temperature control, resulting in a lack of early protection for high PE dies, severe performance drag caused by the frequency reduction of the entire disk when individual dies overheat, inability to distinguish the heat resistance difference between new and old dies after repair and chip replacement, and the lack of foresight in traditional temperature control. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a lifespan-aware thermal management method according to an exemplary embodiment; Figure 2 This is a schematic flowchart illustrating a lifetime-aware thermal management method as shown in an exemplary embodiment; Figure 3 yes Figure 2 A schematic diagram of the channel down-frequency temperature threshold gradient table in the corresponding embodiment; Figure 4 This is a block diagram illustrating a lifespan-sensing thermal management device according to an exemplary embodiment; Figure 5 This is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0021] This invention provides a lifespan-aware thermal management method. By reading the temperature and erase / write cycles of each NAND die, a dynamic temperature threshold model linked to lifespan is constructed at the channel level, enabling differentiated temperature control. This solves the problems of traditional one-size-fits-all temperature control, which lacks early protection for high-PE dies, causes overall drive frequency reduction and performance degradation due to individual die overheating, cannot distinguish the heat resistance differences between new and old dies after repair or replacement, and lacks proactive intervention. This lifespan-aware thermal management method is applicable to lifespan-aware thermal management devices, which can be electronic devices. The lifespan-aware thermal management method in this invention can be applied to various scenarios, such as thermal management of solid-state drives.

[0022] Please see Figure 1 This invention provides a lifespan-aware thermal management method applicable to electronic devices.

[0023] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0024] like Figure 1 As shown, the method may include the following steps: Step 110: Read the die temperature and erase / write count of the NAND flash memory. Collect and average the die temperature and erase / write count of each channel to obtain the average die temperature and average erase / write count of each channel.

[0025] In one possible implementation, real-time temperature data of each die is read from the internal temperature register of the NAND flash memory, and the number of erase / write cycles for each die is counted. The average temperature of all dies under each channel and the average number of erase / write cycles for all dies are calculated separately for each channel, so as to obtain the average die temperature and average number of erase / write cycles for each channel.

[0026] Specifically, NAND Flash has an integrated temperature register that periodically reads the real-time temperature data of each die through firmware. Because the workload of each channel inside an SSD is often uneven—dies closer to the controller generate more heat due to frequent data throughput—temperature is collected at the die level, rather than just reading the average temperature of the entire disk.

[0027] The Program / Erase Count (PE value) is a core indicator of NAND health, accumulated by the firmware during each erase / write operation. A die with a higher PE count has a thinner oxide layer and weaker charge retention, resulting in an exponentially increasing probability of a bit error occurring at the same high temperature.

[0028] Furthermore, the average temperature data of all dies within the same channel is calculated to obtain the channel average die temperature, and the average number of erase / write cycles of all dies within the same channel is calculated to obtain the channel average number of erase / write cycles. Calculating the average at the channel level, rather than at the die level, ensures the statistical representativeness of temperature and lifespan status and lays a data foundation for subsequent channel-level differentiated temperature control.

[0029] In the above process, the embodiments of the present invention use the Channel as the smallest temperature control granularity, collect the temperature in real time from the internal registers of NAND and calculate the average value by combining the PE value statistically obtained from the firmware, so that each Channel has independent temperature-lifetime data, providing the data base required for fine temperature control, realizing accurate perception of the uneven distribution of heat and lifetime distribution inside the SSD, and providing a reliable basis for subsequent differentiation strategies.

[0030] Step 120: Set the wear gradient according to the maximum number of erase / write cycles of the TLC block in the NAND flash memory, and construct a dynamic temperature threshold mathematical model based on the wear gradient, the base frequency reduction temperature determined when the card is opened, and the average number of erase / write cycles.

[0031] In one possible implementation, the entire lifecycle is divided into multiple wear levels based on the maximum number of erase / write cycles of the TLC block. The wear gradient step size M is set, and the erase / write cycles less than M are defined as low wear zone, erase / write cycles between M and 2M are defined as medium wear zone, and erase / write cycles greater than 2M are defined as high wear zone.

[0032] In one possible implementation, the mathematical model for the dynamic temperature threshold is as follows: .

[0033] The core design idea of ​​this model is that the temperature threshold for triggering frequency reduction is strictly negatively correlated with the average number of erases and writes on the Channel. The higher the number of erases and writes, the lower the frequency reduction trigger temperature and the more conservative the temperature control. The lower the number of erases and writes, the higher the frequency reduction trigger temperature and the more aggressive the temperature control.

[0034] Specifically, based on the maximum number of erase / write cycles of a TLC block, the entire lifecycle of a NAND flash memory is divided into multiple wear levels, with a wear gradient step size M (e.g., M=3000). This results in three regions: less than M erase / write cycles (low wear zone, robust period); M to 2M erase / write cycles (medium wear zone, transition period); and more than 2M erase / write cycles (high wear zone, lifespan degradation period). The core purpose of this division is to discretize the continuous lifespan decay process into quantifiable temperature control strategy ranges.

[0035] In the above process, the embodiments of the present invention discretize the entire life cycle of TLC into three wear intervals and introduce a dynamic temperature threshold mathematical model that is negatively correlated with the PE value. This makes the temperature control strategy no longer a fixed 85°C cutoff, but dynamically fluctuates with the actual life state of each channel, providing a quantitative control basis and realizing a shift from passive response to active prediction in temperature control paradigm. In particular, it provides a differentiated threshold solution that can be directly implemented for scenarios where new and old dies coexist after after-sales maintenance and there is a huge PE fracture.

[0036] Step 130: Based on the dynamic temperature threshold mathematical model, the base frequency reduction temperature of each channel is calculated in a negative correlation decreasing manner to obtain the corresponding frequency reduction trigger temperature.

[0037] In one possible implementation, based on a dynamic temperature threshold mathematical model, starting from the base frequency reduction temperature, and combined with the average number of erases and writes for each channel, a negative correlation reduction calculation is performed according to the wear gradient. This results in a larger reduction magnitude for channels with higher erase and write counts, leading to a lower frequency reduction trigger temperature, while a smaller reduction magnitude for channels with lower erase and write counts.

[0038] Specifically, for each channel, starting from the baseline down-frequency temperature determined at the time of card activation, and combining this with the average number of erase / write cycles for that channel, a negative correlation decrease calculation is performed based on the wear gradient step size and temperature adjustment gradient. The decrease magnitude is determined by... Average number of erase / write cycles / wear gradient step size The decision is that for every additional erase / write operation with an increase in the wear gradient step size, the frequency trigger temperature is reduced to lower the temperature adjustment gradient.

[0039] The calculation is performed independently on a channel-by-channel basis. Therefore, even if there is a PE gap caused by the replacement of old and new dies on the disk—for example, if a channel is replaced with a brand new die (PE≈0), its frequency reduction trigger temperature remains at a high level; while the old die of the adjacent channel (PE≈8000) has a very low frequency reduction trigger temperature—the temperature control strategies of the two are completely decoupled and will not interfere with each other.

[0040] In the above process, the embodiments of the present invention use the base frequency reduction temperature as a starting point and perform independent negative correlation reduction calculations on each channel according to the wear gradient, so that each channel has a dedicated frequency reduction trigger temperature that is precisely matched with its lifespan state. This provides a fine-grained temperature tolerance quantification tool down to the channel level, and achieves the dual effect of new dies being able to withstand higher temperatures without being dragged down by old dies, and old dies being protected in advance at lower temperatures. This fundamentally solves the contradiction of "new dies being forced to reduce frequency along with old dies and old dies not being adequately protected" under the traditional one-size-fits-all strategy.

[0041] Step 140: After comparing the frequency reduction trigger temperature with the average die temperature, perform individual frequency reduction on the Channel, continuously monitor the Channel temperature, and resume the original high-frequency operation when the temperature drops below the set temperature of the frequency reduction trigger temperature.

[0042] In one possible implementation, the average die temperature of each channel is compared with the frequency reduction trigger temperature in real time. When the average die temperature is greater than or equal to the frequency reduction trigger temperature, only the channel is subjected to frequency reduction. After frequency reduction is triggered, the real-time temperature of the channel is continuously monitored. When the temperature drops to 5 degrees Celsius below the channel's frequency reduction trigger temperature, the channel is restored to its original high-frequency operating state.

[0043] The 5-degree Celsius hysteresis design is used to prevent frequent frequency conversion when the temperature fluctuates slightly at the threshold edge.

[0044] Specifically, the average die temperature of each channel is compared with its dedicated frequency reduction trigger temperature in real time. When the average die temperature of a channel is greater than or equal to its frequency reduction trigger temperature, frequency reduction is only performed on that channel, and the other channels are unaffected. This is fundamentally different from the traditional approach of "full frequency reduction when any die overheats," avoiding the problem of dragging down the overall I / O performance due to overheating of a few high-PE dies.

[0045] Furthermore, after frequency reduction is triggered, the real-time temperature of the channel is continuously monitored. When the temperature drops below the channel's frequency reduction trigger temperature by 5°C, the channel is restored to its original high-frequency operating state. The core purpose of setting a 5°C hysteresis is to prevent frequent frequency changes caused by small temperature fluctuations at the threshold edge, avoiding secondary damage to NAND lifespan and IO stability caused by repeated frequency increases and decreases. The recovery operation is also executed independently on a channel-by-channel basis—once a channel cools down, it can resume high frequency first without waiting for other channels to synchronize, maximizing the use of the temperature recovery time difference between channels to improve overall IO throughput.

[0046] In the above process, the embodiments of the present invention refine the frequency reduction triggering and recovery control to the channel level and introduce a 5°C hysteresis anti-shake mechanism, so that the high temperature protection is precisely applied to the channel that needs protection without affecting the healthy channel. At the same time, the hysteresis design eliminates the risk of frequent frequency changes at the threshold edge, and provides a closed-loop temperature control execution scheme that takes into account both data reliability and IO performance, achieving the intelligent thermal management effect of "protecting what needs to be protected in advance and releasing what needs to be released boldly".

[0047] Through the above process, this invention first establishes a lifetime-aware data foundation by collecting temperature and PE average values ​​at the channel level; secondly, it constructs a dynamic temperature threshold mathematical model negatively correlated with PE based on the TLC lifetime cycle; thirdly, it independently calculates a dedicated frequency reduction trigger temperature for each channel to achieve differentiated strategy mapping; and finally, it triggers individual frequency reduction through channel-level comparison and intelligently recovers through a 5℃ hysteresis mechanism—completely realizing a lifetime-aware thermal management approach that is "more conservative the older, more aggressive the younger." This fundamentally solves the four major pain points caused by traditional one-size-fits-all temperature control: lack of early protection for high PE dies; severe performance degradation due to overheating of individual dies; inability to distinguish the heat resistance differences between old and new dies after after-sales repair and replacement; and the lack of foresight in traditional temperature control, which can only intervene after the fact. It is particularly suitable for repair disk scenarios with significant PE gaps, ensuring the reliability of old die data while maintaining high IO performance for new dies.

[0048] In one exemplary embodiment, the lifetime-aware thermal management method of the present invention is used for thermal management of SSDs in high-load database write scenarios.

[0049] Figure 2 The flowchart illustrates a lifespan-aware thermal management process, which may include the following steps: Step S1: Update the average number of erase / write cycles for each channel in real time.

[0050] Specifically, the SSD controller firmware reads the real-time temperature data of all dies from the internal temperature register of the NAND Flash at fixed intervals (e.g., 1 second), and simultaneously reads the cumulative erase / write count (PE value) of each die.

[0051] Furthermore, the firmware calculates the average temperature of all dies and the average number of erase / write cycles (PE_curr) for each channel, thereby obtaining the current "thermal-lifetime" health profile of each channel.

[0052] In the above process, the embodiments of the present invention achieve accurate perception of the uneven distribution of internal heat and lifespan of SSD through periodic data acquisition and average calculation, providing a real-time and accurate data foundation for subsequent differentiated temperature control.

[0053] Step S2: Calculate the temperature control threshold that the current channel follows based on the gradient table.

[0054] Specifically, the firmware calls the dynamic temperature threshold mathematical model, starting from the base frequency reduction temperature (T_base, for example 85℃) determined when the card is opened, and combines the average number of erase / write cycles (PE_curr) of each channel calculated in step S1, and performs negative correlation decreasing calculation according to the preset wear gradient (such as PE_step=3000) and temperature adjustment gradient (K=10℃).

[0055] Furthermore, the system substitutes the average number of erase / write cycles into the following formula to calculate the dynamic frequency reduction trigger temperature specific to each channel: .

[0056] like Figure 3 The diagram shows a gradient table of channel downclocking temperature thresholds, clearly illustrating the logical relationship of how the SSD controller dynamically adjusts its downclocking trigger temperature (T_th) based on the average number of erase / write cycles (PE_curr) of the channel in this embodiment of the invention.

[0057] Specifically, the coordinate axes are defined as follows: Horizontal axis (X-axis): Represents the average number of erase / write cycles (PE_curr) of the Channel, measured in cycles. It reflects the wear and tear on the NAND Flash Die; a higher value indicates greater lifespan depletion. Vertical axis (Y-axis): Represents the Channel's frequency reduction trigger temperature threshold (T_th), measured in degrees Celsius (°C). It indicates the temperature at which the Channel needs to activate frequency reduction protection.

[0058] Segmented Threshold Strategy (Stepped Curve): The curve in the figure shows a stepped decrease, indicating that the frequency reduction temperature threshold is not constant, but decreases in segments as the number of erase / write cycles increases. Specifically, it is divided into three wear intervals: Low Wear Zone (0 ~ 3000 cycles): The curve reaches its highest level when the average number of write cycles for the Channel is between 0 and 3000. The corresponding throttling trigger temperature is 85℃ (i.e., the original base throttling temperature). This means that new drives or lightly worn dies can withstand higher operating temperatures, allowing the SSD to maintain high-frequency operation and maximize IO performance.

[0059] Mid-wear zone (3000 ~ 6000 cycles): When the number of erase / write cycles exceeds 3000 but does not reach 6000, the curve drops by one step. The corresponding frequency reduction trigger temperature decreases to 75℃. This indicates that as the die enters the middle of its lifespan, its tolerance to high temperatures decreases, and the system begins to adopt a more conservative temperature control strategy, intervening 10℃ earlier.

[0060] High wear zone (>6000 cycles): After more than 6000 write / erase cycles, the curve drops again and remains at the lowest level. The corresponding frequency reduction trigger temperature is further reduced to 65°C. This is for dies nearing the end of their lifespan, where the oxide layer is extremely thin and data retention capability decreases sharply. Frequency reduction must be triggered at a lower temperature to prevent data flips (BitError) and data loss.

[0061] in, Figure 3 This intuitively demonstrates the core concept of "lifetime sensing" in this invention: the average number of erase / write cycles (PE_curr) of the channel is negatively correlated with the frequency reduction trigger temperature (T_th). More erase / write cycles result in a lower allowable operating temperature; fewer erase / write cycles result in a higher allowable operating temperature. This dynamic adjustment based on wear gradients enables differentiated protection for dies in different health states.

[0062] In the above process, the embodiments of the present invention transform the abstract lifespan state into a specific temperature threshold through a mathematical model, so that the temperature control strategy is no longer a fixed "one-size-fits-all" approach, but dynamically fluctuates according to the actual wear and tear of each channel, achieving quantitative control that is "more conservative as it gets older".

[0063] Step S3: The channel temperature reaches the temperature control threshold.

[0064] Specifically, the main controller monitors the average die temperature of each channel in real time and compares it with the channel-specific frequency reduction trigger temperature (T_th) calculated in step S2. The system determines whether there is a channel whose average temperature is greater than or equal to the channel's T_th. If the result is "yes", the frequency reduction process is triggered; if it is "no", the current high-frequency operation is maintained.

[0065] In the above process, the embodiments of the present invention accurately identify the “overheating” or “high wear” channels that need protection through a real-time comparison mechanism, avoiding the performance waste caused by the overall frequency reduction due to the overheating of individual dies in traditional solutions, and realizing refined thermal protection triggering.

[0066] Step S4: Channel frequency reduction.

[0067] Specifically, when step S3 is determined to be "yes", the main controller only sends a frequency reduction instruction to the channel with the excessive temperature, reducing its operating frequency from high frequency (e.g., 400MT / s) to low frequency (e.g., 200MT / s). The other healthy channels continue to operate at high frequency. The frequency reduction operation is completed through hardware register configuration to ensure low latency in instruction execution.

[0068] In the above process, the embodiments of the present invention limit the impact of thermal protection to the smallest unit through independent frequency reduction control at the channel level, thereby maximizing the preservation of the overall IO throughput of the SSD and solving the traditional pain point of "all things prosper together, all things fail together" in temperature control.

[0069] Step S5: After the frequency is reduced and the monitored temperature drops below 5°C, the channel is restored to its original high frequency.

[0070] Specifically, after the channel is down-frequency, the main controller continuously monitors the real-time temperature of the channel. When the average temperature of the channel drops below its dedicated down-frequency trigger temperature (T_th) by 5°C (i.e., hysteresis temperature), the main controller sends a command to the channel to restore high frequency.

[0071] In the above process, the embodiments of the present invention effectively prevent frequent frequency flickering caused by small temperature fluctuations at the threshold edge by introducing a 5°C hysteresis mechanism, avoiding secondary damage to NAND lifespan and IO stability caused by repeated frequency increases and decreases. At the same time, each channel recovers independently, further improving the system response speed.

[0072] Through the above process, this embodiment of the invention constructs a dynamic temperature threshold model by real-time acquisition of the temperature and PE average of each channel, achieving precise calculation of the dedicated frequency reduction temperature for each channel. When a specific channel's temperature approaches the threshold due to high wear or high load, the system only performs frequency reduction on that channel, rather than reducing the frequency of the entire drive. This protects the high PE die from data flipping while maximizing the performance of the low PE die. After frequency reduction, a 5°C hysteresis mechanism intelligently restores the high frequency, avoiding frequent frequency changes. This solution effectively solves the failure problem of traditional temperature control strategies when facing PE fractures and asymmetric heat distribution within the SSD, significantly improving the stability and IOPS performance of the SSD throughout its entire lifecycle.

[0073] The following are embodiments of the apparatus of the present invention, which can be used to execute the lifetime-aware thermal management method involved in the present invention. For details not disclosed in the apparatus embodiments of the present invention, please refer to the method embodiments of the lifetime-aware thermal management method involved in the present invention.

[0074] Please see Figure 4 This invention provides a lifespan-sensing thermal management device 800.

[0075] The lifespan-aware thermal management device 800 includes, but is not limited to: a thermal data acquisition module 810, a dynamic threshold model construction module 830, a frequency reduction temperature calculation module 850, and a separate frequency reduction thermal management module 870.

[0076] The thermal data acquisition module 810 is used to read the die temperature and erase / write count of the NAND flash memory, collect and average the die temperature and erase / write count of each channel, and obtain the average die temperature and average erase / write count of each channel.

[0077] The dynamic threshold model construction module 830 is used to set the wear gradient based on the maximum number of erase / write cycles of the TLC block in the NAND, and to construct a dynamic temperature threshold mathematical model based on the wear gradient, the base frequency reduction temperature determined when the card is opened, and the average number of erase / write cycles.

[0078] The frequency reduction temperature calculation module 850 is used to perform negative correlation decreasing calculation on the basic frequency reduction temperature of each channel according to the dynamic temperature threshold mathematical model to obtain the corresponding frequency reduction trigger temperature.

[0079] The separate frequency reduction thermal management module 870 is used to compare the frequency reduction trigger temperature with the average die temperature and then perform separate frequency reduction on the Channel. It continuously monitors the Channel temperature and restores the original high-frequency operation when the temperature drops below the set temperature of the frequency reduction trigger temperature.

[0080] It should be noted that the life-sensing thermal management provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the life-sensing thermal management device will be divided into different functional modules to complete all or part of the functions described above.

[0081] Furthermore, the embodiments of the life-sensing thermal management device and the life-sensing thermal management method provided in the above embodiments belong to the same concept, and the specific way in which each module performs its operation has been described in detail in the method embodiments, and will not be repeated here.

[0082] Figure 5 A schematic diagram of the structure of an electronic device according to an exemplary embodiment is shown.

[0083] It should be noted that this electronic device is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of use of the present invention. Furthermore, this electronic device should not be interpreted as requiring or depending on having... Figure 5 One or more components of the exemplary electronic device 2000 shown.

[0084] The hardware structure of electronic devices 2000 can vary significantly due to differences in configuration or performance, such as... Figure 5As shown, the electronic device 2000 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0085] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 2000.

[0086] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted to this invention, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 5 As shown, this does not constitute a specific limitation.

[0087] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0088] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 2000, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0089] Application 253 is a computer-readable instruction based on operating system 251 that performs at least one specific task, and may include at least one module ( Figure 5 (Not shown), each module may contain computer-readable instructions for the electronic device 2000. For example, a life-sensing thermal management device can be considered as an application 253 deployed on the electronic device 2000.

[0090] Data 255 may be signal information, etc., and is stored in memory 250.

[0091] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer-readable instructions stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, a lifespan-aware thermal management method may be implemented by the central processing unit 270 reading a series of computer-readable instructions stored in the memory 250.

[0092] Furthermore, the present invention can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of the present invention is not limited to any specific hardware circuit, software, or combination thereof.

[0093] Please see Figure 6 This invention provides an electronic device 4000, which may include: a desktop computer, a laptop computer, a server, etc., with sensor recognition capabilities.

[0094] exist Figure 6 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0095] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0096] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0097] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0098] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0099] The memory 4003 stores computer-readable instructions, and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002.

[0100] The computer-readable instructions are executed by one or more processors 4001 to implement the lifetime-aware thermal management methods in the above embodiments.

[0101] Furthermore, this embodiment of the invention provides a storage medium storing computer-readable instructions, which are executed by one or more processors to implement the lifetime-aware thermal management method as described above.

[0102] This invention provides a computer program product including computer-readable instructions stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, thereby enabling the electronic device to implement the lifespan-aware thermal management method as described above.

[0103] Compared with related technologies, the beneficial effects of the present invention are: 1. This invention can maximize the overall IO performance of SSD while ensuring data reliability. By refining the temperature control strategy to the channel level and dynamically adjusting the frequency reduction temperature threshold based on the actual number of erases and writes of each channel, healthy channels with low PE can withstand higher temperatures without easily reducing frequency. Frequency reduction is only triggered when the temperature truly reaches its exclusive high threshold, avoiding the problem of dragging down the overall disk performance due to overheating of individual high PE dies in the traditional one-size-fits-all strategy, and realizing the performance release of "the younger, the more aggressive".

[0104] 2. This invention has the ability to proactively protect against high-wear dies, effectively reducing the probability of error bit occurrence. By introducing a dynamic temperature threshold mathematical model that is negatively correlated with the PE value, the frequency reduction trigger temperature is lower for channels with higher write cycles. Dies in the high-wear zone (PE>6000) trigger frequency reduction at 65℃, intervening 20℃ earlier than the basic threshold. Frequency reduction protection is completed before the probability of data flip (Bit Error) increases exponentially, upgrading the traditional temperature control's "passive intervention after the fact" to "predictive intervention before the fact" based on the lifespan status, ensuring that the disk's error bit is always at a low level.

[0105] 3. This invention can perfectly adapt to special scenarios where after-sales maintenance results in a large PE layer fracture within the disk; by independently calculating the frequency reduction trigger temperature on a channel-by-channel basis, the old and new dies do not interfere with each other when they coexist—the channel with the new die has a PE close to 0, so the frequency reduction trigger temperature is still 85°C, which can delay the frequency reduction and maintain high IO performance; while the channels of the other old dies have a higher PE, so the frequency reduction trigger temperature is correspondingly reduced, thus obtaining early protection. In this way, the new die can give full play to its performance while ensuring the reliability of the old die data, solving the temperature control dilemma caused by the wear leveling strategy's inability to equalize the PE in the short term.

[0106] 4. This invention features an intelligent recovery mechanism to prevent frequent frequency changes at the threshold edge, thus improving IO stability. By setting a 5°C hysteresis in the frequency reduction trigger condition—that is, after frequency reduction, the temperature must be monitored to drop to 5°C below the frequency reduction trigger temperature of the channel before resuming the original high-frequency operation—repeated frequency increases and decreases caused by small temperature fluctuations at the threshold edge are effectively avoided. This prevents secondary damage to NAND lifespan and IO stability caused by frequent frequency changes. At the same time, each channel recovers independently without waiting for synchronization, further maximizing the overall IO throughput.

[0107] 5. This invention has adaptive temperature control capability covering the entire life cycle; by dividing the maximum number of erase and write cycles of the TLC block into three gradients—low wear zone, medium wear zone, and high wear zone—and performing a negative correlation decreasing calculation with rounding down, the temperature control strategy automatically and smoothly transitions throughout the entire life cycle of the NAND from the robust period to the decay period. It can adapt to the nonlinear changes in the temperature sensitivity of the die at different life stages without manual intervention, and achieves true life-aware thermal management.

[0108] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0109] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A lifespan-sensing thermal management method, characterized in that, The method includes: Read the die temperature and erase / write cycles of the NAND flash memory, collect and average the die temperature and erase / write cycles of each channel, and obtain the average die temperature and average erase / write cycles of each channel. The wear gradient is set according to the maximum number of erase / write cycles of the TLC block in the NAND, and a dynamic temperature threshold mathematical model is constructed based on the wear gradient, the base frequency reduction temperature determined when the card is opened, and the average number of erase / write cycles. The base down-frequency temperature of each Channel is calculated by negative correlation decreasing according to the dynamic temperature threshold mathematical model to obtain the corresponding down-frequency trigger temperature. After comparing the frequency reduction trigger temperature with the average die temperature, the channel is individually frequency reduced. The temperature of the channel is continuously monitored. When the temperature drops below the set temperature of the frequency reduction trigger temperature, the original high-frequency operation is restored.

2. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The process involves reading the NAND die temperature and erase / write cycles, collecting and averaging the die temperature and erase / write cycles for each channel to obtain the average die temperature and average erase / write cycles for each channel, including: The real-time temperature data of each die is read from the internal temperature register of the NAND flash memory, and the number of erase / write cycles for each die is counted. The average temperature of all dies under each channel and the average number of erase / write cycles for all dies are calculated separately for each channel, so as to obtain the average die temperature and average number of erase / write cycles for each channel.

3. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The step of setting the wear gradient based on the maximum number of erase / write cycles of the TLC block in the NAND includes: Based on the maximum number of erase / write cycles of the TLC block, the entire life cycle is divided into multiple wear levels. The wear gradient step size M is set, and the number of erase / write cycles less than M is set as the low wear zone, the number of erase / write cycles between M and 2M is set as the medium wear zone, and the number of erase / write cycles greater than 2M is set as the high wear zone.

4. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The step of constructing a dynamic temperature threshold mathematical model based on the wear gradient, the baseline frequency reduction temperature determined at the time of card opening, and the average number of erase / write cycles includes: 。 5. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The step of performing a negative correlation decreasing calculation on the base down-frequency temperature of each channel according to the dynamic temperature threshold mathematical model to obtain the corresponding down-frequency trigger temperature includes: Based on the dynamic temperature threshold mathematical model, starting from the base frequency reduction temperature, and combined with the average number of erases and writes for each channel, a negative correlation reduction calculation is performed according to the wear gradient. This results in a larger reduction magnitude for channels with higher erase and write counts, leading to a lower frequency reduction trigger temperature, while a smaller reduction magnitude for channels with lower erase and write counts.

6. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The step of comparing the frequency reduction trigger temperature with the average die temperature and then performing individual frequency reduction on the channel includes: The average die temperature of each channel is compared with the frequency reduction trigger temperature in real time. When the average die temperature is greater than or equal to the frequency reduction trigger temperature, the frequency reduction operation is performed only on the channel.

7. The lifespan-sensing thermal management method as described in claim 1, characterized in that, The continuous monitoring of the channel temperature, and the restoration of original high-frequency operation when the temperature drops below the set temperature for frequency reduction triggering, includes: After frequency reduction is triggered, the real-time temperature of the Channel is continuously monitored. When the temperature drops to 5 degrees Celsius below the Channel's frequency reduction trigger temperature, the Channel is restored to its original high-frequency operating state. The 5-degree Celsius hysteresis design is used to prevent frequent frequency changes when the temperature fluctuates slightly at the threshold edge.

8. A lifespan-sensing thermal management device, characterized in that, The device includes: The thermal data acquisition module is used to read the die temperature and erase / write cycles of the NAND flash memory. It collects and averages the die temperature and erase / write cycles of each channel to obtain the average die temperature and average erase / write cycles of each channel. The dynamic threshold model construction module is used to set the wear gradient based on the maximum number of erase / write cycles of the TLC block in the NAND, and to construct a dynamic temperature threshold mathematical model based on the wear gradient, the base frequency reduction temperature determined at the time of card opening, and the average number of erase / write cycles. The frequency reduction temperature calculation module is used to perform negative correlation decreasing calculation on the basic frequency reduction temperature of each Channel according to the dynamic temperature threshold mathematical model to obtain the corresponding frequency reduction trigger temperature. A separate frequency reduction thermal management module is used to compare the frequency reduction trigger temperature with the average die temperature and then perform a separate frequency reduction on the Channel, continuously monitor the Channel temperature, and restore the original high-frequency operation when the temperature drops below the set temperature of the frequency reduction trigger temperature.

9. An electronic device, characterized in that, include: At least one processor and at least one memory, wherein, The memory stores computer-readable instructions; The computer-readable instructions are executed by one or more of the processors, causing the electronic device to implement the lifetime-aware thermal management method as described in any one of claims 1 to 7.

10. A storage medium having computer-readable instructions stored thereon, characterized in that, The computer-readable instructions are executed by one or more processors to implement the lifetime-aware thermal management method as described in any one of claims 1 to 7.

Images