Memory edge alignment training method, device, equipment, medium and program product

Abstract

This application relates to a memory edge alignment training method, apparatus, device, medium, and program product. The method includes: determining a delay range stored in a delay control register; selecting an initial delay within the delay range, and, starting from the initial delay, progressively adjusting the initial delay in at least two adjustment directions to obtain a training delay; forwarding a training code pattern to each memory chip under both the initial delay and each training delay to obtain data feedback results from each memory chip under both the initial delay and each training delay, wherein the training code pattern is used to trigger the alignment state between the memory chip's feedback data signal and data strobe signal; and determining a target delay based on the data feedback results from each memory chip under both the initial delay and each training delay. This method enables simultaneous training and feedback results from each memory chip, solving the problem of feedback anomalies caused by sampling differences within the chips.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory edge alignment training method, apparatus, computer device, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of the DDR protocol, DDR speeds are increasing, and the clock frequency of the DDR subsystem and the memory clock on the DIMM are also increasing accordingly. The clock frequencies of the chip select (CS) and command control (CA) lines must be consistent with the memory clock. The increased frequency places high demands on the accuracy of the rising and falling edge alignment of the CS / CA signals. To address the stability issues of CS / CA, both the DDR5 specification and the RCD specification have added hardware support for CS / CA training, requiring CPU software in conjunction with DIMM hardware to complete the training process.

[0003] Taking the RCD to DRAM chip link of a DDR5 RDIMM as an example, the delay control register of the chip select signal line CS can be configured in the RCD. The delay of each chip in each rank can be configured independently, but multiple chips in a rank need to share a set of delay control registers (one-to-many). This requires the delay register of a rank to be configured accurately. The command control line (CA) in the RCD also has only one set of delay control registers across multiple ranks, and multiple CA lines need to share a delay configuration (one-to-many). This also places extremely high demands on the delay result.

[0004] However, there are some key details in the current training process. For example, during the training of the chip select signal line CS, QCSTM continuously outputs the 0101 pattern. Due to the different routing of different chips, the time when the 0101 pattern arrives at the DRAM chip will be different. This will cause the feedback inside different chips to be different under the same delay phase of RCD output. Some chips will give feedback of 0, while others will give feedback of 1, resulting in sampling differences inside the chip. Summary of the Invention

[0005] Therefore, it is necessary to provide a memory edge alignment training method, apparatus, device, medium, and program product that can solve the problem of feedback anomalies caused by sampling differences within particles, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a memory edge alignment training method, wherein the memory includes a delay control register and a plurality of memory chips, the delay control register being connected to each of the memory chips respectively, and each of the memory chips sharing the delay control register; the method includes:

[0007] Determine the delay range stored in the delay control register; select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain a training delay; and forward the training code pattern to each memory particle under the initial delay and each training delay to obtain the data feedback results of each memory particle under the initial delay and each training delay. The training code pattern is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle; determine the target delay based on the initial delay and the data feedback results of each memory particle under each training delay.

[0008] In some optional embodiments, selecting the initial delay within the delay range includes:

[0009] The median value of the aforementioned delay range is used as the initial delay.

[0010] In some optional embodiments, the step of gradually adjusting the initial delay in at least two adjustment directions to obtain a training delay, starting from the initial delay, and forwarding the training code to each memory particle under the initial delay and each training delay respectively, to obtain the data feedback results of each memory particle under the initial delay and each training delay, includes:

[0011] Under the initial delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay;

[0012] For each of the aforementioned adjustment directions, the initial time delay is adjusted based on the adjustment direction and the time delay step size to obtain the current training time delay;

[0013] Under the current training latency, the training code pattern is forwarded to each memory particle, and the data feedback results of each memory particle under the current training latency are obtained;

[0014] If the data feedback result does not change, the current training delay is adjusted based on the adjustment direction and the delay step size to obtain a new current training delay. Then, the steps of forwarding the training code to each memory particle and obtaining the data feedback result of each memory particle under the current training delay are continued until the data feedback result changes.

[0015] In some optional embodiments, determining the target latency based on the initial latency and the data feedback results of each memory particle under each training latency includes:

[0016] Based on the initial delay and the data feedback results of each memory particle under each training delay, the data feedback result that caused the jump is determined;

[0017] The training latency corresponding to the data feedback result that causes the jump is used to determine the target latency.

[0018] In some optional embodiments, determining the target latency corresponding to the training latency of the data feedback result that will undergo a jump includes:

[0019] Determine the reference delay corresponding to each adjustment direction, wherein the reference delay is the training delay corresponding to the data feedback result that jumps under the adjustment direction;

[0020] Calculate the mathematical statistics of the reference delay corresponding to each adjustment direction, and use it as the target delay.

[0021] In some alternative embodiments, before determining the delay range stored in the delay control register, the method further includes:

[0022] Send a first training instruction to each memory chip in the memory column, the first training instruction being used to control each memory chip in the memory column to enter training mode;

[0023] A second training instruction is sent to the delay control register, the second training instruction being used to control the delay control register to enter training mode.

[0024] Secondly, this application also provides a memory edge alignment training apparatus, wherein the memory includes a delay control register and a plurality of memory chips, the delay control register being connected to each of the memory chips respectively, and each of the memory chips sharing the delay control register; the apparatus includes:

[0025] The delay range determination module is used to determine the delay range stored in the delay control register;

[0026] The training module is used to select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain a training delay. Under the initial delay and each training delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay and each training delay. The training code pattern is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle.

[0027] The target latency determination module is used to determine the target latency based on the initial latency and the data feedback results of each memory particle under each training latency.

[0028] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0029] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0030] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0031] The aforementioned memory edge alignment training method, apparatus, device, medium, and program product include a memory comprising a delay control register and multiple memory particles. The delay control register is connected to each of the memory particles, and all memory particles share the delay control register. An initial delay is selected within the specified delay range. Starting from the initial delay, the initial delay is gradually adjusted in at least two adjustment directions to obtain a training delay. Training patterns are forwarded to each memory particle under both the initial delay and each training delay to obtain data feedback results from each memory particle under both the initial delay and each training delay. The training patterns are used to trigger the alignment state between the feedback data signal and the data strobe signal of each memory particle. Based on the initial delay and the data feedback results of each memory particle under each training delay, a target delay is determined. This allows each memory particle to train and provide feedback results simultaneously, resolving the problem of feedback anomalies caused by sampling differences within the particles. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of DDR5 memory connections on a DIMM in one embodiment;

[0034] Figure 2 This is a basic pattern diagram of CS training as specified in the DDR5 protocol in one embodiment;

[0035] Figure 3This is a flowchart illustrating a memory edge alignment training method in one embodiment;

[0036] Figure 4 This is a flowchart illustrating the memory edge alignment training method in another embodiment;

[0037] Figure 5 This is a structural block diagram of a memory edge alignment training device in one embodiment;

[0038] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0041] Combination Figure 1 As shown, Figure 1 This is a schematic diagram of DDR5 memory connection on a DIMM in one embodiment. DIMM stands for Dual In-line Memory Module, and DDR stands for Double Data Rate Synchronous Dynamic Random Access Memory, which is the core storage peripheral of the processor.

[0042] The DDR5 and RCD protocols have added hardware support for delay training of CS (chip select) / CA (command control) signals. Both RCD (Registering CLOCK Driver, which helps improve the stability of RDIMM) and DDR5 chips support entering CS / CA training mode. In training mode, RCD sends a specific pattern to the chip, and the chip samples according to fixed rules. The phase pattern that meets the sampling rules is fed back to the controller through the DQ (Data Signal) data line. The controller can then scan to obtain the intervals in which the chip passes or fails.

[0043] However, some key details exist during the training process. For example, during the training of the chip select signal line CS, QCSTM (QCATraining Mode, granular command line signal training mode, mainly used for one-dimensional training of command signal delay) continuously outputs a 0101 pattern. Figure 2 This is a basic pattern diagram of CS training as specified in the DDR5 protocol in one embodiment. Due to the different routing of different chips, the arrival time of the 0101 pattern to the DRAM chip will be different. This will cause differences in the feedback inside different chips even when the RCD output has the same delay phase; some chips will give feedback of 0, while others will give feedback of 1. Solving this kind of problem is a difficult problem in CS training.

[0044] To address the aforementioned problems, in one embodiment, such as Figure 3 As shown, a memory edge alignment training method is provided. The memory includes a delay control register and multiple memory chips. The delay control register is connected to each memory chip, and each memory chip shares the delay control register. This embodiment illustrates the application of this method to a controller. In this embodiment, the method includes the following steps:

[0045] S302: Determine the delay range stored in the delay control register.

[0046] The delay control register RCD stores a delay range, which includes multiple delays. This delay range can be predetermined and is not specifically limited here.

[0047] S304: Select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain the training delay. Then, under the initial delay and each training delay, forward the training code to each memory particle to obtain the data feedback result of each memory particle under the initial delay and each training delay. The training code is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle.

[0048] Determining each delay based on the delay range can be achieved by first determining the initial delay, and then determining the next training delay sequentially based on the delay step size and the initial delay.

[0049] In some optional embodiments, selecting an initial latency within a latency range includes: using the median value of the latency range as the initial latency. That is, the median value of the latency range can be determined as the initial latency first, and then, starting from the initial latency, the initial latency can be gradually adjusted in at least two adjustment directions to obtain the training latency. For example, at least two adjustment directions can be determined first, and the next training latency can be determined sequentially based on the adjustment direction, the initial latency, and the latency step size.

[0050] In this embodiment, the initial delay is the middle value of the delay range. This middle value is generally sufficient to ensure that the data feedback results of each memory chip can be correctly sampled.

[0051] The adjustment direction generally includes two directions: the direction of increasing latency (to the right) and the direction of decreasing latency (to the left). This application can choose any one direction line for training, and then choose the other direction for training. There is no restriction on the order of training the two directions.

[0052] In this application, multiple memory chips are trained simultaneously for the initial latency and each training latency to obtain data feedback results.

[0053] For example, in this application, the controller controls the RCD to forward the training code pattern to each memory chip based on the initial delay, and obtains the data feedback results of each memory chip under the initial delay through the data bus. Then, based on the adjustment direction, the training delay is determined, and the training code pattern is forwarded to each memory chip respectively based on the training delay to obtain the data feedback results of each memory chip under each training delay.

[0054] In this application, for the initial delay and each training delay, the controller sends the training code to each memory chip via RCD. The training code is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory chip. Finally, the data feedback results of each memory chip under the initial delay and each training delay are obtained through the data bus.

[0055] The data feedback results are binary status information sent by the memory chips to the controller via the data bus, indicating whether the received training code pattern has been correctly sampled. Each initial delay and each training delay corresponds to a data feedback result from each memory chip; that is, one delay corresponds to n data feedback results, where n is the number of memory chips.

[0056] S306: Determine the target latency based on the initial latency and the data feedback results of each memory particle under each training latency.

[0057] After determining the initial latency and the data feedback results of each memory particle at each training latency, the target latency is determined based on these data feedback results. The target latency needs to ensure that the data feedback results of each memory particle are correct, and that each memory particle has a large latency margin, meaning it is less prone to failure. Therefore, the data feedback results of each memory particle can be determined as boundary values ​​of the latency at which correct sampling is possible, and then the target latency is calculated based on these boundary values.

[0058] The aforementioned memory edge alignment training method includes a memory comprising a delay control register and multiple memory particles. The delay control register is connected to each memory particle, and all memory particles share the delay control register. An initial delay is selected within the specified delay range. Starting from the initial delay, the initial delay is gradually adjusted in at least two adjustment directions to obtain a training delay. Training patterns are forwarded to each memory particle under both the initial delay and each training delay to obtain data feedback results from each memory particle under both the initial delay and each training delay. The training patterns are used to trigger the alignment between the feedback data signal and the data strobe signal of each memory particle. Based on the initial delay and the data feedback results of each memory particle under each delay, a target delay is determined. This allows each memory particle to train and receive feedback results simultaneously, resolving the problem of feedback anomalies caused by sampling differences within the particles.

[0059] In some optional embodiments, starting from an initial delay, the initial delay is gradually adjusted in at least two adjustment directions to obtain a training delay. Under both the initial delay and each training delay, the training code pattern is forwarded to each memory particle to obtain data feedback results from each memory particle under the initial delay and each training delay. This includes: forwarding the training code pattern to each memory particle under the initial delay to obtain data feedback results from each memory particle under the initial delay; adjusting the initial delay based on the adjustment direction and delay step size for each adjustment direction to obtain the current training delay; forwarding the training code pattern to each memory particle under the current training delay to obtain data feedback results from each memory particle under the current training delay; if the data feedback results do not change, adjusting the current training delay based on the adjustment direction and delay step size to obtain a new current training delay, and continuing to execute the steps of forwarding the training code pattern to each memory particle under the current training delay to obtain data feedback results from each memory particle under the current training delay, until the data feedback results change.

[0060] In this embodiment, under the initial delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay. Then, for each adjustment direction, the initial delay is adjusted based on the adjustment direction and the delay step size. For example, if the adjustment direction is to increase the delay, the current training delay is equal to the sum of the initial delay and the delay step size. Then, under the current training delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the current training delay, and it is determined whether the data feedback result has changed, that is, whether it has changed from indicating that the training code pattern was correctly sampled to indicating that the training code pattern could not be correctly sampled. If so, the adjustment direction is stopped, and the current training delay is recorded. If no change has occurred, a new current training delay is obtained based on the current training delay, the adjustment direction, and the delay step size, that is, the new current training delay is equal to the sum of the current training delay and the delay step size, and then the above process is repeated. This continues until the data feedback result changes. Here, a change is sufficient if the data feedback result of at least one memory particle changes, but it is not necessary for the data feedback results of all memory particles to change. Another possibility is that the data feedback results of the memory chips do not change until the boundary of the delay range is reached. In this case, it is only necessary to record the boundary of the delay range as the position where the data feedback results of the memory chips change, but in reality, no change has occurred. This is only for the convenience of subsequent processing.

[0061] After processing one adjustment direction, the data for the other adjustment directions is processed until all adjustment directions are processed, and the time delay position where the data feedback result for each processing direction jumps is obtained.

[0062] In some optional embodiments, determining the target latency based on the initial latency and the data feedback results of each memory particle under each training latency includes: determining the data feedback result that has jumped based on the initial latency and the data feedback results of each memory particle under each training latency; and determining the target latency based on the training latency corresponding to the data feedback result that has jumped.

[0063] The initial delay and each training delay correspond to the data feedback results of each memory particle. If the data feedback result of at least one memory particle changes, the data feedback result that caused the change is recorded. Alternatively, if the data feedback results of memory particles do not change when the delay range is reached, it is only necessary to record the boundary of the delay range as the position where the data feedback result of the memory particle changes, but in reality, no change has occurred; this is only for the convenience of subsequent processing.

[0064] Finally, the controller determines the target latency based on the training latency corresponding to the data feedback results of the jump.

[0065] Optionally, the training latency corresponding to the data feedback result that jumps is used to determine the target latency, including: determining the reference latency corresponding to each adjustment direction, where the reference latency is the training latency corresponding to the data feedback result that jumps under the adjustment direction; and calculating the mathematical statistics of the reference latency corresponding to each adjustment direction as the target latency.

[0066] Since each adjustment direction corresponds to a data feedback result of a jump, this application first determines the training latency corresponding to the data feedback result of the jump in each adjustment direction, and uses this training latency as a reference latency. For example, two adjustment directions correspond to two reference latencies. Then, the mathematical statistics of the reference latency are calculated as the target latency. Optionally, this application calculates the average value of the reference latency as the target latency.

[0067] In some optional embodiments, before determining the latency range stored in the latency control register, the method further includes: sending a first training instruction to each memory chip in the memory column, the first training instruction being used to control each memory chip in the memory column to enter a training mode; and sending a second training instruction to the latency control register, the second training instruction being used to control the latency control register to enter a training mode.

[0068] Before training, the controller needs to control each memory chip in the memory column and the delay control register RCD to enter training mode. Specifically, the controller can send an MPC command (Mode Register Set Command Pulse) to control all chips in the same rank to enter CS training mode. The controller can also enter CS training mode by operating the RCD via I2C. Specifically, the controller writes a control word to the RCD through the low-speed I2C configuration bus, switching the RCD's working mode from normal signal processor to transparent channel, thus clearing the way for subsequent CS training of DRAM via the high-speed CA bus.

[0069] For ease of understanding, combined with Figure 4 As shown, Figure 4 This is a flowchart of a memory edge alignment training method in another embodiment. Taking the chip select (CS) signal line of a DDR5 chip as an example, it should be noted that the method of this application can be used for edge alignment training of all multiple memories corresponding to a set of control registers. The method includes:

[0070] 1) The DDR controller completes the basic initialization process of the memory.

[0071] 2) The controller sends an MPC command (Mode Register Set Command Pulse) to control all particles in the same rank to enter CS training mode.

[0072] 3) Entering CS training mode via I2C operation of RCD also enters CS training mode.

[0073] 4) Scan the delay step size Step from the middle of the delay range (step=0x40) to the left, i.e., step--, the leftmost part of the delay range is 0x00.

[0074] 5) The RCD updates the delay control register in the RCD according to the delay step size Step.

[0075] 6) The RCD sends the CS training pattern, and the controller obtains the data bus DQ feedback results of all particles.

[0076] 7) If there is no change in the feedback result of the data bus DQ, return to process 4.

[0077] 8) If there is a feedback result from the data bus DQ, then the left boundary is confirmed to have been found, and the corresponding delay step is recorded. In other embodiments, the delay can also be recorded directly.

[0078] 9) Start processing the next debugging direction, scanning the delay step from the middle of the delay range (step=0x40) to the right, i.e. step++, and the rightmost part of the delay range is 0x80.

[0079] 10) The RCD updates the delay control register in the RCD according to the delay step size Step.

[0080] 11) The RCD sends the CS training pattern, and the controller obtains the data bus DQ feedback results of all particles.

[0081] 12) If no data bus DQ feedback result changes, return to process 9.

[0082] 13) If there is a feedback result from the data bus DQ, then the right boundary is confirmed to be found, and the corresponding delay step is recorded. In other embodiments, the delay can also be recorded directly.

[0083] 14) According to the formula center point = (delay step of left boundary Step + delay step of right boundary Step) / 2, the center point delay, which is also the target delay, is obtained. Finally, the target delay is configured into the RCD delay register clock to complete the CS training of the memory column rank.

[0084] To facilitate understanding, actual training data is provided, taking the QCS latency training process of DDR5 as an example. The right edge scan includes: starting from the initial latency, scanning incrementally in one direction (e.g., increasing the latency value), while simultaneously monitoring the data sampling results. When a transition occurs, the training latency corresponding to the data feedback result of the transition is recorded as the right edge. The left edge scan includes: scanning incrementally in the other direction (e.g., decreasing the latency value), similarly monitoring the data sampling results. When a transition occurs, the training latency corresponding to the data feedback result of the transition is recorded as the left edge.

[0085] Finally, the center point is calculated based on the obtained left and right boundaries:

[0086] QCS Final min=0x25, max=0x5f, mid=0x42, margin=58

[0087] Final QCS Delay: 0xc2.

[0088] Where QCS Final min is the left boundary, max is the right boundary, mid is the center point obtained based on the left and right boundaries, margin is the delay margin, and Final QCS Delay is the target delay.

[0089] In the above embodiments, for multi-memory training scenarios with only one set of delay control register edge alignment, a method is proposed to train multiple memories simultaneously and analyze the feedback results concurrently. During training, the transition points of the feedback results are selected as boundaries, automatically completing the intersection of the training results from all memories without needing to consider the signal sampling differences within different memories. Furthermore, by examining the feedback results from all memories together and selecting transition points as boundaries, the intersection of the delay results from all memories is automatically completed, significantly shortening the training time while exhibiting extremely high accuracy and stability. This effectively addresses the time efficiency, accuracy, and stability requirements of delay training results in various application scenarios. Additionally, by searching for the left and right boundaries from the center outwards, ignoring the initial state differences in the training feedback results from different memories, and selecting transition points as boundaries during the scan, the intersection of the delay results from all memories is automatically completed.

[0090] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0091] Based on the same inventive concept, this application also provides a memory edge alignment training apparatus for implementing the memory edge alignment training method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the memory edge alignment training apparatus provided below can be found in the limitations of the memory edge alignment training method described above, and will not be repeated here.

[0092] In one exemplary embodiment, such as Figure 5 As shown, a memory edge alignment training device is provided. The memory includes a delay control register and multiple memory chips. The delay control register is connected to each memory chip, and each memory chip shares the delay control register. The device includes: a delay range determination module 501, a training module 502, and a target delay determination module 503, wherein:

[0093] The delay range determination module 501 is used to determine the delay range stored in the delay control register;

[0094] The training module 502 is used to select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain the training delay. Under the initial delay and each training delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay and each training delay. The training code pattern is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle.

[0095] The target latency determination module 503 is used to determine the target latency based on the initial latency and the data feedback results of each memory particle under each training latency.

[0096] In some alternative embodiments, the training module 502 is specifically used to take the median value of the latency range as the initial latency.

[0097] In some optional embodiments, the training module 502 is specifically configured to: forward the training code pattern to each memory particle under the initial delay to obtain the data feedback results of each memory particle under the initial delay; adjust the initial delay based on the adjustment direction and the delay step size for each adjustment direction to obtain the current training delay; forward the training code pattern to each memory particle under the current training delay to obtain the data feedback results of each memory particle under the current training delay; if the data feedback results do not change, adjust the current training delay based on the adjustment direction and the delay step size to obtain a new current training delay, and continue to execute the steps of forwarding the training code pattern to each memory particle under the current training delay to obtain the data feedback results of each memory particle under the current training delay, until the data feedback results change.

[0098] In some optional embodiments, the target latency determination module 503 is specifically used to determine the data feedback result that has jumped based on the initial latency and the data feedback result of each memory chip under each training latency; and to determine the target latency based on the training latency corresponding to the data feedback result that has jumped.

[0099] In some optional embodiments, the target latency determination module 503 is specifically used to determine the reference latency corresponding to each adjustment direction. The reference latency is the training latency corresponding to the data feedback result that jumps under the adjustment direction; and to calculate the mathematical statistical value of the reference latency corresponding to each adjustment direction as the target latency.

[0100] In some optional embodiments, the above apparatus further includes: an initialization module, specifically configured to send a first training instruction to each memory chip in the memory column, the first training instruction being used to control each memory chip in the memory column to enter a training mode; and to send a second training instruction to a delay control register, the second training instruction being used to control the delay control register to enter a training mode.

[0101] Each module in the aforementioned memory edge alignment training device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0102] In one exemplary embodiment, a computer device is provided, which may be a controller, such as a DDR controller, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, input / output interfaces (I / O), and a communication interface. The processor and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The I / O interfaces are used for exchanging information between the processor and various storage devices. The communication interface is used for communicating with external terminals via a network. When executed by the processor, the computer program implements a memory edge-aligned training method.

[0103] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0104] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0105] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0106] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0107] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0108] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0110] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A memory edge alignment training method, comprising: The memory includes a delay control register and multiple memory chips, wherein the delay control register is connected to each of the memory chips respectively, and each of the memory chips shares the delay control register; the method includes: Determine the delay range stored in the delay control register; select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain a training delay; and forward the training code pattern to each memory particle under the initial delay and each training delay to obtain the data feedback results of each memory particle under the initial delay and each training delay. The training code pattern is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle; determine the target delay based on the initial delay and the data feedback results of each memory particle under each training delay.

2. The method of claim 1, wherein, Selecting an initial delay within the specified delay range includes: The median value of the aforementioned delay range is used as the initial delay.

3. The method according to claim 1, characterized in that, Starting from the initial delay, the training delay is gradually adjusted in at least two adjustment directions to obtain the initial delay. The training code is then forwarded to each memory particle under both the initial delay and each training delay to obtain data feedback results from each memory particle under both the initial delay and each training delay. This includes: Under the initial delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay; For each of the aforementioned adjustment directions, the initial time delay is adjusted based on the adjustment direction and the time delay step size to obtain the current training time delay; Under the current training latency, the training code pattern is forwarded to each memory particle, and the data feedback results of each memory particle under the current training latency are obtained; If the data feedback result does not change, the current training delay is adjusted based on the adjustment direction and the delay step size to obtain a new current training delay. Then, the steps of forwarding the training code to each memory particle and obtaining the data feedback result of each memory particle under the current training delay are continued until the data feedback result changes.

4. The method according to claim 3, characterized in that, The determination of the target latency based on the initial latency and the data feedback results of each memory particle under each training latency includes: Based on the initial delay and the data feedback results of each memory particle under each training delay, the data feedback result that caused the jump is determined; The training latency corresponding to the data feedback result that causes the jump is used to determine the target latency.

5. The method according to claim 4, characterized in that, The determination of the target latency, corresponding to the training latency of the data feedback result that will undergo a jump, includes: Determine the reference delay corresponding to each adjustment direction, wherein the reference delay is the training delay corresponding to the data feedback result that jumps under the adjustment direction; Calculate the mathematical statistics of the reference delay corresponding to each adjustment direction, and use it as the target delay.

6. The method according to any one of claims 1 to 5, characterized in that, Before determining the delay range stored in the delay control register, the method further includes: Send a first training instruction to each memory chip in the memory column, the first training instruction being used to control each memory chip in the memory column to enter training mode; A second training instruction is sent to the delay control register, the second training instruction being used to control the delay control register to enter training mode.

7. A memory edge alignment training device, characterized in that, The memory includes a delay control register and multiple memory chips, the delay control register being connected to each of the memory chips respectively, and each of the memory chips sharing the delay control register; the device includes: The delay range determination module is used to determine the delay range stored in the delay control register; The training module is used to select an initial delay within the delay range, and starting from the initial delay, gradually adjust the initial delay in at least two adjustment directions to obtain a training delay. Under the initial delay and each training delay, the training code pattern is forwarded to each memory particle to obtain the data feedback results of each memory particle under the initial delay and each training delay. The training code pattern is used to trigger the alignment state between the feedback data signal and the data strobe signal of the memory particle. The target latency determination module is used to determine the target latency based on the initial latency and the data feedback results of each memory particle under each training latency.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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