Memory management method and storage device

Abstract

The application provides a memory management method and a storage device. The method comprises: in response to a trigger event, detecting whether the storage device is in a first extreme scenario; in response to the storage device being in the first extreme scenario, starting a first refresh management strategy, and under the first refresh management strategy, prohibiting the execution of a refresh operation on a memory module; and in response to the storage device being out of the first extreme scenario, closing the first refresh management strategy. Thus, a good balance can be achieved between improving the operation efficiency of the storage device, improving the user experience and prolonging the service life.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] For certain types of storage devices, the internal memory controller can periodically or based on specific conditions perform refresh operations on at least a portion of the physical blocks in the memory module to improve the integrity of the stored data. However, in practice, blindly performing high-frequency and / or high-intensity refresh operations when the device is in an unstable state can not only cause unnecessary programming / erase cycle losses, but may also lead to data corruption due to the instability of the refresh process itself. Summary of the Invention

[0003] This invention provides a memory management method and a storage device that can improve the above-mentioned problems and achieve a good balance between improving the operating performance of the storage device, improving the user experience and extending its service life.

[0004] This invention provides a memory management method for a storage device, wherein the storage device includes a memory module, and the memory management method includes: in response to a trigger event, detecting whether the storage device is in a first extreme scenario; in response to the storage device being in the first extreme scenario, starting a first refresh management strategy and prohibiting refresh operations on the memory module under the first refresh management strategy; and in response to the storage device leaving the first extreme scenario, disabling the first refresh management strategy.

[0005] This invention also provides a storage device, including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0006] Based on the above, in response to a triggering event, when the storage device is in a first extreme scenario, a first refresh management strategy can be activated to prohibit refresh operations on the memory module. Subsequently, in response to the storage device leaving the first extreme scenario, the first refresh management strategy can be automatically deactivated. Thus, by actively activating one or more refresh management strategies for the memory module in extreme (and / or non-extreme) scenarios after detecting a triggering event, the present invention can effectively achieve a good balance between improving the operational performance of the storage device, enhancing user experience, and extending its service life. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0008] Figure 2This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0009] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0010] Figure 4 This is a schematic diagram illustrating the performance of a refresh operation on an entity unit according to an embodiment of the present invention;

[0011] Figure 5 This is a schematic diagram illustrating the operation scenario of the memory management module according to an embodiment of the present invention;

[0012] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0013] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0014] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0015] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0016] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0017] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0018] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0019] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0020] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0022] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0026] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage units for non-volatile storage of data.

[0027] In one embodiment, a physical unit may include at least one physical programming unit. For example, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell. In one embodiment, a physical programming unit is also referred to as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the invention is not limited thereto.

[0028] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0029] In one embodiment, a physical erase unit may include multiple physical programming units. For example, the multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the multiple physical programming units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0030] In one embodiment, an entity unit may include at least one entity erase unit. In another embodiment, if an entity unit includes multiple entity erase units, this entity unit is also referred to as a virtual block. Multiple entity erase units contained in the same virtual block can operate synchronously.

[0031] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 can perform a refresh operation (also known as a data refresh operation) on the memory module 122. Figure 3 For example, the memory control circuit 23 can perform a refresh operation on at least one physical cell (also called the target physical cell) in the data area 31 that currently stores valid data. Through this refresh operation, the data quality of the data (i.e., valid data) stored in the memory module 122 can be improved (e.g., the bit error rate of the stored data can be reduced).

[0038] Figure 4 This is a schematic diagram illustrating the performance of a refresh operation on a physical unit according to an embodiment of the present invention. Please refer to... Figure 4 Assume the target entity unit includes entity unit 41. For example, entity unit 41 could be... Figure 3 One of the physical units 301(1)-301(A). In one embodiment, the memory control circuit 23 may perform a refresh operation (i.e., a data refresh operation) on the physical unit 41.

[0039] In one embodiment, during a refresh operation on physical unit 41, memory control circuit 23 may instruct memory module 122 to read data 401 (i.e., valid data) stored in physical unit 41. Then, memory control circuit 23 may instruct decoding circuit 25 to perform a decoding operation on the read data 401 to correct errors (i.e., erroneous bits) in the data 401. After correcting the errors in data 401, memory control circuit 23 may instruct memory module 122 to re-store the corrected data 401 into physical unit 42. For example, physical unit 42 may retrieve data from physical unit 42. Figure 3 The data is extracted from the idle area 32. Therefore, even if the data 401 originally stored in entity unit 41 is of poor quality (e.g., contains many errors), the data 401 re-stored in entity unit 42 can have relatively better data quality. For example, compared to the data 401 in entity unit 41, the data 401 stored in entity unit 42 can have relatively fewer errors.

[0040] In one embodiment, it is assumed that the logical unit to which data 401 belongs (also referred to as the target logical unit) was originally mapped to physical unit 41. After data 401 is stored in physical unit 42, during a refresh operation of physical unit 41, memory control circuit 23 can change the mapping of the logical unit to which data 401 belongs (i.e., the target logical unit) to physical unit 42. Subsequently, in response to a read event for the target logical unit (e.g., a read instruction from host system 11), memory control circuit 23 can read data 401 belonging to the target logical unit from physical unit 42 in response to this read event.

[0041] In one embodiment, after a refresh operation is performed on physical unit 41 (e.g., data 401 is stored in physical unit 42), memory control circuitry 23 may instruct memory module 122 to erase physical unit 41. If (or in response to) physical unit 41 being erased, physical unit 41 may be considered an idle physical unit and added to [the memory module]. Figure 3 The idle area 32. Therefore, in one embodiment, the total number of idle entity units in memory module 122 can be increased by performing a refresh operation.

[0042] In one embodiment, the memory control circuit 23 can detect a trigger event. In one embodiment, this trigger event may include the storage device 12 being powered on (e.g., switching from a power-off state to a power-on state). For example, in response to the storage device 12 being powered on, the memory control circuit 23 may determine that this trigger event has been detected. In one embodiment, this trigger event may also include other types of events defined by the user or manufacturer, which are not limited by this invention.

[0043] In one embodiment, in response to a triggering event, the memory control circuit 23 can detect whether the storage device 12 is in a specific scenario (also referred to as a first extreme scenario). If (or in response to) the storage device 12 is in the first extreme scenario, the memory control circuit 23 can activate a specific strategy (also referred to as a first refresh management strategy). If (or in response to) the storage device 12 is not in the first extreme scenario, the memory control circuit 23 may not activate the first refresh management strategy.

[0044] In one embodiment, the first extreme scenario includes at least one of the following scenarios:

[0045] A. The total number of refresh operations performed on a certain physical unit (also known as the first physical unit) in memory module 122 within a preset time range reaches a critical value (also known as the first critical value);

[0046] B. The total number of refresh operations performed on a certain physical unit (also known as the second physical unit) in memory module 122 reaches a critical value (also known as the second critical value);

[0047] C. The temperature of storage device 12 reaches a critical value (also known as the temperature critical value).

[0048] In one embodiment, after a trigger event is detected, the memory control circuit 23 can monitor whether there is any entity cell in the memory module 122 whose total number of refresh operations performed within a past time range (i.e., a preset time range) reaches the first threshold value. If (or in response to) there is an entity cell in the memory module 122 whose total number of refresh operations performed within the preset time range reaches the first threshold value, the memory control circuit 23 can determine that this entity cell belongs to the first entity cell and determine that the storage device 12 is in the first extreme scenario (i.e., scenario A above).

[0049] In one embodiment, it is assumed that the first count threshold is 15, and there exists a certain entity unit (i.e., the first entity unit) in the memory module 122, which has been refreshed a total of 19 times within a preset time range (greater than the first count threshold). In one embodiment, in response to the first entity unit being refreshed a total of 19 times within the preset time range, the memory control circuit 23 can determine that the storage device 12 is in a first extreme scenario (i.e., scenario A above). It should be noted that the first count threshold can be adjusted according to practical needs, and the present invention does not limit it.

[0050] In one embodiment, after a trigger event is detected, the memory control circuit 23 can monitor whether there is any entity cell in the memory module 122 whose total number of consecutive refresh operations performed within a past time range (i.e., a preset time range) reaches a second threshold value. If (or in response to) there is an entity cell in the memory module 122 whose total number of consecutive refresh operations performed within the preset time range reaches a second threshold value, the memory control circuit 23 can determine that this entity cell belongs to the second entity cell and determine that the storage device 12 is in the first extreme scenario (i.e., scenario B above).

[0051] In one embodiment, it is assumed that the second threshold value is 10, and there exists a certain entity unit (i.e., the second entity unit) in the memory module 122, which has undergone continuous refresh operations a total of 12 times within a preset time range (greater than the second threshold value). In one embodiment, in response to the second entity unit having undergone continuous refresh operations a total of 12 times within the preset time range reaching the second threshold value, the memory control circuit 23 can determine that the storage device 12 is in the first extreme scenario (i.e., scenario B above). It should be noted that the second threshold value can be adjusted according to practical needs, and the present invention does not limit it.

[0052] In one embodiment, the second threshold value may be less than or equal to the first threshold value. In one embodiment, in scenario A, the first entity unit may not be continuously refreshed, as long as the total number of refresh operations performed on the first entity unit within a preset time range reaches the first threshold value. However, in scenario B, the same second entity unit needs to be continuously refreshed, and the total number of consecutive refresh operations performed on the same second entity unit within a preset time range needs to reach the second threshold value.

[0053] In one embodiment, scenario A and / or scenario B described above may reflect that after a triggering event (e.g., power-on of storage device 12) is detected, storage device 12 repeatedly performs multiple (failed) refresh operations on the same physical unit within a short period of time (i.e., a preset time range). This may be because storage device 12 repeatedly loses power within a short period of time (i.e., the preset time range). In this case, memory control circuit 23 can determine that storage device 12 is in a first extreme scenario.

[0054] In one embodiment, after a trigger event is detected, the memory control circuit 23 can detect whether the temperature of the storage device 12 has reached a temperature threshold. For example, the memory control circuit 23 can obtain temperature data corresponding to the storage device 12 through a temperature sensor disposed inside the storage device 12. This temperature data reflects the temperature of the storage device 12. If (or in response to) the temperature of the storage device 12 reaches the temperature threshold, the memory control circuit 23 can determine that the storage device 12 is in a first extreme scenario (i.e., scenario C described above).

[0055] In one embodiment, the temperature threshold may include an upper temperature threshold and / or a lower temperature threshold. The upper temperature threshold is greater than the lower temperature threshold. In one embodiment, if (or in response to) the temperature of the storage device 12 is higher than or equal to the upper temperature threshold, the memory control circuit 23 may determine that the temperature of the storage device 12 has reached the temperature threshold. Alternatively, in one embodiment, if (or in response to) the temperature of the storage device 12 is lower than or equal to the lower temperature threshold, the memory control circuit 23 may determine that the temperature of the storage device 12 has reached the temperature threshold. For example, the upper temperature threshold and the lower temperature threshold may be 80 degrees Celsius and -20 degrees Celsius, respectively. However, the temperature threshold may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0056] In one embodiment, scenario C described above reflects that the storage device 12 is currently in an extreme temperature environment. This extreme temperature environment may include an extreme high temperature environment (e.g., the temperature of the storage device 12 reaches 80 degrees Celsius) or an extreme low temperature environment (e.g., the temperature of the storage device 12 reaches -20 degrees Celsius). In this case, the memory control circuit 23 may determine that the storage device 12 is in the first extreme scenario.

[0057] In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in one of the aforementioned scenarios A, B, and C, the memory control circuit 23 can determine that the storage device 12 is in a first extreme scenario. In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in two of the aforementioned scenarios A, B, and C, the memory control circuit 23 can determine that the storage device 12 is in a first extreme scenario. In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in all of the aforementioned scenarios A, B, and C simultaneously, the memory control circuit 23 can determine that the storage device 12 is in a first extreme scenario. In one embodiment, the memory control circuit 23 can also add more scenarios related to extreme operations and / or extreme environments as first extreme scenarios, according to practical needs.

[0058] In one embodiment, after the first refresh management strategy is initiated, the memory control circuit 23 can prohibit refresh operations on the memory module 122 under the first refresh management strategy. For example, under the first refresh management strategy, the memory control circuit 23 can prohibit refresh operations on any entity cell in the memory module 122. In one embodiment, even if a certain entity cell in the memory module 122 is a selected, identified, or determined entity cell that needs to be refreshed (also referred to as the entity cell to be refreshed), the memory control circuit 23 can prohibit refresh operations on this entity cell (i.e., the entity cell to be refreshed).

[0059] In one embodiment, compared to the traditional approach of allowing invalid or high-probability-of-failure refresh operations on the physical unit to be refreshed regardless of whether the current environment is in an extreme state, by activating a first refresh management strategy and prohibiting refresh operations on the memory module 122, invalid or high-probability-of-failure refresh operations on the physical unit to be refreshed can be effectively prevented in the aforementioned extreme scenario (i.e., the first extreme scenario). In one embodiment, by preventing invalid or high-probability-of-failure refresh operations on the physical unit to be refreshed in extreme scenarios, write amplification and / or other types of physical wear and tear on the memory module 122 caused by extreme environments can be effectively reduced, thereby effectively extending the service life of the memory module 122 without affecting the performance of the storage device 12 and the user experience.

[0060] In one embodiment, the memory module 122 may support multiple write modes to perform data writing (i.e., data storage) on physical units in the memory module 122. These write modes include a first write mode and a second write mode.

[0061] In one embodiment, the programming speed (also referred to as the first programming speed) of a single physical cell in the memory module 122 under the first write mode may be higher than the programming speed (also referred to as the second programming speed) of a single physical cell in the memory module 122 under the second write mode. In one embodiment, the programming speed for a particular physical cell may be directly proportional to the data writing speed to that physical cell. For example, assuming that programming a single physical cell in the memory module 122 to store data in the first write mode takes a certain amount of time (also referred to as the first time length), and programming a single physical cell in the memory module 122 to store data in the second write mode takes another amount of time (also referred to as the second time length), then the first time length will be shorter than the second time length.

[0062] In one embodiment, if data is written to a physical unit in the memory module 122 based on a first write mode, a single storage unit in this physical unit can be used to store a first number of bits. Conversely, if data is written to a physical unit in the memory module 122 based on a second write mode, a single storage unit in this physical unit can be used to store a second number of bits. The first number will be less than the second number. For example, assuming the first number is 1, the second number can be 2, 3, 4, or more. Furthermore, the first and second numbers can be adjusted according to practical needs, as long as they conform to the specification that the first number is less than the second number.

[0063] In one embodiment, the first write mode may include SLC mode. In one embodiment, the second write mode may include MLC mode, TLC mode, QLC mode, or other modes. In one embodiment, the first and second write modes can also be adjusted according to practical needs, as long as they meet the specifications that the first programming speed is higher than the second programming speed and / or the first quantity is less than the second quantity.

[0064] In one embodiment, under a first refresh management strategy, the memory control circuit 23 can obtain a write instruction from the host system 11. This write instruction can be used to instruct the storage device 12 to store or update data belonging to a specific logical unit (also referred to as target data).

[0065] In one embodiment, under a first refresh management policy, according to (or in response to) this write instruction, the memory control circuit 23 can force the activation of a first write mode (e.g., SLC mode) to perform a data write operation on the memory module 122. For example, under the first refresh management policy, according to (or in response to) this write instruction, the memory control circuit 23 can force the extraction of at least one physical cell (also called a cache physical cell) from a specific region (also called a cache area) in the memory module 122. Then, the memory control circuit 23 can use the extracted cache physical cell to store the data (i.e., the target data) indicated by this write instruction, based on the first write mode.

[0066] In one embodiment, under a first refresh management policy, based on (or in response to) this write instruction, the memory control circuit 23 may ignore current usage restrictions on cache physical units and directly retrieve cache physical units from the cache area to store the target data. In one embodiment, this usage restriction may include prohibiting or delaying the retrieval of cache physical units to store data when the total number of cache physical units is less than a threshold (also known as a cache threshold).

[0067] In one embodiment, after disabling the first refresh management policy, the memory control circuit 23 may restore the usage restrictions on the cache physical units. For example, after restoring the usage restrictions on the cache physical units, the memory control circuit 23 must comply with (i.e., cannot ignore) the aforementioned usage restrictions on the cache physical units for write instructions from the host system 11.

[0068] In one embodiment, by forcibly enabling a first write mode (e.g., SLC mode) under a first refresh management strategy to perform data write operations on the memory module 122, the time that data that has not yet been programmed or written is exposed to extreme environments (e.g., within an unstable power-on window) can be minimized. Therefore, even if the storage device 12 is still in an extreme environment, the probability of the target data being correctly programmed or written to the memory module 122 can be effectively increased. When the system stabilizes subsequently (e.g., the storage device 12 is no longer in the first extreme scenario), the memory control circuit 23 can perform refresh operations on the data written under extreme conditions (e.g., refresh operations). Figure 4 As shown in the figure, this effectively improves the data writing quality of the target data. In particular, this data can still maintain relatively high quality even when written under extreme conditions. Therefore, the time spent on subsequent refresh operations on this data can also be effectively reduced, thereby saving system resources.

[0069] In one embodiment, after detecting a trigger event, under the first refresh management strategy, the memory control circuit 23 can also detect whether a specific type of entity cell (also called an enabled cell) exists in the memory module 122. An enabled cell is used to store data migrated in the memory module 122 through a data compaction operation, and the enabled cell is not yet full. For example, assuming that a certain entity cell in the memory module 122 is not yet full, and this entity cell is used to store data migrated in the memory module 122 through a data compaction operation, the memory control circuit 23 can identify or determine this entity cell as an enabled cell.

[0070] In one embodiment, this data defragmentation operation may include garbage collection, wear leveling, hot and cold data splitting, or other operations involving data migration within the memory module 122. In one embodiment, the enabling unit is also referred to as an open block.

[0071] In one embodiment, after a trigger event is detected, under the first refresh management strategy, if (or in response to) the detection of an enabled unit in the memory module 122, the memory control circuit 23 may allow a refresh operation to be performed on the enabled unit after the time length during which refresh operations on the memory module 122 are prohibited reaches a critical value (also known as the time length critical value). In one embodiment, this time length critical value may be 10 seconds and may be adjusted according to practical needs.

[0072] In one embodiment, by prohibiting refresh operations on the memory module 122 for a certain period of time (i.e., a time length threshold) after the trigger event is detected, there is a high probability of successfully avoiding the high-risk time window of repeated power outages (e.g., within 10 seconds after the storage device 12 is powered on). After this high-risk time window has passed, the memory control circuit 23 can initiate a refresh operation on the enabled unit during a relatively stable period of the system. Therefore, in one embodiment, allowing a refresh operation on the enabled unit after the time length during which refresh operations on the memory module 122 are prohibited reaches the time length threshold can be regarded as delaying the refresh operation on the enabled unit after the trigger event is detected, thereby avoiding the high-risk time window of repeated power outages. Thus, the predetermined refresh work can be completed without affecting the performance of the storage device 12 and the user experience, thereby effectively extending the service life of the memory module 122.

[0073] In one embodiment, under the first refresh management strategy, the memory control circuit 23 can continuously (e.g., periodically) determine whether the storage device 12 has left the first extreme scenario (e.g., left the scenarios A, B, and / or C). If (or in response to) the storage device 12 leaving the first extreme scenario, the memory control circuit 23 can disable the first refresh management strategy.

[0074] In one embodiment, in response to a triggering event, the memory control circuit 23 may also detect whether the storage device 12 is in another scenario (also referred to as a second extreme scenario). If (or in response to) the storage device 12 is in the second extreme scenario, the memory control circuit 23 may initiate another strategy (also referred to as a second refresh management strategy).

[0075] In one embodiment, the second extreme scenario includes the following:

[0076] D. The total number of idle physical units in memory module 122 is less than a threshold (also known as the first quantity threshold).

[0077] In one embodiment, after detecting a trigger event, the memory control circuit 23 can determine whether the total number of idle physical units in the memory module 122 is less than a first quantity threshold. In one embodiment, this first quantity threshold can be 2 to 5 and can be adjusted according to practical needs. In one embodiment, once the total number of idle physical units in the memory module 122 is less than this first quantity threshold, the memory control circuit 23 can determine that the idle physical units in the memory module 122 are almost exhausted.

[0078] In one embodiment, upon detecting a trigger event, if (or in response to) the total number of idle physical units being less than this first quantity threshold (i.e., the idle physical units in memory module 122 are almost exhausted), the memory control circuit 23 can determine that the storage device 12 is in a second extreme scenario (i.e., scenario D above) and initiate a second refresh management strategy. However, if (or in response to) the total number of idle physical units being not less than this first quantity threshold (i.e., the storage device 12 is not in the second extreme scenario), the memory control circuit 23 may not initiate the second refresh management strategy.

[0079] In one embodiment, under the second refresh management strategy, the memory control circuit 23 can prioritize using the foreground bandwidth (or foreground resources) of the storage device 12 to perform refresh operations on the memory module 122. For example, under the second refresh management strategy, even if there is a host write operation (for storing target data) that needs to be performed, the memory control circuit 23 can still postpone (e.g., pause) this host write operation and prioritize performing refresh operations over the foreground to accelerate the release of idle physical units. Thus, under the second refresh management strategy, by actively performing refresh operations on the memory module 122, the efficiency of releasing (or reclaiming) idle physical units can be accelerated, thereby avoiding the exhaustion of idle physical units. This effectively improves the operational stability of the storage device 12.

[0080] In one embodiment, under the second refresh management strategy, the memory control circuit 23 can continuously (e.g., periodically) determine whether the storage device 12 has left the second extreme scenario (e.g., left scenario D as described above). If (or in response to) the storage device 12 leaving the second extreme scenario, the memory control circuit 23 can disable the second refresh management strategy.

[0081] In one embodiment, in response to a triggering event, the memory control circuit 23 may also detect whether the storage device 12 is in another scenario (also known as a non-extreme scenario). If (or in response to) the storage device 12 is in a non-extreme scenario, the memory control circuit 23 may activate another strategy (also known as a third refresh management strategy).

[0082] In one embodiment, the non-extreme scenario includes at least one of the following scenarios:

[0083] E. Storage device 12 is in an idle state;

[0084] F. Obtain a specific instruction from the host system 11, and this specific instruction is used to instruct the storage device 12 to enter an idle state or perform a background operation;

[0085] G. The total number of idle physical units in memory module 122 is between a first quantity threshold and another threshold (also known as a second quantity threshold).

[0086] In one embodiment, after detecting a trigger event, the memory control circuit 23 can determine whether the storage device 12 is in an idle state. In one embodiment, if (or in response to) the storage device 12 being in an idle state, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario (i.e., scenario E described above).

[0087] In one embodiment, when the storage device 12 is idle, the memory control circuit 23 may access the memory module 122 without responding to instructions from the host system 11. Conversely, when the storage device 12 is busy, the memory control circuit 23 may access the memory module 122 in response to instructions from the host system 11.

[0088] In one embodiment, the memory control circuit 23 can count the length of time that there is no data flow at the I / O interface (e.g., connection interface 121) between the storage device 12 and the host system 11. If (or in response to) this length of time reaches a threshold (also known as an idle threshold), the memory control circuit 23 can determine that the storage device 12 is in an idle state. In one embodiment, this idle threshold can be 10 ms or other lengths, and the present invention is not limited thereto. However, if (or in response to) this length of time does not reach the idle threshold, the memory control circuit 23 can determine that the storage device 12 is not in an idle state.

[0089] In one embodiment, the memory control circuit 23 can calculate the time elapsed between the time when the storage device 12 completes the previous operation instruction from the host system 11 and the current time. If (or in response to) this time elapsed, the memory control circuit 23 can determine that the storage device 12 is in an idle state. For example, this operation instruction may include a read instruction, a write instruction, an erase instruction, or other types of instructions from the host system 11. However, if (or in response to) this time elapsed, the memory control circuit 23 can determine that the storage device 12 is not in an idle state. In one embodiment, when the storage device 12 is in an idle state, once an operation instruction is obtained from the host system 11, the storage device 12 can automatically switch to a busy state (i.e., leave the idle state).

[0090] In one embodiment, after detecting a trigger event, the memory control circuit 23 may determine whether a specific instruction has been received from the host system 11. Specifically, this specific instruction is used to instruct the storage device 12 to enter an idle state or perform a background operation. In one embodiment, this specific instruction may include a Hibernate Enter instruction. Using the UFS standard as an example, this specific instruction may include the Enter H8 instruction.

[0091] In one embodiment, after a trigger event is detected, if a specific instruction (e.g., the Enter H8 instruction) is obtained (or responded to) from the host system 11, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario (i.e., scenario F described above).

[0092] In one embodiment, after detecting a trigger event, the memory control circuit 23 can determine whether the total number of idle physical units in the memory module 122 is between a first quantity threshold and a second quantity threshold. The second quantity threshold is greater than the first quantity threshold. For example, assuming the first quantity threshold is 5, the second quantity threshold can be 10. Furthermore, both the first and second quantity thresholds can be adjusted according to practical needs. In one embodiment, when the total number of idle physical units in the memory module 122 is between the first and second quantity thresholds, it indicates that although some or even a large number of idle physical units have been consumed, the situation requiring urgent release of idle physical units has not yet been reached (similar to scenario D). Therefore, in one embodiment, if (or in response to) the total number of idle physical units in the memory module 122 is between the first and second quantity thresholds, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario (i.e., scenario G described above).

[0093] In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in one of the aforementioned scenarios E, F, and G, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario. In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in two of the aforementioned scenarios E, F, and G, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario. In one embodiment, upon detecting a trigger event, if (or in response to) the storage device 12 being in all of the aforementioned scenarios E, F, and G simultaneously, the memory control circuit 23 can determine that the storage device 12 is in a non-extreme scenario. In one embodiment, the memory control circuit 23 can also add more scenarios related to non-extreme operation and / or non-extreme environments as non-extreme scenarios according to practical needs.

[0094] In one embodiment, under the third refresh management strategy, the memory control circuit 23 can restrict refresh operations to be performed only in the background. In another embodiment, under the third refresh management strategy, the memory control circuit 23 can allow refresh operations to be performed in the background when the background is idle.

[0095] In one embodiment, under the third refresh management strategy, the memory control circuit 23 can obtain operation instructions from the host system 11. In response to the operation instructions from the host system 11, the memory control circuit 23 can forcibly pause the ongoing refresh operation and execute the operation instructions in the foreground. If (or in response to) the completion of this operation instructions, the memory control circuit 23 can resume executing refresh operations in the background (including executing previously paused refresh operations and / or starting new refresh operations). In one embodiment, by activating a mild refresh strategy (i.e., the third refresh management strategy) in non-extreme scenarios (e.g., scenarios E, F, and / or G), the predetermined refresh work can also be completed without affecting the performance of the storage device 12 and the user experience, thereby effectively extending the lifespan of the memory module 122.

[0096] In one embodiment, under the third refresh management strategy, the memory control circuit 23 can continuously (e.g., periodically) determine whether the storage device 12 has left a non-extreme scenario (e.g., left the scenarios E, F, and / or G mentioned above). If (or in response to) the storage device 12 leaving a non-extreme scenario, the memory control circuit 23 can disable the third refresh management strategy.

[0097] In one embodiment, upon detecting a trigger event, in response to the trigger event, the memory control circuit 23 may sequentially detect whether the storage device 12 is in one of a plurality of scenarios (also referred to as candidate scenarios) based on a preset order (also referred to as performing a scenario scanning operation). Once it is determined that the storage device 12 is in a candidate scenario (also referred to as a target scenario) based on the preset order, the memory control circuit 23 may (immediately) activate a refresh management strategy corresponding to this target scenario (also referred to as a target refresh management strategy). Furthermore, after determining that the storage device 12 is in a target scenario, the memory control circuit 23 may (immediately) stop the aforementioned scenario scanning operation.

[0098] In one embodiment, the target scenario may include at least one of a first extreme scenario, a second extreme scenario, and a non-extreme scenario. Furthermore, the target refresh management strategy may include at least one of a first refresh management strategy, a second refresh management strategy, and a third refresh management strategy. In one embodiment, only one refresh management strategy will be activated at any given time, and multiple refresh management strategies will not be activated simultaneously.

[0099] In one embodiment, the aforementioned preset order reflects the individual refresh control urgency of multiple candidate scenarios. In one embodiment, these candidate scenarios include at least a first extreme scenario and a second extreme scenario. In one embodiment, the second extreme scenario is detected before the first extreme scenario. For example, the second extreme scenario reflects that the storage device 12 is close to being unable to continue performing host write operations; therefore, the refresh control urgency of the second extreme scenario is often higher than that of the first extreme scenario.

[0100] In one embodiment, after determining that the storage device 12 is in the target scene, the memory control circuit 23 continuously detects whether the storage device 12 has left the target scene. Before the storage device 12 leaves the target scene, the memory control circuit 23 continues to manage the memory module 122 based on this target refresh management strategy. However, after the storage device 12 leaves the target scene, the memory control circuit 23 may stop managing the memory module 122 based on this target refresh management strategy.

[0101] Figure 5 This is a schematic diagram illustrating the operation scenario of managing the memory module according to an embodiment of the present invention. Please refer to... Figure 5 In one embodiment, the memory control circuit 23 can detect trigger event 51 ( Figure 5 (This is marked as step 1). Upon detecting trigger event 51, in response to trigger event 51, memory control circuit 23 may perform a scene scan operation on storage device 12.

[0102] In one embodiment, during this scene scanning operation, the memory control circuit 23 can be based on a preset sequence (i.e., Figure 5The inspection sequence is from left to right, sequentially checking whether the storage device 12 is in one of the multiple candidate scenarios 52. Figure 5 (This is marked as step 2). For example, in this scene scanning operation, the memory control circuit 23 can sequentially determine whether the storage device 12 is in extreme scene 501, extreme scene 502, or non-extreme scene 503.

[0103] In one embodiment, once it is determined that the storage device 12 meets one of the extreme scenarios 501, 502, and 503, the memory control circuit 23 can (immediately) stop the scene scanning operation. Then, the memory control circuit 23 can manage the memory module 122 by applying the corresponding refresh management strategy (i.e., the target refresh management strategy) according to the determined scenario (i.e., the target scenario). Figure 5 (This is marked as step 3).

[0104] In one embodiment, during this scene scanning operation, the memory control circuit 23 can first determine whether the storage device 12 is in extreme scene 501. If the storage device 12 is in extreme scene 501, the memory control circuit 23 can identify extreme scene 501 as the target scene and stop the scene scanning operation. If the storage device 12 is not in extreme scene 501, the memory control circuit 23 can then determine whether the storage device 12 is in extreme scene 502. If the storage device 12 is in extreme scene 502, the memory control circuit 23 can identify extreme scene 502 as the target scene and stop the scene scanning operation. If the storage device 12 is still not in extreme scene 502, the memory control circuit 23 can then determine whether the storage device 12 is in a non-extreme scene 503. If the storage device 12 is in a non-extreme scene 503, the memory control circuit 23 can identify non-extreme scene 503 as the target scene and stop the scene scanning operation.

[0105] In one embodiment, extreme scenario 501 includes the aforementioned second extreme scenario (e.g., scenario D), extreme scenario 502 includes the aforementioned first extreme scenario (e.g., scenarios A, B, and / or C), and non-extreme scenario 503 includes the aforementioned non-extreme scenario (e.g., scenarios E, F, and / or G). In one embodiment, the inspection order (i.e., preset order) of the scene scanning operation for multiple candidate scenarios 52 can also be adjusted according to practical needs, and the present invention does not impose any limitations on it.

[0106] In one embodiment, if, after completing the scene scanning operation, the memory control circuit 23 determines that the storage device 12 is not in any candidate scene (e.g., extreme scene 501, extreme scene 502, and non-extreme scene 503), then the memory control circuit 23 can apply a preset refresh management strategy (also known as a conventional refresh management strategy) to manage the memory module 122. This preset refresh management strategy can be set by the user or manufacturer according to practical needs, and this invention does not impose any limitations on it.

[0107] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 6 In step S601, a trigger event is detected. In step S602, in response to the trigger event, it is detected whether the storage device is in a first extreme scenario. If (or in response to) the storage device is not in the first extreme scenario, the process can return to step S601 and reconfirm whether the storage device is in another scenario or perform other preset operations.

[0108] If (or in response to) the storage device being in the first extreme scenario, in step S603, a first refresh management strategy is initiated, and under the first refresh management strategy, refresh operations on the memory module are prohibited. In step S604, it is determined whether the storage device has left the first extreme scenario. If (or in response to) the storage device leaving the first extreme scenario, in step S605, the first refresh management strategy is disabled. If (or in response to) the storage device not leaving the first extreme scenario, the process can return to step S603, and the memory module can continue to be managed based on the first refresh management strategy.

[0109] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, a trigger event is detected. In step S702, the storage device is sequentially detected to determine whether it is in one of multiple candidate scenarios based on a preset order. In step S703, a corresponding refresh management strategy is activated according to (or in response to) the scenario in which the storage device is located, and the memory module is managed based on this refresh management strategy.

[0110] However, Figure 6 and Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 6 and Figure 7 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 6 and Figure 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0111] In summary, the memory management method and memory device proposed in this invention can bring one or more of the following beneficial technical effects:

[0112] Structural / functional improvements: Upgraded from a "fixed execution" to a "scene-aware, dynamic decision-making" intelligent structure. A risk avoidance mechanism (disabling refresh) and an experience optimization mechanism (interruptible, gentle refresh) have been introduced, resulting in more comprehensive functionality.

[0113] Improved reliability and extended lifespan: Effectively avoids data corruption that may be caused by forced refreshes under unstable conditions such as continuous power outages and extreme temperatures. By reducing unnecessary refresh cycles, it directly reduces physical wear and tear on the memory module, extending the device's lifespan.

[0114] Optimize user experience: The "gentle refresh" strategy ensures that background maintenance operations do not compete for foreground resources, the response latency of host commands is guaranteed, and the system runs more smoothly.

[0115] Cost and process: It is achieved entirely through firmware algorithm upgrades, without the need to modify hardware or increase costs, and is easy to deploy and apply on existing storage products.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: In response to a triggering event, it is detected whether the storage device is in a first extreme scenario; In response to the storage device being in the first extreme scenario, a first refresh management policy is initiated, and under the first refresh management policy, refresh operations on the memory module are prohibited; and In response to the storage device being removed from the first extreme scenario, the first refresh management policy is turned off.

2. The memory management method according to claim 1, characterized in that, The triggering event includes the storage device being powered on.

3. The memory management method according to claim 1, characterized in that, The first extreme scenario includes at least one of the following scenarios: The total number of refresh operations performed on the first entity unit in the memory module within a preset time range reaches the first critical value. The total number of consecutive refresh operations performed on the second entity unit in the memory module reaches the second critical value. The temperature of the storage device has reached a critical temperature value.

4. The memory management method according to claim 1, characterized in that, The memory module supports a first write mode and a second write mode, and the memory management method further includes: Under the first refresh management strategy, in response to a write command from the host system, the first write mode is forcibly enabled to perform a data write operation on the memory module. The first write mode has a higher first programming speed for a single physical cell in the memory module than the second write mode has a higher programming speed for the same single physical cell in the memory module.

5. The memory management method according to claim 1, characterized in that, The memory management method further includes: Under the first refresh management strategy, if an enabled unit is detected in the memory module, the refresh operation is allowed to be performed on the enabled unit after the time length during which the refresh operation on the memory module is prohibited reaches a time length threshold.

6. The memory management method according to claim 5, characterized in that, The open unit is used to store data that has been migrated in the memory module through data processing operations, and the open unit is not yet full.

7. The memory management method according to claim 1, characterized in that, The memory management method further includes: In response to the storage device being in the second extreme scenario, a second refresh management strategy is initiated, and under the second refresh management strategy, foreground bandwidth is preferentially used to perform the refresh operation on the storage module.

8. The memory management method according to claim 7, characterized in that, The second extreme scenario includes a total number of idle physical units in the memory module that is less than a critical quantity value.

9. The memory management method according to claim 1, characterized in that, The memory management method further includes: In response to the storage device being in a non-extreme scenario, a third refresh management strategy is initiated, and under the third refresh management strategy, the refresh operation is restricted to be performed only in the background.

10. The memory management method according to claim 9, characterized in that, The memory management method further includes: Under the third refresh management strategy, in response to an operation command from the host system, the ongoing refresh operation is forcibly suspended.

11. The memory management method according to claim 9, characterized in that, The non-extreme scenarios include at least one of the following scenarios: The storage device is in an idle state; Obtain specific instructions from the host system, and the specific instructions are used to instruct the storage device to enter the idle state or perform background operations; The total number of idle entity units in the memory module is between a first quantity threshold and a second quantity threshold.

12. The memory management method according to claim 1, characterized in that, In response to the triggering event, detecting whether the storage device is in the first extreme scenario includes: In response to the triggering event, the storage device is sequentially detected, based on a preset order, to determine whether it is in one of a plurality of candidate scenarios. The preset order reflects the urgency of refresh control for each of the multiple candidate scenarios. The multiple candidate scenarios include at least the first extreme scenario and the second extreme scenario, and the second extreme scenario is detected before the first extreme scenario.

13. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method according to any one of claims 1-12.

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