Memory management method, memory controller and computer program product

Abstract

The present disclosure provides a memory management method, a memory controller and a computer program product. The memory controller maintains a multi-layer mapping table including top layer mapping information as a read entry and at least one non-top layer mapping information. In response to a cumulative amount of received write data reaching a preset threshold, a mapping table update is triggered for a first portion of write data that has been accumulated when the preset threshold is reached, and only target non-top layer mapping information corresponding to the first portion of write data is updated in the at least one non-top layer mapping information before updating the top layer mapping information. When the target non-top layer mapping information is updated, a second portion of write data is obtained, and unit write data is formed based on the first portion of write data and the second portion of write data. In response to confirming that the unit write data meets a programming unit alignment and that programming has been completed, the top layer mapping information is updated to submit the mapping table update. In this way, the filling of data can be reduced, and the utilization of storage space can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to an update control technology for a multi-level mapping table in a storage device, a memory management method, a memory controller, and a computer program product. Background Technology

[0002] In a storage device, the memory controller stores data written by the host system to the memory module and maintains a mapping table to record the storage location of the written data within the memory module. To save storage space and ensure flexibility for random writes, the mapping table typically employs a multi-level management structure, indexing downwards from the top to the bottom, with the bottom level indicating the actual storage location of the written data within the memory module. When the accumulated amount of written data exceeds a preset threshold, the memory controller triggers a mapping table update. In existing practices, to maintain data consistency, the written data must first be programmed into the memory module, and then the mapping information at each level must be updated progressively from the bottom to the top. Furthermore, since the memory module is programmed in fixed-size programming units, if the written data to be programmed is not aligned with a programming unit, padding data must be added to fill the programming unit before programming can proceed. However, padding data increases the additional writes to the memory module, increasing write amplification. Moreover, data programming and mapping table updates are executed serially; updates to the mapping information at each level must wait until the written data has been programmed, extending the overall processing time and consequently impacting write performance. Summary of the Invention

[0003] In view of this, the present disclosure provides a memory management method, a memory controller, and a computer program product. When the accumulated amount of written data received reaches a preset threshold, a mapping table update is triggered for the first portion of written data accumulated at that threshold. Before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first portion of written data is updated in at least one layer of non-top-level mapping information. During the updating of the target non-top-level mapping information, a second portion of written data is acquired, and unit write data is formed based on the first and second portions of written data. After confirming that the unit write data satisfies programming unit alignment and programming is complete, the top-level mapping information is updated to submit the mapping table update. This reduces the need for padding data, ensures that the updating of the target non-top-level mapping information and the acquisition of the second portion of written data and the formation of unit write data overlap at least partially in time, and uses the top-level mapping information as the submission point for the mapping table update.

[0004] According to a first aspect of this disclosure, a memory management method is provided, applicable to a storage device configured with a memory controller and a memory module. The method includes: maintaining a multi-layer mapping table, the multi-layer mapping table including top-level mapping information as a read entry point and at least one layer of non-top-level mapping information; in response to the accumulated amount of written data received reaching a preset threshold, triggering a mapping table update for a first portion of written data accumulated when the preset threshold is reached, and updating only the target non-top-level mapping information corresponding to the first portion of written data in at least one layer of non-top-level mapping information before updating the top-level mapping information; during the updating of the target non-top-level mapping information, obtaining a second portion of written data, and forming unit write data based on the first portion of written data and the second portion of written data; and in response to the confirmation that the unit write data satisfies programming unit alignment and programming has been completed, updating the top-level mapping information to submit the mapping table update.

[0005] According to a second aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with a memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: maintain a multi-layer mapping table, the multi-layer mapping table including top-level mapping information as a read entry point and at least one layer of non-top-level mapping information; in response to the accumulated amount of written data received reaching a preset threshold, trigger a mapping table update for a first portion of written data accumulated when the preset threshold is reached, and before updating the top-level mapping information, update only the target non-top-level mapping information corresponding to the first portion of written data in at least one layer of non-top-level mapping information; during the updating of the target non-top-level mapping information, obtain a second portion of written data, and form unit write data based on the first portion of written data and the second portion of written data; and in response to the confirmation unit write data satisfying programming unit alignment and programming being completed, update the top-level mapping information to submit the mapping table update.

[0006] According to a third aspect of this disclosure, a computer program product is provided, including a computer program. When the computer program is loaded and executed by a memory controller of a storage device configured with a memory module, the memory controller performs the following steps: maintaining a multi-level mapping table, the multi-level mapping table including top-level mapping information as a read entry point and at least one layer of non-top-level mapping information; in response to the accumulated amount of written data received reaching a preset threshold, triggering a mapping table update for a first portion of written data accumulated when the preset threshold is reached, and updating only the target non-top-level mapping information corresponding to the first portion of written data in at least one layer of non-top-level mapping information before updating the top-level mapping information; during the updating of the target non-top-level mapping information, acquiring a second portion of written data, and forming unit write data based on the first portion of written data and the second portion of written data; and in response to the confirmation that the unit write data satisfies programming unit alignment and programming has been completed, updating the top-level mapping information to submit the mapping table update.

[0007] Based on the above, the memory management method, memory controller, and computer program product provided in this disclosure, when the accumulated amount of written data received reaches a preset threshold, triggers a mapping table update for the first portion of written data accumulated at the preset threshold. Before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first portion of written data is updated in at least one layer of non-top-level mapping information. During the update of the target non-top-level mapping information, the second portion of written data is acquired, and unit write data is formed based on the first portion of written data and the second portion of written data. In response to confirming that the unit write data satisfies programming unit alignment and has been programmed, the top-level mapping information is updated to submit the mapping table update. Thus, the effective written data acquired during the update of the target non-top-level mapping information can be used to form unit write data, thereby reducing the padding data added to satisfy programming unit alignment, and ensuring that the update of the target non-top-level mapping information and the acquisition of the second portion of written data and the formation of unit write data overlap at least partially in time, thereby reducing serial waiting. Furthermore, by updating the top-level mapping information to submit the mapping table update only after the unit write data has been programmed, the mapping information can take effect according to a predetermined submission order, thereby maintaining the consistency of the mapping update. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0009] Figure 2 This is a schematic diagram of the structure of a multi-layer mapping table according to an embodiment of the present disclosure;

[0010] Figure 3A This is a main flowchart of a memory management method according to embodiments of the present disclosure;

[0011] Figure 3B This is a detailed flowchart illustrating a memory management method according to embodiments of the present disclosure;

[0012] Figure 4 A flowchart illustrating a conventional mapping table update process according to embodiments of this disclosure;

[0013] Figure 5 This is a comparative schematic diagram showing the natural alignment of programming units according to embodiments of the present disclosure;

[0014] Figure 6 This is a flowchart illustrating the consistency between power failure reconstruction and submission point according to embodiments of this disclosure;

[0015] Figure 7 A timing diagram illustrating the internal execution timing of the memory controller according to an embodiment of the present disclosure;

[0016] Figure 8 A flowchart illustrating the second part of the write data mapping concurrent submission according to embodiments of this disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. (Refer to...) Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110, host memory 120, and a data transfer interface circuit 130. The processor 110 is electrically connected to both the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be electrically connected to each other via a system bus. The processor 110, host memory 120, and data transfer interface circuit 130 may be mounted on the motherboard of the host system 10.

[0019] Storage device 20 includes a memory controller 210, a memory module 220, and a connection interface circuit 230. The memory controller 210 includes a processor 211, a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214. The buffer memory 214 is, for example, random access memory (RAM). The memory module 220 is, for example, a rewritable non-volatile memory module.

[0020] The data transmission interface circuit 130 of the host system 10 is electrically connected to the connection interface circuit 230 of the storage device 20, so that the host system 10 can perform data access operations on the storage device 20. For example, the host system 10 can send write data or read commands to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230, and can receive read data or operation results returned by the storage device 20.

[0021] In one embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 can be interface circuits compatible with the same communication standard, and can transmit data, instructions, and response information via wired or wireless means. The storage device 20 is, for example, a USB flash drive, a memory card, or a solid-state drive (SSD). In other embodiments, the storage device 20 can also be a storage device connected to the host system 10 via wireless communication. This disclosure does not limit the specific form of the data transmission interface circuit 130, the connection interface circuit 230, and the storage device 20.

[0022] The host memory 120 is used to temporarily store instructions or data executed by the processor 110. The host memory 120 is, for example, dynamic random access memory (DRAM), static random access memory (SRAM), or other suitable memory.

[0023] The memory controller 210 controls the data writing, data reading, and data erasure of the memory module 220 according to instructions provided by the host system 10, and executes the memory management method provided in this disclosure. The various functions of the memory controller 210 can be implemented through hardware, firmware, software, or a combination thereof.

[0024] Processor 211 is hardware with computation and control capabilities, used to control the overall operation of memory controller 210. Processor 211 can execute control instructions or program code to control data management circuit 212 and memory interface control circuit 213 to perform write, read, and erase operations on memory module 220. Processor 211 can be, for example, a Central Processing Unit (CPU), microprocessor, digital signal processor (DSP), microcontroller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other circuits with computation and control capabilities.

[0025] Processor 211 is configured to maintain a multi-level mapping table 300, which includes top-level mapping information 301 as a read entry point and at least one layer of non-top-level mapping information 302. The multi-level mapping table 300 is used to record the mapping relationship between the logical address of the written data 310 and the physical storage location of the written data 310 in the memory module 220.

[0026] In response to the cumulative amount of written data 310 being received reaching a preset threshold, the processor 211 triggers a mapping table update for the first part of written data 311 that has been accumulated when the preset threshold is reached. Before updating the top-level mapping information 301, the processor 211 updates only the target non-top-level mapping information corresponding to the first part of written data 311 in at least one layer of non-top-level mapping information 302.

[0027] While updating the target non-top-level mapping information, processor 211 acquires the second part of write data 312 and forms unit write data 313 based on the first part of write data 311 and the second part of write data 312. In response to confirming that the unit write data 313 satisfies programming unit alignment and programming is complete, processor 211 updates the top-level mapping information 301 to submit the mapping table update. The specific structure of the multi-level mapping table 300 and the main and detailed processes of the memory management method are described in detail below. Figure 2 , Figure 3A and Figure 3B Further explanation.

[0028] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used for data transmission and temporary data storage under the control of the processor 211. For example, the data management circuit 212 can receive write data sent by the host system 10 through the connection interface circuit 230 and temporarily store the write data in the buffer memory 214; the data management circuit 212 can also program the write data in the buffer memory 214 into the memory module 220 through the memory interface control circuit 213. For read operations, the data management circuit 212 can obtain the read data from the memory module 220 through the memory interface control circuit 213 and transmit the read data to the host system 10 through the connection interface circuit 230.

[0029] In another embodiment, some or all of the functions of the data management circuit 212 may be implemented by the processor 211. The operations performed by the components of the memory controller 210 can also be regarded as operations performed by the memory controller 210.

[0030] The memory interface control circuit 213 is electrically connected between the processor 211, the data management circuit 212, and the memory module 220, and is used to send instructions, addresses, and data to the memory module 220 according to the control of the processor 211. The memory interface control circuit 213 is also used to receive data or status information returned by the memory module 220. For example, the processor 211 can send write instruction sequences, read instruction sequences, or erase instruction sequences to the memory module 220 through the memory interface control circuit 213 to control the memory module 220 to perform corresponding memory operations.

[0031] The memory controller 210 can establish a mapping relationship between logical addresses and physical addresses, and record this mapping relationship through a multi-level mapping table 300. The processor 211 can query the multi-level mapping table 300 according to the logical address to determine the corresponding physical address, and read the data in the corresponding physical address through the memory interface control circuit 213. The processor 211 can also update the corresponding mapping information when the written data 310 is allocated to a new physical storage location.

[0032] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data read from memory module 220, and system data required for the operation of memory controller 210. In one embodiment, processor 211 also maintains mapping information corresponding to written data 310 in buffer memory 214. When the cumulative amount of written data 310 received has not reached a preset threshold, processor 211 may temporarily not update the mapping information to memory module 220; when the cumulative amount of written data 310 received reaches the preset threshold, processor 211 triggers a mapping table update.

[0033] The memory module 220 is electrically connected to the memory interface control circuit 213 and serves as the storage medium for write data 310 and mapping information. Write data 310 may include user data sent by the host system 10, or data generated by the storage device 20 during internal data transfer, garbage collection (GC), or other internal operations and destined for the memory module 220. Therefore, write data 310 is not limited to data from the host system 10.

[0034] In one embodiment, the memory module 220 includes a plurality of memory chips, each memory chip including one or more planes, each plane including a plurality of physical blocks, and each physical block including a plurality of physical pages. The memory controller 210 can perform programming operations on the memory module 220 in physical pages, multiple physical pages, word lines, or other suitable data units via the memory interface control circuit 213. This disclosure does not limit the number of chips, planes, physical blocks, physical pages, or the specific size of each data unit in the memory module 220.

[0035] Based on the above Figure 1 The hardware structure of the host system and storage device shown indicates that the memory controller can execute the memory management method provided in this disclosure through the cooperation of the processor, data management circuit, memory interface control circuit, and buffer memory. When the cumulative amount of written data received reaches a preset threshold, the processor triggers a mapping table update for the first part of the written data, and before updating the top-level mapping information, only updates the target non-top-level mapping information corresponding to the first part of the written data; the processor also obtains the second part of the written data during the update of the target non-top-level mapping information, and forms unit written data based on the first part of the written data and the second part of the written data; after confirming that the unit written data meets the programming unit alignment and programming has been completed, the processor updates the top-level mapping information to submit the mapping table update.

[0036] Reference Figure 2In one embodiment, the multi-layer mapping table 300 maintained by the memory controller 210 includes a top-level mapping information 301 as a read entry point and at least one layer of non-top-level mapping information 302. Specifically, starting from the top-level mapping information 301, at least one layer of non-top-level mapping information 302 is indexed downwards sequentially. The lowest-level mapping information in the at least one layer of non-top-level mapping information 302 indicates the storage location of the written data 310 in the memory module 220, while the other mapping information in the top-level mapping information 301 and the at least one layer of non-top-level mapping information 302 respectively indicate the storage location of their next-level mapping information in the memory module 220; and the at least one layer of non-top-level mapping information 302 represents a finer-grained address range information than the top-level mapping information 301. In other words, the top-level mapping information 301 does not directly point to the storage location of the written data 310, but rather serves as a read entry point, indexing downwards to each non-top-level mapping information 302, with the lowest-level mapping information ultimately indicating the storage location of the written data 310 in the memory module 220.

[0037] In one embodiment, the non-top-level mapping information 302 can be a single layer. In this case, the multi-layer mapping table 300 consists of the top-level mapping information 301 and the non-top-level mapping information 302 forming a second-level mapping table. The top-level mapping information 301 serves as the read entry point, and the non-top-level mapping information 302 indexes the data to be written to the storage location of the data 310 in the memory module 220. In another embodiment, the non-top-level mapping information 302 is multi-layered, with each layer of non-top-level mapping information 302 indexed sequentially downwards from the top-level mapping information 301, and the address range represented by each layer of non-top-level mapping information 302 being finer than that of the layer above it.

[0038] The data to be written 310 includes, for example, data written by the host system 10 to the storage device 20 via the connection interface circuit 230, and also data generated by the storage device 20 during internal data transfer or garbage collection (GC) operations that is to be written to the memory module 220. In other words, the data to be written 310 is not limited to data from the host system 10; any data to be written to the memory module 220 and whose storage location is recorded by the multi-level mapping table 300 can be used as the data to be written 310.

[0039] In one embodiment, reference is made to Figure 2At least one layer of non-top-level mapping information 302 includes intermediate-level mapping information 303 and bottom-level mapping information 304, so that the multi-layer mapping table 300 constitutes a three-layer mapping table that sequentially includes top-level mapping information 301, intermediate-level mapping information 303, and bottom-level mapping information 304. Specifically, top-level mapping information 301 indicates the storage location of intermediate-level mapping information 303 in memory module 220, intermediate-level mapping information 303 indicates the storage location of bottom-level mapping information 304 in memory module 220, and bottom-level mapping information 304 indicates the storage location of the written data 310 in memory module 220.

[0040] Specifically, such as Figure 2 The data structure of the multi-layer mapping table 300 shown organizes the mapping information of each layer by mapping layer, index granularity, table entry content, and output pointer. The top-level mapping information 301 uses the target plane as the index granularity, and its table entry content records the storage location of the intermediate layer mapping information 303 and outputs a pointer to the intermediate layer mapping information 303 accordingly; the intermediate layer mapping information 303 uses the target block as the index granularity, and its table entry content records the storage location of the bottom-level mapping information 304 and outputs a pointer to the bottom-level mapping information 304; the bottom-level mapping information 304 uses the target page as the index granularity, and its table entry content records the physical storage location of the written data 310 and outputs a pointer to the written data 310. Thus, from the top-level mapping information 301 to the bottom-level mapping information 304, the address range corresponding to each level of mapping information is gradually refined. The top-level mapping information 301 corresponds to a coarser target plane granularity, the intermediate-level mapping information 303 corresponds to a target block granularity, and the bottom-level mapping information 304 corresponds to a finer target page granularity. This allows the bottom-level mapping information 304 to directly indicate the physical storage location of the written data 310 in the memory module 220 as the finest granularity of the mapping information.

[0041] In one embodiment, reference is made to Figure 2The mapping information at each level in the multi-level mapping table 300 can be organized into separate entries, and each entry can include only two fields: a first field indicating the mapping information identifier (ID) and a second field indicating the actual content of the mapping information. The first field indicates the mapping information identifier corresponding to the entry, used to locate the corresponding mapping information during hierarchical indexing; the second field records the actual content of the mapping information. For example, for top-level mapping information 301, the first field of its entry indicates the identifier of top-level mapping information 301, and the second field records its actual content, i.e., the storage location of the intermediate-level mapping information 303 in the memory module 220. Similarly, for bottom-level mapping information 304, the first field of its entry indicates the identifier of bottom-level mapping information 304, and the second field records its actual content, i.e., the physical storage location of the written data 310 in the memory module 220. Therefore, the mapping information at each level of the multi-level mapping table 300 can be organized using entries with only two fields: an identifier indicating the mapping information and an actual content indicating the mapping information.

[0042] In one embodiment, reference is made to Figure 2 In the update of the multi-level mapping table 300, the intermediate-level mapping information 303 is updated in response to a change in the storage location of the bottom-level mapping information 304, and the top-level mapping information 301 is updated in response to a change in the storage location of the intermediate-level mapping information 303. In other words, not every batch of written data 310 triggers a continuous rewrite of all levels in the multi-level mapping table 300, but rather it can be linked upwards from the bottom-level mapping information 304 as needed, only rewriting the upper-level mapping information when the storage location of the lower-level mapping information actually changes. On the other hand, in Figure 3A and Figure 3B In the process shown, updating the top-level mapping information 301 to submit this mapping table update is a submission control, used to make the target non-top-level mapping information a valid mapping; the on-demand linkage mechanism in this section does not exclude this submission control.

[0043] In another embodiment, the multi-layer mapping table 300 is not limited to three layers, but may include four or more layers of mapping information, wherein at least one non-top-level mapping information 302 has three or more layers, and is sequentially indexed downwards from the top-level mapping information 301 to the bottom-level mapping information, with the bottom-level mapping information indicating the storage location of the written data 310 in the memory module 220. That is, regardless of whether the multi-layer mapping table 300 has two, three, or four or more layers, the top-level mapping information 301 serves as the read entry point, and is sequentially indexed downwards to the bottom-level mapping information, with the bottom-level mapping information indicating the storage location of the written data 310 in the memory module 220.

[0044] Based on the above Figure 2The multi-level mapping table structure shown illustrates how the memory controller uses the top-level mapping information as the entry point to index downwards to each non-top-level mapping information. This ensures that the storage location of written data in the memory module is indicated by the lowest-level mapping information among the non-top-level mapping information. The top-level mapping information and the remaining mapping information indicate the storage location of their respective next-level mapping information in the memory module. Therefore, the multi-level mapping table can support two, three, and four or more levels of mapping structures, and can dynamically rewrite the corresponding mapping information from bottom to top as needed when the storage location between levels changes. When a mapping table update requires a commit, the commit is completed by updating the top-level mapping information.

[0045] Reference Figure 3A , Figure 3A This illustrates the main flow of the memory management method provided in this disclosure. This main flow is executed by processor 211 and includes steps S311 to S314. Compared to subsequent... Figure 3B The detailed process shown is as follows: Figure 3A This is used to illustrate the core timing of a mapping table update, namely, before updating the top-level mapping information 301, only the target non-top-level mapping information corresponding to the first part of the write data 311 is updated in at least one layer of non-top-level mapping information 302. During the update of the target non-top-level mapping information, the second part of the write data 312 is obtained. After the confirmation unit write data 313 satisfies the programming unit alignment and the programming is completed, the top-level mapping information 301 is updated to submit this mapping table update.

[0046] In step S311, the processor 211 maintains a multi-level mapping table 300. The multi-level mapping table 300 includes top-level mapping information 301 as a read entry point and at least one layer of non-top-level mapping information 302. In one embodiment, the top-level mapping information 301 serves as the entry point into the multi-level mapping table 300 during reading, and at least one layer of non-top-level mapping information 302 is used to inherit the index of the top-level mapping information 301 and further indicate the storage location of the written data 310 in the memory module 220. By maintaining the multi-level mapping table 300, the processor 211 can determine the physical storage location corresponding to the written data 310 by indexing the related non-top-level mapping information 302 level by level through the top-level mapping information 301 based on the logical address corresponding to the written data 310.

[0047] In step S312, in response to the accumulated received amount of written data 310 reaching a preset threshold, the processor 211 triggers a mapping table update for the first portion of written data 311 accumulated when the preset threshold is reached. Before updating the top-level mapping information 301, it updates only the target non-top-level mapping information corresponding to the first portion of written data 311 in at least one layer of non-top-level mapping information 302. Specifically, in one embodiment, the processor 211 does not update the top-level mapping information 301 in this stage, and only processes the target non-top-level mapping information corresponding to the first portion of written data 311 within the scope of at least one layer of non-top-level mapping information 302. Thus, the target non-top-level mapping information can be updated first, while the top-level mapping information 301 is retained until the subsequent submission stage before being updated. The "update only" in this step is used to limit the scope of non-top-level mapping information updates before the top-level submission, and does not exclude the processor 211 from updating the top-level mapping information 301 in step S314, nor does it exclude the processing of non-top-level mapping information corresponding to the second portion of written data 312 in other embodiments during the top-level submission stage.

[0048] In step S313, the processor 211 acquires the second portion of write data 312 during the update of the target non-top-level mapping information, and forms unit write data 313 based on the first portion of write data 311 and the second portion of write data 312. Specifically, in one embodiment, the second portion of write data 312 is write data 310 acquired during the update of the target non-top-level mapping information, which can be used to supplement the first portion of write data 311, so that the first portion of write data 311 and the second portion of write data 312 together constitute the unit write data 313 to be programmed. Since the second portion of write data 312 is acquired during the update of the target non-top-level mapping information, the acquisition of the second portion of write data 312 and the update of the target non-top-level mapping information can at least partially overlap in time, thereby reducing the serial waiting caused by the sequential execution of data processing and mapping information updates in the conventional processing flow.

[0049] In step S314, in response to the confirmation unit writing data 313 satisfying programming unit alignment and completing programming, the processor 211 updates the top-level mapping information 301 to submit this mapping table update. That is, the processor 211 does not submit this mapping table update immediately after the target non-top-level mapping information is updated, but only after the confirmation unit writing data 313 has satisfied programming unit alignment and been programmed and written to the memory module 220. By treating the update of the top-level mapping information 301 as a submission action, the target non-top-level mapping information updated before the top-level submission is not used as a valid mapping, and the submission of this mapping table update is completed by updating the top-level mapping information 301 after the unit writing data 313 has completed programming.

[0050] Figure 3B Further show Figure 3A A detailed implementation of the main process. Specifically, Figure 3B The process further elaborates on the following steps: maintaining the mapping information in random access memory when the preset threshold is not reached; updating only the target non-top-level mapping information after the preset threshold is reached and before updating the top-level mapping information; obtaining the second part of the written data 312; determining the programming unit alignment of the unit written data 313; adding the padding data 320 when the programming unit alignment is not met; and finally submitting the top-level mapping information 301 for this mapping table update.

[0051] Reference Figure 3B In one embodiment, the memory controller 210 executes the memory management method provided in this disclosure, so that when updating the multi-level mapping table 300, before updating the top-level mapping information 301, it only updates the target non-top-level mapping information corresponding to the first part of the written data 311, and after the confirmation unit writes the data 313 to satisfy the programming unit alignment and completes the programming, the update of the top-level mapping information 301 is used as the submission action for this mapping table update. This detailed process includes steps S321 to S327. Figure 3B The phase divider between China and Israel separates the process into a non-top-level update phase and a top-level commit phase, as described below. Figure 3B Each step is explained in detail.

[0052] In step S321, the processor 211 maintains a multi-layer mapping table 300, and when the cumulative amount of written data 310 received has not reached a preset threshold, it maintains the mapping information corresponding to the written data 310 in the random access memory. Specifically, in one embodiment, the random access memory is a buffer memory 214; during the period when the cumulative amount of written data 310 received has not reached the preset threshold, the processor 211 temporarily maintains the mapping information corresponding to the written data 310 in the buffer memory 214, and does not update the mapping information to the memory module 220, so as to reduce the number of writes to the memory module 220.

[0053] In step S322, in response to the accumulated received amount of written data 310 reaching a preset threshold, the processor 211 triggers a mapping table update for the first portion of written data 311 accumulated when the preset threshold is reached. Before updating the top-level mapping information 301, it updates only the target non-top-level mapping information corresponding to the first portion of written data 311 in at least one layer of non-top-level mapping information 302. Specifically, the first portion of written data 311 is the written data 310 accumulated when the preset threshold is reached. Before updating the target non-top-level mapping information, the processor 211 allocates a target physical storage location in the memory module 220 for the first portion of written data 311, so that the target non-top-level mapping information indicates the target physical storage location. The processor 211 programs the target non-top-level mapping information corresponding to the first portion of written data 311 into the memory module 220, and does not update the top-level mapping information 301 at this stage. At this time, the target non-top-level mapping information has not yet been indexed by the updated top-level mapping information 301, and therefore is not yet used as a valid mapping. The "update only" in this step is used to limit the objects that are updated in at least one layer of non-top-level mapping information 302 before the top-level commit, and does not exclude the processor 211 from updating the top-level mapping information 301 in the subsequent step S327. In one embodiment, the preset threshold is, for example, 16MB, which is accumulated by 4096 write data 310 of size 4KB; when the cumulative received amount of write data 310 has not reached 16MB, the mapping information corresponding to write data 310 is maintained in the buffer memory 214, and when the cumulative received amount reaches 16MB, the mapping table is updated.

[0054] In step S323, the processor 211 acquires the second portion of write data 312 during the update of the target non-top-level mapping information, and forms write data 313 based on the first portion of write data 311 and the second portion of write data 312. Specifically, in one embodiment, the second portion of write data 312 includes, for example, write data 310 subsequently received during the update of the target non-top-level mapping information. The operation of acquiring the second portion of write data 312 and the operation of updating the target non-top-level mapping information overlap at least partially in time, such as... Figure 3B The parallel block of step S323 is shown. The second part of the written data 312 can be used together with the first part of the written data 311 to form the unit written data 313, and can supplement the unit written data 313 to meet the data amount required for programming unit alignment; when the second part of the written data 312 is insufficient to supplement the data amount, padding data 320 can be added in the subsequent step S325. Figure 3B In the illustrated embodiment, the non-top-level mapping information corresponding to the second part of the written data 312 is not included in this mapping table update, but is reserved for the next mapping table update process; in Figure 8In another embodiment shown, the non-top-level mapping information corresponding to the second part of the written data 312 can be included in this mapping table update during the top-level commit phase.

[0055] In step S324, the processor 211 determines whether the data written by the unit 313 satisfies programming unit alignment. Programming unit alignment means that the amount of data written by the unit 313 matches the fixed size required for a single overall programming of the memory module 220. When the processor 211 determines that the data written by the unit 313 satisfies programming unit alignment, the process proceeds to step S326; when the processor 211 determines that the data written by the unit 313 does not satisfy programming unit alignment, the process proceeds to step S325. In one embodiment, the processor 211 can determine whether the data written by the unit 313 satisfies programming unit alignment through a flag bit in the alignment register.

[0056] In step S325, in response to the cell write data 313 not satisfying programming unit alignment, the processor 211 adds padding data 320 to the cell write data 313 so that the cell write data 313 after adding padding data 320 satisfies programming unit alignment and can enter the programming operation. Specifically, when the second part of the write data 312 obtained during updating the target non-top-level mapping information is insufficient to make the cell write data 313 satisfy programming unit alignment, the processor 211 adds padding data 320 to make up the amount of data required for the cell write data 313 to satisfy programming unit alignment. In one embodiment, the padding data 320 includes data with a value of zero or residual data from old pages in the memory module 220.

[0057] In step S326, the processor 211 confirms that the unit-written data 313 satisfies the programming unit alignment and completes the programming. Specifically, regardless of whether the unit-written data 313 is determined to satisfy the programming unit alignment in step S324 and directly proceeds to step S326, or whether it proceeds to step S326 after adding filler data 320 in step S325, the processor 211 programs and writes the unit-written data 313 that satisfies the programming unit alignment into the memory module 220 and confirms that the programming has been completed. In one embodiment, the processor 211 confirms that the unit-written data 313 has completed programming by using a programming completion flag, and only proceeds to step S327 after confirming that the unit-written data 313 has completed programming.

[0058] In step S327, after the processor 211 confirms that the written data 313 in the confirmation unit has completed programming, it updates the top-level mapping information 301 to submit this mapping table update. This makes the previously updated target non-top-level mapping information effective as a mapping through the index of the top-level mapping information 301, thereby allowing the first part of the written data 311 to be read through the multi-level mapping table 300. Regardless of whether the written data 313 originally satisfied the programming unit alignment, or whether it only satisfied the programming unit alignment after the padding data 320 was added in step S325, the processor 211 updates the top-level mapping information 301 only after the written data 313 in the confirmation unit has completed programming. Therefore, both the processing path that directly satisfies the alignment and the processing path that adds padding data 320 end with updating the top-level mapping information 301 as the submission of this mapping table update.

[0059] Based on the above Figure 3B The detailed process is as follows: When the accumulated amount of written data received reaches a preset threshold, the memory controller triggers a mapping table update for the first portion of written data. Before updating the top-level mapping information, it updates only the target non-top-level mapping information corresponding to the first portion of written data in at least one layer of non-top-level mapping information. The processor also uses the second portion of written data obtained during the update of the target non-top-level mapping information to form cell written data together with the first portion of written data. By determining the programming cell alignment and adding padding data when necessary, the processor ensures that the cell written data meets the programming cell alignment. After confirming that the cell written data has been programmed, the processor updates the top-level mapping information to submit this mapping table update. This reduces the need for padding data and ensures that the update of the target non-top-level mapping information and the acquisition of the second portion of written data and the formation of the cell written data overlap at least partially in time.

[0060] In one embodiment, Figure 3B The preset threshold shown can be an integer multiple of the programming unit size, so that the accumulated first part of the written data 311 when the preset threshold is reached is close to an integer multiple of the programming unit size, thereby reducing the amount of data to be filled in as padding data 320. In another embodiment, the processor 211 can adaptively adjust the preset threshold according to the operating status of the memory module 220. For example, when the number of erase / write cycles of the memory module 220 is high, the preset threshold can be increased to reduce the frequency of mapping table updates. Regardless of the value of the preset threshold, the processor 211 triggers a mapping table update when the accumulated amount of written data 310 reaches the preset threshold.

[0061] In one embodiment, Figure 3BThe programming unit used for alignment can be a single physical page of the memory module 220, in which case the data written to the unit 313 must meet the size of a single physical page; in another embodiment, the programming unit can be multiple physical pages or an entire word line of the memory module 220 programmed at once, in which case the data written to the unit 313 must meet the size of multiple physical pages or an entire word line. Regardless of whether the programming unit corresponds to a single physical page, multiple physical pages, or an entire word line, the processor 211 determines in step S324 whether the data written to the unit 313 meets the alignment requirements of the corresponding programming unit.

[0062] Reference Figure 4 , Figure 4 This illustrates a conventional processing flow as described in this disclosure. Figure 3B The detailed process is compared to a benchmark. In this traditional processing flow, to ensure that the mapping information points to the data storage location that has already been programmed, the data to be written is usually padded to meet the alignment requirements of the programming units and the programming is completed before updating the mapping information of each layer in sequence. This traditional processing flow includes steps S410 to S470, which are described below in conjunction with... Figure 4 illustrate.

[0063] In step S410, when the accumulated amount of data reaches a preset threshold, the memory controller triggers the mapping table update of the memory module 220.

[0064] In step S420, when the data does not meet the programming unit alignment requirement, the memory controller inserts padding data 320 to ensure that the data to be programmed meets the programming unit alignment requirement. Specifically, in this conventional processing flow, the mapping information needs to point to the data storage location that has already been programmed; therefore, the data must be programmed into the memory module 220 before the mapping table is updated. When the data to be programmed is insufficient to meet the programming unit alignment requirement, the memory controller typically inserts padding data 320, and the inserted padding data 320 is still written to the memory module 220, thus increasing the additional write to the memory module 220 and increasing write amplification.

[0065] In step S430, the memory controller triggers a programming operation to write data that meets the programming unit alignment requirements into the memory module 220.

[0066] In step S440, the memory controller waits for programming to complete in order to confirm that the data has been programmed into the memory module 220.

[0067] In step S450, the memory controller updates the underlying mapping information 304 after the data is programmed.

[0068] In step S460, the memory controller updates the intermediate layer mapping information 303.

[0069] In step S470, the memory controller updates the top-level mapping information 301. Specifically, in this conventional processing flow, the data programming, the update of the bottom-level mapping information 304, the update of the intermediate-level mapping information 303, and the update of the top-level mapping information 301 are performed sequentially. The update is only completed after the data programming is completed and the mapping information of each layer is updated in sequence, so the overall processing time is relatively long.

[0070] Based on the above Figure 4 The traditional processing flow shown requires that the data to be written must first be padded to meet the alignment of the programming units and the programming completed before the three-level mapping information is updated sequentially. This has two drawbacks: firstly, when the data to be written is insufficient to meet the alignment of the programming units, the padded data increases the additional writing to the memory module and increases write amplification; secondly, the data programming and the updating of each layer of mapping information are performed sequentially, making the overall processing time long. In contrast, this disclosure… Figure 3B In the detailed process shown, the second part of the write data is obtained during the update of the target non-top-level mapping information, and the second part of the write data and the first part of the write data are used together to form the unit write data, thereby reducing the filling of data and making the update of the target non-top-level mapping information overlap with the acquisition of the second part of the write data and the formation of the unit write data in time, thus shortening the overall update time.

[0071] Reference Figure 5 , Figure 5 This is a comparative diagram of the filling of programming units to illustrate the method of reducing the amount of filling data 320 written according to this disclosure. The programming unit is a fixed-size data unit of the memory module 220 that can be programmed entirely at once. Figure 5 The left half illustrates the traditional processing flow using programming unit 330 in a traditional scenario. Figure 5 The right half illustrates the processing flow of this disclosure using programming unit 331 in the scenario described herein. The two are two examples of the same programming unit concept under different processing flows.

[0072] exist Figure 5 In the traditional scenario on the left, the first part of the written data 311 does not meet the alignment requirements of the programming unit 330. Therefore, the traditional processing flow adds padding data 320 to make the programming unit 330 meet the programming unit alignment. Specifically, in one embodiment, the added padding data 320 is not the valid write data that the internal process of the host system 10 or storage device 20 actually needs to write, but it will still be written to the memory module 220, thus increasing the additional write to the memory module 220 and increasing write amplification.

[0073] exist Figure 5In the right half of the present disclosure scenario, during the updating of the target non-top-level mapping information, the processor 211 acquires the second part of write data 312 and makes the second part of write data 312 and the first part of write data 311 together form the cell write data 313. When the second part of write data 312 is sufficient to supplement the amount of data required for programming unit 331 to meet programming unit alignment, the first part of write data 311 and the second part of write data 312 can together constitute the cell write data 313 that meets programming unit alignment. Thus, the padding of fill data 320 can be reduced or avoided, thereby reducing write amplification of memory module 220.

[0074] In one embodiment, when the second part of the written data 312 is insufficient to supplement the amount of data required for programming unit 331 to meet programming unit alignment, the processor 211 adds padding data 320 as a supplementary process, so that the unit written data 313 after adding padding data 320 meets programming unit alignment and can be programmed. Compared with the traditional scenario where padding data 320 is needed to supplement the data to be programmed, in the scenario of this disclosure, the second part of the written data 312 obtained during the update of the target non-top-level mapping information can be used first to supplement the amount of data required for alignment, and padding data 320 is only added when the second part of the written data 312 is insufficient.

[0075] Based on the above Figure 5 The programming cell filling comparison shown illustrates that during the update of the target non-top-level mapping information, the memory controller acquires subsequently arriving write data and uses this subsequently arriving write data as the second part of the write data, which together with the previously accumulated first part of the write data forms the cell write data. Therefore, the amount of data required for programming cell alignment can be prioritized using the effective write data, and filler data is only added when the amount of data is still insufficient, thereby reducing the need for filler data addition.

[0076] Reference Figure 6 , Figure 6 This paper illustrates the power failure reconstruction and commit point consistency process of this disclosure, demonstrating how mapping consistency is maintained in the event of a power failure when the top-level mapping information 301 is used as the commit point. The process includes steps S610 to S650, which are described below in conjunction with... Figure 6 illustrate.

[0077] In step S610, before updating the top-level mapping information 301 to submit the current mapping table update, the processor 211 reads the logical address corresponding to the first part of the written data 311 along the mapping information indexed by the top-level mapping information 301 before the update, and the target non-top-level mapping information updated earlier is not used as a valid mapping. This target non-top-level mapping information is the mapping information corresponding to the first part of the written data 311 in the non-top-level mapping information 302. In other words, before the top-level mapping information 301 is updated and submitted, even if the target non-top-level mapping information corresponding to the first part of the written data 311 has been programmed and written to the memory module 220, this target non-top-level mapping information is still not used as a valid mapping, and the reading is still performed along the mapping information indexed by the top-level mapping information 301 before the update.

[0078] In step S620, processor 211 determines whether a power outage has occurred after updating the target non-top-level mapping information and before updating the top-level mapping information 301. If no power outage has occurred, the process proceeds to step S650; if a power outage has occurred, the process proceeds to the power failure scenario shown in step S630.

[0079] In step S650, the processor 211 updates the top-level mapping information 301 to submit the current mapping table update, so that the previously updated target non-top-level mapping information becomes a valid mapping through the index of the top-level mapping information 301. Accordingly, after the top-level mapping information 301 is updated and submitted, the target non-top-level mapping information corresponding to the first part of the written data 311 becomes effective through the index of the top-level mapping information 301, so that the first part of the written data 311 is read through the multi-level mapping table 300.

[0080] In step S630, in response to a power outage occurring after updating the target non-top-level mapping information but before updating the top-level mapping information 301, the previously updated target non-top-level mapping information is not used as a valid mapping because it was not indexed by the valid top-level mapping information 301 before the power outage. Furthermore, the reading of the logical address corresponding to the first part of the written data 311 is performed along the mapping information indexed by the valid top-level mapping information 301 before the power outage. In other words, since the top-level mapping information 301 was not updated before the power outage, the previously programmed target non-top-level mapping information is not used as a valid mapping because it was not indexed by the valid top-level mapping information 301, thus preventing the read entry from pointing to an uncommitted mapping.

[0081] In step S640, when the processor 211 is powered on again after a power outage, it scans the blocks in the memory module 220 that store the written data 310 page by page, reads the mapping information stored on the same page as the written data 310 to reconstruct the mapping of the corresponding written data 310, updates the target non-top-level mapping information, and finally updates the top-level mapping information 301. Specifically, when the processor 211 stores the written data 310 in the memory module 220, it stores the mapping information corresponding to the written data 310 on the same page as the written data 310. Therefore, when the processor 211 is powered on again after a power outage, it scans the blocks in the memory module 220 that store the written data 310 page by page, reads the mapping information stored on the same page as the written data 310 to reconstruct the mapping of the corresponding written data 310, updates the target non-top-level mapping information, and finally updates the top-level mapping information 301 to complete the submission of this mapping table update.

[0082] Based on the above Figure 6 The power-down reconstruction and commit point consistency process shown employs the memory controller, which uses the top-level mapping information as the commit point. This ensures that previously updated target non-top-level mapping information is only indexed and becomes effective after the top-level mapping information has been committed. Therefore, if a power outage occurs before the top-level mapping information has been committed, the previously updated target non-top-level mapping information is not considered valid because it was not indexed by the valid top-level mapping information before the power outage. Reading continues along the mapping information indexed by the valid top-level mapping information before the power outage. Furthermore, upon power restoration after the power outage, the mapping is reconstructed by scanning the blocks storing the written data page by page, reading the mapping information stored on the same page as the written data, updating the target non-top-level mapping information, and finally updating the top-level mapping information.

[0083] In one embodiment, Figure 6 When storing write data 310 in memory module 220, the mapping information stored on the same page as the write data 310 can be stored in a different area of ​​that page than the write data 310. Specifically, in addition to the data area used to store the write data 310, a physical page of memory module 220 also has an area for storing additional information. Processor 211 stores the mapping information corresponding to the write data 310 in the area for storing additional information, so that when processor 211 scans the page page by page after power-off and power-on, it can read the write data 310 and the corresponding mapping information from that page.

[0084] For example, a physical page of memory module 220 may include a data area for storing write data 310 and a relatively small supplementary information area. When processor 211 programs a write data 310 into the data area of ​​the physical page, it simultaneously programs the mapping information corresponding to the write data 310 into the supplementary information area of ​​the same physical page. This mapping information, for example, records the correspondence between the logical address of the write data 310 and its physical storage location in memory module 220. Accordingly, when processor 211 is powered on again after a power outage, it does not need to read a separately stored mapping table; it only needs to read the physical page storing the write data 310 page by page to simultaneously obtain the write data 310 and its mapping information from the same physical page, thereby reconstructing the mapping of the corresponding write data 310. Compared to storing the write data 310 and its mapping information separately on different physical pages, requiring separate readings during reconstruction, this embodiment uses sequential page access, allowing the write data 310 and its mapping information to be retrieved together in a single page read, thereby reducing the number of reads required to rebuild the mapping after a power outage. This extension is... Figure 6 The illustrated lower-level implementation of same-page sequential mapping does not change Figure 6 The steps shown are: scanning and reconstructing the mapping page by page after power-on.

[0085] In one embodiment, Figure 6 When the processor 211 scans the blocks of written data 310 stored in the memory module 220 page by page to rebuild the mapping after power failure and power-on, it can scan only the most recently programmed blocks that have not yet been committed by the top-level mapping information 301. Specifically, since the mappings committed by the top-level mapping information 301 are persistent and do not need to be rebuilt, the processor 211 can scan only the most recently programmed blocks that have not yet been committed to read the mapping information stored in the same page and rebuild the mapping corresponding to the written data 310, thereby narrowing the scope of the page scan.

[0086] For example, if among the multiple programmed blocks in memory module 220, only the mappings corresponding to some recently programmed blocks have not yet been committed by the top-level mapping information 301, then processor 211 only scans these uncommitted blocks page by page upon power-on, without needing to scan the remaining committed blocks in memory module 220. Accordingly, the scan amount required for processor 211 to rebuild the mapping after power failure is related to the amount of recently uncommitted write data 310, rather than the total capacity of memory module 220. Therefore, when the total capacity of memory module 220 is large and the amount of recently uncommitted data is relatively small, the scan time required to rebuild the mapping after power failure is shortened. This extension... Figure 6 The illustrated lower-level implementation method is a page-by-page scanning reconstruction, without changing the... Figure 6The steps shown are: reading the same-page sequential mapping to rebuild the mapping, then updating the target non-top-level mapping information, and finally updating the top-level mapping information 301.

[0087] Reference Figure 7 , Figure 7 A timing diagram illustrating the memory management method executed by the memory controller 210 shows the interaction sequence and time overlap of the host system 10, buffer memory 214, processor 211, and memory module 220 during a single mapping table update. The buffer memory 214 and processor 211 are located within the memory controller 210, and the memory module 220 is electrically connected to the memory controller 210. In this embodiment, the host system 10 serves as one of the sources of the written data 310. Figure 7 The sequence shown includes, in order, the cumulative triggering of stage 1, the update of the target non-top-level mapping information in stage 2, the alignment and programming in stage 3, and the top-level commit in stage 4, corresponding to steps S711 to S741. The following is a combination of... Figure 7 illustrate.

[0088] In stage 1, at step S711, the host system 10 continuously provides write data 310, and the memory controller 210 receives the write data 310 and temporarily stores it in the buffer memory 214 to accumulate a first portion of write data 311 in the buffer memory 214. At step S712, when the accumulated amount of write data 310 received reaches a preset threshold, the processor 211 triggers an update of the multi-level mapping table 300 for the first portion of write data 311 accumulated when the preset threshold is reached.

[0089] In stage 2, before updating the top-level mapping information 301, the processor 211 updates only the target non-top-level mapping information corresponding to the first part of the written data 311 in at least one layer of non-top-level mapping information 302, and the update of the target non-top-level mapping information at least partially overlaps with the reception and temporary storage time of the second part of the written data 312. Specifically, in step S721, the processor 211 programs the target non-top-level mapping information corresponding to the first part of the written data 311 into the memory module 220, and does not update the top-level mapping information 301 in this stage. In step S722, during the execution of step S721, the host system 10 continues to provide write data 310, and the memory controller 210 temporarily stores the subsequently received write data 310 as the second part of the written data 312 in the buffer memory 214, so that the reception and temporary storage of the second part of the written data 312 at least partially overlaps with the update of the target non-top-level mapping information in time. In step S723, the processor 211 forms a write data 313 based on the first part of the written data 311 and the second part of the written data 312.

[0090] In stage 3, at step S731, processor 211 determines whether the cell write data 313 satisfies programming cell alignment. When the cell write data 313 does not satisfy programming cell alignment, processor 211 adds padding data 320 to the cell write data 313 to make up the amount of data required to satisfy programming cell alignment. At step S732, processor 211 programs the cell write data 313 that satisfies programming cell alignment into memory module 220. At step S733, processor 211 confirms that the programming of cell write data 313 has been completed, and uses the completion of programming as a prerequisite for updating the top-level mapping information 301 to submit this mapping table update.

[0091] In stage 4, at step S741, after the confirmation unit completes the programming of the written data 313, the processor 211 updates the top-level mapping information 301 to submit this mapping table update. In this embodiment, the processor 211 programs the updated top-level mapping information 301 into the memory module 220, so that the previously updated target non-top-level mapping information becomes a valid mapping through the index of the top-level mapping information 301, thereby enabling the first part of the written data 311 to be read through the multi-level mapping table 300.

[0092] Based on the above Figure 7 The execution timing shown illustrates that while updating the target non-top-level mapping information corresponding to the first part of the write data, the memory controller continues to receive and temporarily store subsequently arriving write data. This subsequently arriving write data is then used as the second part of the write data, forming the cell write data together with the first part of the write data. Therefore, the update of the target non-top-level mapping information and the reception and temporary storage of the second part of the write data at least partially overlap in time. Furthermore, after the cell write data satisfies programming cell alignment and programming is completed, the top-level mapping information is updated to submit this mapping table update, thereby reducing the overall processing time caused by serial waiting.

[0093] Reference Figure 8 In another embodiment, the memory controller 210 may update the non-top-level mapping information corresponding to the second part of the written data 312 in conjunction with the top-level mapping information 301 during the current mapping table update, so that the first part of the written data 311 and the second part of the written data 312 can both be read through the multi-level mapping table 300 after the same submission. Figure 8 The process shown includes steps S810 to S840, which will be described in sequence below.

[0094] In step S810, the second part of the written data 312, together with the first part of the written data 311, forms the unit written data 313 and has been programmed and written into the memory module 220. Therefore, the physical storage location of the second part of the written data 312 in the memory module 220 has been determined. Based on this determined physical storage location, the processor 211 can establish or update the non-top-level mapping information corresponding to the second part of the written data 312, so that the non-top-level mapping information indicates the physical storage location of the second part of the written data 312 in the memory module 220.

[0095] In step S820, when the processor 211 updates the top-level mapping information 301 to submit this mapping table update, it also updates the non-top-level mapping information corresponding to the second part of the written data 312 in the non-top-level mapping information 302. The target non-top-level mapping information corresponding to the first part of the written data 311 has been updated in the aforementioned non-top-level update stage and is included in this submission as previously updated mapping information; the non-top-level mapping information corresponding to the second part of the written data 312 is updated in this step and is submitted together with the previously updated target non-top-level mapping information by the update of the top-level mapping information 301.

[0096] In step S830, after the top-level mapping information 301 is updated, the previously updated target non-top-level mapping information and the non-top-level mapping information corresponding to the second part of the written data 312 are both indexed by the top-level mapping information 301 and become valid mappings. That is to say, this update of the top-level mapping information 301 simultaneously establishes a valid index relationship to the above two sets of non-top-level mapping information, making the above two sets of non-top-level mapping information effective in the same submission.

[0097] In step S840, the processor 211 can locate the physical storage locations of the first part of the written data 311 and the second part of the written data 312 in the memory module 220 according to the completed and submitted multi-level mapping table 300, thereby reading the first part of the written data 311 and the second part of the written data 312. Therefore, the non-top-level mapping information corresponding to the second part of the written data 312 does not need to wait for the next mapping table update process, and the second part of the written data 312 can be read by the multi-level mapping table 300 immediately after the current mapping table update is completed and submitted.

[0098] In one embodiment, if the processor 211 has updated the non-top-level mapping information corresponding to the second part of the written data 312, but a power outage occurs before the top-level mapping information 301 is committed, then the previously updated target non-top-level mapping information and the non-top-level mapping information corresponding to the second part of the written data 312 are not used as valid mappings because they were not indexed by the top-level mapping information 301 that was valid before the power outage. After power is restored, the reading of the relevant logical address still follows the mapping information indexed by the top-level mapping information 301 that was valid before the power outage, and can be performed according to... Figure 6 The method shown reconstructs mappings that have not yet been committed.

[0099] It should be noted that, Figure 8 The method shown is the same as Figure 3B The method shown, which reserves the non-top-level mapping information corresponding to the second part of the written data 312 for the next mapping table update, represents two processing methods that can be selected for the same batch of second part written data 312. In a single mapping table update, the memory controller 210 can select one of these processing methods based on the configuration or operational requirements of the storage device 20. When using... Figure 3B In the method shown, the non-top-level mapping information corresponding to the second part of the written data 312 is reserved for the next mapping table update; when using Figure 8 When the method shown is used, the non-top-level mapping information corresponding to the second part of the written data 312 is included in this mapping table update, and takes effect in the same top-level commit as the previously updated target non-top-level mapping information.

[0100] Based on the above Figure 8 The second part of the written data is mapped to the same commit method. After the second part of the written data has been programmed and its physical storage location has been determined, the corresponding non-top-level mapping can be updated simultaneously during the top-level commit process. This ensures that both the first and second parts of the written data can be read after the same commit. This shortens the time the second part of the written data waits for subsequent mapping table updates and reduces the need for subsequent separate mapping updates and top-level commits, while maintaining consistency control to ensure that new mappings are not adopted as valid mappings before the top-level commit.

[0101] It should be noted that the specific values, thresholds, parameter ranges, and condition settings in the above embodiments are used to illustrate feasible implementation methods and are not intended to limit this disclosure. For example, a multi-layer mapping table may include two, three, four, or more layers of mapping information; the index granularity of each layer of mapping information may correspond to a plane, block, page, or other suitable address range; the organization method, table entry content format, and inter-layer indexing method of each layer of mapping information can be set according to the physical organization architecture of the memory module. In addition, the preset threshold for triggering mapping table updates, the programming unit size on which programming unit alignment is based, the content of the fill data, the area configuration when written data and corresponding mapping information are stored on the same page, and the block range scanned page by page when power is turned off and then restored, can all be adjusted according to the characteristics of the storage medium, application requirements, and the operating status of the memory module. Among them, the programming unit may correspond to a single physical page, multiple physical pages, an entire word line, or other data units that the memory module can program as a whole; the fill data may include data with a value of zero, residual data of old pages, or other data that can be used to supplement the amount of data required for programming unit alignment.

[0102] In another embodiment, this disclosure also provides a computer program product including a computer program. When the computer program is loaded and executed by a memory controller of a storage device configured with a memory module, the memory controller performs the memory management method provided in this disclosure. The computer program can be stored in a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory, a magnetic disk, or an optical disk. Thus, the technical solution of this disclosure can be implemented through a computer program product.

[0103] Based on the above, the memory management method, memory controller, and computer program product provided in this disclosure, when the accumulated amount of written data received reaches a preset threshold, triggers a mapping table update for the first portion of written data accumulated at the preset threshold. Before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first portion of written data is updated in at least one layer of non-top-level mapping information. During the update of the target non-top-level mapping information, the second portion of written data is obtained, and unit write data is formed based on the first portion of written data and the second portion of written data. When the second portion of written data is insufficient to satisfy the programming unit alignment, padding data can be added to supplement the amount of data required to satisfy the programming unit alignment. Thus, the update of the target non-top-level mapping information and the acquisition of the second portion of written data and the formation of the unit write data can at least partially overlap in time, thereby reducing serial waiting and reducing the padding data added to satisfy the programming unit alignment. After confirming that the unit write data satisfies the programming unit alignment and that programming has been completed, the top-level mapping information is updated to submit the mapping table update, so that the previously updated target non-top-level mapping information becomes effective as a valid mapping through the index of the top-level mapping information. If a power outage occurs after updating the target non-top-level mapping information but before updating the top-level mapping information, the previously updated target non-top-level mapping information will not be used as a valid mapping because it was not indexed by the top-level mapping information that was valid before the power outage. Reading the logical address corresponding to the first part of the written data will still be performed according to the mapping information indexed by the top-level mapping information that was valid before the power outage. Therefore, this disclosure can simultaneously reduce the writing of fill data, shorten the overall time of mapping table updates, and maintain mapping consistency under power failure conditions.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method, applicable to a storage device configured with a memory controller and a memory module, characterized in that, The method includes: Maintain a multi-level mapping table, which includes top-level mapping information as the entry point for reading and at least one layer of non-top-level mapping information; In response to the cumulative amount of written data received reaching a preset threshold, a mapping table update is triggered for the first part of written data accumulated when the preset threshold is reached, and before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first part of written data is updated in the at least one layer of non-top-level mapping information. During the updating of the target non-top-level mapping information, a second portion of write data is obtained, and data is written based on the first portion of write data and the second portion of write data forming unit; and In response to confirming that the data written to the cell satisfies the programming cell alignment and that programming has been completed, the top-level mapping information is updated to submit the mapping table update.

2. The memory management method according to claim 1, characterized in that, The at least one layer of non-top-level mapping information includes intermediate-level mapping information and bottom-level mapping information, so that the multi-layer mapping table constitutes a three-layer mapping table that sequentially includes the top-level mapping information, the intermediate-level mapping information, and the bottom-level mapping information. The top-level mapping information indicates the storage location of the intermediate-level mapping information in the memory module, the intermediate-level mapping information indicates the storage location of the bottom-level mapping information in the memory module, and the bottom-level mapping information indicates the storage location of the written data in the memory module.

3. The memory management method according to claim 2, characterized in that, The method further includes: In the mapping table update, the intermediate layer mapping information is updated in response to a change in the storage location of the underlying mapping information; and In response to a change in the storage location of the intermediate layer mapping information, the top-level mapping information is updated.

4. The memory management method according to claim 1, characterized in that, The multi-level mapping table includes four or more layers of mapping information. The at least one layer of non-top-level mapping information includes three or more layers of non-top-level mapping information, which are sequentially indexed down from the top-level mapping information to the bottom-level mapping information, and the bottom-level mapping information indicates the storage location of the written data in the memory module.

5. The memory management method according to claim 1, characterized in that, The storage device is further configured with random access memory, and the method further includes: When the cumulative amount of written data received does not reach the preset threshold, the mapping information corresponding to the written data is maintained in the random access memory; and In response to the cumulative amount of written data received reaching the preset threshold, the mapping information maintained in the random access memory is updated to the memory module.

6. The memory management method according to claim 1, characterized in that, The second part of the write data includes subsequently received write data during the updating of the target non-top-level mapping information. The subsequently received write data is used to form the cell write data together with the first part of the write data, and to supplement the amount of data required by the cell write data to meet the alignment of the programming unit. The non-top-level mapping information corresponding to the data written in the second part is not included in this mapping table update, but is reserved for the next mapping table update process.

7. The memory management method according to claim 1, characterized in that, The method further includes: In response to the fact that the cell write data does not meet the programming cell alignment, padding data is added to the cell write data so that the cell write data after adding the padding data meets the programming cell alignment and the programming is completed; and After the populated data is filled in and the programming is completed, the top-level mapping information is updated to submit the mapping table update.

8. The memory management method according to claim 7, characterized in that, The filling data includes data with a value of zero or residual data from old pages in the memory module.

9. The memory management method according to claim 1, characterized in that, The method further includes: Before updating the top-level mapping information to submit the mapping table update, the reading of the logical address corresponding to the first part of the written data is performed along the mapping information indexed by the top-level mapping information before the update, and the target non-top-level mapping information updated first is not used as a valid mapping; and In response to updating the top-level mapping information, the previously updated target non-top-level mapping information is indexed by the updated top-level mapping information and becomes a valid mapping.

10. The memory management method according to claim 1, characterized in that, The method further includes: In response to a power outage occurring after updating the target non-top-level mapping information but before updating the top-level mapping information, the previously updated target non-top-level mapping information is not used as a valid mapping because it is not indexed by the top-level mapping information that was valid before the power outage, and the reading of the logical address corresponding to the first part of the written data is performed along the mapping information indexed by the top-level mapping information that was valid before the power outage.

11. The memory management method according to claim 10, characterized in that, The method further includes: When storing the written data in the memory module, the mapping information corresponding to the written data is stored on the same page as the written data; and In response to power failure and subsequent power restoration, the memory module is scanned page by page to access the blocks where the written data is stored. The mapping information stored on the same page as the written data is read to reconstruct the mapping corresponding to the written data. Then, the target non-top-level mapping information is updated, and finally, the top-level mapping information is updated.

12. The memory management method according to claim 1, characterized in that, The method further includes: When updating the top-level mapping information to submit the mapping table update, the non-top-level mapping information corresponding to the second part of the written data in the at least one layer of non-top-level mapping information is also updated, so that the previously updated target non-top-level mapping information and the non-top-level mapping information corresponding to the second part of the written data are both effective through the index of the top-level mapping information, thereby allowing the first part of the written data and the second part of the written data to be read through the multi-layer mapping table.

13. A memory controller suitable for a storage device configured with a memory module, characterized in that, The memory controller includes: Memory interface control circuitry, for electrically connecting to the memory module; and A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Maintain a multi-level mapping table, which includes top-level mapping information as the entry point for reading and at least one layer of non-top-level mapping information; In response to the cumulative amount of written data received reaching a preset threshold, a mapping table update is triggered for the first part of written data accumulated when the preset threshold is reached, and before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first part of written data is updated in the at least one layer of non-top-level mapping information. During the updating of the target non-top-level mapping information, a second portion of write data is obtained, and data is written based on the first portion of write data and the second portion of write data forming unit; and In response to confirming that the data written to the cell satisfies the programming cell alignment and that programming has been completed, the top-level mapping information is updated to submit the mapping table update.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is loaded and executed by the memory controller of a storage device configured with a memory module, the memory controller performs the following steps: Maintain a multi-level mapping table, which includes top-level mapping information as the entry point for reading and at least one layer of non-top-level mapping information; In response to the cumulative amount of written data received reaching a preset threshold, a mapping table update is triggered for the first part of written data accumulated when the preset threshold is reached, and before updating the top-level mapping information, only the target non-top-level mapping information corresponding to the first part of written data is updated in the at least one layer of non-top-level mapping information. During the updating of the target non-top-level mapping information, a second part of the write data is obtained, and write data is formed based on the first part of the write data and the second part of the write data; as well as In response to confirming that the data written to the cell satisfies the programming cell alignment and that programming has been completed, the top-level mapping information is updated to submit the mapping table update.

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