Data processing method, computer device, storage medium and program product

Abstract

This application discloses a data processing method, computer device, storage medium, and program product. The method is applied to a flash memory chip and includes: for each storage page in the flash memory chip, obtaining the number of read accesses and the bit flip count of the storage page; if the number of read accesses exceeds a real-time refresh threshold, and / or the growth rate of the bit flip count exceeds a preset rate, then the storage page is determined to be a risk page; the real-time refresh threshold is related to the current temperature of the flash memory chip and the current refresh interval of the storage page; the data of the risk page is migrated to a target page, and the logical address of the data is updated based on the address of the target page; the target page is a free storage page within the storage block where the risk page is located. This method enables read interference monitoring at the storage page level, accurately identifies risk pages significantly affected by read interference, and performs timely data migration to eliminate read interference problems of risk pages, thus effectively preventing data errors.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, computer equipment, storage medium, and program product. Background Technology

[0002] SPI NAND flash memory is widely used in embedded devices such as industrial HMIs, data acquisition terminals, and IoT gateways for code and data storage due to its low cost, large capacity, and simple interface. However, NAND flash memory suffers from read / write interference, a physical phenomenon where the applied voltage during data reading and writing to a memory page generates electrical stress on other pages within the same memory block. Especially in high-frequency read / write scenarios, this accumulated electrical stress can cause bit flips in other memory pages. When the number of bit flips exceeds the flash memory's error correction capability, it can lead to data errors, file system corruption, and operating system malfunctions.

[0003] Currently, when the number of reads of a storage block exceeds a threshold, all data in the block is migrated and then erased to refresh the block and avoid data errors caused by accumulated bit flips due to frequent reads. However, refreshing the storage block has drawbacks such as long processing time, high resource consumption, and flash memory wear. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a data processing method, computer equipment, storage medium and program product that can realize read interference monitoring at the storage page level, accurately identify risk pages that are greatly affected by read interference, and perform timely data migration to eliminate read interference problems of risk pages and achieve effective prevention of data errors.

[0005] Firstly, this application provides a data processing method applied to a flash memory chip. The method includes: For each memory page in the flash memory chip, obtain the number of read accesses and the bit flip count for that memory page; If the number of read accesses exceeds the real-time refresh threshold, and / or the growth rate of the bit flip count exceeds the preset rate, the storage page is determined to be a risk page; the real-time refresh threshold is related to the current temperature of the flash memory chip and the current refresh interval of the storage page; The data from the risky page is migrated to the target page, and the logical address of the data is updated based on the address of the target page; the target page is a free storage page within the storage block where the risky page is located.

[0006] In conjunction with the first aspect, in one possible implementation, the data processing method further includes: for each storage page in the flash memory chip, obtaining the write access count of the storage page; if the write access count exceeds the write access threshold, performing bit flip detection on each adjacent page; adjacent pages are other storage pages within the storage block where the storage page is located; for each adjacent page, if a bit flip error exists in the adjacent page, the adjacent page is determined to be a risk page, and the data in the risk page is migrated to other free storage pages within the storage block.

[0007] In conjunction with the first aspect, in one possible implementation, the process of determining the real-time refresh threshold includes: determining the current refresh interval duration of the storage page based on the current time and the last data migration time of the storage page; determining a first coefficient based on the current temperature of the flash memory chip, and determining a second coefficient based on the current refresh interval duration; the first coefficient is negatively correlated with the current temperature, and the second coefficient is negatively correlated with the current refresh interval duration; determining the real-time refresh threshold based on the reference refresh threshold, the first coefficient, and the second coefficient; the reference refresh threshold is related to the erase limit and bit flip error correction limit of the flash memory chip.

[0008] In conjunction with the first aspect, in one possible implementation, the data processing method further includes: determining a refresh limit based on a baseline refresh threshold and a limit coefficient; if the real-time refresh threshold is lower than the refresh limit, then updating the real-time refresh threshold to the refresh limit.

[0009] In conjunction with the first aspect, in one possible implementation, before migrating data to the risk page, the data processing method further includes: generating a refresh task corresponding to the risk page and adding the refresh task to the refresh queue; when the operating system load meets the light load condition, executing the refresh task in the refresh queue; the light load condition includes the CPU resource utilization rate being less than a first threshold and the number of tasks to be executed being less than a second threshold.

[0010] In conjunction with the first aspect, in one possible implementation, data migration of risky pages includes: after determining that a storage page is a risky page, the flash driver in the operating system kernel generates a data copy instruction and sends it to the flash chip, instructing the flash chip to read the data of the risky page into the cache and then write it to the target page.

[0011] In conjunction with the first aspect, in one possible implementation, after migrating the risky page, the data processing method further includes: clearing the read access count and bit flip count of the storage page to zero.

[0012] Secondly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method described in the first aspect.

[0013] Thirdly, this application also provides a computer-readable storage medium. This computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the method described in the first aspect.

[0014] Fourthly, this application also provides a computer program product. This computer program product includes a computer program that, when executed by a processor, implements the method described in the first aspect.

[0015] This application provides a data processing method, computer device, storage medium, and program product that can acquire the read access count and bit flip count of each storage page in a flash memory chip. When the read access count exceeds a real-time refresh threshold and / or the growth rate of the bit flip count exceeds a preset rate, the storage page is identified as a risk page, data is migrated to the risk page, and the logical address of the data is updated based on the address of the target page. The method provided in this application achieves read interference monitoring at the storage page level by setting a counter corresponding to each storage page in the flash memory driver, accurately identifying risk pages significantly affected by read interference, and promptly migrating data to risk pages to eliminate read interference problems. This avoids the cumulative bit flips of storage pages triggering the erasure of the entire storage block, avoiding excessive resource consumption and flash memory wear. Moreover, this application analyzes the degree of read interference using both read access count and bit flip count, and promptly migrates data to risk pages, effectively preventing data errors. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart of a data processing method in one embodiment; Figure 2 This is a schematic diagram illustrating the process of data migration of storage pages under different circumstances in one embodiment; Figure 3 This is another flowchart illustrating the data processing method in one embodiment; Figure 4 This is another flowchart illustrating the data processing method in one embodiment; Figure 5 This is another flowchart illustrating the data processing method in one embodiment; Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0017] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. Furthermore, the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The terms "first" and "second," etc., in the specification and claims of the embodiments of this application are used to distinguish different objects, not to describe a specific order of objects.

[0019] SPI NAND flash memory is widely used in embedded devices such as industrial HMIs, data acquisition terminals, and IoT gateways for code and data storage due to its low cost, large capacity, and simple interface. However, NAND flash memory suffers from read / write interference. When data is read from or written to a memory page, the applied voltage generates electrical stress on other pages within the same memory block. Especially in high-frequency read / write scenarios, accumulated electrical stress can cause bit flips in other memory pages. When the number of bit flips exceeds the flash memory's error correction capability, it can lead to data errors, file system corruption, and operating system malfunctions. Currently, when the number of reads to a memory block exceeds a threshold, all data in the block is migrated and erased to refresh the block and avoid data errors caused by accumulated bit flips from frequent reads. However, refreshing data at the block level has drawbacks such as long refresh times, resource consumption, and flash memory wear.

[0020] Based on this, embodiments of this application provide a data processing method, computer device, storage medium, and program product that can achieve read interference monitoring at the storage page level, accurately identify risk pages that are significantly affected by read interference, and promptly migrate data to eliminate read interference problems of risk pages, thereby effectively preventing data errors.

[0021] In one embodiment, a data processing method is provided, which can be applied to a flash memory chip, specifically to a driver program for the flash memory chip, which performs data processing on the flash memory chip. The flash memory chip can be an SPI NAND flash memory, and the driver for the SPI NAND flash memory is located in the operating system kernel. Figure 1 As shown, the data processing method provided in this application embodiment may include the following steps: Step 101: For each memory page in the flash memory chip, obtain the number of read accesses and the bit flip count of the memory page.

[0022] The method provided in this application can detect and prevent interference during read and write operations on a per-page basis. Specifically, this application can first set a read access counter and a bit flip counter in the flash driver of the operating system kernel to record the number of read accesses and the bit flip count for each memory page. The memory page-related counting information (read access count and bit flip count) recorded by the counters, along with the corresponding memory page information (e.g., address, current refresh interval, bit flip error correction capability, etc.), can be stored in a standard structure. When the operating system is Linux, the above information can be stored in the form of a read_disturb_stats structure.

[0023] In this embodiment of the application, the flash memory driver can monitor the number of read accesses and the number of bit flips of each memory page in real time through a read access counter and a bit flip counter.

[0024] Step 102: If the number of read accesses exceeds the real-time refresh threshold and / or the growth rate of the bit flip count exceeds the preset rate, then the storage page is determined to be a risk page.

[0025] The real-time refresh threshold is related to the current temperature of the flash memory chip and the current refresh interval of the storage page. The current refresh interval refers to the time elapsed since the last data migration of the storage page.

[0026] Considering that the more read accesses a storage page receives, the greater the accumulated electrical stress, the more likely it is to cause bit flip accumulation, leading to uncorrectable data errors in the storage page; and the faster the bit flip count grows, the more likely it is to cause bit flip accumulation. Therefore, this application embodiment determines whether data migration is needed for the storage page to solve the bit flip accumulation problem based on both the number of read accesses and the growth rate of the bit flip count.

[0027] Specifically, the baseline refresh threshold of the flash memory chip can be adjusted based on the current temperature of the flash memory chip and the current refresh interval of the storage pages to determine the real-time refresh threshold. This real-time refresh threshold represents the critical number of read accesses required to migrate data across each storage page of the flash memory chip. The baseline refresh threshold is related to the specifications of the flash memory chip (maximum block erase count, bit flip error correction capability, etc.); the current temperature is negatively correlated with the real-time refresh threshold, meaning that the refresh threshold should be lowered in high-temperature environments to increase the storage page refresh frequency and ensure timely data refresh in high-temperature risk environments; the current refresh interval is negatively correlated with the real-time refresh threshold, meaning that prolonged periods without data refresh can reflect the accumulation of bit flip errors, and the refresh threshold should be lowered to refresh the storage pages in a timely manner and resolve accumulated bit flip errors.

[0028] After determining the real-time refresh threshold, the current read access count of the storage page can be compared with the real-time refresh threshold. If the read access count is greater than the real-time refresh threshold, it means that the read access count has exceeded the critical value. The accumulated bit flips can easily lead to uncorrectable data errors. Therefore, the storage page is identified as a risk page that needs to be migrated.

[0029] Alternatively, the bit flip count per unit time of a storage page can be obtained to determine the growth rate of the bit flip count, which is then compared with a preset rate. The preset rate can be pre-set and stored locally in the operating system, representing a critical growth rate at which data migration of each storage page is required to avoid the accumulation of bit flips. If the bit flip count growth rate exceeds the preset rate, it indicates that the growth rate has exceeded the critical value. In this case, rapid accumulation of bit flips can easily lead to uncorrectable data errors; therefore, the storage page is identified as a risk page requiring data migration.

[0030] Alternatively, if the number of read accesses exceeds the real-time refresh threshold and the bit flip count increases at a rate greater than the preset rate, the storage page is identified as a risk page requiring data migration.

[0031] Step 103: Migrate the data from the risk page to the target page, and update the logical address of the data based on the address of the target page.

[0032] The target page is a free storage page within the storage block where the risk page is located.

[0033] In this embodiment, the flash memory chip migrates data from risky pages by responding to a data copy instruction sent by the driver. Specifically, after determining that a storage page is a risky page, the flash memory driver in the operating system kernel generates a data copy instruction and sends it to the flash memory chip, instructing the flash memory chip to read the data of the risky page into its cache and then write it to the target page.

[0034] In this embodiment, after determining a storage page to be a risky page based on read access counts and bit flip counts, the flash memory driver in the operating system kernel can first identify free storage pages in the storage block where the risky page is located that have been erased and not programmed (written). Then, based on the address of the risky page and the address of the target page, it generates a data copy instruction and sends it to the flash memory chip. Responding to the data copy instruction, the flash memory chip first reads the data of the risky page into its cache, and then writes the data of the risky page in the cache into the target page, thus realizing the data migration of the risky page. For example, the driver of the SPI NAND flash memory chip in the Linux operating system can instruct the SPI NAND flash memory chip to perform a data migration operation for risky pages using a Copy-Back instruction.

[0035] Furthermore, to ensure the accuracy of data access, the address mapping table (such as the FTL mapping table) also needs to be updated to change the logical address of the risk page data to the address of the target page.

[0036] In one possible implementation, after migrating the data for the risky page, the read access count and bit flip count of the storage page are reset to zero. It's understandable that after migrating the data for the risky page, the bit flip problem of the risky page's data is resolved; therefore, the read access count and bit flip count corresponding to the risky page can be reset to zero.

[0037] In one possible implementation, if the bit-flip count of a storage page exceeds the bit-flip error correction limit of the flash memory chip, an uncorrectable error is determined, requiring an erase operation on the storage block containing the page. Specifically, after reading the data from all storage pages containing valid data in the storage block into a cache, the storage block is erased, and finally, the data in the cache is rewritten into the storage block. The bit-flip error correction limit represents the critical number of bit-flipped data bits that the flash memory chip can autonomously correct. That is, as... Figure 2 As shown, there are two scenarios for data migration within a storage page (i.e., Mode 1 and Mode 2 in the diagram). Mode 1 involves data migration at the storage page level when a storage page is identified as a risky page. Here, the source page refers to the risky page, and the free page refers to the target page. Mode 2 involves migrating and erasing the entire storage block when an uncorrectable error has occurred in the storage page (the bit flip count exceeds the flash memory chip's bit flip correction limit).

[0038] In one possible implementation, if it's not possible to modify the flash driver in the operating system kernel (by setting a counter), data migration at the storage page level can be achieved through the operating system's user space. Specifically, inotify can be used to monitor the access frequency of critical files (such as kernel images and configuration files). When the number of accesses to a file exceeds a preset access threshold, ioctl is called to trigger data migration of the storage page containing that file.

[0039] The data processing method provided in this application can obtain the read access count and bit flip count of each storage page in a flash memory chip. When the read access count exceeds the real-time refresh threshold and / or the growth rate of the bit flip count exceeds a preset rate, the storage page is identified as a risk page, data is migrated to the risk page, and the logical address of the data is updated based on the address of the target page. The method provided in this application achieves read interference monitoring at the storage page level by setting a counter corresponding to each storage page in the flash memory driver, accurately identifying risk pages significantly affected by read interference, and promptly migrating data to risk pages to eliminate read interference problems. This avoids the cumulative bit flips of storage pages triggering the erasure of the entire storage block, avoiding excessive resource consumption and flash memory wear. Furthermore, this application analyzes the degree of read interference using both read access count and bit flip count, and promptly migrates data to risk pages, effectively preventing data errors.

[0040] The embodiments described above introduce schemes for eliminating the impact of read interference on storage pages. In another embodiment of this application, the impact of write interference can also be eliminated. This embodiment includes, for example... Figure 3 The steps shown are as follows: Step 201: For each storage page in the flash memory chip, obtain the number of write accesses for that storage page.

[0041] In this embodiment, a write access counter can be set in the flash driver of the operating system kernel to record the number of write accesses to each memory page. This write access count can also be stored in a standard structure. The flash driver can monitor the number of write accesses to each memory page in real time using the write access counter.

[0042] Step 202: If the number of write accesses exceeds the write access threshold, perform bit flip detection on each adjacent page.

[0043] The write access threshold represents the critical number of write accesses required to detect write interference on each page of the flash memory chip. For example, it could be 50,000 times. Neighboring pages are other pages within the same memory block as the current page.

[0044] In this embodiment, when it is determined that the number of write accesses to a certain memory page in the memory block exceeds the write access threshold, considering that the high-voltage pulse applied during the write access will couple to other memory pages within the same memory block through parasitic capacitance, causing significant write interference to other memory pages, and frequent write accesses are more likely to lead to data errors in adjacent pages, it is necessary to detect bit flips in adjacent pages to determine whether adjacent pages are affected by write interference. Specifically, the bit flip information of each adjacent page can be obtained by reading the error status register (e.g., ECC status register) inside the flash memory chip.

[0045] Step 203: For each neighboring page, if a bit flip error exists in the neighboring page, the neighboring page is identified as a risk page, and the data in the risk page is migrated to other free storage pages within the same storage block.

[0046] In this embodiment of the application, if the bit flip information indicates that there is a bit flip in the adjacent page, then the adjacent page is determined to have a bit flip error and is a risk page. Data migration within the storage block is performed on the risk page, and the data in the risk page is migrated to other erased and unprogrammed free storage pages in the same storage block.

[0047] The method provided in this application can analyze the write interference of storage pages by pre-setting write access thresholds for each storage page and bit flip detection. When it is determined that a storage page is affected by write interference and bit flips occur, the data in the storage page is migrated in a timely manner to avoid the accumulation of bit flips due to write interference, which could ultimately lead to data errors.

[0048] In one embodiment, a process for determining a real-time refresh threshold is provided, which includes, as follows: Figure 4 The steps shown are as follows: Step 301: Determine the current refresh interval of the storage page based on the current time and the last data migration time of the storage page.

[0049] Step 302: Determine the first coefficient based on the current temperature of the flash memory chip, and determine the second coefficient based on the current refresh interval duration.

[0050] Step 303: Determine the real-time refresh threshold based on the baseline refresh threshold, the first coefficient, and the second coefficient.

[0051] The first coefficient is negatively correlated with the current temperature, and the second coefficient is negatively correlated with the current refresh interval duration. The baseline refresh threshold is related to the erase limit and bit flip error correction limit of the flash memory chip.

[0052] In this embodiment, a baseline refresh threshold for the flash memory chip can be obtained. This baseline refresh threshold can be pre-set based on the flash memory chip's specifications (erase limit and bit flip correction limit) and stored locally on the flash memory chip. The erase limit represents the maximum number of times the flash memory chip can erase a memory block, and the bit flip correction limit represents the critical number of bit flip data bits that the flash memory chip can autonomously correct. It is understood that the erase limit and the baseline refresh threshold are positively correlated.

[0053] Next, the current temperature of the flash memory chip can be obtained, and a first coefficient can be calculated based on the current temperature and a reference temperature. Specifically, for every preset temperature increase (e.g., 10°C) between the current temperature and the reference temperature, the first coefficient decreases by 10%. Then, based on the current time and the last data migration time of the storage page, the current refresh interval of the storage page can be calculated. For every preset increase in the current refresh interval (e.g., 30 seconds), a second coefficient decreases by 10%. The initial values ​​of both the first and second coefficients are 1; the reference temperature represents the suitable operating temperature of the flash memory chip. Finally, the reference refresh threshold, the first coefficient, and the second coefficient are multiplied to obtain the real-time refresh threshold.

[0054] In one possible implementation, the refresh limit is determined based on a baseline refresh threshold and a limit coefficient. If the real-time refresh threshold is lower than the refresh limit, the real-time refresh threshold is updated to the refresh limit. In this implementation, a lower limit for the real-time refresh threshold, i.e., the refresh limit, can be set, for example, to 90% of the baseline refresh threshold. After determining the real-time refresh threshold based on the first and second coefficients, it can be compared with a pre-set refresh limit. If the real-time refresh threshold is less than the refresh limit, the real-time refresh threshold is updated to the refresh limit, avoiding frequent invalid refreshes caused by excessively low real-time refresh thresholds due to high temperatures or prolonged periods without refresh.

[0055] The method provided in this application can adjust the baseline refresh threshold by taking into account the current temperature of the flash memory chip and the refresh interval, so as to ensure timely refresh of storage page data under high temperature risk environment and long-term non-refresh conditions, and avoid the accumulation of bit flip errors.

[0056] In one embodiment, the data migration of the risky page can also be performed when the operating system is in an idle state to avoid affecting the real-time services of the operating system. That is, before migrating the data to the risky page, this embodiment includes the following: Figure 5 The steps shown are as follows: Step 401: Generate the refresh task corresponding to the risk page and add the refresh task to the refresh queue.

[0057] In this embodiment, after identifying a risky page, the flash drive does not perform data migration for the risky page. Instead, it generates a refresh task corresponding to the risky page and adds it to a pre-created refresh queue, waiting for the operating system to execute it sequentially when it is under light load.

[0058] Step 402: When the operating system load meets the light load condition, execute the refresh task in the refresh queue.

[0059] The light load conditions include a CPU resource utilization rate of less than a first threshold and a number of tasks to be executed of less than a second threshold.

[0060] In this embodiment, the operating system can periodically (e.g., every 10 minutes) start threads to detect the current load status of the operating system. Specifically, it can obtain the resource utilization rate (CPU utilization rate) of the operating system's central processing unit and the number of tasks to be executed. Both can characterize the load of the operating system; a higher CPU utilization rate indicates a heavier operating system load, and a larger number of tasks to be executed also indicates a heavier operating system load.

[0061] Therefore, the light load conditions can be preset as follows: CPU utilization is less than a first threshold (e.g., 5%) and the number of pending tasks is less than a second threshold (e.g., 2). Then, it is determined whether the current CPU utilization and the number of pending tasks meet the light load conditions. If they do, it is determined that the operating system can currently execute the risk page refresh task without affecting the operating system's business operations. The number of pending tasks can be the number of tasks in the ready state (run queue length), or it can be the sum of the run queue length and the number of I / O waiting tasks.

[0062] In one possible implementation, the execution time of refresh tasks in the refresh queue can be recorded. If the execution time exceeds the execution time limit, the refresh tasks in the refresh queue are stopped. The refresh tasks in the refresh queue are then executed again only when the operating system is determined to be in a light-load state, thus preventing continuous execution of refresh tasks from affecting the operating system's business operations.

[0063] The method provided in this application embodiment can perform data migration operations on risky pages only when the operating system is determined to be in a light-load state, which can ensure that data migration does not interfere with the real-time business of the operating system.

[0064] It should be noted that although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0065] The following is for reference. Figure 6 It shows a schematic diagram of the structure of a computer system 500 suitable for implementing terminal devices or servers in the embodiments of this application.

[0066] like Figure 6As shown, the computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 502 or programs loaded from storage section 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the system 500. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0067] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 510 as needed so that computer programs read from it can be installed into storage section 508 as needed.

[0068] In particular, according to embodiments of this disclosure, the above references Figure 1 The described process can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program containing instructions for performing... Figure 1 The program code for the method. In such an embodiment, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable media 511.

[0069] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0070] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0071] The units or modules described in the embodiments of this application can be implemented in software or hardware. The described units or modules can also be located in a processor. The names of these units or modules do not, in some cases, constitute a limitation on the unit or module itself.

[0072] On the other hand, this application also provides a computer-readable storage medium, which may be included in the computer device described in the above embodiments, or may exist independently and not assembled into the computer device. The aforementioned computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the methods described in this application. For example, it may execute... Figure 1 The steps of the method shown.

[0073] This application provides a computer program product including instructions that, when executed, cause the method described in this application to be performed. For example, it can execute... Figure 1 The steps of the method shown.

[0074] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0075] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A data processing method, characterized in that, Applied to flash memory chips, the method includes: For each storage page in the flash memory chip, obtain the number of read accesses and the bit flip count of the storage page; If the number of read accesses exceeds the real-time refresh threshold, and / or the growth rate of the bit flip count exceeds a preset rate, then the storage page is determined to be a risk page; the real-time refresh threshold is related to the current temperature of the flash memory chip and the current refresh interval of the storage page; The data of the risk page is migrated to the target page, and the logical address of the data is updated based on the address of the target page; the target page is a free storage page within the storage block where the risk page is located.

2. The method according to claim 1, characterized in that, The method further includes: For each storage page in the flash memory chip, obtain the number of write accesses for that storage page; If the number of write accesses exceeds the write access threshold, bit flip detection is performed on each neighboring page; the neighboring pages are other storage pages within the storage block where the storage page is located. For each of the adjacent pages, if a bit flip error exists in the adjacent page, the adjacent page is determined to be a risk page, and the data in the risk page is migrated to other free storage pages within the same storage block.

3. The method according to claim 1, characterized in that, The process of determining the real-time refresh threshold includes: The current refresh interval of the storage page is determined based on the current time and the last data migration time of the storage page. A first coefficient is determined based on the current temperature of the flash memory chip, and a second coefficient is determined based on the current refresh interval duration; the first coefficient is negatively correlated with the current temperature, and the second coefficient is negatively correlated with the current refresh interval duration. The real-time refresh threshold is determined based on the baseline refresh threshold, the first coefficient, and the second coefficient; the baseline refresh threshold is related to the erase limit and bit flip error correction limit of the flash memory chip.

4. The method according to claim 3, characterized in that, The method further includes: The refresh limit is determined based on the aforementioned baseline refresh threshold and limit coefficient; If the real-time refresh threshold is lower than the refresh limit, then the real-time refresh threshold is updated to the refresh limit.

5. The method according to claim 1, characterized in that, Before migrating the data to the risk page, the method further includes: Generate a refresh task corresponding to the risk page and add the refresh task to the refresh queue; When the operating system load meets the light load condition, the refresh task in the refresh queue is executed; the light load condition includes the central processing unit resource utilization rate being less than a first threshold and the number of tasks to be executed being less than a second threshold.

6. The method according to claim 1, characterized in that, The data migration of the risk page includes After determining that the storage page is a risky page, the flash driver in the operating system kernel generates a data copy instruction and sends it to the flash memory chip, instructing the flash memory chip to read the data of the risky page into the cache and then write it into the target page.

7. The method according to claim 1, characterized in that, After migrating the data to the risk page, the method further includes: Clear the read access count and bit flip count of the storage page to zero.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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