Audio chip defect identification method, system, device and storage medium

Abstract

The application discloses a defect identification method, system and device of an audio chip and a storage medium. The defect identification method of the audio chip comprises enumerating all logical relationships of the audio chip through an exhaustive method. The logical relationships comprise logical relationships inside the audio chip and logical relationships between a high-speed signal interface group corresponding to the audio chip and a low-speed initialization signal interface group corresponding to the audio chip. Comprehensive detection of the logical relationships of the audio chip is achieved, and all defects of the audio chip in the enumeration process are identified, so that the root cause of the defects can be accurately located, and the defect troubleshooting efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of defect identification of audio chips, and in particular to defect identification methods, systems, devices and storage media for audio chips. Background Technology

[0002] Currently, the mainstream methods for testing the logic relationships of audio chips in the industry mostly employ simplified testing methods such as sampling testing and test vector set extraction. The core idea is to select a portion of typical logic relationships or input combinations for testing, and then infer the correctness of the overall logic of the chip. However, sampling testing cannot cover all the logic relationships of audio chips, especially for audio chips with high integration and complex logical connections. A large number of potential logic anomalies are missed, resulting in some hidden defects not being identified in time, making it difficult to accurately locate the root cause of defects. When a chip fault is detected, a lot of manpower and time are required to check it one by one, resulting in low efficiency. Summary of the Invention

[0003] This application aims to at least address the technical problems existing in the prior art. To this end, this application proposes a method, system, device, and storage medium for defect identification of audio chips, which can achieve comprehensive detection of the logical relationships of audio chips, accurately locate the root cause of defects, and improve the efficiency of defect investigation.

[0004] A first aspect of this application provides a method for identifying defects in an audio chip, comprising the following steps: The audio chip's logical relationships are enumerated using an exhaustive method. These logical relationships include those within the audio chip itself, as well as those between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. Identify all defects in the audio chip during the exhaustive search process.

[0005] The defect identification method for audio chips according to the embodiments of this application has at least the following beneficial effects: This application exhaustively enumerates all logical relationships of an audio chip, including the internal logical relationships of the audio chip as well as the logical relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. This enables comprehensive detection of the logical relationships of the audio chip and identifies all defects of the audio chip during the exhaustive process, thereby accurately locating the root cause of defects and improving the efficiency of defect investigation.

[0006] A second aspect of this application provides a defect identification system for an audio chip, the audio chip defect identification system comprising: The logical relationship enumeration module is used to enumerate all logical relationships of the audio chip through an exhaustive method. The logical relationships include the internal logical relationships of the audio chip and the logical relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. The defect identification module is used to identify all defects in the audio chip during the exhaustive search process.

[0007] This system exhaustively searches all logical relationships of the audio chip, including the internal logic of the audio chip and the logic between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. This enables comprehensive detection of the audio chip's logical relationships and identifies all defects in the audio chip during the exhaustive search process, thereby accurately locating the root cause of defects and improving defect detection efficiency.

[0008] A third aspect of this application provides an electronic device including at least one controller and a memory for communicatively connecting to the controller; the memory stores instructions executable by the at least one controller, the instructions being executed by the at least one controller to cause the at least one controller to perform a defect identification method for an audio chip as described in the first aspect of this application.

[0009] A fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a defect identification method for an audio chip as described in the first aspect of this application.

[0010] It should be noted that the beneficial effects of the third and fourth aspects of this application with respect to the prior art are the same as the beneficial effects of the above-mentioned method for identifying defects in an audio chip with respect to the prior art, and will not be described in detail here.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating an embodiment of the defect identification method for audio chips provided in this application; Figure 2 This is a schematic diagram of the AI ​​statistical logic relationship of an embodiment of the audio chip defect identification method provided in this application; Figure 3This is a schematic diagram of AI exhaustive input and output of an embodiment of the audio chip defect identification method provided in this application; Figure 4 This is a schematic diagram illustrating the identification of all defects in an embodiment of the audio chip defect identification method provided in this application; Figure 5 This is a schematic diagram illustrating defect avoidance in an embodiment of the defect identification method for audio chips provided in this application; Figure 6 This is a schematic diagram of the structure of an embodiment of the audio chip defect identification system provided in this application; Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0014] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0015] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0016] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0017] Currently, the mainstream methods for testing the logic relationships of audio chips in the industry mostly employ simplified testing methods such as sampling testing and test vector set extraction. The core idea is to select a portion of typical logic relationships or input combinations for testing, and then infer the correctness of the overall logic of the chip. However, sampling testing cannot cover all the logic relationships of audio chips, especially for audio chips with high integration and complex logical connections. A large number of potential logic anomalies are missed, resulting in some hidden defects not being identified in time, making it difficult to accurately locate the root cause of defects. When a chip fault is detected, a lot of manpower and time are required to check it one by one, resulting in low efficiency.

[0018] To address the aforementioned technical deficiencies, embodiments of this application provide a method, system, device, and storage medium for identifying defects in audio chips.

[0019] Please see Figure 1 This is a flowchart illustrating a defect identification method for an audio chip provided in an embodiment of this application. The method is applied to electronic devices, such as servers. Figure 1 As shown, the defect identification method for this audio chip includes: Step S101: Enumerate all logical relationships of the audio chip using an exhaustive method. The logical relationships include the internal logical relationships of the audio chip and the logical relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. Reference Figure 2 and Figure 3 The above-mentioned high-speed signal interface group ( Figure 2 The TDM in the middle may include a high-speed clock interface ( Figure 2 SCK clock in the middle), synchronization signal interface ( Figure 2 FSYNC synchronization), audio data input interface ( Figure 2 The SDIN audio data input and audio data output interfaces are located in the middle. Figure 2 SDOUT audio data output; the above low-speed initialization signal interface group ( Figure 2 The IIC in the system can include a serial clock interface ( Figure 2 The SCL serial clock and serial data interface (in the serial data interface) Figure 2 SDA serial data in the middle.

[0020] Step S102: Identify all defects in the audio chip during the exhaustive search process.

[0021] Specifically, in step S102, the above-mentioned identification of all defects of the audio chip during the exhaustive search process can be performed after exhaustive search, identifying all defects of the audio chip during the exhaustive search process.

[0022] This application exhaustively enumerates all logical relationships of an audio chip, including the internal logical relationships of the audio chip as well as the logical relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. This enables comprehensive detection of the logical relationships of the audio chip and identifies all defects of the audio chip during the exhaustive process, thereby accurately locating the root cause of defects and improving the efficiency of defect investigation.

[0023] In some embodiments, all logical relationships of the audio chip are exhaustively enumerated, including: The logical relationships between high-speed clock synchronization signals, audio data input, audio data output, serial clock, and serial data in the high-speed signal interface group and the low-speed initialization signal interface group are exhaustively enumerated using the enumeration method.

[0024] This application uses an exhaustive approach to clearly focus on the logical relationships of six key signal types: high-speed clock, synchronization signal, audio data input, audio data output, serial clock, and serial data. When a defect is detected, it can be directly correlated to the specific signal interaction scenario, eliminating the need for extensive manpower to check all interfaces and signals one by one. It can quickly identify the signal combination and logical relationship type corresponding to the defect, providing precise guidance for chip interface design optimization and signal timing adjustment, significantly shortening the R&D cycle and reducing the cost of defect detection and repair.

[0025] In some embodiments, the logical relationships of high-speed clocks, synchronization signals, audio data inputs, audio data outputs, serial clocks, and serial data of high-speed signal interface groups and low-speed initialization signal interface groups are exhaustively enumerated using a method including: The AI ​​accelerator of the main control chip is used to perform an exhaustive search to exhaustively search for the logical relationships of high-speed clock, synchronization signal, audio data input, audio data output, serial clock and serial data of the high-speed signal interface group and the low-speed initialization signal interface group.

[0026] Specifically, refer to Figure 2First, the audio chip needs to undergo TDM initialization and IIC initialization. In the chip design, the TDM main frequency and IIC settings have a logical relationship during initialization. Therefore, the AI ​​accelerator of the main control chip performs an exhaustive search to enumerate the logical relationships of high-speed clock, synchronization signal, audio data input, audio data output, serial clock, and serial data in the high-speed signal interface group and the low-speed initialization signal interface group. Among them, TDM is the high-speed signal interface group, which is divided into four types of signals: high-speed clock, synchronization signal, audio data input, and audio data output, mainly used for audio data transmission. IIC is the low-speed initialization signal interface group, which has two types of signals: serial clock and serial data, mainly used for chip initialization. In vehicle operation, the Android system is used to communicate between the SoC (main control chip) and the audio chip. The order of TDM and IIC in the Android system is random, resulting in random logical relationships between them. The AI ​​accelerator in the SoC is used to exhaustively search all logical relationships in the audio chip, as well as the relationships between all sub-modules in TDM and IIC, such as the relationship between the opening and closing of transistors.

[0027] Specifically, refer to Figure 3 By using the AI ​​accelerator inside the SoC to exhaustively enumerate the logical relationships of six types of signals: high-speed clock, synchronization signal, audio data input and output, serial clock and serial data, such as the logical relationship between the control transistor and the controlled transistor of the internal SCK high-speed clock, audio data input and serial data, and the influence between their mutual opening and closing, that is, the effect of opening a transistor on other transistors. By using the AI ​​accelerator to exhaustively enumerate the logical relationships of each transistor, all possibilities are taken into account, thereby accurately locating the root cause of defects and improving the efficiency of defect investigation.

[0028] In some embodiments, the method further includes: Identify the triggering cause of each defect in the audio chip during the exhaustive search process.

[0029] Specifically, refer to Figure 4 , Figure 4 After clock checking, a clock mismatch was found, and the SDA (serial data line) data channel was shut down, preventing data from being written to the audio chip and causing chip failure. Because in the Android system, SCK (serial clock line) and SDA are independent systems and have no connection with each other, the mismatch was an intermittent phenomenon. During the exhaustive process, all defects were identified, and the triggering cause was identified, i.e., under what circumstances the defect would be triggered. In this case, the IIC's SDA module has a clock frequency judgment. If the clock frequency is not within the range required by SDA, it will shut down SDA data, causing chip initialization failure.

[0030] This application identifies the triggering cause of each defect in the audio chip during the exhaustive search process, accurately pinpoints the nature of the defect, thereby reducing the generation of defects from the source, improving the rationality and reliability of chip design, and laying a solid foundation for subsequent chip iteration and upgrades.

[0031] In some embodiments, the method further includes: Based on all the triggering causes, determine the defect avoidance plan; Implement the defect avoidance plan and verify it.

[0032] This application determines a defect avoidance scheme based on all triggering causes, which can achieve defect source avoidance, significantly reduce the probability of recurrence of similar defects, and then execute the defect avoidance scheme and verify it to ensure that all logical relationships and signal interactions of the audio chip meet the design requirements, thereby guaranteeing the basic working performance of the chip.

[0033] In some embodiments, a defect avoidance scheme is determined based on all triggering causes, including: Determine the value of the software interlock flag based on all triggering reasons; Based on the software interlock flag value, a defect avoidance scheme is generated.

[0034] This application determines the software interlock flag value based on all triggering causes, transforming the abstract defect triggering logic into a quantifiable and identifiable software identifier. This enables precise mapping and standardized control of defect triggering scenarios. Furthermore, defect avoidance solutions are generated based on the software interlock flag value. By relying on the defect triggering causes and logical scenarios mapped by the flag value, the avoidance solutions can be generated with precision and standardization, significantly improving the efficiency and feasibility of avoidance solution development. At the same time, it ensures that the solution can specifically address various defects, fundamentally reducing the probability of defect recurrence.

[0035] In some embodiments, implementing a defect avoidance scheme and verifying it includes: When implementing the defect avoidance scheme, the AI ​​accelerator of the main control chip is used to exhaustively enumerate the logical relationships of high-speed clock synchronization signals, audio data input, audio data output, serial clock and serial data of high-speed signal interface group and low-speed initialization signal interface group.

[0036] Specifically, refer to Figure 5After exhaustively identifying all defects, software interlocks are set up. In the TDM process, the SCK clock initialization is completed, the synchronization signal is set up, the information in the audio initialization state is processed, the SCK clock parameters are updated, the main frequency is reset, the interlock flag is set after the main frequency is set, and then the normal communication state is entered. In normal communication, synchronization and data input / output are completed twice. In the IIC process, the software interlock flag is read first, and then the SCL serial clock and SDA serial data process is entered to perform IIC initialization.

[0037] This application, by employing the AI ​​accelerator of the main control chip and using a defect avoidance scheme, exhaustively searches for the logical relationships of high-speed clock synchronization signals, audio data input, audio data output, serial clock, and serial data in the high-speed signal interface group and the low-speed initialization signal interface group. This ensures that all logical relationships and signal interactions of the audio chip meet the design requirements, thereby guaranteeing the chip's basic operating performance.

[0038] Additionally, refer to Figure 6 One embodiment of this application provides a defect identification system for an audio chip, including a logic relationship exhaustive enumeration module 1100 and a defect identification module 1200, wherein: The logic relationship enumeration module 1100 is used to enumerate all logic relationships of the audio chip through an exhaustive method. The logic relationships include the internal logic relationships of the audio chip as well as the logic relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. The defect identification module 1200 is used to identify all defects in the audio chip during the exhaustive search process.

[0039] This system exhaustively searches all logical relationships of the audio chip, including the internal logic of the audio chip and the logic between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. This enables comprehensive detection of the audio chip's logical relationships and identifies all defects in the audio chip during the exhaustive search process, thereby accurately locating the root cause of defects and improving defect detection efficiency.

[0040] It should be noted that the system embodiments described above are based on the same inventive concept as the method embodiments described above. Therefore, the relevant content of the method embodiments described above is also applicable to the system embodiments described above, and will not be repeated here.

[0041] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with relevant regulations. The acquisition, storage, use and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0042] like Figure 7 One embodiment of this application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned method for identifying defects in an audio chip. The electronic device includes: At least one battery; At least one memory; At least one processor; At least one program; The program is stored in memory, and the processor executes at least one program to implement a defect identification method for an audio chip according to the above embodiments of this disclosure.

[0043] Electronic devices can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0044] The electronic devices according to embodiments of this application will now be described in detail.

[0045] The processor 1600 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure. The memory 1700 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 1700 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1700 and is called and executed by the processor 1600 to execute a defect identification method for an audio chip according to an embodiment of this disclosure.

[0046] The input / output interface 1800 is used to implement information input and output. The communication interface 1900 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 2000 transmits information between various components of the device (e.g., processor 1600, memory 1700, input / output interface 1800, and communication interface 1900); The processor 1600, memory 1700, input / output interface 1800 and communication interface 1900 are connected to each other within the device via bus 2000.

[0047] This disclosure also provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the detection method of the pressurized water reactor containment pressure control system described above.

[0048] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0049] The above is a detailed description of the preferred embodiments of this application. However, the embodiments of this application are not limited to the above-described implementation methods. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the embodiments of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of the embodiments of this application.

Claims

1. A method for defect identification in an audio chip, characterized in that, The defect identification method for the audio chip includes: The audio chip's logical relationships are enumerated using an exhaustive method. These logical relationships include those within the audio chip itself, as well as those between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. Identify all defects in the audio chip during the exhaustive search process.

2. The method for defect identification of an audio chip according to claim 1, characterized in that, The high-speed signal interface group includes a high-speed clock interface, a synchronization signal interface, an audio data input interface, and an audio data output interface. The low-speed initialization signal interface group includes a serial clock interface and a serial data interface. The method of exhaustively enumerating all logical relationships of the audio chip includes: The logical relationships between the high-speed clock synchronization signal, audio data input, audio data output, serial clock, and serial data of the high-speed signal interface group and the low-speed initialization signal interface group are exhaustively enumerated using the exhaustive method.

3. The method for defect identification of an audio chip according to claim 2, characterized in that, The method of exhaustively enumerating the logical relationships of high-speed clock, synchronization signal, audio data input, audio data output, serial clock, and serial data of the high-speed signal interface group and the low-speed initialization signal interface group includes: The AI ​​accelerator of the main control chip executes the exhaustive method to exhaustively enumerate the logical relationships of high-speed clock synchronization signals, audio data input, audio data output, serial clock, and serial data of the high-speed signal interface group and the low-speed initialization signal interface group.

4. The method for defect identification of an audio chip according to claim 1, characterized in that, The method further includes: Identify the triggering cause of each defect in the audio chip during the exhaustive search process.

5. The method for defect identification of an audio chip according to claim 4, characterized in that, The method further includes: Based on all the aforementioned triggering causes, a defect avoidance plan is determined; Implement the defect avoidance scheme and verify it.

6. The method for defect identification of an audio chip according to claim 5, characterized in that, The process of determining defect avoidance schemes based on all the aforementioned triggering causes includes: Based on all the aforementioned triggering reasons, determine the value of the software interlock flag; The defect avoidance scheme is generated based on the software interlock flag value.

7. The method for defect identification of an audio chip according to claim 6, characterized in that, The execution and verification of the defect avoidance scheme includes: When implementing the defect avoidance scheme, the AI ​​accelerator of the main control chip is used to exhaustively enumerate the logical relationships of the high-speed clock synchronization signal, audio data input, audio data output, serial clock and serial data of the high-speed signal interface group and the low-speed initialization signal interface group.

8. A defect identification system for an audio chip, characterized in that, The defect identification system for the audio chip includes: The logical relationship enumeration module is used to enumerate all logical relationships of the audio chip through an exhaustive method. The logical relationships include the internal logical relationships of the audio chip and the logical relationships between the high-speed signal interface group and the low-speed initialization signal interface group corresponding to the audio chip. The defect identification module is used to identify all defects in the audio chip during the exhaustive search process.

9. An electronic device, characterized in that, It includes at least one controller and a memory for communicatively connecting with the controller; the memory stores instructions executable by the at least one controller, which, when executed by the at least one controller, causes the at least one controller to perform a defect identification method for an audio chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions for causing a computer to perform a defect identification method for an audio chip as described in any one of claims 1 to 7.

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