G function acceleration method, apparatus, device and storage medium

Abstract

The application discloses a G function acceleration method and device, equipment and storage medium. The application is applied to a G function acceleration device, and comprises a three-input adder, an exclusive OR operation unit, a barrel shifter and a register. First-stage grouping and second-stage grouping are formed by grouping G function serial operation steps, the hardware processing logic of two groups of operations can be unified, and the same set of operation hardware can be conveniently reused. The three-input adder, the exclusive OR operation unit and the barrel shifter are used to complete first-stage grouping calculation and store intermediate states in the register, the logic path of the combination of the previous stage and the next stage can be interrupted, and the intermediate data in the cache operation is stable. The intermediate states in the register are read and the second message word is used to complete second-stage grouping calculation, the operation unit can be time-multiplexed to complete all G function operations, the number of hardware circuits is reduced, the overall operation delay is shortened, and the hardware resource utilization is improved.

Description

Technical Field

[0001] This invention relates to the field of hardware acceleration technology for cryptographic algorithms, and in particular to a method, apparatus, device, and storage medium for accelerating the G function. Background Technology

[0002] With the increasing demand for data encryption and integrity verification, the BLAKE3 hash algorithm has been widely used due to its high throughput and strong security. As the core computing unit of the BLAKE3 compression function, the G function's computing performance directly determines the processing efficiency of the entire hash algorithm. Therefore, hardware acceleration of the G function has become a key research and development direction for cryptographic acceleration modules in security chip field programmable gate arrays (FPGAs).

[0003] Existing BLAKE3 hardware implementations typically follow the original computational logic of the G function, executing eight computational operations sequentially. The hardware architecture requires the sequential construction of independent addition, XOR, and shift operation links, completing the entire computational process step by step.

[0004] Traditional serial implementations cannot reuse hardware resources for addition, XOR, and shift operations. The serial execution of the computation link leads to significant processing latency. A single G-function operation requires a large number of clock cycles, resulting in low hardware resource utilization and difficulty in meeting the real-time requirements of hash operations in high-speed data transmission scenarios. Summary of the Invention

[0005] This invention provides a method, apparatus, device, and storage medium for accelerating G-functions. By grouping the serial computation steps of the BLAKE3 hash algorithm G-function and employing a pipelined, time-division multiplexing computation unit for hardware paths, it solves the technical problems of long computation cycles, low hardware resource utilization, and large computation latency in traditional serial G-function execution schemes.

[0006] According to one aspect of the present invention, a G-function acceleration method is provided, applied to a G-function acceleration device, comprising a three-input adder, an XOR operation unit, a barrel shifter, and a register, the method comprising: Obtain the sequential operation steps of the G function, group the sequential operation steps, and generate the first-stage group and the second-stage group; The initial state and the first message word are obtained. The initial state and the first message word are then grouped and calculated in the first stage using a three-input adder, an XOR operation unit and a barrel shifter to obtain the intermediate state. The intermediate state is then stored in a register. The intermediate state is read from the register, the second message word is obtained, and the intermediate state and the second message word are sequentially grouped and calculated using a three-input adder, an XOR operation unit, and a barrel shifter to obtain the calculation result of the G function.

[0007] Optionally, both the first-stage group and the second-stage group include two step groups, each of which includes two serial operation steps, and each step group occupies one clock cycle.

[0008] Optionally, a three-input adder, an XOR operation unit, and a barrel shifter are sequentially used to perform a first-stage group calculation on the initial state and the first message word to obtain an intermediate state. This includes: using the three-input adder, in the first clock cycle, obtaining a first addition result based on the initial state and the first message word, and directly sending the first addition result to the XOR operation unit; sequentially using the XOR operation unit and the barrel shifter, performing XOR operation and shift calculation based on the first addition result to obtain a first shift result, and sending the first shift result back to the three-input adder; using the three-input adder, in the second clock cycle, obtaining a second addition result based on the first shift result, and directly sending the second addition result to the XOR operation unit; sequentially using the XOR operation unit and the barrel shifter, performing XOR operation and shift calculation based on the second addition result to obtain the intermediate state.

[0009] Optionally, a three-input adder, an XOR operation unit, and a barrel shifter are sequentially used to perform a second-stage grouping calculation on the intermediate state and the second message word to obtain the G function calculation result. This includes: using the three-input adder, in the third clock cycle, obtaining the third addition result based on the intermediate state and the second message word, and directly sending the third addition result to the XOR operation unit; sequentially using the XOR operation unit and the barrel shifter, performing XOR operation and shift calculation based on the third addition result to obtain the second shift result, and sending the second shift result back to the three-input adder; using the three-input adder, in the fourth clock cycle, obtaining the fourth addition result based on the second shift result, and directly sending the fourth addition result to the XOR operation unit; sequentially using the XOR operation unit and the barrel shifter, performing XOR operation and shift calculation based on the fourth addition result to obtain the G function calculation result.

[0010] Optionally, the barrel shifter is a configurable barrel shifter, which is equipped with two shift control signals to select the number of cyclic right shifts, including 7 bits, 8 bits, 12 bits, and 16 bits.

[0011] Optionally, the three-input adder is a carry-retaining three-input adder (CSA), which contains 32 parallel full adders, each of which synchronously outputs the sum and carry signals.

[0012] Optionally, the register is a pipeline register used to latch all intermediate states after the first stage of grouping calculation is completed.

[0013] According to another aspect of the present invention, a G-function acceleration device is provided, the device comprising: a three-input adder, an XOR operation unit, a barrel shifter, and a register; The three-input adder, XOR operation unit, and barrel shifter are cascaded in sequence via wires, and the output of the barrel shifter is connected to the register.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to execute a G-function acceleration method according to any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer storage medium is provided, the computer storage medium storing computer instructions for causing a processor to execute a G-function acceleration method as described in any embodiment of the present invention.

[0016] The technical solution of this invention, by grouping the serial operation steps of the G function into a first-stage group and a second-stage group, can unify the hardware processing logic of the two groups of operations, facilitating the reuse of the same set of computing hardware. By using a three-input adder, an XOR operation unit, and a barrel shifter to complete the calculation of the first-stage group and storing the intermediate state in a register, the combinational logic path between the preceding and following stages can be isolated, and the intermediate data of the operation can be stably cached. By reading the intermediate state in the register and cooperating with the second message word to complete the calculation of the second-stage group, the operation unit can be time-division multiplexed to complete all G function operations, reducing the number of hardware circuits, shortening the overall operation latency, and improving the utilization rate of hardware resources.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a flowchart of a G-function acceleration method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of another G-function acceleration method provided in Embodiment 2 of the present invention; Figure 3 This is a hardware concept diagram provided according to Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of a hardware pipeline for calculating a G function according to Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the structure of a G-function acceleration device according to Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device that implements a G-function acceleration method according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Example 1 Figure 1 The flowchart illustrates a G-function acceleration method provided in Embodiment 1 of the present invention. This embodiment is applicable to hash function encryption calculation scenarios. The method can be executed by a G-function acceleration device, including a three-input adder, an XOR operation unit, a barrel shifter, and a register. Figure 1 As shown, the method includes: S110. Obtain the serial operation steps of the G function, group the serial operation steps, and generate the first stage group and the second stage group.

[0023] The G function is the core computational unit in the BLAKE3 hash algorithm and a fundamental component of the compression function. The traditional implementation of the G function involves eight serial steps, including addition, XOR, and circular right shift operations, used to process 32-bit status and message words, ultimately outputting the updated status value. The G function acceleration method in this application groups and merges the traditionally serially executed steps, completing the computation in fewer clock cycles using dedicated hardware units, while also improving throughput through pipeline technology. The G function acceleration device includes a three-input adder, an XOR operation unit, a barrel shifter, and registers. The three-input adder uses a carry-save adder (CSA), which can sum three 32-bit operands in one clock cycle, replacing the traditional serial implementation requiring two additions. The XOR operation unit performs bitwise XOR operations, and the output is directly fed into the shifter, cascaded with the addition and shift operations. The barrel shifter is a configurable cyclic right shift hardware unit. It allows selection of 7 / 8 / 12 / 16 bit shifts via a 2-bit control signal, supporting shift requirements at different steps in the G function and reducing hardware area. Registers are used to store intermediate state data, supporting pipelined operation and enabling parallelization of computations at different stages.

[0024] Specifically, we can first extract the original eight-step operation process of the BLAKE3 standard G function, and then divide the eight steps into two major groups according to the characteristics of the operation structure. The first four steps form the first stage group, and the last four steps form the second stage group. Both groups can share the same set of addition, XOR, and shift hardware circuits.

[0025] Optionally, both the first-stage group and the second-stage group include two step groups, each of which includes two serial operation steps, and each step group occupies one clock cycle.

[0026] Specifically, the original G function's 8-step serial operation is divided into four groups. The first two groups belong to the first stage group, and the last two groups belong to the second stage group. Each group contains two consecutive original serial operation steps. In the first stage, the first group includes steps 1 and 2. The hardware integrates all the operation logic through a CSA three-input adder, an XOR unit, and a configurable barrel shifter, completing the summation, XOR, and 16-bit circular right shift operations within the same clock cycle. The second group in the first stage includes steps 3 and 4, which also rely on cascaded hardware to complete the addition, XOR, and 12-bit circular right shift operations in a single clock cycle. The first stage group occupies two clock cycles in total. After the two groups of steps are completed, an intermediate state is generated and stored in the pipeline register. The second-stage grouping includes the remaining two groups of steps. The first group of steps includes steps 5 and 6, which read the intermediate state of the register buffer and combine it with the second message word to complete the three-input addition, XOR and 8-bit circular right shift within one clock cycle. The second group of steps includes steps 7 and 8, which take another independent clock cycle to complete the addition, XOR and 7-bit circular right shift. The second-stage grouping as a whole also takes two clock cycles. The entire logic relies on fused cascaded circuits and configurable barrel shifters to compress each two-step serial operation into a single clock cycle instead of executing it in multiple cycles, thus reducing the total cycle of the complete G function operation.

[0027] S120. Obtain the initial state and the first message word, and sequentially use a three-input adder, an XOR operation unit and a barrel shifter to perform the first stage grouping calculation on the initial state and the first message word to obtain the intermediate state, and store the intermediate state into a register.

[0028] Here, the first message word and the second message word refer to the input message words processed by the G function, that is, the 32-bit message blocks obtained after the data to be hashed is divided into blocks. The intermediate state refers to the output result of the first stage of group calculation, which serves as the input state for the second stage of group calculation. It is temporarily stored in a register to support pipelined parallel processing.

[0029] Specifically, the initial state and the first message word of the G function input can be read, and the three-input adder, the XOR operation unit and the barrel shifter can be called in sequence to complete all the operations corresponding to the first stage group. After the operation is completed, a temporary intermediate state is generated and then the intermediate state is saved into the pipeline register.

[0030] Optionally, the barrel shifter is a configurable barrel shifter, which is equipped with two shift control signals to select the number of cyclic right shifts, including 7 bits, 8 bits, 12 bits, and 16 bits.

[0031] A barrel shifter is a hardware circuit capable of performing multi-bit data shifting operations in parallel, eliminating the need for bit-by-bit shifting and achieving the target shift number in one operation. A configurable barrel shifter refers to a shift module that supports switching between multiple shift specifications via external control signals and reuses the same hardware circuit to meet different shifting requirements. The shift control signal is a binary control level used to switch shift modes. Cyclic right shift refers to cyclically shifting binary data from the least significant bit to the most significant bit, with overflowing low-order bits padded to high-order bits.

[0032] Specifically, the configurable barrel shifter in this application is equipped with a 2-bit binary shift control signal sel[1:0], which has four encoding combinations corresponding to the four cyclic right shift bits required by the G function. When the shift control signal is 00, the hardware performs a 32-bit data cyclic right shift of 7 bits to match the eighth step of the G function. When the shift control signal is 01, it performs a cyclic right shift of 8 bits to match the sixth step of the G function. When the shift control signal is 10, it performs a cyclic right shift of 12 bits to match the fourth step of the G function. When the shift control signal is 11, it performs a cyclic right shift of 16 bits to match the second step of the G function. The shifter is built using a 4-to-1 multiplexer array, and the corresponding data line is rearranged according to the shift control signal. Compared with the traditional scheme of designing independent shift circuits for each of the four shift values, the hardware logic area is reduced. At the same time, it can be directly cascaded at the back end of the XOR operation unit, and the shift operation is completed in a single cycle in the fusion path, adapting to the shift calculation requirements within each group of steps.

[0033] Optionally, the three-input adder is a carry-holding three-input adder (CSA), which contains 32 parallel full adders, each of which synchronously outputs the local sum signal and the carry signal.

[0034] A three-input adder is a hardware module capable of simultaneously receiving three operands to perform addition. Unlike a typical two-input adder, a carry-retaining three-input adder does not require step-by-step accumulation of values. A full adder is a fundamental arithmetic unit in digital circuits that can simultaneously input three bits and output the sum bit and carry bit. The sum signal represents the result of adding the three inputs at a single bit position without considering the carry, while the carry signal represents the carry value that needs to be passed to higher bits after adding the single bits.

[0035] Specifically, the carry-preserving three-input adder in this application integrates 32 parallel full adders, each corresponding to a bit of the 32-bit data. Each full adder synchronously receives three input values ​​(a, b, mx, or my) for the corresponding bit and performs single-bit operations in parallel at the same time. Here, a and b represent the initial state, and mx and my represent the first and second message words, respectively. Each full adder outputs two signals simultaneously: one is the sum signal sum[i], calculated by bitwise XOR of the three input bits, and the other is the carry signal carry[i], obtained by AND-OR logic operation of the three input bits. After the 32 full adders operate in parallel, there is no carry delay due to step-by-step propagation. The output is a 32-bit sum vector and a 32-bit carry vector, which are then fed into the carry propagation adder to complete the final summation. This achieves a single-cycle three-number addition operation of a+b+mx or a+b+my, eliminating the multi-cycle delay caused by traditional two-input addition.

[0036] Optionally, the register is a pipeline register used to latch all intermediate states after the first stage of grouping calculation is completed.

[0037] Registers are sequential hardware units in digital circuits used to temporarily store computational data. Pipeline registers are dedicated registers inserted between different stages of a pipeline to isolate combinational logic between stages and temporarily store intermediate data during stage operations. The intermediate states refer to the updated 32-bit state values ​​(a_new, b_new, c_new, d_new) generated after the first stage of grouped operations. Specifically, a pipeline register can be set up between the first-stage grouping and the second-stage grouping operation paths. After the first-stage grouping completes the operation of the two sets of step groups, that is, after completing the fusion operation of steps 1+2 and 3+4 in two clock cycles, all intermediate states a_new, b_new, c_new, and d_new obtained from the current operation are latched and saved into the pipeline register. On the one hand, this isolates the combinational logic path between the first and second stages, eliminates the timing delay caused by long paths, and constructs a two-stage pipeline architecture. On the other hand, it provides stable input data for the second-stage grouping operation. When the second-stage grouping operation starts, it directly reads the latched intermediate states from the pipeline register and, together with the second message word my, completes the addition, XOR, and shift fusion operations of the subsequent two sets of step groups. Relying on the buffering effect of the pipeline register, the entire G-function operation can be executed in two orderly stages, and the hardware can process more data in parallel, improving the overall computing throughput performance.

[0038] S130. Read the intermediate state from the register, obtain the second message word, and sequentially use a three-input adder, an XOR operation unit, and a barrel shifter to perform the second-stage group calculation on the intermediate state and the second message word to obtain the calculation result of the G function.

[0039] Specifically, the intermediate state previously cached can be read from the register, and the second message word can be read at the same time. Then, the three-input adder, the XOR operation unit and the barrel shifter are used to perform the operation corresponding to the second stage group in sequence. After all calculations are completed, the complete G function operation result is output.

[0040] The technical solution of this invention, by grouping the serial operation steps of the G function into a first-stage group and a second-stage group, can unify the hardware processing logic of the two groups of operations, facilitating the reuse of the same set of computing hardware. By using a three-input adder, an XOR operation unit, and a barrel shifter to complete the calculation of the first-stage group and storing the intermediate state in a register, the combinational logic path between the preceding and following stages can be isolated, and the intermediate data of the operation can be stably cached. By reading the intermediate state in the register and cooperating with the second message word to complete the calculation of the second-stage group, the operation unit can be time-division multiplexed to complete all G function operations, reducing the number of hardware circuits, shortening the overall operation latency, and improving the utilization rate of hardware resources.

[0041] Example 2 Figure 2 This is a flowchart of a G-function acceleration method provided in Embodiment 2 of the present invention. This embodiment adds specific processes for the calculation of the first-stage grouping and the second-stage grouping based on Embodiment 1. The specific content of step S210 is largely the same as step S110 in Embodiment 1, therefore it will not be described again in this embodiment. Figure 2 As shown, the method includes: S210. Obtain the serial operation steps of the G function, group the serial operation steps, and generate the first stage group and the second stage group.

[0042] Optionally, both the first-stage group and the second-stage group include two step groups, each of which includes two serial operation steps, and each step group occupies one clock cycle.

[0043] S220: Through the three-input adder, the first addition result is obtained according to the initial state and the first message word in the first clock cycle, and the first addition result is directly sent to the XOR operation unit.

[0044] The three-input adder, specifically the CSA carry-retaining three-input adder, can simultaneously perform parallel summation of three 32-bit values. The XOR operation unit is a 32-bit parallel bitwise XOR hardware array. The barrel shifter is a configurable barrel shifter capable of cyclically shifting a specified number of bits to the right based on control signals. The initial state consists of four 32-bit status words (a, b, c, d) from the original input of the G function. The first message word is mx. The first clock cycle and the second clock cycle are the standard timing units for the hardware to complete a set of grouped operations. The first addition result is the sum of the initial states a and b and the first message word mx obtained through the CSA three-input adder.

[0045] Specifically, when performing the first stage of group calculation, the initial states a, b, c, d and the first message word mx are input first, and the operation process of the first clock cycle is entered. The carry-retaining three-input adder is called to calculate a+b+mx in parallel to obtain the first addition result. The hardware circuit directly cascades the first addition result and sends it to the XOR operation unit.

[0046] S230. The XOR operation unit and the barrel shifter are used in sequence to perform XOR operation and shift calculation based on the first addition result to obtain the first shift result, and the first shift result is sent to the three-input adder again.

[0047] The first shift result is the value of d_new obtained by XORing and shifting the first addition result.

[0048] Specifically, the XOR operation unit reads the original d value and performs a bitwise XOR operation with the first addition result. The output data is sent to a configurable barrel shifter. The shift control signal selects a 16-bit cyclic right shift to complete the shift calculation and obtain the first shift result, which is the updated d_new. This first shift result will be used as input to the three-input adder of the next set of operations.

[0049] S240: Through the three-input adder, in the second clock cycle, the second addition result is obtained based on the first shift result, and the second addition result is directly sent to the XOR operation unit.

[0050] The second addition result is the numerical value obtained by adding c to the first shift result d_new.

[0051] Specifically, the second clock cycle then begins, and the three-input adder reads the original c and the first shift result d_new to perform the addition operation and obtain the second addition result, which is then directly sent to the XOR operation unit.

[0052] S250: Using an XOR operation unit and a barrel shifter in sequence, XOR operation and shift calculation are performed based on the second addition result to obtain an intermediate state.

[0053] The intermediate states are the temporary state data a_new, b_new, c_new, and d_new generated after all the calculations in the first phase grouping are completed.

[0054] Specifically, the XOR unit reads the original b value and performs an XOR operation with the result of the second addition. The output data is sent to a configurable barrel shifter. The shift control signal selects a 12-bit cyclic right shift to complete the shift calculation. After two sets of fusion operations over two clock cycles, the complete intermediate states a_new, b_new, c_new, and d_new are finally generated.

[0055] S260: Through the three-input adder, in the third clock cycle, the third addition result is obtained based on the intermediate state and the second message word, and the third addition result is directly sent to the XOR operation unit.

[0056] The third and fourth clock cycles correspond to the hardware timing cycles of the two sets of steps within the second phase grouping, respectively. The third addition result is the sum of the intermediate states a_new and b_new and the second message word my obtained through CSA operation.

[0057] Specifically, when performing the second-stage group calculation, the intermediate state is first read from the pipeline register, and the second message word my is input to enter the third clock cycle operation process. First, the carry-retaining three-input adder is called to calculate a_new+b_new+my in parallel to obtain the third addition result. The hardware cascade path directly sends the third addition result to the XOR operation unit.

[0058] S270. The XOR operation unit and the barrel shifter are used in sequence to perform XOR operation and shift calculation based on the third addition result to obtain the second shift result, and the second shift result is sent to the three-input adder again.

[0059] The second shift result is d_final, which is obtained by XORing and shifting the third addition result.

[0060] Specifically, the XOR operation unit reads d_new and performs a bitwise XOR operation with the third addition result. The output data is sent to a configurable barrel shifter. The shift control signal selects an 8-bit cyclic right shift to complete the shift calculation and obtain the second shift result d_final. This second shift result is then passed as input to the three-input adder for the next set of operations.

[0061] S280: Through the three-input adder, in the fourth clock cycle, the fourth addition result is obtained based on the second shift result, and the fourth addition result is directly sent to the XOR operation unit.

[0062] The fourth addition result is the value obtained by adding c_new and the second shift result d_final.

[0063] Specifically, the fourth clock cycle then begins, and the three-input adder reads c_new and the second shift result d_final to perform the addition operation and obtain the fourth addition result, which is then directly sent to the XOR operation unit.

[0064] S290. Using an XOR operation unit and a barrel shifter in sequence, XOR operation and shift calculation are performed based on the result of the fourth addition to obtain the calculation result of the G function.

[0065] The result of the G function is the complete final state a_final, b_final, c_final, and d_final output after four sets of fusion operations.

[0066] Specifically, the XOR unit reads b_new and performs an XOR operation with the result of the fourth addition. The output data is sent to a configurable barrel shifter. The shift control signal selects a 7-bit cyclic right shift to complete the shift calculation. After two sets of fusion operations in the third and fourth clock cycles, the complete data a_final, b_final, c_final, and d_final are output, which are the calculation results of the G function.

[0067] In one specific implementation method Figure 3 This is a hardware concept diagram provided for Embodiment 2 of the present invention. Figure 3 In this architecture, the CSA three-input adder is a carry-retaining adder used to achieve parallel summation of three inputs. XOR+ROT refers to the Exclusive OR (XOR) unit and the configurable barrel shifter (ROT), representing the fusion operation path of XOR operation combined with the configurable barrel shifter. The fusion cycle represents the hardware clock cycle corresponding to a single group of steps. Pipeline register R1 is a timing storage unit used to latch the intermediate state of the operation. mx is the first message word, and my is the second message word. The overall architecture is divided into two main operation stages. The upper stage is the first-stage grouping operation using message word mx, which occupies two fusion cycles. The CSA three-input adder completes the operation within the first fusion cycle. The carry-preserving addition operation yields a_new, and the result is sent to the XOR+ROT module for execution. The 16-bit right shift operation yields d_new, which is then executed by the CSA three-input adder in the second fusion cycle. The summation operation is performed, and the output is fed into the XOR+ROT module for completion. The 12-bit right shift operation generates an intermediate state after the first stage of operations is completed. The data is then latched into pipeline register R1, which isolates the combinational logic of the preceding and following stages and ensures stable transmission of the computational data. Below is the second-stage grouping operation using the message word 'my', which also takes two fusion cycles. The intermediate state is read from the buffered state in pipeline register R1 as input. The first fusion cycle is completed using a CSA three-input adder. The calculation and output are sent to the XOR+ROT module for execution. The 8-bit right shift operation yields d_new, and the second fusion cycle is implemented using a CSA three-input adder. Summation is then performed using the XOR+ROT module. The circuit performs a 7-bit right shift operation and finally outputs the complete G function result. The entire circuit reuses the same CSA three-input adder and XOR+ROT operation hardware, splitting the original 8-step serial operation into four fused cycles executed in two pipelines. By relying on the cascaded fused logic of addition, XOR, and shift, the critical path is shortened, and hardware acceleration of the G function is achieved.

[0068] Figure 4 This is a schematic diagram of a hardware pipeline for calculating the G function provided in Embodiment 2 of the present invention. Figure 4 In this code, Phase-A is the first-stage group operation, using the message word mx, and Phase-B is the second-stage group operation, using the message word my. ADD32 represents a 32-bit addition operation, implemented in this embodiment using a CSA carry-retaining three-input adder. XOR represents a bitwise XOR operation, and ROR stands for Rotate Right (ROR). ROR16, ROR12, ROR8, and ROR7 correspond to 16-bit, 12-bit, 8-bit, and 7-bit cyclic right shifts, respectively. XOR+ROR corresponds to the fused operation path formed by the XOR unit and the configurable barrel shifter. state[a], state[b], state[c], and state[d] are the state variables of the G function. The pipeline register is the timing storage hardware used to latch intermediate states between the two-stage operations. During the process execution, the first stage is Phase-A, where the initial states state[a], state[b], state[d], and state[c] and the message word mx are input. The ADD32 operation is then executed first. The calculation result is sent to the XOR+ROR16 module for execution. Then continue executing the ADD32 operation to complete. The output is sent to the XOR+ROR12 module for execution. After all operations in Phase-A are completed, the updated intermediate state is obtained and written to the pipeline register for latching, thereby isolating the combinational logic paths of the preceding and following stages. Then, Phase-B begins, where the intermediate state is read from the pipeline register, the message word "my" is introduced, and the ADD32 operation is executed sequentially to complete the process. Then, it is implemented through the XOR+ROR8 module. Then the ADD32 operation is completed. Finally, it is executed via the XOR+ROR7 module. After the operation is completed, the updated state[a], state[b], state[c], and state[d] are output, which are the final calculation results of a single G function. This process divides the eight serial instructions of the standard G function into two stages, inserts a pipeline register in the middle, reuses the same set of addition, XOR, and shift hardware paths, and merges the multi-step serial operation into four clock cycles to reduce the hardware operation latency of the G function and accelerate the operation.

[0069] The technical solution of this invention, by grouping the serial operation steps of the G function into a first-stage group and a second-stage group, can unify the hardware processing logic of the two groups of operations, facilitating the reuse of the same set of computing hardware. By using a three-input adder, an XOR operation unit, and a barrel shifter to complete the calculation of the first-stage group and storing the intermediate state in a register, the combinational logic path between the preceding and following stages can be isolated, and the intermediate data of the operation can be stably cached. By reading the intermediate state in the register and cooperating with the second message word to complete the calculation of the second-stage group, the operation unit can be time-division multiplexed to complete all G function operations, reducing the number of hardware circuits, shortening the overall operation latency, and improving the utilization rate of hardware resources.

[0070] Example 3 Figure 5 This is a schematic diagram of a G-function acceleration device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device includes: a three-input adder 310, an XOR operation unit 320, a barrel shifter 330, and a register 340; The three-input adder, XOR operation unit, and barrel shifter are cascaded in sequence via wires, and the output of the barrel shifter is connected to the register.

[0071] Optionally, the barrel shifter is a configurable barrel shifter, which is equipped with two shift control signals to select the number of cyclic right shifts, including 7 bits, 8 bits, 12 bits, and 16 bits.

[0072] Optionally, the three-input adder is a carry-retaining three-input adder (CSA), which contains 32 parallel full adders, each of which synchronously outputs the sum and carry signals.

[0073] Optionally, the register is a pipeline register used to latch all intermediate states after the first stage of grouping calculation is completed.

[0074] The technical solution of this invention, by grouping the serial operation steps of the G function into a first-stage group and a second-stage group, can unify the hardware processing logic of the two groups of operations, facilitating the reuse of the same set of computing hardware. By using a three-input adder, an XOR operation unit, and a barrel shifter to complete the calculation of the first-stage group and storing the intermediate state in a register, the combinational logic path between the preceding and following stages can be isolated, and the intermediate data of the operation can be stably cached. By reading the intermediate state in the register and cooperating with the second message word to complete the calculation of the second-stage group, the operation unit can be time-division multiplexed to complete all G function operations, reducing the number of hardware circuits, shortening the overall operation latency, and improving the utilization rate of hardware resources.

[0075] The G-function acceleration device provided in this embodiment of the invention can execute a G-function acceleration method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0076] Example 4 Figure 6 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0077] like Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0078] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0079] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a G-function acceleration method.

[0080] In some embodiments, a G-function acceleration method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the G-function acceleration method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute a G-function acceleration method by any other suitable means (e.g., by means of firmware).

[0081] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0082] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0083] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0084] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0085] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0086] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0087] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0088] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A G-function acceleration method, characterized by, Applied to a G-function acceleration device, including a three-input adder, an XOR operation unit, a barrel shifter, and registers, the method includes: Obtain the serial operation steps of the G function, group the serial operation steps, and generate a first-stage group and a second-stage group; The initial state and the first message word are obtained. The initial state and the first message word are then grouped and calculated in the first stage using a three-input adder, an XOR operation unit and a barrel shifter to obtain an intermediate state. The intermediate state is then stored in a register. The intermediate state is read from the register to obtain the second message word. Then, the intermediate state and the second message word are sequentially grouped and calculated using a three-input adder, an XOR operation unit, and a barrel shifter to obtain the G function calculation result.

2. The method of claim 1, wherein, Both the first-stage grouping and the second-stage grouping include two-step groups, each of which includes two serial operation steps, and each step group occupies one clock cycle.

3. The method according to claim 2, characterized in that, The process involves sequentially using a three-input adder, an XOR operation unit, and a barrel shifter to perform a first-stage grouping calculation on the initial state and the first message word to obtain an intermediate state, including: In the first clock cycle, the first addition result is obtained by the three-input adder based on the initial state and the first message word, and the first addition result is directly sent to the XOR operation unit. The XOR operation unit and the barrel shifter are used sequentially to perform XOR operation and shift calculation based on the first addition result to obtain the first shift result, and the first shift result is sent back to the three-input adder; In the second clock cycle, the second addition result is obtained based on the first shift result using a three-input adder, and the second addition result is directly sent to the XOR operation unit. The XOR operation unit and the barrel shifter are used sequentially to perform XOR operation and shift calculation based on the second addition result to obtain the intermediate state.

4. The method according to claim 3, characterized in that, The intermediate state and the second message word are sequentially grouped and calculated using a three-input adder, an XOR operation unit, and a barrel shifter to obtain the G-function calculation result, including: The three-input adder obtains the third addition result in the third clock cycle based on the intermediate state and the second message word, and the third addition result is directly sent to the XOR operation unit. The XOR operation unit and the barrel shifter are used sequentially to perform XOR operation and shift calculation based on the third addition result to obtain the second shift result, and the second shift result is sent back to the three-input adder; In the fourth clock cycle, the fourth addition result is obtained based on the second shift result using a three-input adder, and the fourth addition result is directly sent to the XOR operation unit. The XOR operation unit and the barrel shifter are used sequentially to perform XOR operation and shift calculation based on the fourth addition result to obtain the calculation result of the G function.

5. The method according to any one of claims 1-4, characterized in that, The barrel shifter is a configurable barrel shifter, which is equipped with two shift control signals. The shift control signals are used to select the number of cyclic right shifts, which can be 7, 8, 12, or 16 bits.

6. The method according to any one of claims 1-4, characterized in that, The three-input adder is a carry-holding three-input adder (CSA), which includes 32 parallel full adders, each of which synchronously outputs the sum signal and the carry signal.

7. The method according to any one of claims 1-4, characterized in that, The register is a pipelined register used to latch all intermediate states after the first stage of grouping calculation is completed.

8. A G-function acceleration device for performing the method according to any one of claims 1-7, characterized in that, include: Three-input adder, XOR unit, barrel shifter and register; The three-input adder, XOR operation unit, and barrel shifter are cascaded in sequence via wires, and the output of the barrel shifter is connected to the register.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-7.

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