A divider and electronic device

Abstract

The application relates to a divider and an electronic device, and belongs to the technical field of electronics. The divider comprises a preprocessing circuit, a division iteration circuit and a postprocessing circuit. The preprocessing circuit is used for obtaining an initial partial remainder according to a dividend, a number of leading zeros of the dividend and a sign of a final quotient; wherein the initial partial remainder is jointly represented by a carry vector and a sum vector, and an actual value of the initial partial remainder is equal to the carry vector minus the sum vector; the division iteration circuit is used for performing iterative operation on the initial partial remainder and a preprocessed dividend, and outputting a first partial remainder at the end of iteration; wherein the first partial remainder is jointly represented by the carry vector and the sum vector, and an actual value of the first partial remainder is equal to the carry vector minus the sum vector; and the postprocessing circuit is used for generating an initial remainder according to the sign of the final quotient, the first partial remainder and the preprocessed dividend. Compared with an existing divider, the circuit structure of the application is simpler, and the timing performance of an operation path is better.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a divider and an electronic device. Background Technology

[0002] The difference between division and addition or multiplication is that it is difficult to obtain a result with sufficient precision in a single operation within one or two clock cycles. To balance computational efficiency and hardware overhead, dividers are generally designed based on the SRT (proposed by Sweeney, Robertson, and Tocher) algorithm. This type of divider is based on shift subtraction and obtains the correct quotient through multiple iterations.

[0003] In the iterative process of the SRT algorithm, some remainders are typically represented using a carry-saving form. This involves using a carry vector (carry) and a sum vector (sum) to represent the partial remainders, with the actual value equal to the sum of carry and sum. The advantage of this approach is that it allows for iterative calculations using a carry-save adder (CSA), avoiding the need for a carry-propagate adder (CPA) with significant latency. The redundant form is only converted to standard binary numbers after the final iteration to obtain the final remainder.

[0004] However, existing SRT dividers based on the "carry + sum" carry-preserving structure suffer from timing and area bottlenecks caused by redundant representations in both the initial value preparation stage of the first iteration and the remainder calculation stage after the iteration. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a divider and electronic device to simplify the circuit structure of existing dividers, reduce hardware area overhead, and optimize the timing performance of the operation path.

[0006] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a divider, comprising: a preprocessing circuit, a division iteration circuit, and a postprocessing circuit. The output terminal of the preprocessing circuit is coupled to the input terminal of the division iteration circuit; the output terminal of the division iteration circuit is coupled to the input terminal of the postprocessing circuit. The preprocessing circuit is used to obtain an initial partial remainder based on the dividend, the number of leading zeros in the dividend, and the sign of the final quotient. The initial partial remainder is represented by a carry vector and a sum vector, and the true value of the initial partial remainder is equal to the carry vector minus the sum vector. The division iteration circuit is used to perform iterative operations on the initial partial remainder and the preprocessed divisor, and output a first partial remainder at the end of the iteration. The first partial remainder is represented by a carry vector and a sum vector, and the true value of the first partial remainder is equal to the carry vector minus the sum vector. The postprocessing circuit is used to generate an initial remainder based on the sign of the final quotient, the first partial remainder, and the preprocessed divisor.

[0007] In the above implementation scheme, a redundant "carry-sum" representation is used to store and transmit part of the remainder, replacing the "carry + sum" representation in the traditional scheme. To adapt to the "carry-sum" representation, this application completes the division operation through three collaborative stages: preprocessing, division iteration, and postprocessing. This effectively reduces the circuit area and significantly improves the timing performance of the relevant critical paths in both the initial value preparation stage of the first iteration and the remainder calculation stage after the iteration.

[0008] Specifically, in the preprocessing stage, the left-shifted result |x| (obtained by left-shifting the absolute value of the dividend based on the number of leading zeros in the dividend) is directly assigned to the carry vector carry or the sum vector sum based on the sign of the final quotient. This eliminates the need for the "invert and add 1" operation on the carry vector when the quotient is negative, as is done in traditional schemes, thus shortening the critical path before the first iteration. Specifically, based on the "carry + sum" representation, when the quotient is positive, carry = |x|, sum = 0; when the quotient is negative, carry = ~|x| + 1, sum = 0. Conversely, based on the "carry - sum" representation, when the quotient is positive, carry = |x|, sum = 0; when the quotient is negative, carry = 0, sum = |x|. This simplifies the initial carry and sum values ​​to a single case, eliminating the need for the "invert and add 1" operation, effectively simplifying the preceding logic and shortening the critical path delay.

[0009] During the division iteration phase, the partial remainder is passed using the "carry-sum" representation in each iteration. In the post-processing phase, after adopting the "carry-sum" representation, since the opposite of carry-sum is sum-carry, when it is necessary to take the opposite of a partial remainder, it is only necessary to swap the order of carry and sum, without performing a full-width increment operation.

[0010] In one possible implementation of the first aspect embodiment, the preprocessing circuit is specifically configured to: left-shift the absolute value of the dividend according to the number of leading zeros in the dividend to obtain a left-shift result |x|, and determine the initial partial remainder according to the left-shift result and the sign of the final quotient; wherein, when the sign of the final quotient is positive, the carry vector of the initial partial remainder is the left-shift result and the sum vector is zero; when the sign of the final quotient is negative, the carry vector of the initial partial remainder is zero and the sum vector is the left-shift result.

[0011] In the above implementation scheme, the "carry - sum" representation is adopted, so that when the quotient is positive, carry = |x| and sum = 0; when the quotient is negative, carry = 0 and sum = |x|. In this way, the initial carry value and the initial sum value are simplified to a single case, without the need to perform the "invert and add 1" operation, thereby effectively simplifying the front-end logic and shortening the critical path delay.

[0012] In one possible implementation of the first aspect embodiment, when determining the initial partial remainder, the preprocessing circuit is specifically used to: perform a logical AND operation on the sign of the left shift result and the final quotient to obtain the carry vector of the initial partial remainder; and perform a logical AND operation on the inverted value of the sign of the left shift result and the final quotient to obtain the sum vector of the initial partial remainder.

[0013] In the above implementation scheme, by performing a logical AND operation on the left shift result and the sign and inverse of the final quotient, the carry vector and sum vector under different quotient values ​​can be obtained quickly.

[0014] In one possible implementation of the first aspect embodiment, the division iteration circuit is specifically configured to: generate three candidate sum vectors based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, and select and output the sum vector for the next iteration from the three candidate sum vectors based on the quotient of the current iteration step; generate three candidate carry vectors based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, and select and output the carry vector for the next iteration from the three candidate carry vectors based on the quotient of the current iteration step; wherein the carry vector and sum vector at the first iteration are obtained based on the initial partial remainder.

[0015] In the above implementation scheme, based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, three candidate sum vectors and three candidate carry vectors are generated simultaneously. Then, based on the quotient of the current iteration step, the sum vector for the next iteration is selected from the three candidate sum vectors, and the carry vector for the next iteration is selected from the three candidate carry vectors. This ensures that within each iteration cycle, regardless of the quotient, the candidate vectors have been calculated in parallel within the same iteration. Subsequent iterations only require the candidate vector corresponding to the quotient of the current iteration step, thus balancing the efficiency of iterative computation with the timing optimization of the critical path.

[0016] In one possible implementation of the first aspect embodiment, when generating the corresponding three candidate sum vectors, the division iteration circuit is specifically used to: XOR the carry vector, sum vector, and the inverted value of the preprocessed divisor of the current iteration step to obtain a first candidate sum vector representing the quotient value of 1 in the current iteration step; XOR the carry vector, sum vector, and the preprocessed divisor of the current iteration step to obtain a second candidate sum vector representing the quotient value of -1 in the current iteration step; and XOR the carry vector and sum vector of the current iteration step to obtain a third candidate sum vector representing the quotient value of 0 in the current iteration step.

[0017] In the above implementation scheme, under the "carry-sum" representation, the candidate sum vectors under different quotient values ​​(1, -1, 0) can be obtained quickly and accurately through the above XOR operation.

[0018] In one possible implementation of the first aspect embodiment, when generating the corresponding three candidate carry vectors, the division iteration circuit is specifically used to: generate a first candidate carry vector representing a quotient of 1 in the current iteration step based on the carry vector of the current iteration step, the inverted value of the sum vector, and the inverted value of the preprocessed divisor; generate a second candidate carry vector representing a quotient of -1 in the current iteration step based on the carry vector of the current iteration step, the inverted value of the sum vector, and the preprocessed divisor; and generate a third candidate carry vector representing a quotient of 0 in the current iteration step based on the carry vector of the current iteration step and the inverted value of the sum vector.

[0019] In the above implementation scheme, under the "carry-sum" representation, the candidate carry vectors for different quotient values ​​(1, -1, 0) can be obtained quickly and accurately based on the above input.

[0020] In one possible implementation of the first aspect embodiment, the post-processing circuit is specifically configured to: generate a first remainder based on the sign of the final quotient and the first part of the remainder, generate a second remainder based on the sign of the final quotient, the first part of the remainder and the preprocessed divisor, and select to output the first remainder or the second remainder based on the highest bit of the first remainder to obtain the initial remainder.

[0021] In the above implementation scheme, the first and second remainders are calculated in parallel. Then, the first or second remainder is selected as the initial remainder based on the highest bit of the first remainder. This ensures that regardless of the highest bit of the first remainder, both candidate remainders are calculated in parallel within the same timeframe. This avoids the extra delay caused by calculating the first remainder first and then adjusting it based on its highest bit to obtain the second remainder. This effectively shortens the critical path in the post-processing stage and improves the timing performance and throughput efficiency of the overall divider pipeline.

[0022] In one possible implementation of the first aspect embodiment, when generating the first remainder, the post-processing circuit is specifically used to: generate the first remainder based on the inverted value of the first data, the second data, and a fixed value; wherein, when the sign of the final quotient is positive, the first data is the carry vector of the first part of the remainder, and the second data is the sum vector of the first part of the remainder; when the sign of the final quotient is negative, the first data is the sum vector of the first part of the remainder, and the second data is the carry vector of the first part of the remainder.

[0023] In the above implementation scheme, when the final quotient is positive, a first remainder is generated based on the first partial remainder (the value of the first remainder is equal to carry - sum, which is equivalent to carry + (~sum) + 1), where the first partial remainder is equal to the carry vector minus the sum vector; when the final quotient is negative, a first remainder is generated based on the opposite of the first partial remainder (the value of the first remainder is equivalent to sum - carry, which is equivalent to sum + (~carry) + 1), where the opposite of the first partial remainder is equal to the sum vector minus the carry vector. Thus, when it is necessary to take the opposite of a partial remainder, only the order of carry and sum needs to be swapped, without needing to perform a full-width increment operation.

[0024] In one possible implementation of the first aspect embodiment, the post-processing circuit is specifically configured to: extend the first data by 1 bit and pad the most significant bit of the extension with 0 to obtain the extended first data; extend the inverted value of the second data by 1 bit and pad the most significant bit of the extension with 0 to obtain the inverted value of the extended second data; add the extended first data, the inverted value of the extended second data, and the fixed value to obtain the first remainder.

[0025] In the above implementation scheme, by extending by one bit and padding with 0 in the high bit, a first remainder with a sign bit is obtained, and the initial remainder is subsequently selected based on the sign bit (the highest bit of the first remainder).

[0026] In one possible implementation of the first aspect embodiment, when generating the second remainder, the post-processing circuit is specifically used to: generate the second remainder based on the first data, the inverted value of the second data, a fixed value, and the preprocessed divisor; wherein, when the sign of the final quotient is positive, the first data is the carry vector of the first part of the remainder, and the second data is the sum vector of the first part of the remainder; when the sign of the final quotient is negative, the first data is the sum vector of the first part of the remainder, and the second data is the carry vector of the first part of the remainder.

[0027] In the above implementation scheme, when the final quotient is positive, a second remainder is generated based on the first remainder and the preprocessed divisor, where the first remainder is equal to the carry vector minus the sum vector; when the final quotient is negative, a second remainder is generated based on the opposite of the first remainder and the preprocessed divisor, where the opposite of the first remainder is equal to the sum vector minus the carry vector. Thus, when it is necessary to take the opposite of a partial remainder, only the order of carry and sum needs to be swapped, without needing to perform a full-width increment operation.

[0028] In one possible implementation of the first aspect embodiment, the post-processing circuit is specifically configured to: compress the inverted values ​​of the first data and the second data, and the preprocessed divisor, into a new carry vector and a new sum vector; extend the new carry vector by 1 bit and pad the least significant bit of the extension with the fixed value to obtain an extended carry vector; extend the new sum vector by 1 bit and pad the most significant bit of the extension with 1 to obtain an extended sum vector; and add the extended carry vector and the extended sum vector together to obtain the second remainder.

[0029] In the above implementation scheme, the above processing makes the second remainder equal to the sum of the first remainder and the preprocessed divisor, so that when the first remainder is negative, the second remainder is selected as the initial remainder to ensure the accuracy of the final remainder.

[0030] In one possible implementation of the first aspect embodiment, the post-processing circuit is specifically configured to: generate a first remainder based on the sign of the final quotient and a first portion of the remainder; output the first remainder as an initial remainder when the highest bit of the first remainder is a first preset value; output a second remainder as an initial remainder when the highest bit of the first remainder is a second preset value; wherein the second remainder is equal to the sum of the first remainder and the preprocessed divisor.

[0031] In the above implementation scheme, the first remainder can be generated first, and then the highest bit of the first remainder can be used to select whether the first remainder needs to be adjusted to obtain the adjusted first remainder (i.e., the second remainder), which can further simplify the circuit structure.

[0032] Secondly, embodiments of this application also provide an electronic device, including: a divider provided as described in the first aspect embodiments and / or in any possible implementation of the first aspect embodiments.

[0033] The technical effects of any implementation method in the second aspect can be seen in the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0034] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0036] Figure 1 A schematic diagram of a divider provided in an embodiment of this application is shown.

[0037] Figure 2 A schematic diagram of a preprocessing circuit provided in an embodiment of this application is shown.

[0038] Figure 3 The diagram illustrates the principle of a sum-vector circuit with different quotient values ​​according to an embodiment of this application.

[0039] Figure 4a The diagram shows a schematic of a carry vector circuit with a quotient of 1 provided in an embodiment of this application.

[0040] Figure 4b The diagram shows a schematic of a carry vector circuit with a quotient of -1 provided in an embodiment of this application.

[0041] Figure 4c The diagram illustrates the principle of a carry vector circuit with a quotient of 0 provided in an embodiment of this application.

[0042] Figure 5 This illustration shows a schematic diagram of the principle of generating a first remainder according to an embodiment of this application.

[0043] Figure 6 This illustration shows a schematic diagram of the principle of generating a second remainder according to an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0045] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0046] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0047] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0048] Given that existing SRT dividers based on the "carry + sum" carry-preserving structure still have the following shortcomings: First, there is a timing bottleneck in the preparation of initial values ​​(initial carry and initial sum) before the first iteration. In the first iteration w[1] = w[0] - dq[1], the initial remainder w[0] needs to be set according to the sign of the quotient (final quotient): when the sign of the final quotient is positive, carry = |x| and sum = 0; when the sign of the final quotient is negative, carry = ~|x| + 1 and sum = 0. When the sign of the final quotient is negative, it is necessary to perform an additional operation of inverting (i.e., ~|x|) and adding 1 on the absolute value of the dividend x. This "inverting and adding 1" operation is on the critical path, which increases the logical complexity of the first stage before the first iteration, and brings additional timing pressure and area overhead.

[0049] Second, the remainder calculation after iteration is highly complex. After iteration, the remainder needs to be post-processed based on the sign of the final quotient and the sign of the remainder to ensure the correctness of the result. When the sign of the final quotient is negative, a portion of the remainder (2w[j] - dq(j+1), where subtracting dq(j+1) is equivalent to inverting dq(j+1) and adding 1. Usually, the addition of 1 is not calculated initially, but is added to the lowest bit after left shift of carry when adding sum). This is equivalent to calculating dq(j+1) - 2w[j]. In the "carry + sum" representation, this inverse calculation is equivalent to dq(j+1) + (~2carry) + (~2sum) + 2. Compared to the positive remainder calculation 2w[j] - dq(j+1), an additional full-width (e.g., 66-bit) addition of 1 is required. This extra increment operation not only increases the hardware area but also introduces additional latency on the critical path of remainder post-processing, limiting further improvements in the overall timing performance of the divider.

[0050] Existing SRT dividers based on a "carry + sum" carry-preserving structure suffer from timing and area bottlenecks due to redundant representations in both the initial value preparation stage of the first iteration and the remainder calculation stage after the iteration. Currently, there is no systematic optimization based on the redundant representation of some remainders. To address these issues, this application provides an improved divider based on a "carry-sum" form, aiming to simplify the circuit structure, reduce hardware area overhead, and optimize the timing performance of the computation path. Compared to existing solutions, this application effectively reduces the circuit area and significantly improves the timing performance of relevant critical paths in both the initial value preparation stage of the first iteration and the remainder calculation stage after the iteration.

[0051] It should be noted that this application uses the redundant "carry - sum" representation instead of the traditional "carry + sum" representation. Although the representation has changed, the final calculated quotient and remainder are completely consistent with the existing scheme, and the correctness of the calculation results is not affected.

[0052] This application employs a redundant "carry-sum" representation to store and transmit partial remainders, replacing the traditional "carry + sum" representation. Throughout the SRT iteration, the partial remainder is continuously represented by two components: the carry vector (carry) and the sum vector (sum), with its actual value equal to carry - sum. Based on this representation, this application achieves effective optimization of timing performance and hardware area in stages such as initial value preparation for the first iteration and remainder calculation after the iteration.

[0053] To facilitate understanding, the SRT2 algorithm will be used as an example below. The core of the SRT algorithm is the iterative equation: w[j+1] = rw[j] - dq[j+1]; where w[j+1] is called the partial remainder, the initial value w[0] is equal to the dividend, r is the base (in the SRT2 algorithm, the base r = 2), d is the divisor, and q is the quotient generated in each iteration. Therefore, the following expression can be obtained: w[0] = |x|(dividend); w[1] = w[0] – dq[1], in the first iteration, based on the cutoff value of w[0] and the cutoff value of d, we look up the table to get q[1] = 1; w[2] = 2w[1] – dq[2], in the second iteration, based on the cutoff value of 2w[1] and the cutoff value of d, we can find q[2] = 1 by looking up the table; w[3] = 2w[2] – dq[3], in the third iteration, based on the cutoff value of 2w[2] and the cutoff value of d, we look up the table to get [3]; ... w[j+1]=2w[j]– dq[j+1], in the (j+1)th iteration, based on the truncation value of 2w[j] and the truncation value of d, look up q[j+1].

[0054] Generally, integer division has four possible cases. To avoid the need for two lookup tables due to the divisor being positive or negative, and to prevent the handling of remainders from becoming complicated, the circuit implementation only considers the cases of "positive number divided by positive number" and "negative number divided by positive number" to ensure that the divisor is always positive. The quotient and remainder in other cases can be calculated using additional logic (e.g., keeping the quotient unchanged and adjusting the remainder based on the sign of the dividend (taking the opposite number)). Signed integer division has the four cases shown in Table 1 below: Table 1

[0055] In circuit implementation, direct calculations are performed only for the following two cases: 1) If the dividend is positive and the divisor is positive (if the dividend is negative and the divisor is negative, the quotient is the same and the remainders are opposites), the quotients are the same.

[0056] 2) If the dividend is negative and the divisor is positive (if the dividend is positive and the divisor is negative, the calculation is also performed in this way, the quotients are the same and the remainders are opposites).

[0057] The advantage of this is that when calculating the remainder, it is not necessary to judge the signs of both the dividend and the divisor; only the remainder needs to be adjusted based on the sign of the final quotient.

[0058] In the preprocessing stage of the dividend and divisor, the absolute value of the dividend has been processed. In the previous iteration, the dividend and divisor need to be led zeroed and left-shifted before the initial value of the partial remainder is selected. According to the conventional approach, the first iteration is w[1]=w[0]–dq[0], where the initial partial remainder w[0]=carry+sum. It needs to be determined in the previous iteration based on the sign of the final quotient. That is, when the quotient is positive, carry=|x|, sum=0; when the quotient is negative, carry=~|x|+1, sum=0. This gives the initial carry value an additional case, and the critical path is at ~|x|+1.

[0059] According to the carry-sum expression, the actual initial remainder w[0] = carry-sum. For the first iteration, we only need to make the following judgment based on the sign of the final quotient in the previous iteration: when the quotient is positive, carry = |x|, sum = 0; when the quotient is negative, carry = 0, sum = |x|. In this way, the initial carry value and the initial sum value are simplified to a single case, without the need to perform the "invert and add 1" operation, thus effectively simplifying the preceding logic and shortening the critical path delay.

[0060] The feasibility of the carry-sum redundancy representation in the iteration process is introduced below. We will use a partial remainder width of 66 bits and an initial quotient of 1 as an example (the cases for other quotients are similar). The first iteration operation can be expressed as: w1 = w0 - div = carry-sum - div; where div represents the preprocessed divisor. Through the equivalent transformation of subtraction, the above equation can be rewritten as: w1 = carry + (~sum) + 1 + (~div) + 1. Therefore, the three inputs of the 3-2 compressor (CSA32) are the carry vector carry, and the inverse of the vector. sum, the inverse of the divisor div.

[0061] The sum vector new_sum[65:0] output by the compressor 3-2 satisfies: new_sum[65:0]=~sum[65:0] ^carry[65:0]^ ~div[65:0]; the high-order bit new_carry[65:1] of the output carry vector new_carry[65:0] satisfies: new_carry[65:1]=(~sum[64:0]&carry[64:0]) | (~sum[64:0]&~div[64:0]) |(carry[64:0]&~div[64:0]), and the lowest-order bit new_carry[0]=1 (this 1 represents the extra 1 needed to subtract the divisor (i.e. The 1 in div+1). Therefore, we have: carry+( sum)+( div)+1=new_carry+new_sum. Therefore, w1 can be expressed as: w1=new_carry+new_sum+1=new_carry-(~new_sum). In the formula, “^” represents logical XOR, “|” represents logical OR, and “&” represents logical AND.

[0062] Define the carry vector for the next iteration as nxt_carry = new_carry, and the sum vector for the next iteration as nxt_sum = Then, for `new_sum`, we have `w1 = nxt_carry - nxt_sum`. The partial remainder `w1` after the first iteration and the initial partial remainder `w0 = carry` are then considered. The sum has a completely consistent "carry-sum" representation. This representation can be continuously passed during the iteration process, thus proving the feasibility of the redundant "carry-sum" representation used in this application in iterative calculations.

[0063] Based on the truth table shown in Table 2 below, we can derive ~(~sum^x)=sum^x, where x is equivalent to carry ^ ~div. Then we have: ~new_sum[65:0]=sum[65:0]^ carry[65:0]^ ~div[65:0], and we can then design the division iteration circuit based on the above principle.

[0064] Table 2

[0065] The following explains how the redundant representation of "carry-sum" can further simplify the computational complexity of the remainder calculation stage after the iteration. After the iteration is complete, quotient and remainder adjustments are required.

[0066] Regarding quotient adjustment, the traditional "carry+sum" scheme's judgment logic is as follows: If the quotient is positive, no adjustment is needed when carry+sum is non-negative, and the quotient needs to be decremented by 1 when carry+sum is negative; if the quotient is negative, no adjustment is needed when carry+sum is non-positive, and the quotient needs to be incremented by 1 when carry+sum is positive. This judgment logic is basically consistent with the quotient adjustment logic under the "carry-sum" scheme of this application, that is, both require corresponding adjustments to the quotient based on the sign of the remainders and the sign of the quotient after iteration.

[0067] Regarding remainder adjustment, the conventional iterative formula is w[j+1] = 2w[j] - dq[j+1], where subtracting dq[j+1] is equivalent to inverting dq[j+1] and adding 1. This "add 1" operation is usually delayed until later when adding carry and sum, at which point the "1" is added to the lowest bit of carry after left shifting. Simultaneously, dq[j+1] - 2w[j] needs to be calculated to ensure that the remainder is inverted when the quotient is negative. This inversion calculation, in the "carry+sum" representation, is actually equivalent to dq[j+1] + (~2carry) + (~2sum) + 2, which requires an additional 66-bit increment operation compared to the forward calculation of 2w[j] - dq[j+1].

[0068] By adopting the "carry-sum" representation in this application, the advantages of negation processing become apparent: since the negation of carry-sum is sum-carry, it is only necessary to select the order of the minuend and subtrahend based on the sign of the final quotient before performing subtraction, eliminating the need for an additional 66-bit increment operation. Therefore, compared to conventional schemes, this application achieves significant area savings and timing benefits in the remainder calculation stage.

[0069] To better understand the above solution, the following will combine... Figure 1 The structure of the divider provided in this application will be described. To accommodate the "carry-sum" representation, the divider provided in this application includes a preprocessing circuit, a division iteration circuit, and a postprocessing circuit. The output terminal of the preprocessing circuit is coupled to the input terminal of the division iteration circuit; the output terminal of the division iteration circuit is coupled to the input terminal of the postprocessing circuit.

[0070] This divider completes the division operation through three collaborative stages: preprocessing, division iteration, and postprocessing. The specific working principle is as follows: The preprocessing circuit generates an initial partial remainder represented in a redundant form (i.e., a carry vector and a sum vector) based on the dividend, the number of leading zeros in the dividend, and the sign of the final quotient. The true value of the initial partial remainder is equal to the carry vector minus the sum vector, i.e., carry-sum. The division iteration circuit receives this redundant initial partial remainder and the preprocessed divisor, and performs iterative operations. In each iteration, it selects the partial remainder for the next iteration based on the quotient value of the current iteration step. After the iteration is completed, it outputs the first partial remainder, also represented in a redundant form. The postprocessing circuit performs final processing on the first partial remainder based on the sign of the final quotient and combines it with the preprocessed divisor to generate the initial remainder. After obtaining the initial remainder, the post-processing circuit needs to perform a right shift, the amount of which is the number of leading zeros of the divisor in the preprocessing stage, to offset the left shift in the elimination preprocessing stage. Finally, the right shift result is adjusted again according to the sign of the dividend (e.g., whether to invert and add one to the right shift result; if the sign of the dividend is negative, then the right shift result needs to be inverted and added one to obtain the final remainder).

[0071] The following description focuses on the improvements made in the preprocessing and division iteration parts. For other parts not described herein, existing implementations in existing dividers can be referenced. For example, the logic for looking up q[j+1] and its corresponding lookup table based on the partial remainder truncation values ​​w[j] and d during the division iteration process, as well as other parts of the iteration, are the same as existing implementations and will not be elaborated upon here.

[0072] The preprocessing section also involves preprocessing the input divisor and dividend to provide standardized operands for subsequent iterative operations. This typically includes extracting and determining the sign bit of the divisor and dividend (for signed and negative numbers, they are usually converted to their corresponding two's complement values ​​for iteration, and their sign information is recorded for sign correction of the quotient and remainder in post-processing), determining the sign of the final quotient, determining the sign of the final remainder (the final remainder sign must match the dividend sign), detecting zero values ​​(if the divisor is zero, an exception is triggered; if the dividend is zero, the result is output directly), and detecting leading zeros and left-shifting (if the first digit of the divisor or dividend is not 1, i.e., 0, a left shift is required), etc.

[0073] In some possible implementations, the preprocessing circuit can also be used to obtain an initial partial remainder based on the preprocessed dividend |x| (the dividend after left shift) and the sign of the final quotient. In one implementation, when the preprocessing circuit in this application obtains the initial partial remainder based on the absolute value of the dividend (e.g., |x_init|), the number of leading zeros in the dividend (e.g., lzd), and the sign of the final quotient (e.g., res_is_pos), it is specifically used to: left-shift the absolute value of the dividend, such as |x_init|, based on the number of leading zeros in the dividend to obtain the left-shifted result (i.e., the dividend after left shift, corresponding to the aforementioned |x|), and determine the initial partial remainder based on the left-shifted result and the sign of the final quotient; wherein, when the sign of the final quotient is positive, the carry vector of the initial partial remainder is the left-shifted result, and the sum vector is zero; when the sign of the final quotient is negative, the carry vector of the initial partial remainder is zero, and the sum vector is the left-shifted result. That is, when the quotient is positive, carry = |x|, sum = 0; when the quotient is negative, carry = 0, sum = |x|.

[0074] When determining the initial partial remainder based on the sign of the left shift result and the final quotient, the preprocessing circuit specifically performs the following: a logical AND operation (e.g., &) on the sign of the left shift result and the final quotient to obtain the carry vector of the initial partial remainder; and a logical AND operation on the inverted sign of the left shift result and the final quotient to obtain the sum vector of the initial partial remainder. The corresponding circuit principle is as follows: Figure 2 As shown, first, leading zero detection is performed on |x_init| to obtain the corresponding number of leading zeros lzd. Then, it is shifted left (corresponding to shift_left) according to the number of leading zeros to obtain |x|. Then, a logical AND is performed with the sign of the final quotient res_is_pos and the inverse value ~res_is_pos to obtain the initial carry and the initial sum. Figure 2 The "~" symbol in the text indicates negation.

[0075] In another possible implementation, the preprocessing circuit may not perform a logical AND operation on the left-shifted result and the sign and inverse of the final quotient. Instead, it may achieve the same effect in other ways. For example, the preprocessing circuit may include a first selector and a second selector. The first input of the first selector is connected to |x|, its second input is connected to a fixed value of 0, and its control terminal is connected to the sign signal of the final quotient, res_is_pos. Similarly, the first input of the second selector is connected to a fixed value of 0, its second input is connected to |x|, and its control terminal is connected to the sign signal of the final quotient. Under the control of the sign signal of the final quotient, the first and second selectors output the carry vector carry and the sum vector sum of the initial partial remainders: when the quotient is positive, carry = |x|, sum = 0; when the quotient is negative, carry = 0, sum = |x|.

[0076] The following describes the process by which the division iteration circuit performs iterative calculations on the initial remainder (w0) and the preprocessed divisor (i.e., the divisor div after left shift), and outputs the first remainder at the end of the iteration.

[0077] Based on the above iterative equations, it can be seen that this process involves multiple iterations. In each iteration, the division iterative circuit is specifically used to: generate three candidate sum vectors based on the carry vector (carry), sum vector (sun), and preprocessed divisor (div) of the current iteration step, and select the sum vector for the next iteration from the three candidate sum vectors based on the quotient of the current iteration step; and generate three candidate carry vectors based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, and select the carry vector for the next iteration from the three candidate carry vectors based on the quotient of the current iteration step. In the first iteration, w1 is obtained by iterating from w0, and the carry vector and sum vector of w0 are obtained from the initial partial remainder; w2 is obtained by iterating from w1, and so on, until the iteration ends.

[0078] The division iteration circuit may include a sum vector circuit and a carry vector circuit. The sum vector circuit generates three candidate sum vectors based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, and selects the sum vector from the three candidate sum vectors to output for the next iteration based on the quotient of the current iteration step. The carry vector circuit generates three candidate carry vectors based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, and selects the carry vector from the three candidate carry vectors to output for the next iteration based on the quotient of the current iteration step.

[0079] The quotient of the current iteration step comes from the set {-1, 0, +1}. When generating the three corresponding candidate sum vectors, the division iteration circuit is specifically used to: XOR the carry vector, sum vector, and the inverted value (~div) of the preprocessed divisor of the current iteration step to obtain the first candidate sum vector (e.g., nxt_sum_p1[65:0]) representing the quotient of 1 in the current iteration step; XOR the carry vector, sum vector, and preprocessed divisor of the current iteration step to obtain the second candidate sum vector (e.g., nxt_sum_m1[65:0]) representing the quotient of -1 in the current iteration step; and XOR the carry vector and sum vector of the current iteration step to obtain the third candidate sum vector (nxt_sum_z[65:0]) representing the quotient of 0 in the current iteration step. The circuit diagrams for nxt_sum under different quotient values ​​are shown below. Figure 3 As shown, the sum vector for the next iteration can be selected based on the quotient of the current iteration step. For example, if the quotient of the current iteration step is 1, then... Figure 3The sum vector on the left side; when the quotient of the current iteration step is -1, choose... Figure 3 The sum vector located in the middle; when the quotient of the current iteration step is 0, select... Figure 3 The sum vector on the right side of the middle.

[0080] Understandable, Figure 3 The vector circuit shown is merely an exemplary implementation, and its function is not limited to using an XOR gate. In practical applications, this circuit can also employ other logic combinations or equivalent substitutions to achieve the same functional effect as the XOR operation. Any alternative circuit structure that can achieve the same input-output mapping relationship should be considered an equivalent implementation of the technical solution of this application, and this application does not specifically limit it in this regard.

[0081] Optionally, when generating the three corresponding candidate carry vectors, the division iteration circuit is specifically used to: generate a first candidate carry vector (e.g., {nxt_carry_p1[65:1],1'b1}) representing the quotient of 1 in the current iteration step, based on the carry vector of the current iteration step, the inverted value of the sum vector, and the inverted value of the preprocessed divisor; generate a second candidate carry vector (e.g., {nxt_carry_m1[65:1],1'b0}) representing the quotient of -1 in the current iteration step, based on the carry vector of the current iteration step, the inverted value of the sum vector, and the preprocessed divisor; and generate a third candidate carry vector (e.g., {nxt_carry_z[65:1],1'b0}) representing the quotient of 0 in the current iteration step, based on the carry vector of the current iteration step and the inverted value of the sum vector. Then, the carry vector for the next iteration is selected from the three candidate carry vectors based on the quotient of the current iteration step. For example, if the quotient of the current iteration step is 1, then the first candidate carry vector is output; if the quotient of the current iteration step is -1, then the second candidate carry vector is output; if the quotient of the current iteration step is 0, then the third candidate carry vector is output.

[0082] In one possible implementation, when generating the first candidate carry vector representing the quotient of 1 in the current iteration step based on the carry vector of the current iteration step, the inverted value of the vector (~sum), and the inverted value of the preprocessed divisor (~div), the principle is as follows: Figure 4a When the quotient is 1, w1 = carry + (~sum) + 1 + (~div) + 1, nxt_carry_p1[65:1] = (~sum[64:0] & carry[64:0]) | (~sum[64:0] & ~div[64:0]) | (carry[64:0] & ~div[64:0]), nxt_carry_p1[0] = 1.

[0083] In one possible implementation, when generating a second candidate carry vector representing a quotient of -1 in the current iteration step based on the carry vector of the current iteration step, the inverse of the vector (~sum), and the preprocessed divisor (div), the principle is as follows: Figure 4b When the quotient is -1, w1 = carry + (~sum) + 1 + div, then nxt_carry_m1[65:1] = (~sum[64:0] & carry[64:0]) | (~sum[64:0] & div[64:0]) | (carry[64:0] & div[64:0]), nxt_carry_m1[0] = 0 (since it is +div instead of -div at this time, there is no need to add 1).

[0084] In one possible implementation, when generating a third candidate carry vector representing a quotient of 0 in the current iteration step based on the carry vector of the current iteration step and the inverse of the sum vector, the principle is as follows: Figure 4c When the quotient is 0, w1 = carry + (~sum) + 1, then nxt_carry_z1[65:1] = (~sum[64:0] & carry[64:0]), nxt_carry_z[0] = 0.

[0085] It is understandable that the above Figure 4a , Figure 4b , Figure 4c The carry vector circuit shown is merely an exemplary implementation, and its function is not limited to implementation using logical AND and logical OR. In practical applications, this circuit can also employ other logical combinations or equivalent substitutions to achieve the same functional effect. Any alternative circuit structure that can achieve the same input-output mapping relationship should be considered an equivalent implementation of the technical solution of this application, and this application does not specifically limit it in this regard.

[0086] In one possible implementation, the post-processing circuit is specifically used to: generate a first remainder based on the sign of the final quotient and the first part of the remainder; generate a second remainder based on the sign of the final quotient and the first part of the remainder; and select to output either the first remainder or the second remainder based on the highest bit of the first remainder (a highest bit of a first preset value (e.g., 1) indicates a positive carry-sum, and a highest bit of a second preset value (e.g., 0) indicates a negative carry-sum) to obtain the initial remainder. In this implementation, the first remainder and the second remainder can be calculated in parallel, and then the first remainder or the second remainder can be output based on the highest bit of the first remainder as the initial remainder. For example, when the highest bit of the first remainder is 1, the initial remainder is the first remainder; when the highest bit of the first remainder is 0, the initial remainder is the second remainder. The second remainder is the sum of the first remainder and the preprocessed divisor.

[0087] In one possible implementation, the post-processing circuit, when generating the initial remainder, specifically performs the following: when the final quotient is positive, it generates a first remainder based on the first part of the remainder, generates a second remainder based on the first part of the remainder and the preprocessed divisor, and selects to output either the first remainder or the second remainder based on the highest bit of the first remainder to obtain the initial remainder; when the final quotient is negative, it generates a first remainder based on the opposite of the first part of the remainder, generates a second remainder based on the opposite of the first part of the remainder and the preprocessed divisor, and selects to output either the first remainder or the second remainder based on the highest bit of the first remainder to obtain the initial remainder. In this implementation, the first part of the remainder and its opposite may not exist simultaneously; the choice between using the first part of the remainder or its opposite can be made based on the sign of the final quotient.

[0088] It is understandable that, in some implementations, the first remainder and its opposite can coexist. In this case, when generating the initial remainder, the post-processing circuit specifically performs the following steps: generating a first remainder based on the first remainder; generating a second remainder based on the first remainder and the pre-processed divisor; and selecting to output either the first or second remainder based on the highest bit of the first remainder to obtain the first initial remainder; generating a third remainder based on the opposite of the first remainder (corresponding to the first remainder when the sign of the final quotient is negative); generating a fourth remainder based on the opposite of the first remainder and the pre-processed divisor (corresponding to the second remainder when the sign of the final quotient is negative); and selecting to output either the third or fourth remainder based on the sign of the third remainder to obtain the second initial remainder; and selecting to output either the first or second initial remainder based on the sign of the final quotient to obtain the initial remainder.

[0089] Optionally, when generating the first remainder, the post-processing circuit is specifically used to: generate the first remainder based on the inverted value (i.e., ~cal_sum[65:0]) of the first data (e.g., cal_carry[65:0]), the second data (cal_sum[65:0]), and a fixed value of 1; wherein, when the sign of the final quotient (res_is_pos) is positive (e.g., 1), the first data is the carry vector of the first part of the remainder (e.g., last_carry[65:0]), and the second data is the sum vector of the first part of the remainder (e.g., last_sum[65:0]); when the sign of the final quotient is negative (e.g., 0), the first data is the sum vector of the first part of the remainder, and the second data is the carry vector of the first part of the remainder. That is, when the sign of the final quotient is positive, the first remainder is generated based on the first part of the remainder, where the first part of the remainder is equal to the carry vector minus the sum vector; when the sign of the final quotient is negative, the first remainder is generated based on the opposite of the first part of the remainder, where the opposite of the first part of the remainder is equal to the sum vector minus the carry vector.

[0090] Optionally, the post-processing circuit is specifically used to: extend the first data by 1 bit and pad the most significant bit of the extension with 0 to obtain the extended first data (e.g., {1'b0, cal_carry[65:0]}); extend the inverted value of the second data by 1 bit and pad the most significant bit of the extension with 0 to obtain the inverted value of the extended second data (e.g., {1'b0, ~cal_sum[65:0]}); add the extended first data, the inverted value of the extended second data, and a fixed value (e.g., {66'h0, 1'b1}) to obtain the first remainder (e.g., rem_res1[66:0]). By extending the 66-bit vector to 67 bits, it is easier to select the first or second remainder based on the most significant bit of the extension.

[0091] To better understand, let's combine the following... Figure 5 The process of generating the first remainder is explained as follows: when res_is_pos is 1 (indicating a positive quotient), then cal_carry[65:0] = last_carry[65:0] and cal_sum[65:0] = last_sum[65:0]; conversely, when res_is_pos is 0 (indicating a negative quotient), then cal_carry[65:0] = last_sum[65:0] and cal_sum[65:0] = last_carry[65:0]. Next, cal_carry[65:0] is expanded to get {1'b0, cal_carry[65:0]}. The inverse value of cal_sum[65:0], ~cal_sum[65:0], is expanded to get {1'b0, ~cal_sum[65:0]}. Finally, {1'b0, cal_carry[65:0]}, {1'b0, ~cal_sum[65:0]}, and {66'h0, 1'b1} are added together to get {rem_ge_zero, rem_res1[65:0]}, where rem_ge_zero is the highest bit of the first remainder (such as rem_res1[66:0]), and rem_res1[65:0] is the remaining part of the first remainder.

[0092] pass Figure 5 As can be seen, after the iteration, this application performs remainder calculation based on the "carry-sum" redundant representation, which effectively simplifies the circuit structure. Since the opposite of the "carry-sum" form is "sum-carry", the opposite of the remainder can be directly obtained by simply adjusting the order of the carry vector and the sum vector, thus facilitating the execution of subsequent shift operations. Compared with conventional schemes, this application has better timing performance and smaller area overhead in the remainder calculation stage.

[0093] When generating the second remainder, the post-processing circuit is specifically used to: generate the second remainder based on the inverse value of the first data (e.g., cal_carry[65:0]), the second data (e.g., cal_sum[65:0]), a fixed value (e.g., 1), and the preprocessed divisor div[65:0]. That is, when the sign of the final quotient is positive, the second remainder is generated based on the first part of the remainder and the preprocessed divisor; when the sign of the final quotient is negative, the second remainder is generated based on the opposite of the first part of the remainder and the preprocessed divisor.

[0094] Optionally, the post-processing circuit is specifically used to: compress the inverted values ​​of the first data and the second data, and the preprocessed divisor into a new carry vector (e.g., rem_carry[65:0]) and a new sum vector (e.g., rem_sum[65:0]); extend the new carry vector by 1 bit and pad the least significant bit of the extension with 1 (i.e., the fixed value mentioned above) to obtain the extended carry vector (e.g., {rem_carry[65:0], 1'b1}); extend the new sum vector by 1 bit and pad the most significant bit of the extension with 1 to obtain the extended sum vector (e.g., {1'b1, rem_sum[65:0]}); add the extended carry vector and the extended sum vector together to obtain the second remainder (e.g., rem_res2[66:0]).

[0095] To better understand, let's combine the following... Figure 6 To explain the process of generating the second remainder, the CSA32 compressor can be used to compress cal_carry[65:0], cal_sum[65:0], and div[65:0] into rem_carry[65:0] and rem_sum[65:0]. Then, rem_carry[65:0] is expanded to get {rem_carry[65:0],1'b1}, and rem_sum[65:0] is expanded to get {1'b1,rem_sum[65:0]}. Finally, {rem_carry[65:0],1'b1} and {1'b1,rem_sum[65:0]} are added together to get rem_res2[66:0].

[0096] In one possible implementation, the first remainder and the second remainder may not be generated in parallel. Instead, the first remainder is generated first and then the second remainder is generated. In this case, the post-processing circuit described above, when generating the initial remainder based on the sign of the final quotient, the first part of the remainder, and the pre-processed divisor, is specifically used to: generate the first remainder based on the sign of the final quotient and the first part of the remainder. When the highest bit of the first remainder is 1 (first preset value), the first remainder is output as the initial remainder; when the highest bit of the first remainder is 0 (second preset value), the adjusted first remainder (i.e., the second remainder) is output as the initial remainder, where the adjusted first remainder (i.e., the second remainder) is equal to the sum of the first remainder and the preprocessed divisor.

[0097] Specifically, when generating the first remainder based on the sign of the final quotient and the first part of the remainder, it can be done as follows: when the sign of the final quotient is positive, generate the first remainder based on the sign of the final quotient and the first part of the remainder; when the sign of the final quotient is negative, generate the first remainder based on the opposite of the first part of the remainder.

[0098] To ensure the remainder is positive before the right shift and avoid precision loss, this application denotes the first remainder obtained after post-processing as rem_res1. The initial remainder before the actual shift has the following two possibilities based on the highest bit of the first remainder: 1) The highest bit of the first remainder is 1, so choose rem_res1 as the remainder before shifting; 2) If the highest bit of the first remainder is 0, select the adjusted remainder rem_res2 as the remainder before shifting.

[0099] When the quotient is positive, the adjustment of the remainder is easy to understand: if the first remainder is greater than or equal to 0, no adjustment is needed; when the first remainder is less than 0, the pre-processed divisor needs to be added for adjustment.

[0100] When the quotient is negative, to ensure the remainder before the shift is positive, the corresponding remainder should also be negative. In this case, the remainder is inversely multiplied to obtain a positive remainder. Since the first remainder is greater than or equal to 0, no adjustment is needed. If the first remainder is less than 0, the actual remainder should be greater than or equal to 0, requiring adjustment by adding the preprocessed divisor. For example, with -5 / 3, if the iteration yields a quotient of -2 and a remainder of 1, the scenario is that the quotient is negative, and the remainder 1 is inversely multiplied to obtain -1. Therefore, -1 needs to be added to the divisor 3 to obtain an initial remainder of 2, which ensures the initial remainder used for the right shift is positive.

[0101] After obtaining the initial remainder, further adjustments are needed to obtain the final remainder. For example, the selected initial remainder can be shifted to the right by the number of leading zeros of the divisor. Then, the remainder after the right shift can be adjusted according to the sign of the dividend (e.g., by inverting and adding one) to obtain the final remainder.

[0102] This application also provides an electronic device, which includes the aforementioned divider. The electronic device in this application includes, but is not limited to, mobile phones, tablets, personal computers (PCs), netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other devices equipped with dividers.

[0103] The electronic device provided in this application embodiment has the same implementation principle and technical effect as the aforementioned divider embodiment. For the sake of brevity, any parts not mentioned in the electronic device embodiment can be referred to the corresponding content in the aforementioned divider embodiment. It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0104] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functionality, and operation of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0105] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A divider, characterized in that, include: The system includes a preprocessing circuit, a division iteration circuit, and a postprocessing circuit, wherein the output of the preprocessing circuit is coupled to the input of the division iteration circuit. The output of the division iteration circuit is coupled to the input of the post-processing circuit; The preprocessing circuit is used to obtain an initial partial remainder based on the dividend, the number of leading zeros in the dividend, and the sign of the final quotient; wherein the initial partial remainder is represented by the carry vector and the sum vector, and the true value of the initial partial remainder is equal to the carry vector minus the sum vector; The division iteration circuit is used to perform iterative calculations on the initial partial remainder and the preprocessed divisor, and output the first partial remainder at the end of the iteration; wherein the first partial remainder is represented by the carry vector and the sum vector, and the true value of the first partial remainder is equal to the carry vector minus the sum vector. The post-processing circuit is used to generate an initial remainder based on the sign of the final quotient, the first part of the remainder, and the preprocessed divisor.

2. The divider according to claim 1, characterized in that, The preprocessing circuit is specifically used for: The absolute value of the dividend is shifted to the left based on the number of leading zeros in the dividend to obtain the left-shifted result. The initial partial remainder is determined based on the left-shifted result and the sign of the final quotient. Wherein, when the sign of the final quotient is positive, the carry vector of the initial partial remainder is the left shift result and the sum vector is zero; when the sign of the final quotient is negative, the carry vector of the initial partial remainder is zero and the sum vector is the left shift result.

3. The divider according to claim 2, characterized in that, When determining the initial partial remainder, the preprocessing circuit is specifically used for: Perform a logical AND operation between the left shift result and the sign of the final quotient to obtain the carry vector of the initial partial remainder; Perform a logical AND operation between the left-shifted result and the inverted sign of the final quotient to obtain the sum vector of the initial partial remainders.

4. The divider according to claim 1, characterized in that, The division iteration circuit is specifically used for: Based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, generate three corresponding candidate sum vectors, and select the sum vector from the three candidate sum vectors to output for the next iteration based on the quotient of the current iteration step. Based on the carry vector, sum vector, and preprocessed divisor of the current iteration step, generate three corresponding candidate carry vectors, and select the carry vector from the three candidate carry vectors based on the quotient of the current iteration step to output for the next iteration. The carry vector and sum vector in the first iteration are obtained based on the initial partial remainder.

5. The divider according to claim 4, characterized in that, When generating the corresponding three candidate vectors, the division iteration circuit is specifically used for: XOR the carry vector, sum vector, and the inverted value of the preprocessed divisor of the current iteration step to obtain the first candidate sum vector representing the quotient value of 1 in the current iteration step. XOR the carry vector, sum vector, and preprocessed divisor of the current iteration step to obtain the second candidate sum vector, which represents the quotient value of -1 in the current iteration step. XOR the carry vector and sum vector of the current iteration step to obtain the third candidate sum vector that represents the quotient value of 0 in the current iteration step.

6. The divider according to claim 4, characterized in that, When generating the three corresponding candidate carry vectors, the division iteration circuit is specifically used for: Based on the carry vector of the current iteration step, the inverted value of the sum vector, and the inverted value of the preprocessed divisor, generate the first candidate carry vector representing the quotient value of 1 in the current iteration step; Based on the carry vector of the current iteration step, the inverse of the sum vector, and the preprocessed divisor, generate a second candidate carry vector that represents the quotient of -1 in the current iteration step. Based on the carry vector of the current iteration step and the inverse of the sum vector, generate a third candidate carry vector that represents the quotient of 0 in the current iteration step.

7. The divider according to claim 1, characterized in that, The post-processing circuit is specifically used for: A first remainder is generated based on the sign of the final quotient and the first part of the remainder, and a second remainder is generated based on the sign of the final quotient, the first part of the remainder and the preprocessed divisor. The first remainder or the second remainder is output based on the highest bit of the first remainder to obtain the initial remainder.

8. The divider according to claim 7, characterized in that, When generating the first remainder, the post-processing circuit is specifically used to: generate the first remainder based on the inverted value of the first data, the second data, and a fixed value; Wherein, when the sign of the final quotient is positive, the first data is the carry vector of the first part of the remainders, and the second data is the sum vector of the first part of the remainders; when the sign of the final quotient is negative, the first data is the sum vector of the first part of the remainders, and the second data is the carry vector of the first part of the remainders.

9. The divider according to claim 8, characterized in that, The post-processing circuit is specifically used for: Extend the first data by 1 bit and pad the most significant bit of the extension with 0 to obtain the extended first data; Extend the inverted value of the second data by 1 bit and fill the most significant bit of the extension with 0 to obtain the inverted value of the extended second data. The first remainder is obtained by adding the expanded first data, the inverted value of the expanded second data, and the fixed value.

10. The divider according to claim 7, characterized in that, When generating the second remainder, the post-processing circuit is specifically used to: generate the second remainder based on the first data, the inverted value of the second data, a fixed value, and the pre-processed divisor; Wherein, when the sign of the final quotient is positive, the first data is the carry vector of the first part of the remainders, and the second data is the sum vector of the first part of the remainders; when the sign of the final quotient is negative, the first data is the sum vector of the first part of the remainders, and the second data is the carry vector of the first part of the remainders.

11. The divider according to claim 10, characterized in that, The post-processing circuit is specifically used for: Compress the inverted values ​​of the first data and the second data, and the preprocessed divisor, into a new carry vector and a new sum vector; Extend the new carry vector by 1 bit and fill the least significant bit with the fixed value to obtain the extended carry vector; Extend the new sum vector by 1 bit and pad the highest bit of the extension with 1 to obtain the extended sum vector; Add the expanded carry vector and the expanded sum vector together to obtain the second remainder.

12. The divider according to claim 1, characterized in that, The post-processing circuit is specifically used for: The first remainder is generated based on the sign of the final quotient and the first part of the remainder; When the highest bit of the first remainder is the first preset value, output the first remainder as the initial remainder; When the highest bit of the first remainder is the second preset value, the second remainder is output as the initial remainder; wherein, the second remainder is equal to the sum of the first remainder and the preprocessed divisor.

13. An electronic device, characterized in that, include: The divider as described in any one of claims 1-12.

Images