An accelerating chip implementation device and method for elliptic curve point operation and quadratic extension field operation

Abstract

The application discloses an accelerating chip implementation device and method for elliptic curve point operation and quadratic extension field operation, which comprises an operation module, a data transmission module and a control module, wherein the data transmission module is used for receiving external input data, sequentially arranging the to-be-calculated data according to the operation number, and transmitting the arranged operation number, a calculation mode and a running signal to the control module; the control module is connected with the data transmission module and the operation module respectively, is used for receiving the running signal and the operation number, jumping to the corresponding calculation state according to the calculation mode, and calling the operation module to execute the required base field operation in each calculation state through an internal state machine; and the operation module is connected with the control module, is used for executing the operation in parallel under the scheduling of the control module. The method is implemented based on the device. The application has the advantages of simple structure, high resource utilization, more high-performance scene requirements, high processing efficiency and the like.

Description

Technical Field

[0001] This invention mainly relates to the field of cryptographic hardware acceleration technology, specifically to an acceleration chip implementation device and method for elliptic curve point operations and quadratic extended field operations. Background Technology

[0002] With the continuous expansion of data scale and user numbers in the information age, information security and cryptographic protocols have become hot research areas in cybersecurity. In emerging fields such as blockchain, cloud computing, and the Internet of Things, systems often need to support tens of thousands or even hundreds of thousands of cryptographic operations per second while ensuring security. The demands of massive data processing and high concurrency performance place higher requirements on key indicators such as security and encryption / decryption speed in cryptographic operations.

[0003] Bilinear pairing is a special bilinear mapping that maps two points on an elliptic curve to elements of its extended field. It provides richer algebraic structures for cryptographic systems and is a core technology for implementing advanced cryptographic functions such as attribute-based encryption, identity cryptography, and zero-knowledge proofs. Compared to traditional public-key cryptosystems, bilinear pairing-based cryptographic schemes have unique advantages in functional expression and can support more complex cryptographic protocol designs. However, bilinear pairing operations are computationally extremely complex, involving numerous large integer modular multiplications, modular inverses, extended field operations, and iterative operations involving elliptic curve point addition and doubling. The computational paths are long and highly dependent on data. Traditional software implementations struggle to fully utilize parallel computing resources, resulting in persistently high latency. Existing hardware acceleration solutions generally suffer from low resource utilization, high computational overhead, and long execution times, severely limiting their deployment in scenarios such as blockchain nodes and IoT security, and failing to meet the urgent needs of practical applications for low-latency, high-throughput cryptographic operations. Summary of the Invention

[0004] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides an accelerated chip implementation device and method for elliptic curve point operations and secondary extended field operations that is simple in structure, can improve resource utilization, is applicable to more high-performance scenarios, and has high processing efficiency.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: An accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations includes an operation module, a data transmission module, and a control module, wherein: The data transmission module is used to receive external input data, arrange the data to be calculated in the order of operands, and transmit the arranged operands, calculation mode, and operation signal to the control module. The control module is connected to the data transmission module and the arithmetic module respectively. It is used to receive running signals and operands, and jump to the corresponding calculation state according to the calculation mode. In each calculation state, the control module sequentially calls the arithmetic module through the internal state machine to execute the required base domain operations. The computing module is connected to the control module and is used to perform computing in parallel under the scheduling of the control module.

[0006] As a further improvement of the present invention: the data transmission module is used to transmit the input operands to be calculated and the operation mode to the control module. The input operands include the coordinates of points on the elliptic curve, the extended domain elements, and system parameters. The data transmission module aligns and sorts the operands according to a preset data format so that the control module can correctly parse them.

[0007] As a further improvement of the present invention: the control module consists of an overall state machine and several smaller state machines; the overall state machine jumps to the corresponding calculation state according to the operation mode and is responsible for managing the overall operation process; the smaller state machines are used to control the specific calculation logic of the extended domain operation and the point operation on the elliptic curve, and call the calculation unit in the operation module to perform the corresponding operation according to each calculation stage, and determine whether the calculation is over after obtaining the result; if the calculation is over, the final result is passed to the data transmission module for output; if it is not over, the algorithm flow jumps to the next calculation step.

[0008] As a further improvement of the present invention, the control module is also provided with a register file for storing and managing intermediate operands, so as to reduce the data interaction overhead with external storage.

[0009] As a further improvement of the present invention: the arithmetic module includes two base field modular addition and subtraction arithmetic units, three base field modular multiplication arithmetic units, and one base field modular inverse arithmetic unit; wherein: The base domain modular addition and subtraction operation unit is implemented by combining AND gates, OR gates, NOT gates, XOR gates and multiplexers, reusing the same hardware computing resources; The modular multiplication unit of the base field employs the Montgomery modular multiplication algorithm for large integer factorization; it first decomposes the large integer, and then utilizes an efficient multiply-adder unit. Perform multiplication and addition calculations; The base domain modular inverse operation unit controls the result of the shifted operand through a state machine, determines whether the loop condition is met, and performs the modular inverse operation accordingly.

[0010] As a further improvement of the present invention: the base domain modular addition and subtraction operation unit uses a signal flag bit Decide whether to perform a modulo addition or modulo subtraction operation: when When the value is 1, the subtrahend will be 1. Invert the value to perform the subtraction operation; when When the modulus is 0, the modulus will be... Invert the values ​​to perform pre-calculation and modulo operations; finally, calculate based on the addition / subtraction flags. The carry signal of each operation result is used to select the correct result for output.

[0011] As a further improvement of the present invention: the multiply-adder unit in the base domain performs four small-width multiplications in parallel, implemented by one bit-stored adder (CSA) and three ordinary adders, and completes a larger-width multiplication-add operation in one pipeline cycle; the modular multiplication operation shares a modular addition calculation unit in each loop stage and is executed internally by pipeline.

[0012] As a further improvement of the present invention: the base domain modular inverse operation unit includes two shift registers for storing the value of the current iteration; two counters for recording the number of shifts of even factors; and a comparator and a subtraction unit for calculating the subtraction based on the size relationship to finally obtain the modular inverse result.

[0013] The present invention further provides a method for implementing the above-described apparatus, comprising: Step S1: Data reception and parsing; The data transmission module receives raw data from external input, including elliptic curve point coordinates, extended domain elements, calculation mode, and start signal; the data transmission module determines the required number and order of operands according to the mode code, writes the arranged operands into the register file of the control module, and writes the mode code into the input register of the overall state machine; Step S2: Calculate pattern recognition and state machine transition; After receiving the data to be calculated and the calculation mode, the control module stores the data and jumps to the corresponding calculation state according to the mode code based on the overall state machine; Step S3: Scheduling of computing units; After the small state machine jumps to the corresponding operation state, each state under the control module's small state machine will perform parallel operations without data dependencies, and schedule the corresponding operation units to shorten the critical path delay; Step S4: Output the result; Once the overall state machine determines that all calculation steps have been completed, the control module transmits the final result to the data transmission module. The data transmission module packages the result according to the data format agreed upon by the external interface, sets the completion flag signal, and notifies the external device to read the calculation result.

[0014] As a further improvement to the implementation method of the present invention: in step S2, the calculation mode includes: elliptic curve point addition, point doubling, scalar multiplication, quadratic extended field multiplication, quadratic extended field addition, quadratic extended field subtraction, and quadratic extended field inversion; after the overall state machine determines the operation type, the corresponding small state machine is activated and the specific calculation process begins to be executed.

[0015] Compared with the prior art, the advantages of the present invention are as follows: 1. The present invention provides an accelerated chip implementation device and method for elliptic curve point operations and quadratic extended field operations, aiming to solve the problems of low resource utilization and difficulty in meeting the requirements of high-performance scenarios in the prior art. The accelerated chip includes a data transmission module, a control module, and a computation module. The data transmission module receives and arranges external input data, transmitting operands and computation modes to the control module. The control module jumps to the corresponding computation state according to the computation mode, including point addition, point doubling, scalar multiplication, quadratic extended field modular addition, quadratic extended field modular subtraction, quadratic extended field modular multiplication, and quadratic extended field modular inverse operations, and sequentially calls the computation module to execute the computation. The computation module includes two base field modular addition / subtraction operation units, three base field modular multiplication operation units, and one base field modular inverse operation unit, which execute basic operations such as modular addition / subtraction, modular multiplication, and modular inverse in parallel under the scheduling of the control module. The present invention transforms complex point operations and extended field operations into a data-independent computation queue, reduces the computation cycle through a parallel scheduling mechanism, and integrates data paths into a single module.

[0016] 2. The accelerated chip implementation device and method for elliptic curve point operations and secondary extended field operations of the present invention proposes for the first time a hardware device and method that integrates elliptic curve operations and extended field operations. By transforming complex point operations and extended field operations into data-independent operation queues and setting up multiple parallel operation units, the computational throughput per unit time is improved.

[0017] 3. The accelerated chip implementation device and method for elliptic curve point operation and secondary extended field operation of the present invention, through state machine scheduling, makes full use of hardware parallel resources and realizes elliptic curve point operation and extended field operation functions in the same module, which can solve the problems of low resource utilization and difficulty in meeting the requirements of high-performance scenarios in the prior art. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the topological structure principle of the present invention in a specific embodiment.

[0019] Figure 2 This is a schematic diagram of the structural principle of the modular addition and subtraction operation unit in a specific embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structural principle of the multiply-adder operation unit in a specific embodiment of the present invention.

[0021] Figure 4 This is a flowchart illustrating the implementation method of the present invention in a specific embodiment. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1 As shown, this invention provides an accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations, including an operation module, a data transmission module, and a control module, wherein: The data transmission module is used to receive external input data, arrange the data to be calculated in the order of operands, and transmit the arranged operands, calculation mode, and operation signal to the control module. The control module is connected to the data transmission module and the arithmetic module respectively. It is used to receive running signals and operands, and jump to the corresponding calculation state according to the calculation mode, including point addition, point doubling, scalar multiplication, second-order extended domain modular addition, second-order extended domain modular subtraction, second-order extended domain modular multiplication, and second-order extended domain modular inverse operation. In each calculation state, the control module sequentially calls the arithmetic module through the internal state machine to execute the required base domain operation. The arithmetic module is connected to the control module and is used to perform basic operations such as modular addition, subtraction, multiplication, and inversion in parallel under the scheduling of the control module.

[0024] In a specific application example, the operation module includes two base field modular addition and subtraction operation units, three base field modular multiplication operation units, and one base field modular inverse operation unit; wherein: The base domain modular addition and subtraction unit is implemented by combining AND gates, OR gates, NOT gates, XOR gates, and multiplexers, reusing the same hardware computing resources. See also Figure 2 via signal flag bits Decide whether to perform a modulo addition or modulo subtraction operation: when When the value is 1, the subtrahend will be 1. Invert the value to perform the subtraction operation; when When the modulus is 0, the modulus will be... Invert the values ​​to perform pre-calculation and modulo operations; finally, calculate based on the addition / subtraction flags. The carry signal of each operation result is used to select the correct result for output.

[0025] The modular multiplication unit of the base field employs the Montgomery modular multiplication algorithm for large integer factorization. First, the large integer is factored, and then an efficient multiply-adder unit is used. Perform multiplication and addition calculations. See also Figure 3The multiply-adder unit performs four small-bit-width multiplications in parallel, implemented with one bit-stored adder (CSA) and three ordinary adders, enabling large-bit-width multiply-add operations to be completed within one pipeline cycle. Modular multiplication operations share a modular addition computation unit in each loop stage and are executed internally via pipeline.

[0026] The base domain modular inverse operation unit controls the result of the shifted operands through a state machine. It then determines whether the loop condition is met and performs the modular inverse operation accordingly. Its internal structure includes: two shift registers to store the value of the current iteration; two counters to record the number of shifts for even factors; and a comparator and subtraction unit to calculate the modular inverse result by performing subtraction based on the size relationship.

[0027] In a specific application example, the data transmission module is used to transmit the input operands to be calculated, along with the operation mode, to the control module. The input operands include the coordinates of points on the elliptic curve, extended domain elements, and system parameters, etc. The data transmission module aligns and sorts the operands according to a preset data format to ensure that the control module can correctly parse them.

[0028] In a specific application example, the control module consists of an overall state machine and several smaller state machines. The overall state machine jumps to the corresponding computation state according to the operation mode, and is responsible for managing the overall computation process. The smaller state machines are responsible for controlling the specific computation logic of extended domain operations and point operations on elliptic curves. They call the computation units in the operation module to execute the corresponding operations according to each computation stage, and determine whether the computation is complete after obtaining the result. If the computation is complete, the final result is passed to the data transmission module for output; if it is not complete, the module jumps to the next computation step according to the algorithm flow. Since a large number of intermediate values ​​are generated during the computation process, the control module also has a register file for storing and managing intermediate operands to reduce the data interaction overhead with external storage.

[0029] See Figure 4 The present invention further provides a method for implementing the above-described accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations, comprising: Step S1: Data reception and parsing; The data transmission module receives raw data from external input, including elliptic curve point coordinates, extended domain elements, calculation mode, and start signal.

[0030] The data transmission module determines the required number and order of operands based on the pattern code, writes the arranged operands into the register file of the control module, and writes the pattern code into the input register of the overall state machine.

[0031] That is, the data transmission module arranges the data according to the preset operand order and sends the arranged data along with the calculation mode to the control module.

[0032] Step S2: Calculate pattern recognition and state machine transition; After receiving the data to be calculated and the calculation mode, the control module stores the data and jumps to the corresponding calculation state according to the mode code based on the overall state machine.

[0033] The calculation modes include: elliptic curve point addition, point doubling, scalar multiplication, quadratic extended field multiplication, quadratic extended field addition, quadratic extended field subtraction, and quadratic extended field inversion, etc.

[0034] Once the overall state machine determines the operation type, it activates the corresponding sub-state machine and begins executing the specific calculation process.

[0035] Input information includes: Secondary expansion elements ,in For elements in a 384-bit prime field, ; Coordinates of points on the elliptic curve: , ， Elements in a 384-bit field Pattern Encoding : 3-bit value, controlling the state machine of the specific operation, the pattern encoding mapping is as follows: 0x01: Secondary expansion modulo addition; 0x02: Secondary expansion modulo reduction; 0x03: Quadratic extended field modular multiplication; 0x04: Second-order extended field modular inverse; 0x05: Elliptic curve point addition; 0x06: Elliptic curve multiple point; 0x07: Elliptic curve scalar multiplication; Step S3: Scheduling of computing units; After jumping to the corresponding operation state in the small state machine, each state under the control module's small state machine will perform parallel operations without data dependencies, and schedule the corresponding operation units to shorten the critical path delay, so that they can accelerate the execution of basic operations such as second-order extended domain modular addition and subtraction, modular multiplication, modular inverse, as well as point operations on elliptic curves.

[0036] That is, after jumping to the corresponding operation state and process, the control module identifies the operation tasks without data dependencies and schedules the base domain operation units in parallel. It can independently perform basic operations such as quadratic extended domain modular addition and subtraction, modular multiplication, modular inverse and point operations on elliptic curves, thereby shortening the critical path delay.

[0037] Step S4: Output the result; Once the overall state machine determines that all calculation steps have been completed, the control module will transmit the final result to the data transmission module.

[0038] The data transmission module packages the results according to the data format agreed upon by the external interface, sets the completion flag signal, and notifies the external device to read the calculation results.

[0039] In a specific application example, step S3 includes: 1. Second-order extended-domain modular addition and subtraction operations; When a quadratic extended-domain modular addition / subtraction operation is required, the quadratic extended-domain modular addition / subtraction state machine is activated based on the calculation mode. This unit consists of two base-domain modular addition / subtraction units. For quadratic extended-domain elements... and Modular addition is performed by calling two base domain modular addition and subtraction units in parallel to calculate the operation. and Implemented; modular subtraction operations are computed in parallel. and Implementation. The base-domain modular addition and subtraction unit controls the calculation type by using the same combinational logic circuit through the signal flag s, effectively reducing hardware resource overhead. Only one base-domain addition and subtraction cycle is needed to complete the second-order extended-domain modular addition and subtraction operation. This is for the second-order extended-domain base... 2. Quadratic extended field modular multiplication operation; When a quadratic extended-field modular multiplication operation is required, the quadratic extended-field modular multiplication state machine is activated. This unit consists of three base-field modular multiplication units. For quadratic extended-field elements... and The result of its multiplication Calculate using the following formula: , )-(

[0040] The three base field modular multiplication units are computed in parallel. and The three terms are then combined using modular addition and subtraction units to obtain the final result. Only one base field multiplication cycle and several addition cycles are needed to complete the second extended field modular multiplication operation.

[0041] 3. Second-order expansion of the field and modular inverse operation; The quadratic extension modular inverse operation unit is activated when a quadratic extension modular inverse operation is required. This unit consists of three base field modular multiplication units and one base field modular inverse operation unit. For quadratic extension elements... and Its inverse element First, call the modular multiplication unit of the base field to calculate. and The denominator is obtained through modular addition and subtraction; then the modular inverse operation unit of the base field and the modular multiplication operation unit of the base field are called to calculate respectively. and The inverse result is obtained. The modular inverse operation unit of the base field controls the shifted operands through a state machine, judges the loop condition, and executes the modular inverse algorithm to complete the inversion operation on the finite field.

[0042] 4. Elliptic curve point addition and doubling operations; When elliptic curve point addition or doubling operations are required, the control module decomposes the point addition formula into a sequence of basic operations such as modular subtraction, modular inverse, modular multiplication, and modular addition. Based on data dependencies, this sequence is divided into multiple computational stages and written into a small state machine. The three base domain computation units are called in parallel as much as possible to perform dependency-free operations. The doubling operation follows the same principle.

[0043] 5. Elliptic curve scalar multiplication; When elliptic curve point addition or doubling operations are required, the control module enters a judgment state based on the scalar multiplier, and selects to enter either the point addition state or the doubling state based on the current bit value. The final scalar multiplication result is then obtained.

[0044] During computation, the control module stores intermediate operands in the register file. When subsequent computation steps require the previously calculated intermediate results, the control module reads them directly from the register file, avoiding redundant calculations. The register file employs a multi-port design, supporting simultaneous read and write operations to meet the data access bandwidth requirements of parallel scheduling.

[0045] Through the above steps, the accelerated chip implementation scheme proposed in this invention can efficiently complete elliptic curve point operations and extended field operations. The control module decomposes complex cryptographic operations into a sequence of basic operations that can be executed in parallel through the coordinated scheduling of the overall state machine and the small state machines; the dedicated extended field operation units within the operation module work together to make full use of hardware parallel resources; and the register file effectively manages intermediate data, reducing external access overhead.

[0046] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations, characterized in that, It includes a computing module, a data transmission module, and a control module, among which: The data transmission module is used to receive external input data, arrange the data to be calculated in the order of operands, and transmit the arranged operands, calculation mode, and operation signal to the control module. The control module is connected to the data transmission module and the arithmetic module respectively. It is used to receive running signals and operands, and jump to the corresponding calculation state according to the calculation mode. In each calculation state, the control module sequentially calls the arithmetic module through the internal state machine to execute the required base domain operations. The computing module is connected to the control module and is used to perform computing in parallel under the scheduling of the control module.

2. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 1, characterized in that, The data transmission module is used to transmit the input operands to be calculated along with the operation mode to the control module. The input operands include the coordinates of points on the elliptic curve, extended domain elements, and system parameters. The data transmission module aligns and sorts the operands according to a preset data format so that the control module can parse them correctly.

3. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 1, characterized in that, The control module consists of an overall state machine and several smaller state machines. The overall state machine jumps to the corresponding calculation state according to the operation mode and is responsible for managing the overall operation process. The smaller state machines are used to control the specific calculation logic of the extended domain operation and the point operation on the elliptic curve. According to each calculation stage, they call the calculation unit in the operation module to perform the corresponding operation, and determine whether the calculation is over after obtaining the result. If the calculation is over, the final result is transmitted to the data transmission module for output. If the process is not complete, proceed to the next calculation step according to the algorithm flow.

4. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 3, characterized in that, The control module also has a register file for storing and managing intermediate operands, thereby reducing the overhead of data interaction with external storage.

5. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to any one of claims 1-4, characterized in that, The computation module includes two base field modular addition and subtraction units, three base field modular multiplication units, and one base field modular inverse unit; wherein: The base domain modular addition and subtraction operation unit is implemented by combining AND gates, OR gates, NOT gates, XOR gates and multiplexers, reusing the same hardware computing resources; The modular multiplication unit of the base field employs the Montgomery modular multiplication algorithm for large integer factorization; it first decomposes the large integer, and then utilizes an efficient multiply-adder unit. Perform multiplication and addition calculations; The base domain modular inverse operation unit controls the result of the shifted operand through a state machine, determines whether the loop condition is met, and performs the modular inverse operation accordingly.

6. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 5, characterized in that, The base domain modular addition and subtraction unit uses signal flags. Decide whether to perform a modulo addition or modulo subtraction operation: when When the value is 1, the subtrahend will be 1. Invert the value to perform the subtraction operation; when When the modulus is 0, the modulus will be... Invert the values ​​to perform pre-calculation and modulo operations; finally, calculate based on the addition / subtraction flags. The carry signal of each operation result is used to select the correct result for output.

7. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 5, characterized in that, The modular multiplication unit of the base domain performs four small-width multiplications in parallel using a multiply-adder unit, implemented by one bit-stored adder (CSA) and three ordinary adders, completing a large-width multiplication-add operation within one pipeline cycle. The modular multiplication operation shares a modular addition calculation unit in each loop stage and is executed internally in a pipelined manner.

8. The accelerated chip implementation device for elliptic curve point operations and quadratic extended field operations according to claim 5, characterized in that, The base domain modular inverse operation unit includes two shift registers for storing the value of the current iteration; two counters for recording the number of shifts of even factors; and a comparator and a subtraction unit for calculating the subtraction based on the size relationship to finally obtain the modular inverse result.

9. A method for implementing the apparatus based on any one of claims 1-8, characterized in that, include: Step S1: Data reception and parsing; The data transmission module receives raw data from external input, including elliptic curve point coordinates, extended domain elements, calculation mode, and start signal; The data transmission module determines the number and order of operands required based on the pattern code, writes the arranged operands into the register file of the control module, and writes the pattern code into the input register of the overall state machine. Step S2: Calculate pattern recognition and state machine transition; After receiving the data to be calculated and the calculation mode, the control module stores the data and jumps to the corresponding calculation state according to the mode code based on the overall state machine; Step S3: Scheduling of computing units; After the small state machine jumps to the corresponding operation state, each state under the control module's small state machine will perform parallel operations without data dependencies, and schedule the corresponding operation units to shorten the critical path delay; Step S4: Output the result; Once the overall state machine determines that all calculation steps have been completed, the control module will transmit the final result to the data transmission module. The data transmission module packages the results according to the data format agreed upon by the external interface, sets the completion flag signal, and notifies the external device to read the calculation results.

10. The implementation method according to claim 9, characterized in that, In step S2, the calculation modes include: elliptic curve point addition, point doubling, scalar multiplication, quadratic extended field multiplication, quadratic extended field addition, quadratic extended field subtraction, and quadratic extended field inversion; after the overall state machine determines the operation type, the corresponding small state machine is activated, and the specific calculation process begins to be executed.

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