An AI computing power chip interface data synchronization consistency verification method

Abstract

The application relates to the technical field of digital data processing, in particular to an AI computing power chip interface data synchronization consistency verification method, which comprises the following steps: receiving and concurrently accessing a data stream in a hardware layer of a master control computing unit, dividing the data stream into blocks by adopting a sliding window mechanism, and generating an algebraic characteristic value stream by dimension reduction calculation based on a light-weight algebraic mapping algorithm; synchronously transmitting the concurrently accessed data stream and the algebraic characteristic value stream to a slave computing unit; taking the received algebraic characteristic value stream as comparison input in the hardware layer of the slave computing unit, feeding the algebraic characteristic value stream into a double-buffered verification pipeline, and generating a local characteristic value stream based on the received concurrently accessed data stream; performing hardware-level parallel characteristic value comparison in the double-buffered verification pipeline; when the verification is inconsistent, calculating a characteristic value deviation by utilizing a matrix orthogonality principle, and locating a data channel with an error code. The application triggers data retransmission operation of the corresponding data channel by a retransmission control engine, and completes data synchronization consistency verification.

Description

Technical Field

[0001] This invention relates to the field of digital data processing technology, specifically to a method for verifying the consistency of data synchronization at the interface of an AI computing chip. Background Technology

[0002] With the development of artificial intelligence technology, AI computing chips need to perform massive concurrent data access and interaction between multiple computing units, which places extremely high demands on the synchronization and consistency of interface data transmission.

[0003] In existing data processing technologies, traditional mechanisms such as cyclic redundancy check (CRC) or full data mirroring serial comparison are typically used to ensure the accuracy of bus data transmission. However, in the context of AI computing chips with extremely high bandwidth and ultra-short clock cycles in memory access scenarios, traditional full data comparison consumes a significant amount of additional bus bandwidth, leading to communication congestion. Furthermore, conventional verification logic often requires fully buffering the data stream before serial computation; this blocking verification operation disrupts the chip's original memory access and computation pipeline, resulting in a substantial clock delay. In addition, existing error reporting mechanisms typically only report macroscopic errors at the bus transaction level when inconsistencies are detected.

[0004] Therefore, the main problems with existing technologies are: when faced with high-concurrency memory access data streams, it is difficult to achieve low-latency real-time synchronous verification in a clock-free blocking state; and when transmission errors occur, it is impossible to accurately locate the specific underlying physical channel where the fault occurred, resulting in blind coarse-grained global retransmission during error recovery. This not only wastes valuable bus bandwidth, but also seriously reduces the overall effective computing throughput of AI chips.

[0005] To address this, a method for verifying the consistency of AI computing chip interface data synchronization is proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a method for verifying the consistency of AI computing chip interface data synchronization. Through lightweight algebraic dimensionality reduction and matrix orthogonal solution, the method can accurately locate the error channel.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A method for verifying the consistency of data synchronization at an AI computing chip interface includes: The main control computing unit receives concurrent memory access data streams at the hardware layer, divides the concurrent memory access data streams into blocks using a sliding window mechanism, and performs dimensionality reduction calculations on the data within each sliding window based on a lightweight algebraic mapping algorithm to generate corresponding algebraic feature value streams. The concurrent memory access data stream and the algebraic eigenvalue stream are synchronously transmitted to the subordinate computing unit; At the hardware layer of the subordinate computing unit, the received algebraic feature value stream is used as the comparison input and fed into the double-buffered verification pipeline, and a local feature value stream is generated based on the concurrent memory access data stream received by the subordinate computing unit. In the double-buffered verification pipeline, the algebraic eigenvalue stream and the local eigenvalue stream are compared in hardware-level parallel eigenvalues. When the verification is inconsistent, the eigenvalue deviation is solved using the matrix orthogonality principle to locate the data channel where the error occurred. The positioning results of the data channel are output to the retransmission control engine, which then triggers the data retransmission operation of the corresponding data channel based on the positioning results to complete the data synchronization consistency verification.

[0008] Preferably, the concurrent memory access data stream includes a cross-core bus transaction identifier with a time stamp, a physical memory access address, read / write control signals, and a tensor data payload; dimensionality reduction calculations are performed on the data within each sliding window based on a lightweight algebraic mapping algorithm to generate the corresponding algebraic feature value stream, including: The tensor data load within each sliding window is reconstructed into a source data matrix according to the bus clock cycle using a hardware bus parser. The number of rows in the source data matrix corresponds to the total number of parallel channels in the bus physical link, and the number of columns corresponds to the total number of bus clock cycles contained in the sliding window. A preloaded orthogonal basis projection matrix is ​​extracted from the internal register of the main control computing unit, wherein the feature dimension of the orthogonal basis projection matrix is ​​less than the total number of parallel channels. The source data matrix and the orthogonal basis projection matrix are input to the hardware multiplier-adder array of the main control computing unit for hardware-level matrix multiplication, and a dimension-reduced feature matrix is ​​output. The dimension-reduced feature matrix is ​​then serialized and extracted column by column according to the bus clock cycle to generate the algebraic feature value stream that is sent synchronously with the concurrent memory access data stream.

[0009] Preferably, the construction of the orthogonal basis projection matrix specifically includes: the orthogonal basis projection matrix is ​​composed of a set of column vectors, wherein the total number of column vectors is equal to the total number of parallel channels of the bus physical link, and the spatial arrangement index of each column vector in the register uniquely maps to a bus physical link.

[0010] Preferably, the double-buffered verification pipeline includes: a first cache array and a second cache array controlled by a hardware read / write state machine; during the current bus synchronization cycle, the hardware read / write state machine controls the first cache array to be in a write latch state, writing the received algebraic feature value stream and the generated local feature value stream in parallel; simultaneously, it controls the second cache array to be in a read comparison state, outputting the feature values ​​latched in the previous bus synchronization cycle to the on-chip logic comparison tree to perform the hardware-level parallel feature value comparison; during the next bus synchronization cycle, the hardware read / write state machine triggers a flag bit to alternately flip, switching the read / write states of the first cache array and the second cache array, realizing clock-free pipeline overlap operation for feature value read / write and comparison.

[0011] Preferably, the eigenvalue deviation is calculated using the matrix orthogonality principle to locate the data channel where the error occurred. This includes: inputting the algebraic eigenvalue streams and the local eigenvalue streams that are inconsistent in the double-buffered verification pipeline to the hardware subtractor array of the subordinate computing unit for difference calculation to obtain the eigenvalue deviation vector; synchronously inputting the eigenvalue deviation vector and all column vectors of the orthogonal basis projection matrix preloaded in the internal register into the hardware multiply-accumulate tree logic to perform hardware-level parallel inner product matching operation; inputting the inner product matching operation results of all column vectors into the hardware comparison tree network to filter out the target column vector that presents the maximum response peak as the candidate error direction; extracting the spatial arrangement index of the target column vector in the orthogonal basis projection matrix, decoding the spatial arrangement index into the corresponding underlying hardware topology coordinates through a hardware mapping table, and outputting the bus physical link pointed to by the underlying hardware topology coordinates as the data channel where the error occurred for location.

[0012] Preferably, the retransmission control engine triggers a transaction retry operation on the corresponding bus physical link based on the positioning result, including: the retransmission control engine has a built-in transaction status tracing logic module and a rollback signaling generator; through the transaction status tracing logic module, based on the received underlying hardware topology coordinates and the bus clock tick where the comparison is inconsistent, the target cross-core bus transaction identifier where data corruption occurred is reverse-matched in the suspended transaction queue of the subordinate computing unit; a hardware-level cache cleaning mechanism is triggered to remove the received tensor data payload corresponding to the target cross-core bus transaction identifier from the subordinate... The data is erased from the receive buffer of the computing unit and the corresponding physical memory access address space is released simultaneously. The rollback signaling generator generates a transaction retry instruction containing the target cross-core bus transaction identifier and the underlying hardware topology coordinates. The transaction retry instruction is fed back to the main control computing unit via an on-chip control link independent of the data bus, forcing the main control computing unit to retrieve the original data from the internal storage queue based on the target cross-core bus transaction identifier, and initiate a transaction retry operation based on the located bus physical link, according to the retry granularity allowed by the target interconnect protocol.

[0013] Preferably, generating a local feature stream based on the concurrent memory access data stream received by the subordinate computing unit specifically includes: reconstructing the tensor data payload in the received concurrent memory access data stream into a target data matrix according to the bus clock cycle; calling a preset mirror-synchronous orthogonal basis projection matrix in the internal register of the subordinate computing unit, and inputting the mirror-synchronous orthogonal basis projection matrix and the target data matrix into the symmetric hardware multiplier-adder array of the subordinate computing unit to perform hardware-level matrix multiplication operations; and sequentially extracting the matrix output by the operation according to the bus clock cycle to generate the local feature stream that is strictly aligned with the received algebraic feature stream on the clock cycle.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention combines a sliding window and a lightweight algebraic mapping algorithm to perform hardware-level dimensionality reduction calculations on the reconstructed memory access data and orthogonal basis projection matrices. This mechanism significantly reduces the bus bandwidth required for synchronous transmission of eigenvalues, effectively avoiding communication congestion caused by full data comparison; at the same time, relying on the low-latency processing of the underlying hardware multiply-accumulator array, it achieves efficient extraction and transmission of algebraic eigenvalue streams, ensuring smooth interaction of massive concurrent data streams.

[0015] 2. This invention introduces a dual-buffered parity pipeline controlled by a hardware read / write state machine. By alternately flipping flag bits during the bus synchronization cycle, it precisely switches the write latch and read comparison states of the two high-speed cache arrays. This design achieves seamless pipeline overlap between feature value writing and feature value reading and comparison in the previous cycle, eliminating the clock blocking problem caused by traditional serial parity checking. It maintains the full-speed throughput of the system without interrupting the original high-concurrency memory access pipeline.

[0016] 3. This invention utilizes the principle of matrix orthogonality to calculate eigenvalue deviations and filters the dominant peak value of the inner product through a hardware comparison tree network, directly decoding the spatial permutation index into underlying hardware topology coordinates. This mechanism can accurately pinpoint a specific bus physical link when an error occurs and trigger a local transaction retry for the corresponding channel via the retransmission control engine. This eliminates the inefficient blind rollback of global data, shortens error recovery time, and significantly improves the effective utilization rate of the bus. Attached Figure Description

[0017] Figure 1 This is a flowchart of a method for verifying the consistency of AI computing chip interface data synchronization proposed in this invention; Figure 2 This is a flowchart of a data synchronization consistency verification method for an AI computing chip interface proposed in this invention. Figure 3 This is a flowchart of the dual-buffered verification pipeline proposed in this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1 Please see Figures 1 to 3 This invention provides a method for verifying the consistency of AI computing chip interface data synchronization, the technical solution of which is as follows: A method for verifying the consistency of data synchronization at an AI computing chip interface includes: The main control computing unit receives concurrent memory access data streams at the hardware layer, divides the concurrent memory access data streams into blocks using a sliding window mechanism, and performs dimensionality reduction calculations on the data within each sliding window based on a lightweight algebraic mapping algorithm to generate corresponding algebraic feature value streams. The concurrent memory access data stream and the algebraic eigenvalue stream are synchronously transmitted to the subordinate computing unit; At the hardware layer of the subordinate computing unit, the received algebraic feature value stream is used as the comparison input and fed into the double-buffered verification pipeline, and a local feature value stream is generated based on the concurrent memory access data stream received by the subordinate computing unit. In the double-buffered verification pipeline, the algebraic eigenvalue stream and the local eigenvalue stream are compared in hardware-level parallel eigenvalues. When the verification is inconsistent, the eigenvalue deviation is solved using the matrix orthogonality principle to locate the data channel where the error occurred. The positioning results of the data channel are output to the retransmission control engine, which then triggers the data retransmission operation of the corresponding data channel based on the positioning results to complete the data synchronization consistency verification.

[0020] Furthermore, the concurrent memory access data stream includes a time-stamped cross-core bus transaction identifier, physical memory access address, read / write control signals, and tensor data payload; dimensionality reduction calculations are performed on the data within each sliding window based on a lightweight algebraic mapping algorithm to generate the corresponding algebraic feature value stream, including: The tensor data load within each sliding window is reconstructed into a source data matrix according to the bus clock cycle using a hardware bus parser. The number of rows in the source data matrix corresponds to the total number of parallel channels in the bus physical link, and the number of columns corresponds to the total number of bus clock cycles contained in the sliding window. A preloaded orthogonal basis projection matrix is ​​extracted from the internal register of the main control computing unit, wherein the feature dimension of the orthogonal basis projection matrix is ​​less than the total number of parallel channels. The source data matrix and the orthogonal basis projection matrix are input to the hardware multiplier-adder array of the main control computing unit for hardware-level matrix multiplication, and a dimension-reduced feature matrix is ​​output. The dimension-reduced feature matrix is ​​then serialized and extracted column by column according to the bus clock cycle to generate the algebraic feature value stream that is sent synchronously with the concurrent memory access data stream.

[0021] To ensure the physical executability of the dimensionality reduction calculation within the hardware multiply-accumulator array, and to guarantee the strict orthogonal positioning capability during subsequent verification and comparison, the specific mathematical expression model of the hardware-level matrix multiplication operation is shown in the following formula: ; in, This represents the output of the dimensionality-reduced feature matrix; Represents the orthogonal basis projection matrix; This represents the reconstructed source data matrix. The mapping relationship between the variables in the formula in the hardware space is specifically as follows: the source data matrix The number of rows is the total number of parallel channels. The number of columns is the total number of bus clock cycles. The orthogonal basis projection matrix The number of rows is the feature dimension. The number of columns is the total number of parallel channels. and feature dimension Strictly less than the total number of parallel channels .

[0022] Extract the preloaded orthogonal basis projection matrix from the internal registers of the main control computing unit. Previously, the orthogonal basis projection matrix The specific preset generation steps include: During the offline initialization phase, a dimension is constructed. The standard Hadamard matrix, wherein the internal elements of the standard Hadamard matrix are composed of binary integer constants; Extract the preceding from the standard Hadamard matrix Lines construct the projection space; The extracted The projection space is constructed by arranging the indexes according to the physical pin sorting logic of the target hardware bus. The initial projection matrix of dimension; The binary integer constants in the initial projection matrix are mapped to hardware quantized values ​​that match the input bit width of the hardware multiply-accumulator array, resulting in the final orthogonal basis projection matrix. And project the orthogonal basis matrix The firmware is burned into the internal register of the main control computing unit.

[0023] Dimensionality reduction mapping of this invention Algebraically, this falls under the categories of compressed sensing and linear projection. Assume the original data matrix is ​​subject to error perturbation. Then the characteristic deviation matrix calculated by the receiver is Only if the error matrix Exactly within the projection matrix of the orthogonal basis Within the null space (i.e. Only when the eigenvalue does not respond (i.e., a missed detection) will a feature value not respond.

[0024] Due to the projection matrix The column vectors form a quasi-orthogonal basis in high-dimensional space. For any single-channel or sparse multi-channel data error, its error vector is related to... The probability that the column vectors are linearly uncorrelated is extremely low. Under this configuration, the theoretical probability of random data perturbations falling into the null space is less than [a certain value]. That is, the theoretical error detection rate within a single sliding window is higher than .

[0025] This invention constructs an orthogonal basis projection matrix based on the Hadamard matrix to perform hardware-level dimensionality reduction operations on the reconstructed memory access data. This mechanism effectively reduces the bandwidth overhead of eigenvalue synchronous transmission; at the same time, thanks to its orthogonality, it ensures the independence of each physical link feature after dimensionality reduction mapping. Combined with underlying hardware bit-width quantization adaptation, it provides a reliable foundation for accurate solution and location of subsequent error channels with low logical latency.

[0026] To prevent bit flipping due to electromagnetic interference during the transmission of algebraic eigenvalue streams on independent on-chip physical side band / dedicated line links, this invention employs the following protection and error differentiation mechanisms in the eigenvalue transmission and comparison architecture: 1) Before sending the algebraic feature stream, the master computing unit adds protection to the feature stream through the built-in lightweight single-error correction-double-error detection Hamming code encoder; when receiving, the slave computing unit first corrects the single-bit error on the physical link through the Hamming decoder to eliminate the influence of weak electromagnetic interference on the feature stream itself.

[0027] 2) When the double-buffered verification pipeline outputs inconsistent results, and the characteristic deviation vector... After inputting into the hardware multiply-accumulate tree for computation, if the scalar response of the inner product of all column vectors satisfies (That is, if no obvious response peak is observed, indicating that the deviation vector does not conform to the projection characteristics of any data channel), or if the Hamming decoder reports an uncorrectable double-bit error, the logic control circuit determines that the anomaly is caused by an error in the feature value stream transmission, rather than damage to the physical channel of the data bus. In this case, the retransmission control engine does not initiate data retransmission to the data bus, but only requests the main control computing unit to retransmit the algebraic feature values ​​of the current sliding window through sideband control signaling.

[0028] Furthermore, the construction of the orthogonal basis projection matrix specifically includes: the orthogonal basis projection matrix is ​​composed of a set of column vectors, wherein the total number of column vectors is equal to the total number of parallel channels of the bus physical link, and the spatial arrangement index of each column vector in the register uniquely maps to a bus physical link.

[0029] The column vector set is specifically represented as a set of quasi-orthogonal vectors that satisfy the lower bound of cross-correlation theory in the reduced-dimensional space. The specific preset generation and mapping configuration steps of the orthogonal basis projection matrix include: During the offline hardware compilation phase, a set of pseudo-random reference sequences with a period greater than or equal to the total number of parallel channels is generated over a finite field using a linear feedback shift register. Multiple sequences of length equal to the feature dimension are extracted from the pseudo-random reference sequence set to form multiple column vectors of the orthogonal basis projection matrix. Wherein, let the th... The column vectors are , No. The column vectors are The normalized cross-correlation inner product between any two distinct column vectors must satisfy the following quasi-orthogonality constraint formula: ; In the quasi-orthogonal constraint formula and A positive integer representing the column index and ; Represents column vectors The result of the transpose operation; Representing column vectors respectively and The vector 2 norm; The threshold is the preset lower bound threshold of cross-coherence theory, and satisfies... The lower bound threshold of the cross-coherence theory. The introduction of this feature ensures that when a code error occurs, the autocorrelation peak of the column vector corresponding to a specific physical link is significantly higher than the cross-coherent sidelobe generated when compared with other column vectors, thus enabling accurate identification in the hardware comparison tree network.

[0030] The specific implementation method for uniquely mapping the spatial arrangement index of each column vector in the register to a single bus physical link is as follows: Construct a hardware-based fixed mapping table based on programmable logic gates, and project the first element in the orthogonal basis projection matrix. column vectors The column pointer address is defined as the spatial arrangement index; The column pointer address is hardwired to the first physical pin of the bus physical link through the one-to-one physical pin connection logic in the hardware-fixed mapping table. A data transmission channel enables the column pointer address calculated and located to be directly decoded into the underlying hardware topology coordinates of the fault channel.

[0031] This invention utilizes cross-coherence lower bound constraints to construct a quasi-orthogonal vector set, ensuring that the autocorrelation peak of a specific link is highlighted during code errors, effectively avoiding multi-channel feature interference. Simultaneously, a hardware-based fixed mapping table is used to hardwire the column vector indexes to the physical transmission channel, eliminating additional software addressing overhead and enabling the column pointers to be directly and with low latency decoded into underlying hardware topology coordinates, achieving rapid and accurate location of faulty channels.

[0032] Furthermore, the double-buffered verification pipeline includes: a first cache array and a second cache array controlled by a hardware read / write state machine; during the current bus synchronization cycle, the hardware read / write state machine controls the first cache array to be in a write latch state, writing the received algebraic feature value stream and the generated local feature value stream in parallel; simultaneously, it controls the second cache array to be in a read comparison state, outputting the feature values ​​latched in the previous bus synchronization cycle to the on-chip logic comparison tree to perform the hardware-level parallel feature value comparison; during the next bus synchronization cycle, the hardware read / write state machine triggers a flag bit to alternately flip, switching the read / write states of the first cache array and the second cache array, realizing clock-free pipeline overlap operation for feature value read / write and comparison.

[0033] To ensure strict clock-free pipeline overlap during concurrent memory access data stream processing, the alternating toggling of the flag bits is controlled by underlying timing state triggering constraints. Specifically, the hardware read / write state machine incorporates edge detection and determination logic circuitry, and its state transitions are strictly executed according to the following timing constraint formula: ; in Indicates the absolute duration of a single bus synchronization cycle; This indicates the physical time taken for the first cache array or the second cache array to complete the parallel writing of local data stream feature values ​​in write latch state; This refers to the physical time taken for a cache array in the read comparison state to completely output the latched feature value to the on-chip logic comparison tree and complete the comparison. and These respectively characterize the inherent hardware setup time and hardware hold time required for the internal triggers of the hardware read / write state machine to alternately toggle the flag bits.

[0034] When the clock cycle configuration of the on-chip hardware clock domain satisfies the above timing constraint formula, the hardware read / write state machine captures the synchronization clock edge at the end of each bus synchronization cycle and sends an address addressing switching signal to the corresponding cache array, ensuring the flow of feature values ​​at the hardware physical level. Under the conditions that the cache is not full, the downstream can be received, and the timing is converged, it allows steady-state continuous reception of adjacent window data.

[0035] This invention employs a dual-buffered high-speed cache array, achieving seamless pipeline overlap between feature value writing and the previous cycle's feature value reading and comparison through alternating hardware read / write state machine transitions. Combined with a strict underlying timing constraint mechanism, it precisely matches the physical latency of read / write operations with the setup and hold times of triggers, ensuring pipelined flow of feature values ​​under conditions of timing convergence and cache insufficiency at the physical level. This design effectively eliminates bus congestion caused by the verification process, maintaining the continuous processing capability of the AI ​​chip's high-concurrency memory access flow.

[0036] Furthermore, the eigenvalue deviation is calculated using the principle of matrix orthogonality to locate the data channel where the error occurred. This includes: inputting the algebraic eigenvalue streams and the local eigenvalue streams that are inconsistent in the double-buffered verification pipeline to the hardware subtractor array of the subordinate computing unit for difference calculation to obtain the eigenvalue deviation vector; synchronously inputting the eigenvalue deviation vector and all column vectors of the orthogonal basis projection matrix preloaded in the internal register into the hardware multiply-accumulate tree logic to perform hardware-level parallel inner product matching operation; inputting the inner product matching operation results of all column vectors into the hardware comparison tree network to filter out the target column vector that presents the maximum response peak as the candidate error direction; extracting the spatial arrangement index of the target column vector in the orthogonal basis projection matrix, decoding the spatial arrangement index into the corresponding underlying hardware topology coordinates through a hardware mapping table, and outputting the bus physical link pointed to by the underlying hardware topology coordinates as the data channel where the error occurred.

[0037] In this invention, the eigenvalue deviation is calculated using the matrix orthogonality principle, primarily targeting the precise location of transient bit errors in single physical channels, which are most common in high-frequency memory access scenarios. To address the extreme scenario where errors occur simultaneously in multiple physical channels, the hardware comparison tree network of this invention further integrates sub-peak suppression and multi-error degradation judgment logic: The hardware comparison tree network filters out the scalar of the largest inner product response. Simultaneously, extract the second largest inner product response scalar. And calculate the peak isolation ratio. ,in To prevent tiny constants with a denominator of zero.

[0038] when And peak isolation ( The preset single-channel exclusive threshold is preferably set to a value of [value to be filled in]. When a single channel error occurs, the system outputs the target column vector and the underlying hardware topology coordinates, triggering a precise retransmission of the corresponding single channel. when But peak isolation When this occurs, it indicates that the current feature deviation vector is composed of multiple column vectors superimposed (i.e., a multi-channel concurrent error has occurred, causing peak aliasing). At this time, the hardware calculation logic outputs a multi-channel fault flag. After receiving the multi-channel fault flag, the retransmission control engine automatically degrades to a global transaction-level / sliding window full retransmission mechanism and records the fault log for subsequent link degradation or retraining decisions.

[0039] To ensure accurate identification and quantization of the main peak value of the inner product in the underlying circuitry and to avoid misjudgment caused by bus transient noise, the specific mathematical model and threshold determination logic for performing hardware-level parallel inner product matching operations and peak selection are as follows: Let the feature deviation vector be The first of the preloaded orthogonal basis projection matrices The column vectors are Then the first output of the hardware multiply-accumulate tree logic scalar response of inner product The calculation formula is: ; in, The feature deviation vector The feature dimension; and The corresponding vectors at the th The hardware numerical components of the dimension. After synchronously inputting the set of inner product response scalars corresponding to all column vectors into the hardware comparison tree network, the largest inner product response scalar is extracted in parallel by a comparator array. The system then obtains the corresponding target column vector. Simultaneously, to ensure the validity of the positioning results, the system determines the maximum inner product response scalar. Does it satisfy the adaptive amplitude discrimination formula? ; in, This represents the mean of the expected values ​​of all inner product response scalars within the synchronization period. This is a hardware-defined sensitivity coefficient based on the signal-to-noise ratio of the underlying physical link. Only when this amplitude discrimination formula is satisfied can the result corresponding to the maximum inner product response scalar be confirmed as a candidate for the main peak value of the inner product.

[0040] This invention utilizes the principle of matrix orthogonality and performs parallel inner product matching through underlying hardware logic. This ensures that feature deviations generate the main response peak only in the error direction, thereby achieving accurate mapping and location of faulty physical channels. Simultaneously, an adaptive amplitude discrimination mechanism based on the underlying signal-to-noise ratio is introduced to verify the maximum response peak value. This design effectively avoids misjudgments caused by bus transient noise, ensuring the authenticity and validity of the error resolution results and the overall anti-interference capability of the system.

[0041] Furthermore, the retransmission control engine triggers a transaction retry operation on the corresponding bus physical link based on the positioning result, including: the retransmission control engine has a built-in transaction status tracing logic module and a rollback signaling generator; through the transaction status tracing logic module, based on the received underlying hardware topology coordinates and the bus clock tick where the mismatch occurs, the target cross-core bus transaction identifier where data corruption occurred is reverse-matched in the suspended transaction queue of the slave computing unit; a hardware-level cache cleaning mechanism is triggered to remove the received tensor data payload corresponding to the target cross-core bus transaction identifier from the slave... The data is erased from the receive buffer of the computing unit and the corresponding physical memory access address space is released simultaneously. The rollback signaling generator generates a transaction retry instruction containing the target cross-core bus transaction identifier and the underlying hardware topology coordinates. The transaction retry instruction is fed back to the main control computing unit via an on-chip control link independent of the data bus, forcing the main control computing unit to retrieve the original data from the internal storage queue based on the target cross-core bus transaction identifier, and initiate a transaction retry operation based on the located bus physical link, according to the retry granularity allowed by the target interconnect protocol.

[0042] The channel positioning and retransmission control engine proposed in this invention achieves layered decoupling and perfect compatibility within the framework of standard on-chip / inter-chip interconnection protocols (including but not limited to PCIe, CXL, UCIe, or custom die-to-die protocols): The physical data channel positioning results (underlying hardware topology coordinates) of this invention have a dual function in the hardware system: On the one hand (link layer retransmission granularity compatibility): Modern interconnect protocols (such as UCIe / CXL) use Flit or Transaction as the basic retransmission granularity for link layer retransmission (LLR). The transaction status tracing logic module uses the underlying hardware topology coordinates and the clock tick at the time of the error to... The system accurately reverse-matches the target cross-core bus transaction identifier and its corresponding Flit that are currently being transmitted on the physical channel at that moment. The rollback signaling generator encapsulates the target cross-core bus transaction identifier into a standard protocol NAK / Retry message and sends it to the master control unit via the on-chip control link, invoking the standard protocol's native LLR retransmission mechanism to resend the damaged Flit / transaction.

[0043] On the other hand (physical layer channel management and degradation): the located underlying hardware topology coordinates are synchronously output to the on-chip physical layer management module. The physical layer management module counts the cumulative error frequency of a specific channel; when the number of retransmissions of a physical channel exceeds a threshold within a set time, the physical layer is triggered to perform channel masking or link width degradation, such as downgrading from x16 to x8, to isolate the faulty physical link without interrupting bus communication.

[0044] To ensure that the transaction status tracing logic module can accurately and uniquely reverse-match damaged transactions in a highly concurrent pipeline, and to avoid the risk of misjudgment of cross-core transactions due to bus physical propagation delay, the specific hardware circuit addressing mechanism and time compensation calculation formula for the reverse matching are as follows: ; in, This represents the calculated target cross-core bus transaction identifier; This refers to the suspended transaction queue; This represents the absolute count value of the bus clock ticks where inconsistencies occurred. This indicates the fixed number of clock cycles for the pre-calibrated physical propagation pipeline from the master computing unit to the slave computing unit; Parallel key-value matching operations for hardware content-addressable memory. When the suspended transaction queue... The original send timestamp of a pending transaction satisfy When the pin resource to which the suspended transaction is bound contains the underlying hardware topology coordinates, the hardware content addressing memory outputs its identifier as the target cross-core bus transaction identifier. The preset physical propagation pipeline delay fixed number of beats. During the chip power-on initialization phase, the round-trip delay is measured by sending and receiving standard calibration signaling through the hardware bus parser, and the one-way delay is calculated. The result is then hard-coded into a specific read-only register as a physical constant.

[0045] This invention employs a time-compensated hardware parallel matching mechanism, effectively eliminating cross-core transaction misjudgments caused by physical propagation delays and enabling accurate reverse tracing of damaged transactions in high-concurrency pipelines. Simultaneously, by combining hardware-level cache cleaning with an independent sideband control link, this invention can precisely initiate local retransmissions only for specific faulty channels. This design avoids inefficient global data rollback and reduces the bandwidth consumption of the main data bus during error recovery.

[0046] Further, generating a local feature stream based on the concurrent memory access data stream received by the subordinate computing unit specifically includes: reconstructing the tensor data load in the received concurrent memory access data stream into a target data matrix according to the bus clock cycle; calling the preset mirror-synchronous orthogonal basis projection matrix in the internal register of the subordinate computing unit, and inputting the mirror-synchronous orthogonal basis projection matrix and the target data matrix into the symmetric hardware multiplier-adder array of the subordinate computing unit to perform hardware-level matrix multiplication operations; and extracting the matrix output by the operation column by column according to the bus clock cycle to generate the local feature stream that is strictly aligned with the received algebraic feature stream on the clock cycle.

[0047] To ensure absolute consistency of the underlying hardware parsing architecture at both the transmitting and receiving ends and the accuracy of timing alignment, the specific method for obtaining the preset mirror synchronization orthogonal basis projection matrix and the local feature generation model are as follows: The mirror-synchronous orthogonal basis projection matrix is ​​generated during the chip mask or firmware offline programming stage based on a set of pseudo-random reference sequences identical to those of the main control computing unit, and hard-coded into the internal read-only register of the subordinate computing unit. Let the mirror-synchronous orthogonal basis projection matrix be... The target data matrix is The formula for the local dimension reduction matrix operation performed by the symmetric hardware multiply-accumulator array is as follows: ; in, This is the output local dimensionality-reduced feature matrix. The target data matrix. The number of rows is the total number of parallel channels. The number of columns is the total number of bus clock ticks. The mirror-synchronized orthogonal basis projection matrix The number of rows is the feature dimension. The number of columns is the total number of parallel channels. The output local dimensionality reduction feature matrix for This results in a dimensional matrix, thus achieving consistency with the dimension of the received algebraic eigenvalue stream in both mathematical principles and physical space.

[0048] Furthermore, to achieve strict alignment of dual-channel data on clock ticks and avoid race conditions caused by different physical link lengths, the column-by-column serialization extraction step is controlled by the underlying hardware-level elastic alignment depth formula: ; in: This indicates the local first-in-first-out buffer compensation depth configured before serialization extraction; This represents the sum of inherent clock delays during the transmission of concurrent memory access data streams on the on-chip interconnect network and the reconstruction of the local matrix; This represents the inherent clock delay of the algebraic eigenvalue stream in an independent transmission link; This represents the fixed pipeline cycle overhead for the symmetric hardware multiply-accumulator array performing matrix multiplication. The compensation depth is injected into the serialization extraction logic. As a hysteresis cancellation factor, this ensures that the generated local eigenvalue stream and the received algebraic eigenvalue stream achieve zero-phase clock-level synchronization when inputting to a double-buffered check pipeline. In actual hardware configurations, when calculated according to the formula... When this occurs, it indicates that the inherent delay of the feature value stream transmission and computation link is not less than the data stream path overhead. At this point, the serialization extraction logic configures the compensation depth as follows: The timing (i.e., no additional hysteresis buffering is required) allows for direct input of dual-channel feature streams into the verification pipeline.

[0049] This invention hard-codes the mirror-synchronous orthogonal basis projection matrix in the subordinate unit, ensuring absolute consistency between the underlying hardware parsing architecture and the dimensionality-reduced feature space at both the transmitting and receiving ends. Simultaneously, a hardware-level elastic alignment mechanism is introduced. By calculating and injecting buffer hysteresis compensation, the latency differences caused by multi-link transmission and computational overhead are offset, achieving zero-phase-difference clock-level alignment of the dual-channel feature value streams at the input of the verification pipeline.

[0050] This invention effectively reduces the bandwidth overhead of synchronous transmission of verification data through lightweight algebraic dimensionality reduction; it utilizes a double-buffered pipeline for hardware-level parallel comparison, ensuring non-blocking continuous transmission of high-concurrency memory access data streams. Simultaneously, based on the principle of matrix orthogonality, it accurately calculates and locates the physical channels of error codes, enabling targeted channel-level local retransmission. This method avoids the inefficient blind rollback of global data used in traditional methods, improving the effective utilization of the interface bus and the overall computational throughput of the AI ​​chip.

[0051] Example 2 This embodiment provides a specific application scenario based on a multi-core AI acceleration chip architecture. In this scenario, the main control computing unit is specifically the neural network processing unit (NPU) core computing cluster in the AI ​​acceleration chip, and the subordinate computing unit is specifically the external high-bandwidth memory (HBM) controller mounted on the on-chip network (NoC). The two communicate with each other via an on-chip bus with 256 parallel data channels (i.e., the total number of parallel channels M=256) to access and exchange massive tensor data.

[0052] A method for verifying the consistency of AI computing chip interface data synchronization, with the following specific workflow in this scenario: At the hardware layer of the NPU core computing cluster, activation value tensors (i.e., tensor data payloads) of the neural network are continuously being written to the HBM controller. The interface hardware layer of the NPU core computing cluster receives concurrent memory access data streams, which contain 256-bit wide tensor data payloads, physical memory access addresses, read / write control signals, and cross-core bus transaction identifiers. The system uses a sliding window mechanism, setting each 16 bus clock cycles as a block window (i.e., N=16), to divide the concurrent memory access data stream into blocks.

[0053] Subsequently, the NPU core computing cluster performs dimensionality reduction calculations on the data within each sliding window based on a lightweight algebraic mapping algorithm. Specifically, the hardware bus resolver reconstructs the 256 channels of data within these 16 clock cycles into a 256×16 source data matrix. Next, a preloaded orthogonal basis projection matrix is ​​extracted from the NPU's internal registers (this matrix is ​​generated offline, with a feature dimension K set to 16, less than the total number of parallel channels 256, and consists of 16 quasi-orthogonal row vectors of length 256). The source data matrix and the orthogonal basis projection matrix are input to the NPU's hardware multiplier-accumulator array for hardware-level matrix multiplication, outputting a 16×16 dimensionality-reduced feature matrix. This dimensionality-reduced feature matrix is ​​then serialized and extracted column-by-column according to the bus clock cycle, generating a 16-bit wide algebraic feature value stream corresponding to the current window.

[0054] During the data transmission phase, the NPU core computing cluster synchronously transmits the 256-bit wide concurrent memory access data stream and the aforementioned 16-bit wide algebraic eigenvalue stream to the HBM controller via their respective physical links.

[0055] At the hardware layer of the HBM controller, the received algebraic eigenvalue stream is used as the comparison input and fed into its internal double-buffered verification pipeline (which includes first and second cache arrays, using a state machine for alternating non-blocking read and write operations). Simultaneously, the HBM controller generates a local eigenvalue stream based on the received concurrent memory access data stream. During this process, the HBM controller calls the hard-coded mirror-synchronous orthogonal basis projection matrix in its internal read-only registers and performs dimension reduction matrix operations identical to those at the transmitting end using a symmetric hardware multiplier-accumulator array. To compensate for the transmission delay difference between the main data bus and the dedicated eigenvalue line, the system injects a pre-calculated buffer compensation depth into the serialization extraction logic, generating a local eigenvalue stream that is strictly aligned with the received algebraic eigenvalue stream on the clock cycle.

[0056] Next, in the double-buffered parity pipeline, the on-chip logic comparison tree of the HBM controller performs hardware-level parallel feature value comparison between the algebraic feature value stream and the local feature value stream. Assume that during a certain synchronization cycle, a bit on physical channel 128 flips due to transient electromagnetic interference on the bus.

[0057] At this point, the verification results are inconsistent. The system immediately uses the principle of matrix orthogonality to solve the eigenvalue deviation and locate the data channel where the error occurred. Specifically, the hardware subtractor array performs differential calculation on the two eigenvalue streams to obtain the eigenvalue deviation vector. Then, this eigenvalue deviation vector is matched with all column vectors of the internally preloaded orthogonal basis projection matrix in a parallel inner product matching operation in the hardware multiply-add tree. Due to the quasi-orthogonality of the matrix, the eigenvalue deviation vector generates a significant inner product peak in the column vector direction corresponding to channel 128, and this peak passes the judgment of the adaptive amplitude discrimination formula and the preset rejection condition. The system extracts the spatial permutation index of the target column vector, decodes it through a hardware mapping table, and directly outputs the fault location as the physical link of bus 128 (i.e., locates the data channel where the error occurred).

[0058] Finally, the HBM controller outputs the location result of the data channel (topology coordinates of channel 128) to the retransmission control engine. The transaction status tracing logic module within the retransmission control engine, combined with the time compensation formula, reverse-matches the damaged cross-core bus transaction identifier in the suspended transaction queue and cleans the contaminated local cache. Subsequently, the rollback signaling generator sends a transaction retry instruction containing the transaction identifier and the corresponding data channel coordinates to the NPU core computing cluster via a separate on-chip control link. The retransmission control engine triggers a transaction retry operation on the corresponding bus physical link based on the location result, and the interconnect error recovery module performs recovery according to the retry or link degradation granularity allowed by the target interconnect protocol, thereby completing data synchronization consistency verification and error recovery.

[0059] As a slave computing unit, the HBM controller's hardware interface layer incorporates transaction status tracking and sideband error response logic compliant with on-chip bus protocols (such as AXI or CXL). When the HBM controller detects a checksum inconsistency at the hardware layer, the retransmission control engine of the HBM controller interface layer sends a retry request containing the target transaction identifier to the NPU via an independent sideband control link. It also cleans the corrupted receive buffer in the interface layer that has not been written to disk, and the master NPU re-initiates the data transmission of the transaction. This mechanism fully utilizes the bus control capabilities of the HBM controller interface layer, ensuring absolute consistency of storage access data in high-concurrency write scenarios.

[0060] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for verifying the consistency of data synchronization at an AI computing chip interface, characterized in that, include: The main control computing unit receives concurrent memory access data streams at the hardware layer, divides the concurrent memory access data streams into blocks using a sliding window mechanism, and performs dimensionality reduction calculations on the data within each sliding window based on a lightweight algebraic mapping algorithm to generate corresponding algebraic feature value streams. The concurrent memory access data stream and the algebraic eigenvalue stream are synchronously transmitted to the subordinate computing unit; At the hardware layer of the subordinate computing unit, the received algebraic feature value stream is used as the comparison input and fed into the double-buffered verification pipeline, and a local feature value stream is generated based on the concurrent memory access data stream received by the subordinate computing unit. In the double-buffered verification pipeline, hardware-level parallel feature value comparison is performed between the algebraic feature value stream and the local feature value stream. When the verification is inconsistent, the principle of matrix orthogonality is used to solve the eigenvalue deviation and locate the data channel where the error occurred. The method utilizes the principle of matrix orthogonality to calculate eigenvalue deviations and locate the data channel where errors occur. This includes: inputting the algebraic eigenvalue streams and the local eigenvalue streams from the double-buffered verification pipeline that are inconsistent to the hardware subtractor array of the subordinate computing unit for difference calculation to obtain a eigenvalue deviation vector; synchronously inputting the eigenvalue deviation vector and all column vectors of the orthogonal basis projection matrix preloaded in the internal register into the hardware multiply-accumulate tree logic to perform hardware-level parallel inner product matching operations; inputting the inner product matching results of all column vectors into a hardware comparison tree network to filter out the target column vector exhibiting the largest response peak as a candidate error direction; extracting the spatial arrangement index of the target column vector in the orthogonal basis projection matrix, decoding the spatial arrangement index into the corresponding underlying hardware topology coordinates through a hardware mapping table, and outputting the bus physical link pointed to by the underlying hardware topology coordinates as the data channel where the error occurred; the eigendimensionality of the orthogonal basis projection matrix is ​​less than the total number of parallel channels. The positioning results of the data channel are output to the retransmission control engine, which then triggers the data retransmission operation of the corresponding data channel based on the positioning results to complete the data synchronization consistency verification.

2. The AI ​​computing chip interface data synchronization consistency verification method according to claim 1, characterized in that, The concurrent memory access data stream includes a time-stamped cross-core bus transaction identifier, physical memory access address, read / write control signals, and tensor data payload; a lightweight algebraic mapping algorithm is used to perform dimensionality reduction calculations on the data within each sliding window to generate the corresponding algebraic feature value stream, including: The tensor data load within each sliding window is reconstructed into a source data matrix according to the bus clock cycle using a hardware bus parser. The number of rows in the source data matrix corresponds to the total number of parallel channels in the bus physical link, and the number of columns corresponds to the total number of bus clock cycles contained in the sliding window. A preloaded orthogonal basis projection matrix is ​​extracted from the internal register of the main control computing unit, wherein the feature dimension of the orthogonal basis projection matrix is ​​less than the total number of parallel channels. The source data matrix and the orthogonal basis projection matrix are input to the hardware multiplier-adder array of the main control computing unit for hardware-level matrix multiplication, and a dimension-reduced feature matrix is ​​output. The dimension-reduced feature matrix is ​​then serialized and extracted column by column according to the bus clock cycle to generate the algebraic feature value stream that is sent synchronously with the concurrent memory access data stream.

3. The method for verifying the consistency of AI computing chip interface data synchronization according to claim 2, characterized in that, The construction of the orthogonal basis projection matrix specifically includes: the orthogonal basis projection matrix is ​​composed of a set of column vectors, wherein the total number of column vectors is equal to the total number of parallel channels of the bus physical link, and the spatial arrangement index of each column vector in the register is uniquely mapped to a bus physical link.

4. The AI ​​computing chip interface data synchronization consistency verification method according to claim 1, characterized in that, The double-buffered verification pipeline includes: a first cache array and a second cache array controlled by a hardware read / write state machine; during the current bus synchronization cycle, the hardware read / write state machine controls the first cache array to be in a write latch state, writing the received algebraic feature value stream and the generated local feature value stream in parallel; simultaneously, it controls the second cache array to be in a read comparison state, outputting the feature values ​​latched in the previous bus synchronization cycle to the on-chip logic comparison tree to perform the hardware-level parallel feature value comparison; during the next bus synchronization cycle, the hardware read / write state machine triggers a flag bit to alternately toggles, switching the read / write states of the first cache array and the second cache array, realizing clock-free pipeline overlap operation for feature value read / write and comparison.

5. The method for verifying the consistency of AI computing chip interface data synchronization according to claim 1, characterized in that, The retransmission control engine triggers a transaction retry operation on the corresponding bus physical link based on the positioning result, including: the retransmission control engine has a built-in transaction status tracing logic module and a rollback signaling generator; through the transaction status tracing logic module, based on the received underlying hardware topology coordinates and the bus clock tick where the mismatch occurs, the target cross-core bus transaction identifier where data corruption occurred is reverse-matched in the suspended transaction queue of the subordinate computing unit; a hardware-level cache cleaning mechanism is triggered to remove the received tensor data payload corresponding to the target cross-core bus transaction identifier from the subordinate computing unit. The data is erased from the receive buffer of the unit and the corresponding physical memory access address space is released simultaneously. The rollback signaling generator generates a transaction retry instruction containing the target cross-core bus transaction identifier and the underlying hardware topology coordinates. The transaction retry instruction is fed back to the main control computing unit via an on-chip control link independent of the data bus, forcing the main control computing unit to retrieve the original data from the internal storage queue based on the target cross-core bus transaction identifier, and initiate a transaction retry operation based on the located bus physical link, according to the retry granularity allowed by the target interconnect protocol.

6. The method for verifying the consistency of AI computing chip interface data synchronization according to claim 1, characterized in that, Generating a local feature stream based on the concurrent memory access data stream received by the subordinate computing unit specifically includes: reconstructing the tensor data payload in the received concurrent memory access data stream into a target data matrix according to the bus clock cycle; calling the preset mirror-synchronous orthogonal basis projection matrix in the internal register of the subordinate computing unit, and inputting the mirror-synchronous orthogonal basis projection matrix and the target data matrix into the symmetric hardware multiplier-adder array of the subordinate computing unit to perform hardware-level matrix multiplication operations; and extracting the matrix output by the operation column by column according to the bus clock cycle to generate the local feature stream that is strictly aligned with the received algebraic feature stream on the clock cycle.

Images