Adaptive compressed address mapping method and device for frequency converter

Abstract

The application discloses an adaptive compression address mapping method and device of a frequency converter, and relates to the field of address mapping.The method comprises the following steps: acquiring parameters to be mapped and address information of the parameters to be mapped, encoding parameter segments with continuous addresses into compression mapping items, and encoding discrete parameters into single mapping items; counting access frequencies of the mapping items in a preset period, and configuring data refresh periods for the mapping items according to the access frequencies; calculating a predicted bus load rate; if the predicted bus load rate exceeds a preset safety threshold, merging and updating the mapping items in a dynamic mapping window according to address gaps between adjacent items of the mapping items, and recalculating the predicted bus load rate until the predicted bus load rate does not exceed the preset safety threshold; and updating parameter values of the mapping items to a communication register interface according to the updated dynamic mapping window and the data refresh periods.The technical scheme provided by the application can solve the problem of a small number of parameter mappings.

Description

Technical Field

[0001] This application relates to the field of address mapping, specifically to an adaptive compressed address mapping method and apparatus for frequency converters. Background Technology

[0002] Frequency converters are widely used in industrial automation. To achieve centralized monitoring and data acquisition, programmable logic controllers (PLCs) typically read the internal parameters of the frequency converter periodically via a communication bus. Since the register resources that the communication bus can carry are limited, the frequency converter needs to map its internal parameters to the communication register interface for access by the PLC.

[0003] Currently, inverters typically use a method of assigning fixed register addresses to each parameter during parameter mapping. However, this method is limited by the number of registers and the communication protocol frame structure, resulting in a very limited number of parameters that can be mapped at a time. When users need to monitor multiple inverter operating parameters simultaneously, they often need to poll in batches or reduce the range of monitored parameters. This is cumbersome and cannot meet the needs of concurrent monitoring of multiple parameters. In other words, there is a problem of a limited number of parameter mappings under the constraints of limited register resources and communication bandwidth.

[0004] Therefore, there is an urgent need for an adaptive compressed address mapping method and device for frequency converters. Summary of the Invention

[0005] This application provides an adaptive compressed address mapping method and apparatus for frequency converters, which solves the problem of a small number of parameter mappings under the constraints of limited register resources and communication bandwidth.

[0006] This application provides an adaptive compressed address mapping method for a frequency converter in its first aspect. The method includes: acquiring parameters to be mapped and their address information; sorting the parameters to be mapped according to the address information; encoding consecutively addressed parameter segments into compressed mapping items and discrete parameters into single mapping items; constructing a dynamic mapping window from the compressed mapping items and the single mapping items; statistically analyzing the access frequency of each mapping item within a preset period and configuring a data refresh period for each mapping item according to the access frequency; calculating a predicted bus load rate based on the data frame length, data refresh period, and baud rate of the communication bus for each mapping item; if the predicted bus load rate exceeds a preset safety threshold, merging and updating the mapping items in the dynamic mapping window according to the address gap between adjacent items of each mapping item, and recalculating the predicted bus load rate until the predicted bus load rate does not exceed the preset safety threshold; and updating the parameter values ​​of each mapping item to the communication register interface according to the updated dynamic mapping window and the data refresh period.

[0007] By adopting the above technical solution, the parameter segments with consecutive addresses are encoded into compressed mapping entries, so that a single mapping entry can carry the address information of multiple consecutive parameters. This breaks through the limitation of the number of registers on the number of mappable parameters at the mapping mechanism level, and greatly increases the scale of parameters that can be mapped in a single configuration. At the same time, the data refresh cycle is configured differently according to the access frequency of each mapping entry, so that high-frequency access parameters can obtain faster response speed and low-frequency parameters can reduce bus occupation. Combined with the closed-loop adjustment mechanism of predicting bus load rate and adaptive merging update, the risk of bus timeout is actively suppressed when the number of mapped parameters increases.

[0008] Optionally, the predicted bus load rate is calculated based on the data frame length, data refresh cycle, and baud rate of each mapping item. Specifically, this includes: calculating the total data frame length required for a single refresh of each mapping item based on the parameter data volume corresponding to each mapping item and the length of the data frame encapsulation overhead field specified by the communication protocol; calculating the total data frame transmission time of all mapping items per unit time based on the total data frame length of each mapping item and its corresponding data refresh cycle; determining the available transmission time of the communication bus based on the baud rate of the communication bus; and using the ratio of the total data frame transmission time to the available transmission time as the predicted bus load rate.

[0009] By adopting the above technical solution, when calculating the predicted bus load rate, the length of the data frame encapsulation overhead field specified by the communication protocol is introduced. The fixed overhead of the protocol layer is included in the calculation of the total length of the data frame required for a single refresh, making the load rate prediction closer to the actual bus occupancy. This avoids the problem of underestimating the load rate due to ignoring the encapsulation overhead, which in turn leads to untimely optimization. It improves the accuracy of load prediction and the reliability of adaptive optimization triggering.

[0010] Optionally, the mapping items in the dynamic mapping window are merged and updated according to the address gap between adjacent items. Specifically, this includes: obtaining the address gap between the end address of an adjacent mapping item and the start address of the next mapping item in the dynamic mapping window; merging adjacent mapping items with address gaps less than a preset merging threshold into a new compressed mapping item; if there are addresses not occupied by the original parameters within the merged address range, inserting placeholder parameters at the addresses not occupied by the original parameters, and using the greatest common divisor of the address steps of each original mapping item within the merged address range as the unified address step to form the updated compressed mapping item. The placeholder parameters do not participate in the access frequency statistics and are set to a preset null value during bus transmission.

[0011] By adopting the above technical solution, when merging adjacent mapping items, by inserting placeholder parameters at the address gaps and using the greatest common divisor of the address steps of each original mapping item as the unified address step, the merged address range forms a regular continuous parameter structure. The parameter data of the entire address range can be read completely in one bus interaction, avoiding the additional bus overhead caused by splitting into multiple communication interactions due to address discontinuity, and maximizing the effect of merging operation on reducing bus load rate.

[0012] Optionally, after calculating the access frequency of each mapping item within a preset statistical period, the method further includes: obtaining the parameter value change frequency of each parameter in the compressed mapping item within the preset statistical period; calculating the ratio of the maximum to the minimum value among the parameter value change frequencies; when the ratio exceeds a preset splitting threshold, splitting the compressed mapping item into multiple single mapping items; dynamically establishing priority groups of corresponding levels according to the access frequency of each single mapping item, and configuring corresponding data refresh periods for each priority group.

[0013] By adopting the above technical solution, when the frequency of value changes of each parameter within a compression mapping item varies greatly, it is split into multiple single mapping items and each is assigned to a different priority group to configure the refresh cycle differently. This allows parameters that change frequently to receive a higher refresh frequency, while parameters that change slowly are refreshed at a lower frequency. This avoids the bandwidth waste caused by uniformly refreshing the entire compression mapping item at a high frequency, and further reduces bus occupancy while maintaining the timeliness of monitoring information.

[0014] Optionally, after configuring the data refresh cycle for each mapping item according to the access frequency, the method further includes: monitoring the change in the number of mapping items in the current data refresh queue; when the number of mapping items increases, calculating the total communication time required for all mapping items in the data refresh queue to perform a complete refresh; dividing the total communication time by the current data refresh cycle to obtain the communication cycle percentage; if the communication cycle percentage exceeds the preset percentage upper limit, then proportionally extending the data refresh cycle of all mapping items in the data refresh queue until the communication cycle percentage drops to within the preset percentage upper limit.

[0015] By adopting the above technical solution, when the number of mapping items increases, the ratio of the total communication time required for all mapping items in the current data refresh queue to complete the refresh to the current refresh cycle is calculated. When the proportion of communication cycle exceeds the upper limit, the data refresh cycle of all mapping items is extended proportionally. This proactive adjustment prevents the bus load from gradually accumulating to the limit as the number of mapping items increases, ensuring a smooth transition of communication stability when the mapping scale expands.

[0016] Optionally, the predicted bus load rate is calculated, specifically including: obtaining the data frame length required for a single refresh of each mapping item in the dynamic mapping window; taking the least common multiple of the data refresh cycles of each mapping item as the complete refresh cycle, simulating the superimposed distribution of refresh events of each mapping item on the time axis within the complete refresh cycle according to the data frame length of each mapping item and its corresponding data refresh cycle; calculating the peak value of the bus occupancy rate based on the superimposed distribution, and using the peak value as the predicted bus load rate.

[0017] By adopting the above technical solution, the least common multiple of the refresh cycles of each mapping item is used as the complete refresh cycle for time axis superposition simulation, and the peak value of bus occupancy is used as the predicted bus load rate. Compared with only calculating the average load rate, it can capture the instantaneous superposition congestion caused by the cycle difference of each mapping item refresh event, thereby more accurately identifying the risk of communication timeout and providing a more reliable triggering basis for adaptive optimization.

[0018] Optionally, when multiple programmable logic controllers (PLCs) simultaneously act as master stations accessing the communication register interface, the predicted bus load rate is calculated. Specifically, this includes: obtaining the timing characteristics of the access requests from each PLC; superimposing the access requests onto a preset load model to calculate the predicted bus load rate under a multi-master concurrent scenario; if the predicted bus load rate under a multi-master concurrent scenario exceeds a preset safety threshold, the predicted bus load rate is reported to the master station controller of the communication bus, and a polling cycle reconfiguration instruction is received from the master station controller; and the data refresh cycle of each mapping item is updated according to the polling cycle reconfiguration instruction.

[0019] By adopting the above technical solution, in the scenario of concurrent access by multiple programmable logic controllers, the timing characteristics of access requests from each master station are superimposed on the load calculation, and the data refresh cycle of each mapping item is updated by receiving the polling cycle reconfiguration instruction issued by the master station controller. This enables the frequency converter to cooperate with the global scheduling strategy of the master station to complete load balancing, avoids scheduling conflicts that may be caused by each master station independently adjusting its own polling parameters, and improves the overall communication efficiency and stability of the multi-master station system.

[0020] In a second aspect, this application provides an adaptive compressed address mapping device for a frequency converter, the device including an acquisition unit and a processing unit;

[0021] The acquisition unit is used to acquire the parameters to be mapped and their address information, sort the parameters to be mapped according to the address information, encode the parameter segments with continuous addresses into compressed mapping items, encode the discrete parameters into single mapping items, and construct a dynamic mapping window from the compressed mapping items and the single mapping items.

[0022] The processing unit is used to count the access frequency of each mapping item within a preset period and configure the data refresh period for each mapping item according to the access frequency; it is also used to calculate the predicted bus load rate according to the data frame length, data refresh period and baud rate of each mapping item and the communication bus; if the predicted bus load rate exceeds the preset safety threshold, it is also used to merge and update the mapping items in the dynamic mapping window according to the address gap between adjacent items of each mapping item and recalculate the predicted bus load rate until the predicted bus load rate does not exceed the preset safety threshold; it is also used to update the parameter values ​​of each mapping item to the communication register interface according to the updated dynamic mapping window and data refresh period.

[0023] Optionally, the processing unit is used to calculate the total length of the data frame required for a single refresh of each mapping item based on the parameter data volume corresponding to each mapping item and the length of the data frame encapsulation overhead field specified by the communication protocol; calculate the total data frame transmission time of all mapping items per unit time based on the total data frame length of each mapping item and its corresponding data refresh cycle; determine the available transmission time of the communication bus based on the baud rate of the communication bus; and use the ratio of the total data frame transmission time to the available transmission time as the predicted bus load rate.

[0024] Optionally, the acquisition unit is used to acquire the address gap between the end address of an adjacent mapping item and the start address of the next mapping item in the dynamic mapping window, and merge adjacent mapping items with address gaps less than a preset merging threshold into a new compressed mapping item. The processing unit is used to insert placeholder parameters at addresses not occupied by original parameters within the merged address range if such addresses exist. The greatest common divisor of the address steps of each original mapping item within the merged address range is used as the unified address step to form an updated compressed mapping item. The placeholder parameters do not participate in the access frequency statistics and are set to a preset null value during bus transmission.

[0025] Optionally, the acquisition unit is used to acquire the frequency of parameter value changes of each parameter in the compression mapping item within a preset statistical period; the processing unit is used to calculate the ratio of the maximum value to the minimum value among the frequency of parameter value changes, and when the ratio exceeds the preset splitting threshold, the compression mapping item is split into multiple single mapping items; according to the access frequency of each single mapping item, priority groups of corresponding levels are dynamically established, and corresponding data refresh cycles are configured for each priority group.

[0026] Optionally, the processing unit is used to monitor the change in the number of mapping items in the current data refresh queue; when the number of mapping items increases, it calculates the total communication time required for all mapping items in the data refresh queue to perform a complete refresh; it divides the total communication time by the current data refresh cycle to obtain the communication cycle ratio; if the communication cycle ratio exceeds the preset ratio upper limit, it extends the data refresh cycle of all mapping items in the data refresh queue proportionally until the communication cycle ratio drops to within the preset ratio upper limit.

[0027] Optionally, the acquisition unit is used to acquire the data frame length required for a single refresh of each mapping item in the dynamic mapping window; the processing unit is used to take the least common multiple of the data refresh cycles of each mapping item as the complete refresh cycle, and simulate the superimposed distribution of refresh events of each mapping item on the time axis within the complete refresh cycle according to the data frame length of each mapping item and its corresponding data refresh cycle; calculate the peak value of the bus occupancy rate according to the superimposed distribution, and use the peak value as the predicted bus load rate.

[0028] Optionally, the acquisition unit is used to acquire the timing characteristics of the access requests of each programmable logic controller; the processing unit is used to superimpose the access requests onto a preset load model and calculate the predicted bus load rate in a multi-master concurrent scenario; if the predicted bus load rate in a multi-master concurrent scenario exceeds a preset safety threshold, the predicted bus load rate is reported to the master controller of the communication bus, and the polling cycle reconfiguration instruction issued by the master controller is received; according to the polling cycle reconfiguration instruction, the data refresh cycle of each mapping item is updated.

[0029] This application provides an electronic device in a third aspect, including a processor, a memory, a user interface, and a network interface. The memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform the first aspect or any possible implementation of the first aspect.

[0030] In a fourth aspect, this application provides a computer-readable storage medium storing a computer program, which is executed by a processor as described in the first aspect or any possible implementation thereof.

[0031] In summary, one or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: 1. Encoding contiguous parameter segments into compressed mapping entries allows a single mapping entry to carry the address information of multiple contiguous parameters. This breaks through the limitation of the number of registers on the number of mappable parameters at the mapping mechanism level, significantly increasing the scale of mappable parameters in a single configuration. At the same time, the data refresh cycle is configured differently according to the access frequency of each mapping entry, enabling high-frequency access parameters to obtain faster response speeds and low-frequency parameters to reduce bus occupancy. Combined with a closed-loop adjustment mechanism of predicting bus load rate and adaptive merging update, the risk of bus timeout is actively suppressed when the number of mapped parameters increases.

[0032] 2. When the frequency of change of the values ​​of the parameters within a compression mapping item varies greatly, it is split into multiple single mapping items and each is assigned to a different priority group to configure the refresh cycle differently. This allows parameters that change frequently to receive a higher refresh frequency, while parameters that change slowly are refreshed at a lower frequency. This avoids the bandwidth waste caused by uniformly refreshing the entire compression mapping item at a high frequency, and further reduces bus occupancy while maintaining the timeliness of monitoring information.

[0033] 3. When the number of mapping items increases, the ratio of the total communication time required to perform a complete refresh of all mapping items in the current data refresh queue to the current refresh cycle is calculated. When the proportion of communication cycles exceeds the upper limit, the data refresh cycle of all mapping items is extended proportionally. This proactive adjustment prevents the bus load from gradually accumulating to the limit as the number of mapping items increases, ensuring a smooth transition of communication stability when the mapping scale expands. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating an adaptive compressed address mapping method for a frequency converter provided in an embodiment of this application.

[0035] Figure 2 This is a schematic diagram of the structure of an adaptive compression address mapping device for a frequency converter provided in an embodiment of this application.

[0036] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0037] Explanation of reference numerals in the attached drawings: 201, acquisition unit; 202, processing unit; 300, electronic device; 301, processor; 302, communication bus; 303, user interface; 304, network interface; 305, memory. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0039] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0040] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0041] When performing parameter mapping, frequency converters typically use a method of assigning fixed register addresses to each parameter. However, due to limitations in the number of registers and the communication protocol frame structure, the number of parameters that can be mapped at a time is extremely limited. When users need to monitor multiple frequency converter operating parameters simultaneously, they often need to poll in batches or reduce the range of monitored parameters. This operation is cumbersome and cannot meet the needs of concurrent monitoring of multiple parameters. In other words, there is a problem of a limited number of parameter mappings under the constraints of limited register resources and communication bandwidth. Therefore, this embodiment provides an adaptive compressed address mapping method and apparatus for frequency converters.

[0042] The adaptive compression address mapping method for frequency converters provided in this application can be referenced. Figure 1 , Figure 1 This is a flowchart illustrating an adaptive compressed address mapping method for a frequency converter, provided in an embodiment of this application, and applied to a frequency converter. The method includes steps S101 to S105.

[0043] S101. Obtain the parameters to be mapped and their address information. Sort the parameters to be mapped according to the address information. Encode the parameter segments with continuous addresses into compressed mapping items and the discrete parameters into single mapping items. Construct a dynamic mapping window from the compressed mapping items and the single mapping items.

[0044] In the above steps, the inverter first obtains the list of parameters to be mapped selected by the user through the operation panel or host computer software, as well as the address information of each parameter in the inverter's internal parameter address space. The inverter sorts the parameters to be mapped in ascending order of address. After sorting, the inverter traverses the sorted list and checks whether the addresses of adjacent parameters are continuous. Address continuity means that the difference in memory address between adjacent parameters equals the number of address units occupied by the parameter's data type. For example, in a certain model of inverter, parameter A has an address of 0x0100, occupying 2 address units, and parameter B has an address of 0x0102; therefore, parameter A and parameter B are continuous. For multiple parameters that meet the continuity condition and have the same step size, the inverter encodes them into a compressed mapping item, which records three fields: starting address, number of parameters, and address step size. For discrete parameters that do not meet the continuity condition, the inverter encodes them separately into a single mapping item, recording their parameter address. All compressed mapping items and single mapping items together constitute a dynamic mapping window, which is a data structure table stored in the inverter's memory.

[0045] S102. Calculate the access frequency of each mapping item within the preset period, and configure the data refresh period for each mapping item according to the access frequency.

[0046] In the above steps, the inverter continuously monitors the data interaction on the communication bus during operation and counts the number of times the programmable logic controller (PLC) accesses each mapping item within a preset period. The preset period can be set according to the actual application scenario, such as 100 communication cycles or 1 second. For each mapping item, the inverter maintains an access counter. Whenever the PLC initiates a read request for the register address corresponding to the mapping item, the corresponding counter is incremented by one. At the end of the preset period, the inverter reads the count value of each mapping item as the access frequency, and then resets the counter to zero to enter the next statistical period. Based on the statistically obtained access frequency, the inverter configures a data refresh period for each mapping item. Mapping items with higher access frequencies are assigned shorter data refresh periods, and mapping items with lower access frequencies are assigned longer data refresh periods. The configuration relationship can adopt a linear mapping, such as directly normalizing the access frequency and mapping it to a value between the preset minimum and maximum refresh periods; or it can adopt a segmented mapping, such as configuring a 10ms refresh period for the top 20% of mapping items by access frequency, 50ms for the middle 60%, and 200ms for the bottom 20%.

[0047] In one possible implementation, after calculating the access frequency of each mapping item within a preset period, the method further includes: obtaining the parameter value change frequency of each parameter in the compressed mapping item within the preset statistical period; calculating the ratio of the maximum to the minimum value among the parameter value change frequencies; when the ratio exceeds a preset splitting threshold, splitting the compressed mapping item into multiple single mapping items; dynamically establishing priority groups of corresponding levels according to the access frequency of each single mapping item, and configuring corresponding data refresh periods for each priority group.

[0048] Specifically, the frequency converter monitors the frequency of parameter value changes for each parameter within each compression mapping item in the dynamic mapping window. The frequency converter records the number of times each parameter value changes within the same compression mapping item within a preset statistical period, obtaining the parameter value change frequency for each parameter. Then, the frequency converter calculates the ratio of the maximum to the minimum value among all parameter value change frequencies within that compression mapping item. For example, if a compression mapping item covers four parameters, and the parameter value change frequencies within the statistical period are 50, 48, 5, and 3 times respectively, with a maximum value of 50 and a minimum value of 3, the ratio is approximately 16.7. The preset splitting threshold can be set empirically, for example, to 10. When the ratio exceeds the preset splitting threshold, it indicates a significant difference in the dynamic characteristics of the parameters within that compression mapping item. The frequency converter then splits the compression mapping item into multiple single mapping items, each single mapping item corresponding to one parameter in the original compression mapping item. After splitting, the frequency converter dynamically establishes priority groups of corresponding levels based on the access frequency of each single mapping item, such as high, medium and low levels, and configures the corresponding data refresh cycle for each priority group, so that parameters that change frequently get shorter refresh cycles and parameters that change slowly get longer refresh cycles.

[0049] In one possible implementation, after configuring the data refresh cycle for each mapping item according to the access frequency, the method further includes: monitoring the change in the number of mapping items in the current data refresh queue; when the number of mapping items increases, calculating the total communication time required for all mapping items in the data refresh queue to perform a complete refresh; dividing the total communication time by the current data refresh cycle to obtain the communication cycle percentage; if the communication cycle percentage exceeds the preset percentage upper limit, then proportionally extending the data refresh cycle of all mapping items in the data refresh queue until the communication cycle percentage drops to within the preset percentage upper limit.

[0050] Specifically, the inverter maintains a data refresh queue, which records all mapping items requiring refresh in the current dynamic mapping window and their data refresh cycles. The inverter monitors the number of mapping items in the data refresh queue in real time. When a user adds a parameter to be mapped or a merging operation reduces the number of mapping items, the number of mapping items in the data refresh queue changes accordingly. When the number of mapping items increases, the inverter calculates the total communication time required for all mapping items in the data refresh queue to perform a complete refresh, which is the sum of the data frame transmission times for each mapping item's single refresh. The inverter divides this total communication time by the shortest data refresh cycle in the data refresh queue to obtain the communication cycle percentage. For example, if the data refresh cycles of three mapping items in the data refresh queue are 10ms, 20ms, and 50ms respectively, and the shortest refresh cycle is 10ms, the communication cycle percentage is calculated based on 10ms. If the communication cycle percentage exceeds a preset percentage limit, such as exceeding 80%, the inverter proportionally extends the data refresh cycle of all mapping items in the data refresh queue, for example, by multiplying it by a coefficient of 1.2, and then recalculates the communication cycle percentage. This process is repeated until the communication cycle percentage drops below the preset percentage limit.

[0051] S103. Calculate the predicted bus load rate based on the data frame length, data refresh cycle, and baud rate of each mapping item.

[0052] In the above steps, for each mapping item in the dynamic mapping window, the inverter calculates the data frame length (in bits or bytes) required for a single refresh of that mapping item based on its corresponding parameter data volume and the fixed overhead inherent in the communication protocol frame structure, such as the frame header, frame trailer, and checksum field. Based on the data refresh cycle of each mapping item, the inverter calculates the total amount of data that all mapping items need to transmit per unit time. For example, if a communication bus baud rate is 115200bps, and there are 5 mapping items in the dynamic mapping window, with data frame lengths of 80 bits, 80 bits, 160 bits, 80 bits, and 160 bits per refresh, and refresh cycles of 20ms, 20ms, 50ms, 100ms, and 100ms respectively, the inverter calculates and sums the data transmission volume of each mapping item per unit time. Dividing the sum by the available transmission volume per unit time corresponding to the baud rate, the resulting ratio is the predicted bus load rate.

[0053] In one possible implementation, the predicted bus load rate is calculated based on the data frame length of each mapping item, the data refresh cycle, and the baud rate of the communication bus. Specifically, this includes: calculating the total data frame length required for a single refresh of each mapping item based on the parameter data volume corresponding to each mapping item and the length of the data frame encapsulation overhead field specified by the communication protocol; calculating the total data frame transmission time of all mapping items per unit time based on the total data frame length of each mapping item and its corresponding data refresh cycle; determining the available transmission time of the communication bus based on the baud rate of the communication bus; and using the ratio of the total data frame transmission time to the available transmission time as the predicted bus load rate.

[0054] Specifically, when calculating the total length of the data frame required for a single refresh of each mapping item, the inverter considers not only the number of bytes of the parameter data itself, but also the length of the data frame encapsulation overhead field specified by the communication protocol. Taking the Modbus RTU protocol as an example, the data frame encapsulation overhead includes 1 byte for the address field, 1 byte for the function code, and 2 bytes for the CRC check, totaling 4 bytes. If a mapping item corresponds to 4 16-bit parameters, and the parameter data size is 8 bytes, then after adding the encapsulation overhead, the total length of the data frame for a single refresh of this mapping item is 12 bytes. Taking the CANopen protocol as an example, the data frame encapsulation overhead of a PDO message includes 2 bytes for COB-ID, 1 byte for the control field, etc. If a mapping item corresponds to 2 16-bit parameters, and the parameter data size is 4 bytes, then after adding the encapsulation overhead, the total length of the data frame is approximately 7 bytes. The inverter calculates the total data frame transmission time of all mapping items per unit time based on the total length of the data frame of each mapping item and its corresponding data refresh cycle, that is, the sum of the total length of the data frame of each mapping item divided by its data refresh cycle. The inverter determines the available transmission time per unit time based on the baud rate of the communication bus, and uses the ratio of the total data frame transmission time to the available transmission time as the predicted bus load rate.

[0055] In one possible implementation, calculating the predicted bus load rate specifically includes: obtaining the data frame length required for a single refresh of each mapping item in the dynamic mapping window; using the least common multiple of the data refresh cycles of each mapping item as the complete refresh cycle, simulating the superimposed distribution of refresh events of each mapping item on the time axis within the complete refresh cycle based on the data frame length of each mapping item and its corresponding data refresh cycle; calculating the peak value of the bus occupancy rate based on the superimposed distribution, and using the peak value as the predicted bus load rate.

[0056] Specifically, the inverter uses peak prediction to calculate the predicted bus load rate. First, the inverter obtains the data frame length required for a single refresh of each mapping item in the dynamic mapping window. Then, it calculates the least common multiple of the data refresh cycles of each mapping item, using this as the complete refresh cycle. For example, if the data refresh cycles of three mapping items are 10ms, 20ms, and 50ms, the complete refresh cycle is 100ms; or if the data refresh cycles of two mapping items are 15ms and 25ms, the complete refresh cycle is 75ms. On the time axis of the complete refresh cycle, the inverter simulates the refresh events of each mapping item, determines the data transmission time for each refresh based on the data frame length of each mapping item, and expands these refresh events on the time axis according to their respective cycles, obtaining the superimposed distribution of each refresh event on the time axis. The inverter scans the entire complete refresh cycle, counts the amount of superimposed data transmitted simultaneously at any given time, calculates the bus occupancy rate corresponding to the maximum superimposed data amount as the peak bus occupancy rate, and uses this peak value as the predicted bus load rate. Compared to the average load rate calculation method, peak prediction can capture the instantaneous superposition of congestion caused by the multiple relationship between the refresh cycles of each mapping item, and identify potential communication timeout risks in advance.

[0057] In one possible implementation, when multiple programmable logic controllers (PLCs) simultaneously act as master stations accessing the communication register interface, the predicted bus load rate is calculated. Specifically, this includes: acquiring the timing characteristics of the access requests from each PLC; superimposing the access requests onto a preset load model to calculate the predicted bus load rate under a multi-master concurrent scenario; if the predicted bus load rate under a multi-master concurrent scenario exceeds a preset safety threshold, then reporting the predicted bus load rate to the master station controller of the communication bus and receiving a polling cycle reconfiguration instruction from the master station controller; and updating the data refresh cycle of each mapping item according to the polling cycle reconfiguration instruction.

[0058] Specifically, when multiple programmable logic controllers (PLCs) in an industrial network simultaneously access the inverter's communication register interface via the same communication bus, the inverter needs to obtain the timing characteristics of each PLC's access requests during the calculation of the predicted bus load rate. These timing characteristics can be obtained by monitoring communication messages on the bus, including the polling cycle of each master and the length of the data frame for each poll. The inverter superimposes the access requests from each master into the load model for calculation; that is, it simultaneously superimposes the refresh events of each mapping item of the inverter and the polling access events of each master on the timeline of the complete refresh cycle to obtain the predicted bus load rate in a multi-master concurrent scenario. If the predicted bus load rate exceeds a preset safety threshold, the inverter reports the current predicted bus load rate value to the device acting as the master controller on the communication bus. After comprehensively analyzing the load status of all slaves on the bus, the master controller performs global scheduling optimization and issues polling cycle reconfiguration instructions to each PLC. The frequency converter receives the polling cycle reconfiguration command issued by the master station controller, and updates the data refresh cycle of each mapping item according to the parameters in the command, thereby realizing collaborative load balancing in multi-master station scenarios.

[0059] S104. If the predicted bus load rate exceeds the preset safety threshold, the mapping items in the dynamic mapping window are merged and updated according to the address gap between adjacent items of each mapping item, and the predicted bus load rate is recalculated until the predicted bus load rate does not exceed the preset safety threshold.

[0060] In the above steps, the inverter compares the calculated predicted bus load rate with a preset safety threshold. The preset safety threshold can be set according to the actual carrying capacity of the communication bus, typically set to 70% to 80%, to reserve a certain communication margin to cope with sudden transmission demands. If the predicted bus load rate exceeds the preset safety threshold, the inverter initiates a merging and updating process. The inverter obtains the arrangement information of each mapping item in the dynamic mapping window after sorting by address, calculates the address gap between the end address of an adjacent mapping item and the start address of the next mapping item, and merges adjacent mapping items with address gaps smaller than the preset merging threshold into a new compressed mapping item. After merging, the inverter recalculates the predicted bus load rate based on the merged and updated dynamic mapping window. If it still exceeds the preset safety threshold, the merging operation continues, forming an iterative closed loop, until the predicted bus load rate drops below the preset safety threshold. The preset merging threshold can be set according to actual conditions, for example, set to 5 address units.

[0061] In one possible implementation, the mapping items in the dynamic mapping window are merged and updated according to the address gap between adjacent items. Specifically, this includes: obtaining the address gap between the end address of an adjacent mapping item and the start address of the next mapping item in the dynamic mapping window; merging adjacent mapping items with address gaps less than a preset merging threshold into a new compressed mapping item; if there are addresses not occupied by the original parameters within the merged address range, inserting placeholder parameters at the addresses not occupied by the original parameters, and using the greatest common divisor of the address steps of each original mapping item within the merged address range as the unified address step to form the updated compressed mapping item. The placeholder parameters do not participate in the access frequency statistics and are set to a preset null value during bus transmission.

[0062] Specifically, during the merging and updating process, the inverter traverses adjacent mapping pairs sorted by address in the dynamic mapping window, calculates the difference between the end address of the previous mapping item and the start address of the next mapping item, and obtains the address gap. If the address gap is less than a preset merging threshold, the two mapping items are merged into a new compressed mapping item. After merging, if there are addresses within the address range that are not occupied by the original parameters due to the address gap, the inverter inserts placeholder parameters at these address positions. The values ​​of the placeholder parameters are set to preset null values ​​during bus transmission, such as all being set to zero. The programmable logic controller can identify the placeholder parameters as invalid data and discard them when parsing the data frame. In order to form a uniform address step size within the merged address range, the inverter calculates the greatest common divisor of the address step sizes of the original mapping items before merging and uses it as the uniform address step size. For example, if the address step sizes of the two original compressed mapping items are 4 and 6 respectively, and the greatest common divisor is 2, the merged compressed mapping item organizes the parameter sequence with a step size of 2, and the placeholder parameter insertion points also follow this step size. For example, the address steps of the original three mapping items are 2, 4, and 8 respectively, and their greatest common divisor is also 2. Using 2 as the unified address step size ensures compatibility with the address alignment of the original parameters. Placeholder parameters are not included in the access frequency statistics, and their data refresh cycle inherits the unified configuration of the merged compressed mapping items. Through this process, a single data frame read can cover the entire merged address range, eliminating the need for multiple communication interactions due to address discontinuities.

[0063] S105. Update the parameter values ​​of each mapping item to the communication register interface according to the updated dynamic mapping window and data refresh cycle.

[0064] In the above steps, once the predicted bus load rate drops below the preset safety threshold, the inverter, according to the final structure of the current dynamic mapping window and the data refresh cycle configured for each mapping item, reads the real-time parameter value of the corresponding mapping item from the inverter's internal parameter storage area at each refresh time and writes it to the corresponding register address in the communication register interface. The programmable logic controller (PLC) can obtain the inverter's real-time operating parameters by periodically reading the register values ​​in the communication register interface through the communication bus. For compressed mapping items, the inverter sequentially packages the parameter values ​​within the entire continuous address range into data frames for updating in a single refresh operation, reducing the number of communication interactions.

[0065] This application also provides an adaptive compression address mapping device for a frequency converter, referring to... Figure 2 The device is a frequency converter, which includes an acquisition unit 201 and a processing unit 202.

[0066] The acquisition unit 201 is used to acquire the parameters to be mapped and their address information, sort the parameters to be mapped according to the address information, encode the parameter segments with continuous addresses into compressed mapping items, encode the discrete parameters into single mapping items, and construct a dynamic mapping window from the compressed mapping items and the single mapping items.

[0067] The processing unit 202 is used to count the access frequency of each mapping item within a preset period and configure the data refresh period for each mapping item according to the access frequency; it is also used to calculate the predicted bus load rate according to the data frame length, data refresh period and baud rate of each mapping item and the communication bus; if the predicted bus load rate exceeds the preset safety threshold, it is also used to merge and update the mapping items in the dynamic mapping window according to the address gap between adjacent items of each mapping item and recalculate the predicted bus load rate until the predicted bus load rate does not exceed the preset safety threshold; it is also used to update the parameter values ​​of each mapping item to the communication register interface according to the updated dynamic mapping window and data refresh period.

[0068] In one possible implementation, the processing unit 202 is used to calculate the total length of the data frame required for a single refresh of each mapping item based on the parameter data volume corresponding to each mapping item and the length of the data frame encapsulation overhead field specified by the communication protocol; calculate the total data frame transmission time of all mapping items per unit time based on the total data frame length of each mapping item and its corresponding data refresh cycle; determine the available transmission time of the communication bus based on the baud rate of the communication bus; and use the ratio of the total data frame transmission time to the available transmission time as the predicted bus load rate.

[0069] In one possible implementation, the acquisition unit 201 is used to acquire the address gap between the end address of an adjacent mapping item and the start address of the next mapping item in the dynamic mapping window, and merge adjacent mapping items with address gaps less than a preset merging threshold into a new compressed mapping item. The processing unit 202 is used to insert a placeholder parameter at the address not occupied by the original parameter if there is an address not occupied by the original parameter in the merged address range, and use the greatest common divisor of the address steps of each original mapping item in the merged address range as the unified address step size to form an updated compressed mapping item. The placeholder parameter does not participate in the access frequency statistics and is set to a preset null value in bus transmission.

[0070] In one possible implementation, the acquisition unit 201 is used to acquire the frequency of parameter value changes of each parameter in the compression mapping item within a preset statistical period; the processing unit 202 is used to calculate the ratio of the maximum value to the minimum value among the frequency of parameter value changes, and when the ratio exceeds the preset splitting threshold, the compression mapping item is split into multiple single mapping items; according to the access frequency of each single mapping item, priority groups of corresponding levels are dynamically established, and corresponding data refresh cycles are configured for each priority group.

[0071] In one possible implementation, the processing unit 202 is used to monitor the change in the number of mapping items in the current data refresh queue; when the number of mapping items increases, it calculates the total communication time required for all mapping items in the data refresh queue to perform a complete refresh; it divides the total communication time by the current data refresh cycle to obtain the communication cycle ratio; if the communication cycle ratio exceeds the preset ratio upper limit, it extends the data refresh cycle of all mapping items in the data refresh queue proportionally until the communication cycle ratio drops to within the preset ratio upper limit.

[0072] In one possible implementation, the acquisition unit 201 is used to acquire the data frame length required for a single refresh of each mapping item in the dynamic mapping window; the processing unit 202 is used to take the least common multiple of the data refresh cycles of each mapping item as the complete refresh cycle, and simulate the superimposed distribution of refresh events of each mapping item on the time axis within the complete refresh cycle according to the data frame length of each mapping item and its corresponding data refresh cycle; calculate the peak value of the bus occupancy rate according to the superimposed distribution, and use the peak value as the predicted bus load rate.

[0073] In one possible implementation, the acquisition unit 201 is used to acquire the timing characteristics of the access requests of each programmable logic controller; the processing unit 202 is used to superimpose the access requests onto a preset load model and calculate the predicted bus load rate in a multi-master concurrent scenario; if the predicted bus load rate in a multi-master concurrent scenario exceeds a preset safety threshold, the predicted bus load rate is reported to the master controller of the communication bus, and the polling cycle reconfiguration instruction issued by the master controller is received; according to the polling cycle reconfiguration instruction, the data refresh cycle of each mapping item is updated.

[0074] It should be noted that the above embodiments of the apparatus are only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0075] This application also provides an electronic device. (See reference...) Figure 3 , Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 300 may include: at least one processor 301, at least one communication bus 302, at least one user interface 303, a network interface 304, and a memory 305.

[0076] The communication bus 302 is used to enable communication between these components.

[0077] The user interface 303 may include a display screen and a camera. Optionally, the user interface 303 may also include a standard wired interface and a wireless interface.

[0078] The network interface 304 may include standard wired interfaces and wireless interfaces (such as Wi-Fi interfaces).

[0079] The processor 301 may include one or more processing cores. The processor 301 connects to various parts of the server using various interfaces and lines, and performs various server functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory 305, and by calling data stored in memory 305. Optionally, the processor 301 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 301 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 301 and may be implemented as a separate chip.

[0080] The memory 305 may include random access memory (RAM) or read-only memory. Optionally, the memory 305 may include a non-transitory computer-readable storage medium. The memory 305 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 305 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. The memory 305 may also be at least one storage device located remotely from the aforementioned processor 301. (Refer to...) Figure 3 The memory 305, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program for an adaptive compression address mapping method for a frequency converter.

[0081] exist Figure 3In the illustrated electronic device 300, the user interface 303 is mainly used to provide an input interface for the user and to acquire user input data; while the processor 301 can be used to call an application program of an adaptive compression address mapping method for a frequency converter stored in the memory 305. When executed by one or more processors 301, the electronic device 300 performs one or more methods as described in the above embodiments. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] This application also provides a computer-readable storage medium storing instructions. When executed by one or more processors, these instructions cause an electronic device to perform one or more of the methods described in the above embodiments.

[0084] In the various embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0085] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0087] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0088] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure.

[0089] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope of this disclosure is defined by the claims.

Claims

1. An adaptive compressed address mapping method for a frequency converter, characterized in that, The method includes: Obtain the parameters to be mapped and their address information, sort the parameters to be mapped according to the address information, encode the parameter segments with continuous addresses into compressed mapping items, encode the discrete parameters into single mapping items, and construct a dynamic mapping window from the compressed mapping items and the single mapping items; The access frequency of each mapping item within a preset period is statistically analyzed, and a data refresh period is configured for each mapping item based on the access frequency. The predicted bus load rate is calculated based on the data frame length of each mapping item, the data refresh cycle, and the baud rate of the communication bus. If the predicted bus load rate exceeds the preset safety threshold, the mapping items in the dynamic mapping window are merged and updated according to the address gap between adjacent items of each mapping item, and the predicted bus load rate is recalculated until the predicted bus load rate does not exceed the preset safety threshold. Based on the updated dynamic mapping window and the data refresh cycle, the parameter values ​​of each mapping item are updated to the communication register interface.

2. The method according to claim 1, characterized in that, The step of calculating the predicted bus load rate based on the data frame length of each mapping item, the data refresh period, and the baud rate of the communication bus specifically includes: Based on the parameter data volume corresponding to each mapping item and the length of the data frame encapsulation overhead field specified by the communication protocol, calculate the total length of the data frame required for a single refresh of each mapping item; Based on the total length of the data frame of each mapping item and its corresponding data refresh cycle, calculate the total data frame transmission time of all mapping items per unit time. The available transmission time of the communication bus is determined based on the baud rate of the communication bus; The ratio of the total data frame transmission time to the available transmission time is used as the predicted bus load rate.

3. The method according to claim 1, characterized in that, The step of merging and updating the mapping items in the dynamic mapping window based on the address gap between adjacent items specifically includes: Obtain the address gap between the end address of an adjacent mapping item and the start address of the next mapping item in the dynamic mapping window, and merge adjacent mapping items with an address gap smaller than a preset merging threshold into a new compressed mapping item; If there are addresses not occupied by the original parameters within the merged address range, placeholder parameters are inserted at the addresses not occupied by the original parameters, and the greatest common divisor of the address steps of each original mapping item within the merged address range is used as the unified address step to form the updated compressed mapping item. The placeholder parameters do not participate in the statistics of the access frequency and are set to a preset null value during bus transmission.

4. The method according to claim 1, characterized in that, After calculating the access frequency of each mapping item within the preset statistical period, the method further includes: Obtain the frequency of parameter value changes for each parameter in the compression mapping item within the preset statistical period; Calculate the ratio of the maximum to the minimum value among the frequency of changes of each parameter value. When the ratio exceeds a preset splitting threshold, split the compressed mapping item into multiple single mapping items. Based on the access frequency of each single mapping item, priority groups of corresponding levels are dynamically established, and corresponding data refresh cycles are configured for each priority group.

5. The method according to claim 1, characterized in that, After configuring the data refresh cycle for each mapping item according to the access frequency, the method further includes: Monitor changes in the number of mapping items in the current data refresh queue; As the number of mapping items increases, calculate the total communication time required for all mapping items in the data refresh queue to perform a complete refresh; Divide the total communication time by the current data refresh cycle to obtain the communication cycle percentage; If the proportion of the communication cycle exceeds the preset upper limit, the data refresh cycle of all mapping items in the data refresh queue will be extended proportionally until the proportion of the communication cycle drops below the preset upper limit.

6. The method according to claim 1, characterized in that, The calculation and prediction of the bus load rate specifically includes: Obtain the data frame length required for a single refresh of each mapping item in the dynamic mapping window; Using the least common multiple of the data refresh cycles of each mapping item as the complete refresh cycle, and based on the data frame length of each mapping item and its corresponding data refresh cycle, the superposition distribution of refresh events of each mapping item on the time axis within the complete refresh cycle is simulated. The peak value of the bus occupancy rate is calculated based on the superimposed distribution, and the peak value is used as the predicted bus load rate.

7. The method according to claim 1, characterized in that, When multiple programmable logic controllers simultaneously access the communication register interface as master stations, the calculation and prediction of the bus load rate specifically includes: Obtain the timing characteristics of the access requests from each programmable logic controller; The access requests are superimposed onto a preset load model to calculate the predicted bus load rate in a multi-master concurrent scenario; If the predicted bus load rate in the multi-master concurrent scenario exceeds the preset safety threshold, the predicted bus load rate is reported to the master station controller of the communication bus, and the polling cycle reconfiguration instruction issued by the master station controller is received. The data refresh cycle of each mapping item is updated according to the polling cycle reconfiguration instruction.

8. An adaptive compression address mapping device for a frequency converter, characterized in that, The device includes an acquisition unit (201) and a processing unit (202): The acquisition unit (201) is used to acquire the parameters to be mapped and their address information, sort the parameters to be mapped according to the address information, encode the parameter segments with continuous addresses into compressed mapping items, encode the discrete parameters into single mapping items, and construct a dynamic mapping window from the compressed mapping items and the single mapping items. The processing unit (202) is used to count the access frequency of each mapping item within a preset period, and configure a data refresh period for each mapping item according to the access frequency; The processing unit (202) is also used to calculate the predicted bus load rate based on the data frame length of each mapping item, the data refresh cycle, and the baud rate of the communication bus; The processing unit (202) is further configured to, if the predicted bus load rate exceeds a preset safety threshold, merge and update the mapping items in the dynamic mapping window according to the address gap between adjacent items of each mapping item, and recalculate the predicted bus load rate until the predicted bus load rate does not exceed the preset safety threshold. The processing unit (202) is further configured to update the parameter values ​​of each mapping item to the communication register interface according to the updated dynamic mapping window and the data refresh cycle.

9. An electronic device, characterized in that, The device includes a processor (301), a memory (305), a user interface (303), and a network interface (304). The memory (305) is used to store instructions. The user interface (303) and the network interface (304) are used to communicate with other devices. The processor (301) is used to execute the instructions stored in the memory (305) to cause the electronic device (300) to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7 above.

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