An artificial intelligence chip processing system

Abstract

The application discloses an artificial intelligence chip processing system, comprising an analog impedance perception masking unit, an asynchronous event-driven hardware logic routing network, a cross-domain counter-pressure physical feedback loop and a streaming space-time data fusion and storage-computing integrated macro unit. The analog impedance perception masking unit converts heterogeneous data streams into physical currents and performs truncation or release by using a cutoff threshold current; the asynchronous event-driven hardware logic routing network encapsulates the release signal into an asynchronous data packet for single-hop transmission; the cross-domain counter-pressure physical feedback loop extracts the handshake time difference of the transmission node to generate a reverse bias voltage to dynamically adjust the cutoff threshold current; the streaming space-time data fusion and storage-computing integrated macro unit uses a time delay characteristic quantity decay characteristic reference voltage amplitude and injects an analog cross-multiplication array to perform in-memory computing. The application realizes adaptive negative feedback congestion control and physical fusion of space-time feature calculation weight in the underlying hardware physical domain.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence chip technology, and more specifically to an artificial intelligence chip processing system. Background Technology

[0002] Artificial intelligence (AI) chip processing systems are the hardware carriers that support deep learning and data fusion computing. With the development of multimodal sensing technology, AI chips need to process multi-source heterogeneous data streams from external sources. These data streams are characterized by high concurrency and spatiotemporal differences, which places demands on the chip's underlying data acquisition, on-chip network transmission, and the collaborative processing capabilities of its in-memory computing architecture.

[0003] In existing processing architectures, analog feature signals input from the external environment are typically all sent to an analog-to-digital converter (ADC) to be quantized into digital signals, and then injected into the on-chip digital network for routing, distribution, and multiplication-accumulation operations. This processing architecture relies on a global clock tree for data driving, transmits sampled data to the subsequent computing array through fixed digital logic channels, and depends on backend software algorithms or digital domain modules to identify feature validity and adjust computational weights.

[0004] However, existing processing mechanisms suffer from power redundancy and hardware resource overload. Because the front-end access layer lacks a physical-level sensing and interception structure for weak analog characteristics with amplitudes below a preset threshold, the data stream is fully digitized and injected into the chip, causing invalid logic level flips in subsequent digital circuits and resulting in redundant computational dynamic power consumption. Simultaneously, indiscriminate data injection easily leads to on-chip communication link congestion. Existing systems lack physical feedback circuits capable of dynamically throttling the front-end analog source, and the physical delay of the data caused by congestion cannot be directly mapped at the hardware level to attenuate the corresponding in-memory computation weights, making it difficult for the system to achieve adaptive allocation of physical resources. Summary of the Invention

[0005] To address the problems mentioned in the background, this invention provides an artificial intelligence chip processing system, comprising: an analog impedance sensing mask unit, an asynchronous event-driven hardware logic routing network, a streaming spatiotemporal data fusion and in-memory computing macro unit, and a cross-domain backpressure physical feedback loop.

[0006] It should be noted that the reverse bias voltage mentioned in this application does not refer to the reverse bias voltage of the PN junction of the semiconductor device or the substrate of the MOSFET, but rather to the feedback control voltage generated by the cross-domain reverse voltage physical feedback loop and used to reversely adjust the amplitude of the cutoff threshold current.

[0007] The analog impedance sensing mask unit is located on the input side of the artificial intelligence chip processing system, and its output is connected to an asynchronous pulse generator. The analog impedance sensing mask unit is used to receive multi-source heterogeneous data streams, convert the discrete feature vectors in the multi-source heterogeneous data streams into physical current signals, and use the cutoff threshold current to physically truncate or allow the physical current signals.

[0008] The asynchronous event-driven hardware logic routing network connects to the output of the asynchronous pulse generator. The asynchronous pulse generator quantizes the allowed physical current signal and encapsulates it into asynchronous data packets. The asynchronous event-driven hardware logic routing network contains multiple routing nodes, and asynchronous data packets are transmitted between these nodes according to a handshake protocol.

[0009] A cross-domain reverse voltage physical feedback loop connects the asynchronous event-driven hardware logic routing network and the analog impedance sensing mask unit. This loop extracts the handshake time difference between routing nodes, converts it into a reverse bias voltage, and inputs this reverse bias voltage to the analog impedance sensing mask unit to dynamically adjust the cutoff threshold current.

[0010] The streaming spatiotemporal data fusion and in-memory computing macrocell is connected to the output of the asynchronous event-driven hardware logic routing network. It is used to receive asynchronous data packets and time delay features, use the time delay features to perform amplitude attenuation operation on the feature reference voltage corresponding to the asynchronous data packets, and inject the attenuated modulation feature voltage into the internal analog cross-multiply-accumulate array to perform in-memory computing.

[0011] This invention achieves physical-level data truncation in the analog circuit domain through an analog impedance-sensing masking unit. Combined with an asynchronous event-driven hardware logic routing network, it establishes a clock-independent dynamic handshake communication link, blocking invalid data from causing logic level flips in subsequent digital circuits and reducing the overall dynamic power consumption of the system. A cross-domain reverse-pressure physical feedback loop extracts the congestion state of the asynchronous communication link and converts it into a reverse bias voltage. This reverse feedback adjusts the cutoff threshold current at the analog end, forming an adaptive negative feedback tuning closed loop that controls the total data injection. Furthermore, the streaming spatiotemporal data fusion and in-memory computing macrocell converts the time delay accumulated during asynchronous data packet transmission into an analog attenuated voltage, directly participating in the computational weight modulation within the in-memory computing array, achieving direct coupling between spatiotemporal characteristics and underlying physical computing features.

[0012] Preferably, the analog impedance sensing mask unit includes a digital-to-analog converter interface, a controlled dynamic impedance network, a differential comparator, and a switching circuit. The digital-to-analog converter interface receives multi-source heterogeneous data streams, converts discrete feature vectors into physical current signals as feature input currents, and transmits these feature input currents to the signal input terminal of the differential comparator. The controlled dynamic impedance network generates a cutoff threshold current and transmits it to the reference input terminal of the differential comparator. The differential comparator receives the feature input current and the cutoff threshold current in parallel, compares the amplitude of the feature input current with the amplitude of the cutoff threshold current in real time, and outputs a mask state parameter to the control terminal of the switching circuit based on the comparison result. When the mask state parameter is 0, the differential comparator outputs a low-level control signal, the switching circuit is in the open state and switches to a high-impedance cutoff state, cutting off the conduction path of the feature input current. When the mask state parameter is 1, the differential comparator outputs a high-level control signal, the switching circuit is in the closed state and maintains a low-impedance conduction state, allowing the feature input current to be transmitted to the asynchronous pulse generator.

[0013] The logic for determining the mask state parameter output by the differential comparator satisfies the following conditions: when the amplitude of the characteristic input current corresponding to the input channel is greater than or equal to the amplitude of the cutoff threshold current, the mask state parameter is set to 1; when the amplitude of the characteristic input current corresponding to the input channel is less than the amplitude of the cutoff threshold current, the mask state parameter is set to 0.

[0014] The controlled dynamic impedance network integrates a bias current source, a reference voltage source, a voltage-to-current converter, and a superposition node. The reference voltage source is connected to the control terminal of the bias current source, outputting a static constant voltage to cause the bias current source to output a static reference threshold current. The voltage-to-current converter receives the reverse bias voltage from the cross-domain reverse voltage physical feedback loop and converts the reverse bias voltage into a dynamically regulated current. The output terminal of the voltage-to-current converter is connected in parallel with the output terminal of the bias current source at the superposition node. The dynamically regulated current and the static reference threshold current are superimposed in the same direction at the superposition node to generate the cutoff threshold current input to the differential comparator.

[0015] Preferably, the asynchronous pulse generator internally includes an analog-to-digital conversion module, a data packet encapsulation circuit, and a timestamp generator. The analog-to-digital conversion module receives the released physical current signal and quantizes the amplitude of the physical current signal into a digital characteristic quantity. The timestamp generator generates the initial timestamp of the current moment. The data packet encapsulation circuit acquires the digital characteristic quantity, the input channel identifier of the corresponding characteristic signal, and the initial timestamp, and combines and encapsulates the three to form an asynchronous data packet. The asynchronous data packet includes a data header and a payload segment. The data header records the input channel identifier and the initial timestamp, and the payload segment stores the digital characteristic quantity.

[0016] Preferably, each routing node is internally configured with an asynchronous controller and a data buffer. Two routing nodes located at adjacent communication positions are designated as a front-end routing node and a rear-end routing node. A data bus and handshake signal lines including request and response lines are configured between the front-end and rear-end routing nodes. The asynchronous controller of the front-end routing node sends a logic high-level request signal to the rear-end routing node via the request line. The asynchronous controller of the rear-end routing node detects the storage occupancy status of its own data buffer. If there is free storage space, it returns a logic high-level response signal to the front-end routing node via the response line. In response to the response signal, the asynchronous controller of the front-end routing node pushes the asynchronous data packet from its data buffer to the data buffer of the rear-end routing node via the data bus. Upon detecting that the push is complete, it cancels the request signal on the request line, and the rear-end routing node synchronously cancels its response signal.

[0017] Each routing node is equipped with a latency monitor, and the preceding routing node contains a header update circuit with a hardware adder. The latency monitor is physically connected in parallel to the request and response lines. It uses its internal subtractor circuit to subtract the second timestamp triggered by the response signal from the first timestamp triggered by the request signal, generating a single-hop handshake time difference. The header update circuit reads this single-hop handshake time difference and uses the hardware adder to accumulate it, writing it into the header of the asynchronous data packet. The accumulated values ​​from multiple routing nodes constitute the time delay characteristic.

[0018] Preferably, the cross-domain backpressure physical feedback loop internally includes a congestion signal aggregation bus, a low-pass filter circuit, a backpressure bias voltage generator, and a congestion tolerance threshold register. The delay monitor transmits the single-hop handshake time difference to the congestion signal aggregation bus. The low-pass filter circuit receives the discrete single-hop handshake time difference sequence and performs an exponential moving average calculation to output the average delay duration. The backpressure bias voltage generator internally configures a limiting amplifier circuit, which receives the average delay duration and the congestion tolerance threshold output by the congestion tolerance threshold register in parallel.

[0019] Preferably, the input side of the streaming spatiotemporal data fusion and in-memory computing macrocell is configured with an asynchronous receiving interface, which internally includes a voltage-controlled attenuator array. The asynchronous receiving interface includes a data packet parsing circuit and a feature digital-to-analog converter network. The data packet parsing circuit extracts time delay features, input channel identifiers, and digital features from the asynchronous data packets. The feature digital-to-analog converter network converts the digital features into a feature reference voltage. The voltage-controlled attenuator array includes a delay voltage converter and a variable gain amplifier. The delay voltage converter converts the time delay features into an analog attenuated voltage, which is input to the control input of the variable gain amplifier. The variable gain amplifier uses the analog attenuated voltage to perform amplitude attenuation on the feature reference voltage at the input signal terminal, and outputs a modulated feature voltage for transmission to the analog cross-multiply-accumulate array.

[0020] Preferably, the streaming spatiotemporal data fusion and in-memory computing macrocell also includes an analog cross-multiply-accumulate array, a voltage row driver, a current sensing amplifier, an analog-to-digital converter, a timing alignment controller, a FIFO storage buffer array, and a bit line reset circuit. The voltage row driver receives the modulation characteristic voltage and drives the word line input voltage of the analog cross-multiply-accumulate array. Each resistive variable storage cell within the analog cross-multiply-accumulate array generates a converged current on the bit line based on Kirchhoff's current law, according to its conductance weight value. The current sensing amplifier converts the bit line converged current into a sense voltage. The analog-to-digital converter samples and quantizes the sense voltage, converting it into a digital tensor result. The timing alignment controller controls the FIFO storage buffer array to receive the tensor result, performing buffering, sorting, and alignment output based on the timestamp information in the data header. After quantization output is complete, the bit line reset circuit inputs a reset voltage to the bit line of the analog cross-multiply-accumulate array, forcing internal charge discharge.

[0021] The present invention, by adopting the above technical solution, can bring the following beneficial effects:

[0022] 1. This invention maps multi-source heterogeneous data streams into physical current signals by arranging an analog impedance sensing mask unit containing a controlled dynamic impedance network and a differential comparator on the system input side. The signal is then compared in real time with the internally generated cutoff threshold current. This directly controls the switching circuit in the analog physical domain to cut off the conduction path of characteristic input currents below the cutoff threshold, blocking invalid characteristic signals from entering the subsequent asynchronous pulse generator. This achieves the effect of avoiding invalid logic flips at the source of the data stream and eliminating redundant calculations of dynamic power consumption in digital circuits.

[0023] 2. This invention constructs a cross-domain reverse pressure physical feedback loop between the asynchronous hardware logic routing network and the analog impedance sensing mask unit. It uses a delay monitor to extract the single-hop handshake time difference of asynchronous data packets transmitted between routing nodes in real time, and the reverse pressure bias voltage generator converts the time difference, which represents the degree of congestion, into a reverse bias voltage (i.e., a feedback control voltage used to reverse adjust the cutoff threshold current). This voltage is fed back to the controlled dynamic impedance network to dynamically adjust the front-end analog interception threshold, thereby achieving the effect of adaptively adjusting the data injection amount and alleviating congestion in the internal communication link of the chip by utilizing the underlying physical state of the hardware.

[0024] 3. This invention, by configuring a voltage-controlled attenuator array containing a delay voltage converter and a variable gain amplifier on the input side of the in-memory computing macrocell, extracts the time delay characteristics accumulated by asynchronous data packets in the routing network and converts them into an analog attenuation voltage. In the analog domain, the amplitude attenuation operation is performed on the characteristic reference voltage. Finally, the attenuated modulation characteristic voltage is injected into the analog cross-multiply-accumulate array to perform in-memory calculation. This invention achieves the effect of directly and physically coupling the communication delay timing characteristics to the underlying hardware calculation weight modulation to reduce the contribution of high-latency data to the calculation results. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the artificial intelligence chip processing system of the present invention;

[0026] Figure 2 This is a circuit structure diagram of the analog impedance sensing mask unit of the present invention;

[0027] Figure 3 This is a schematic diagram of the cross-domain reverse pressure physical feedback loop of the present invention;

[0028] Figure 4 This is a structural diagram of the spatiotemporal data fusion and storage-computing integrated macrocell of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1

[0031] Please refer to the appendix. Figure 1-4 This invention provides an artificial intelligence chip processing system, comprising: an analog impedance sensing mask unit 100, an asynchronous event-driven hardware logic routing network 200, a streaming spatiotemporal data fusion and in-memory computing macro unit 300, and a cross-domain backpressure physical feedback loop 400. The specific structure and connection relationship of each unit are as follows:

[0032] The analog impedance sensing mask unit 100 is arranged on the input side of the artificial intelligence chip processing system. Its input end is equipped with a multi-parallel digital-to-analog converter interface 110, and its output end is connected to an asynchronous pulse generator 120. The digital-to-analog converter interface 110 is used to access multi-source heterogeneous data streams.

[0033] The analog impedance sensing mask unit 100 includes a controlled dynamic impedance network 130, a differential comparator 140, and a switching circuit 150. The controlled dynamic impedance network 130 is used to establish a cutoff threshold current. The analog impedance sensing mask unit 100 receives the characteristic current output by the digital-to-analog converter interface 110, performs a differential comparison between the characteristic current and the cutoff threshold current, and switches the transmission path corresponding to the characteristic signal with an amplitude lower than the cutoff threshold current to a high-impedance cutoff state within the analog impedance sensing mask unit 100.

[0034] The digital-to-analog converter interface 110 is located at the front-end input of the analog impedance sensing mask unit 100, receiving multi-source heterogeneous data streams. These data streams contain multi-channel parallel discrete feature vectors. The digital-to-analog converter interface 110 converts the discrete feature vectors into continuous physical current signals. Let the input channel number of the digital-to-analog converter interface 110 be... Discrete feature vectors in the input channel The characteristic input current generated by the mapping is denoted as The output of the digital-to-analog converter interface 110 is connected to the signal input node of the analog impedance sensing mask unit 100, which receives the characteristic input current. ;

[0035] The controlled dynamic impedance network 130 is arranged inside the analog impedance sensing mask unit 100 and includes an adjustable resistor array and a bias current source to generate a cutoff threshold current, denoted as . The output of the controlled dynamic impedance network 130 is connected to the reference input of the differential comparator 140, and the output of the digital-to-analog converter interface 110 is connected to the signal input of the differential comparator 140. The controlled dynamic impedance network 130 cuts off the threshold current. The signal is transmitted to differential comparator 140, which receives the characteristic input current in parallel. With cutoff threshold current For characteristic input current Amplitude and cutoff threshold current The amplitude is compared in real time, and the mask state parameter is output based on the comparison result. The mask state parameter is denoted as... ;

[0036] Mask state parameter The decision logic satisfies the following conditions:

[0037] in, for real-time input channel The amplitude of the corresponding characteristic input current, for The amplitude of the cutoff threshold current output by the constantly controlled dynamic impedance network 130;

[0038] The control terminal of the switching circuit 150 is connected to the output terminal of the differential comparator 140, and the signal input terminal receives the characteristic input current. The signal output terminal is connected to the asynchronous pulse generator 120, when the mask state parameter When the value is 0, the differential comparator 140 outputs a low-level control signal to the switching circuit 150, the switching circuit 150 is in the open state, and the physical communication link it is connected to switches to a high-impedance cutoff state, cutting off the characteristic input current. The internal conduction path of the analog impedance sensing mask unit 100 blocks the transmission of the characteristic signal of the corresponding channel to the subsequent circuit. When the mask state parameter When the value is 1, the differential comparator 140 outputs a high-level control signal to the switching circuit 150, the switching circuit 150 is in the closed state, and the physical communication link it belongs to maintains a low-impedance on state, allowing the characteristic input current. The characteristic input current that is conducted passes through the interior of the analog impedance sensing mask unit 100. The signal output terminal of the self-switching circuit 150 is transmitted to the asynchronous pulse generator 120;

[0039] The controlled dynamic impedance network 130 integrates a bias current source 131, a reference voltage source 132, and a voltage-to-current converter 133. The reference voltage source 132 is connected to the control terminal of the bias current source 131 and outputs a static constant voltage. The bias current source 131 receives the static constant voltage and outputs a static reference threshold current.

[0040] The output of the cross-domain reverse voltage physical feedback loop 400 is connected to the controlled dynamic impedance network 130. The cross-domain reverse voltage physical feedback loop 400 includes a time-delay voltage conversion circuit 410, which is a component of the reverse bias voltage generator (403). The time-delay voltage conversion circuit 410 outputs a reverse bias voltage (i.e., a feedback control voltage used to reverse regulate the cutoff threshold current). The voltage-to-current converter 133 in the controlled dynamic impedance network 130 receives the reverse bias voltage and converts the reverse bias voltage into a dynamically regulated current.

[0041] The controlled dynamic impedance network 130 is also equipped with a superposition node 134. The output terminal of the voltage-to-current converter 133 and the output terminal of the bias current source 131 are connected in parallel at the superposition node 134. The polarity of the dynamic adjustment current output by the voltage-to-current converter 133 and the polarity of the static reference threshold current output by the bias current source 131 are kept in the same direction. The dynamic adjustment current and the static reference threshold current are superimposed in the same direction at the superposition node 134 to generate the cutoff threshold current. The superposition node 134 is connected to the reference input terminal of the differential comparator 140. The controlled dynamic impedance network 130 provides the cutoff threshold current to the reference input terminal of the differential comparator 140 through the superposition node 134.

[0042] The dynamic modulation process of the cutoff threshold current satisfies the following calculation model:

[0043] in, for The amplitude of the cutoff threshold current output by the constantly controlled dynamic impedance network 130. This represents the amplitude of the static reference threshold current output by the bias current source 131. for The amplitude of the reverse bias voltage output by the time-delay voltage conversion circuit 410 within the 400-second cross-domain reverse voltage physical feedback loop. The transconductance conversion coefficient of the voltage-to-current converter 133;

[0044] When the handshake time difference within the asynchronous event-driven hardware logic routing network 200 increases, the reverse bias voltage output by the delay voltage conversion circuit 410... The amplitude increases synchronously, and the voltage-to-current converter 133 adjusts according to the reverse bias voltage. The amplitude change synchronously increases the dynamically adjusted current, and the superimposed cutoff threshold current The amplitude increases with the increase of the dynamically adjusted current, and the differential comparator 140 in the analog impedance sensing mask unit 100 obtains the increased cutoff threshold current. Using the cutoff threshold current The characteristic input current at the digital-to-analog converter interface 110 is cut off, and the controlled dynamic impedance network 130 adjusts the cutoff threshold current. By changing the number of conduction channels within the analog impedance sensing mask unit 100, the total amount of characteristic signal injected into the asynchronous event-driven hardware logic routing network 200 is controlled.

[0045] An asynchronous pulse generator 120 is positioned after the signal output of the switching circuit 150. Internally, it includes an analog-to-digital converter module 121, a data packet encapsulation circuit 122, and a timestamp generator 123. When the switching circuit 150 is in a closed state, it inputs a characteristic input current to the asynchronous pulse generator 120. The analog-to-digital converter module 121 receives the characteristic input current and quantizes its amplitude into a digital characteristic quantity. The timestamp generator 123 generates the initial timestamp for the current moment. The data packet encapsulation circuit 122 acquires the digital characteristic quantity, the input channel identifier corresponding to the characteristic input current, and the initial timestamp, and combines these three elements to encapsulate an asynchronous data packet.

[0046] The structure of an asynchronous data packet includes a header and a payload segment. The header records the input channel identifier and the initial timestamp, and the payload segment stores digital characteristic values. The data packet encapsulation circuit 122 outputs the asynchronous data packet to the asynchronous event-driven hardware logic routing network 200.

[0047] An asynchronous event-driven hardware logic routing network 200 is arranged after the analog impedance sensing mask unit 100. The output of the asynchronous pulse generator 120 is connected to the input of the asynchronous event-driven hardware logic routing network 200. The asynchronous event-driven hardware logic routing network 200 contains multiple routing nodes 210 arranged in a grid. Adjacent routing nodes 210 are cascaded together through handshake signal lines. A delay monitor 220 is configured inside or in a bypass configuration of the routing node 210. The output port of the delay monitor 220 is connected to the cross-domain backpressure physical feedback loop 400.

[0048] The handshake signal line transmits request and response levels. The asynchronous event-driven hardware logic routing network (200) does not depend on the global clock tree distribution and uses an asynchronous handshake mechanism for data transmission. The characteristic signal in the on state is encapsulated into an asynchronous data packet after amplitude quantization by the asynchronous pulse generator 120 and then transmitted between the routing nodes 210 according to the handshake protocol.

[0049] The routing node 210 is internally configured with an asynchronous controller 211 and a data buffer 212. Two routing nodes 210 located in adjacent communication positions are defined as a front-end routing node 210 and a rear-end routing node 210. A data bus 213 and a handshake signal line are configured between the front-end routing node 210 and the rear-end routing node 210. The asynchronous controller 211 of the front-end routing node 210 and the asynchronous controller 211 of the rear-end routing node 210 are physically connected through the handshake signal line, which includes a request line in the sending direction and an acknowledgment line in the returning direction.

[0050] After the preceding routing node 210 obtains the asynchronous data packet, it stores the asynchronous data packet in its own data buffer 212. Its asynchronous controller 211 sends a logic high-level request signal to the following routing node 210 through the request line. The asynchronous controller 211 of the following routing node 210 receives the request signal and checks the storage occupancy status of its own data buffer 212. When the data buffer 212 of the following routing node 210 has free storage space, the asynchronous controller 211 of the following routing node 210 returns a logic high-level response signal to the preceding routing node 210 through the response line.

[0051] After receiving the acknowledgment signal, the asynchronous controller 211 of the preceding routing node 210 pushes the asynchronous data packet from the data buffer 212 of the preceding routing node 210 to the data buffer 212 of the following routing node 210 via the data bus 213. After detecting that the asynchronous data packet has been pushed, the asynchronous controller 211 of the preceding routing node 210 cancels the request signal on the request line and restores the logic low level. In response to the cancellation action of the request signal, the asynchronous controller 211 of the following routing node 210 synchronously cancels the acknowledgment signal on the acknowledgment line. The preceding routing node 210 and the following routing node 210 return to their initial states, completing the single-hop node transmission of the asynchronous data packet.

[0052] Delay monitor 220 is configured within routing node 210, and its signal acquisition terminal is physically connected in parallel to the request line and the response line. Delay monitor 220 integrates a time-to-digital converter and a subtractor circuit 221. When the asynchronous controller 211 of the preceding routing node 210 sends a request signal to the following routing node 210, delay monitor 220 detects the level transition of the request signal and records the first timestamp triggered by the request signal. Let the sequence number of the current transmission node be... The first time it was stamped as When the asynchronous controller 211 of the downstream routing node 210 returns an acknowledgment signal to the upstream routing node 210, the delay monitor 220 detects the level transition of the acknowledgment signal and records the second timestamp triggered by the acknowledgment signal; the second timestamp is denoted as ;

[0053] The subtractor circuit 221 inside the delay monitor 220 subtracts the second timestamp from the first timestamp to generate the single-hop handshake time difference; the single-hop handshake time difference is denoted as... The calculation logic is as follows:

[0054] in, Characterizing asynchronous data packets in the first Queuing and physical transmission time generated at routing node 210;

[0055] The front-end routing node 210 is internally configured with a header update circuit 214, which includes a hardware adder. The asynchronous controller 211 of the front-end routing node 210 reads the single-hop handshake time difference. And send it to the header update circuit 214; the header update circuit 214 uses a hardware adder to convert the single-hop handshake time difference. The data header of the asynchronous data packet is accumulated and written. As the asynchronous data packet passes through multiple routing nodes 210 in the asynchronous event-driven hardware logic routing network 200, the data header update circuit 214 in each routing node 210 accumulates the single-hop handshake time difference in the data header. The accumulated value constitutes the time delay feature. The time delay feature is transmitted to the streaming spatiotemporal data fusion and storage-computing macro unit 300 with the asynchronous data packet.

[0056] The cross-domain backpressure physical feedback loop 400 is configured with a congestion signal aggregation bus 401, and the feedback output of the delay monitor 220 is connected to the congestion signal aggregation bus 401; the delay monitor 220 will measure the single-hop handshake time difference. Transmitted to congestion signal aggregation bus 401, single-hop handshake time difference The asynchronous event-driven hardware logic routing network 200 is constructed by the congestion physical quantity on the local communication link. The cross-domain backpressure physical feedback loop 400 collects the single-hop handshake time difference output by multiple routing nodes 210 in parallel via the congestion signal aggregation bus 401, and uses the single-hop handshake time difference to trigger the backpressure tuning mechanism.

[0057] The streaming spatiotemporal data fusion and in-memory computing macrocell 300 is connected to the output end of the asynchronous event-driven hardware logic routing network 200, and its input side is configured with an asynchronous receiving interface 330; the streaming spatiotemporal data fusion and in-memory computing macrocell 300 contains a voltage-controlled attenuator array 310 and an analog cross-multiply-accumulate array 320.

[0058] The input of the voltage-controlled attenuator array 310 receives asynchronous data packets and time delay characteristics from the asynchronous receiver interface 330, and the output is connected to the word line of the analog cross-multiply-accumulate array 320; the bit line of the analog cross-multiply-accumulate array 320 is connected to the current sensing amplifier.

[0059] The asynchronous receiving interface 330 is configured on the input side of the streaming spatiotemporal data fusion and in-memory computing macro unit 300. It contains a data packet parsing circuit 331 and a feature digital-to-analog conversion network 332. The input end of the asynchronous receiving interface 330 is connected to the last-level routing node 210 of the asynchronous event-driven hardware logic routing network 200 to receive asynchronous data packets transmitted by the last-level routing node 210.

[0060] The data packet parsing circuit 331 reads the asynchronous data packet, extracts the time delay feature and input channel identifier from the data header of the asynchronous data packet, and extracts the digital feature from the payload segment of the asynchronous data packet; the data packet parsing circuit 331 transmits the digital feature to the feature digital-to-analog converter network 332, the feature digital-to-analog converter network 332 receives the digital feature and converts the digital feature into a feature reference voltage.

[0061] The voltage-controlled attenuator array 310 internally includes multiple sets of parallel delay voltage converters 311 and variable gain amplifiers 312. The delay voltage converter 311 internally integrates a digital exponential mapping circuit 313 and a bias digital-to-analog converter 314. The data packet parsing circuit 331 transmits the time delay characteristic to the digital exponential mapping circuit 313. The digital exponential mapping circuit 313 receives the time delay characteristic, performs an exponential mapping operation on the time delay characteristic according to the hardware attenuation factor, and outputs an attenuated digital value. The bias digital-to-analog converter 314 receives the attenuated digital value and converts the attenuated digital value into an analog attenuated voltage.

[0062] The output of the characteristic digital-to-analog converter network 332 is connected to the signal input of the variable gain amplifier 312, and the output of the delay voltage converter 311 is connected to the control input of the variable gain amplifier 312. The characteristic digital-to-analog converter network 332 inputs the characteristic reference voltage to the signal input of the variable gain amplifier 312, and the delay voltage converter 311 inputs the analog attenuation voltage to the control input of the variable gain amplifier 312. The variable gain amplifier 312 uses the analog attenuation voltage to perform amplitude attenuation operation on the characteristic reference voltage and outputs a modulated characteristic voltage.

[0063] The amplitude attenuation mapping of the modulation characteristic voltage satisfies the following calculation formula:

[0064] in, Identify the corresponding channel for the input channel. The amplitude of the modulation characteristic voltage, The amplitude of the characteristic reference voltage output by the characteristic digital-to-analog converter network 332 is given. The value of the time delay feature extracted by the packet parsing circuit 331. The hardware attenuation factor configured for the digital exponential mapping circuit 313 has the dimension of the reciprocal of time (e.g., ), used to represent time delay features Mapped to a dimensionless exponential decay coefficient;

[0065] The value of the time delay characteristic increases with the dwell time of the asynchronous data packet in the asynchronous event-driven hardware logic routing network 200. The analog attenuation voltage output by the delay voltage converter 311 increases with the increase of the time delay characteristic. The gain coefficient of the variable gain amplifier 312 decreases with the increase of the analog attenuation voltage. The amplitude of the modulation characteristic voltage decreases with the decrease of the gain coefficient of the variable gain amplifier 312. The streaming spatiotemporal data fusion and in-memory computing macro unit 300 reduces the amplitude of the modulation characteristic voltage and reduces the contribution of congested data in subsequent multiply-accumulate operations.

[0066] The word line of the analog cross-multiply-accumulate array 320 is connected to the output of the variable gain amplifier 312. The variable gain amplifier 312 transmits the modulation feature voltage to the analog cross-multiply-accumulate array 320. The analog cross-multiply-accumulate array 320 receives the modulation feature voltage and performs in-memory calculation.

[0067] The simulated cross-multiply-accumulate array 320 internally contains multiple resistive variable memory cells arranged in a matrix, and the resistive variable memory cells constitute a conductance weight matrix; let the first... Line 1 The conductivity of the column resistive variable memory cell is The voltage line driver 350 receives the modulation characteristic voltage at its input and outputs the modulation characteristic voltage to the word line of the analog cross-multiply-accumulate array 320, driving the word line of the analog cross-multiply-accumulate array 320. The input voltage of the line word is ;

[0068] Each column of bit lines inside the analog cross-multiply-accumulate array 320 is connected to a current sensing amplifier 340. The analog cross-multiply-accumulate array 320 generates a converging current on the corresponding bit line based on Kirchhoff's current law. The current sensing amplifier 340 acquires the converging current and converts it into a sensing voltage. The analog cross-multiply-accumulate array 320 in the... Current value collected on the column line Satisfies the following physical model:

[0069] in, For the first The convergence current output from the column line, For input to the number The modulation characteristic voltage of the line character, For the first Line 1 The conductance of the column resistive variable memory cell, To simulate the number of rows in a 320-row cross-multiply-accumulate array;

[0070] The current sensing amplifier 340 converts the bit line converged current into a sense voltage and outputs the sense voltage to the analog-to-digital converter 360; the analog-to-digital converter 360 samples and quantizes the sense voltage and converts the sense voltage into a digital tensor result;

[0071] The timing alignment controller 370 acquires the instantaneous timing of the digital tensor result output by the analog-to-digital converter 360 and controls the FIFO storage buffer array 371 to receive the tensor result. The FIFO storage buffer array 371 performs buffering and sorting of the tensor result according to the timestamp information in the data header. The timing alignment controller 370 reads the sorted digital tensor result. The streaming spatiotemporal data fusion and in-memory computing macro unit 300 outputs the tensor result through the FIFO storage buffer array 371 and aligns the output tensor result with the preset output protocol.

[0072] After the analog-to-digital converter 360 completes quantization, the streaming spatiotemporal data fusion and in-memory computing macrocell 300 updates the status flag bit. The timing alignment controller 370 controls the bit line reset circuit 380 to operate based on the status flag bit. The bit line reset circuit 380 inputs a reset voltage to the bit line of the analog cross-multiply-accumulate array 320, forcing the charge in the analog cross-multiply-accumulate array 320 to be discharged, so that the analog cross-multiply-accumulate array 320 returns to the initial level to execute the next cycle calculation.

[0073] The cross-domain backpressure physical feedback loop 400 is connected between the asynchronous event-driven hardware logic routing network 200 and the analog impedance sensing mask unit 100, and its data acquisition end is collected from the delay monitor 220; the delay monitor 220 outputs the handshake time difference of the routing node 210.

[0074] The cross-domain reverse voltage physical feedback loop 400 contains a delay voltage conversion circuit 410. The control output terminal of the delay voltage conversion circuit 410 is physically coupled to the bias voltage control terminal of the analog impedance sensing mask unit 100. The cross-domain reverse voltage physical feedback loop 400 converts the handshake time difference into a reverse bias voltage and inputs the reverse bias voltage to the analog impedance sensing mask unit 100 to adjust the cutoff threshold current.

[0075] The input of the cross-domain backpressure physical feedback loop 400 is configured with a congestion signal aggregation bus 401. The congestion signal aggregation bus 401 is physically connected to multiple delay monitors 220 in the asynchronous event-driven hardware logic routing network 200. The delay monitors 220 output digital single-hop handshake time difference. The congestion signal aggregation bus 401 receives the single-hop handshake time difference output by multiple delay monitors 220 in parallel and arranges the single-hop handshake time difference into a delay time sequence.

[0076] The input of the low-pass filter circuit 402 is connected to the congestion signal aggregation bus 401, receives the delay time series, performs an exponential moving average operation on the delay time series, smooths the numerical fluctuations in the delay time series, and outputs the average delay time.

[0077] The reverse bias voltage generator 403 is internally configured with a digital comparator circuit 405, a digital-to-analog converter 406, and a limiting amplifier circuit. The congestion tolerance threshold register 404 internally stores the congestion tolerance threshold, which represents the upper limit of communication dwell time that the asynchronous event-driven hardware logic routing network 200 can tolerate. The output of the congestion tolerance threshold register 404 is connected to the digital comparator circuit 405, and the output of the low-pass filter circuit 402 is also connected to the digital comparator circuit 405. The digital comparator circuit 405 receives the average delay time and the congestion tolerance threshold in parallel, performs a subtraction operation on the two, and outputs the digital difference.

[0078] The input terminal of the digital-to-analog converter 406 is connected to the output terminal of the digital comparator circuit 405, and the input terminal of the limiting amplifier circuit is connected to the output terminal of the digital-to-analog converter 406. The digital-to-analog converter 406 converts the digital difference into an analog reference voltage. The limiting amplifier circuit receives the analog reference voltage, amplifies it, and performs threshold truncation to generate a reverse bias voltage.

[0079] The logic for generating the reverse bias voltage satisfies the following calculation formula:

[0080] in, for The amplitude of the reverse bias voltage output by the reverse bias voltage generator 403 at any given time. for The average delay time of the output of the low-pass filter circuit 402 at any given time. The congestion tolerance threshold is output by the congestion tolerance threshold register 404. This represents the closed-loop voltage gain coefficient of the limiting amplifier circuit. This is the function that takes the maximum value for the limiting amplifier circuit.

[0081] The function is implemented by the digital comparator circuit (405) and the limiting amplifier circuit: when the average delay time is less than or equal to the congestion tolerance threshold, the digital comparator circuit 405 outputs a digital difference that is not greater than zero. After being limited by the lower limit of the limiting amplifier circuit, the digital-to-analog converter 406 and the limiting amplifier circuit are in a zero-input state, and the reverse bias voltage generator 403 outputs a reverse bias voltage with an amplitude of zero. When the average delay time is greater than the congestion tolerance threshold, the digital comparator circuit 405 outputs a digital difference that is greater than zero, the digital-to-analog converter 406 generates the corresponding analog reference voltage, and the reverse bias voltage generator 403 outputs a reverse bias voltage with an amplitude greater than zero.

[0082] The output of the reverse bias voltage generator 403 is physically coupled to the voltage-to-current converter 133 inside the controlled dynamic impedance network 130, and the reverse bias voltage is input to the voltage-to-current converter 133. The voltage-to-current converter 133 generates a dynamic adjustment current based on the reverse bias voltage to adjust the cutoff threshold current in the analog impedance sensing mask unit 100.

[0083] Example 2

[0084] Please refer to the appendix. Figure 1-4 Based on Embodiment 1 and the aforementioned artificial intelligence chip processing system, this embodiment provides an artificial intelligence chip processing method, comprising the following steps:

[0085] In step S101, the analog impedance sensing mask unit 100 receives multi-source heterogeneous data streams; the digital-to-analog conversion interface 110 converts the discrete feature vectors in the multi-source heterogeneous data streams into physical current signals.

[0086] In step S102, the controlled dynamic impedance network within the analog impedance sensing mask unit 100 generates a cutoff threshold current. The analog impedance sensing mask unit 100 compares the amplitude of the physical current signal with the amplitude of the cutoff threshold current. When the amplitude of the physical current signal is lower than the amplitude of the cutoff threshold current, the analog impedance sensing mask unit 100 controls the corresponding input channel to be in a high-impedance cutoff state and blocks the physical current signal of the corresponding input channel. When the amplitude of the physical current signal is greater than or equal to the amplitude of the cutoff threshold current, the analog impedance sensing mask unit 100 controls the corresponding input channel to be turned on.

[0087] In step S103, the asynchronous pulse generator 120 receives the conducting physical current signal; the asynchronous pulse generator 120 encapsulates the physical current signal into an asynchronous data packet after amplitude quantization, and the asynchronous data packet records the characteristic signal amplitude; the asynchronous event-driven hardware logic routing network 200 receives the asynchronous data packet.

[0088] Step S104: The asynchronous event-driven hardware logic routing network 200 includes multiple routing nodes 210; the routing node 210 sends a request level to the adjacent routing node 210 according to the handshake protocol, and the adjacent routing node 210 returns an acknowledgment level when it has the conditions to receive; the routing node 210 completes the transmission of asynchronous data packets after receiving the acknowledgment level.

[0089] In step S105, the delay monitor 220 records the first timestamp of the request level sent by the routing node 210 and the second timestamp of the response level received by the routing node 210; the delay monitor 220 subtracts the second timestamp from the first timestamp to calculate the handshake time difference; the routing node 210 adds the handshake time difference to the header of the asynchronous data packet to form a time delay feature.

[0090] In step S106, the digital comparison circuit (405) in the cross-domain reverse voltage physical feedback loop 400 compares the average delay time with the congestion tolerance threshold, outputs a digital difference, and generates a reverse bias voltage after digital-to-analog conversion and limiting amplification; the cross-domain reverse voltage physical feedback loop 400 transmits the reverse bias voltage to the analog impedance sensing mask unit 100; the analog impedance sensing mask unit 100 increases the cutoff threshold current of the controlled dynamic impedance network according to the reverse bias voltage;

[0091] In step S107, the asynchronous receiving interface 330 receives asynchronous data packets passing through the asynchronous event-driven hardware logic routing network 200; the asynchronous receiving interface 330 extracts the time delay feature quantity attached to the data packet header; and the voltage-controlled attenuator array 310 receives the time delay feature quantity.

[0092] In step S108, the voltage-controlled attenuator array 310 converts the time delay characteristic into an analog attenuation voltage; the voltage-controlled attenuator array 310 uses the analog attenuation voltage to adjust the amplitude of the characteristic reference voltage corresponding to the asynchronous data packet.

[0093] In step S109, the streaming spatiotemporal data fusion and in-memory computing macro unit 300 acquires the timing sequence of asynchronous data packets arriving at the asynchronous receiving interface 330; the streaming spatiotemporal data fusion and in-memory computing macro unit 300 reconstructs the amplitude-adjusted characteristic reference voltages into a fusion input vector based on the timing sequence.

[0094] Step S110: The analog cross-multiply-accumulate array 320 receives the fused input vector; the voltage signal of the fused input vector is input to the word line of the analog cross-multiply-accumulate array 320; the analog cross-multiply-accumulate array 320 generates a converged current on the bit line according to the conductance distribution of the internal cross nodes.

[0095] In step S111, the current sensing amplifier 340 receives the converged current of the bit line; the current sensing amplifier 340 converts the converged current into a sensing voltage; the analog-to-digital converter 360 samples and quantizes the sensing voltage, converting it into a tensor result in digital form; the streaming spatiotemporal data fusion and in-memory computing macrocell 300 outputs the tensor result.

[0096] Example 3

[0097] Please refer to the appendix. Figure 1-4Based on Embodiments 1 and 2, in the above-mentioned artificial intelligence chip processing method,

[0098] Specifically, in step S101, a multi-source heterogeneous data stream containing multi-channel parallel discrete feature vectors is received through the digital-to-analog converter interface 110, and the discrete feature vectors of each channel are mapped and converted into continuous physical current signals, i.e., feature input currents. The characteristic input current is transmitted to the signal input node inside the analog impedance sensing mask unit 100 to provide an analog domain input signal for subsequent mask screening.

[0099] Specifically, in step S102, a cutoff threshold current is generated through the controlled dynamic impedance network 130. The input is then fed to the reference terminal of the differential comparator 140; the differential comparator 140 compares the amplitude of the characteristic input current of each channel with the cutoff threshold current in real time, and outputs the mask state parameter of the corresponding channel. When the amplitude of the characteristic input current is lower than the cutoff threshold, the mask state parameter is 0, the switch circuit 150 is open, and the corresponding channel switches to the high-impedance cutoff state, blocking the transmission of invalid signals to the next stage; when the amplitude of the characteristic input current is greater than or equal to the cutoff threshold, the mask state parameter is 1, the switch circuit 150 is closed, the corresponding channel remains in the low-impedance conduction state, and the effective characteristic current is transmitted to the next stage.

[0100] Specifically, in step S103, the analog-to-digital converter module 121 inside the asynchronous pulse generator 120 receives the conducting characteristic input current and quantizes the current amplitude into a digital characteristic quantity; the timestamp generator 123 generates the current initial timestamp; the data packet encapsulation circuit 122 combines the digital characteristic quantity, the input channel identifier, and the initial timestamp into an asynchronous data packet, wherein the data header stores the channel identifier and the timestamp, and the payload segment stores the digital characteristic quantity; the encapsulated asynchronous data packet is output to the head routing node of the asynchronous event-driven hardware logic routing network 200;

[0101] Specifically, in step S104, after receiving the asynchronous data packet through the front-end routing node 210, it first stores it in its own data buffer 212. The asynchronous controller 211 then sends a high-level request signal to the back-end routing node 210 through the request line. The back-end routing node 210 checks the idle state of its own buffer and returns a high-level response signal when it has sufficient receiving capacity. After receiving the response, the front-end routing node pushes the data packet to the data buffer of the back-end routing node through the data bus 213. After the push is completed, the front-end routing node cancels the request signal, and the back-end routing node synchronously cancels the response signal, completing the single-hop asynchronous transmission. The data packet is transmitted hop-by-hop in the meshed routing network according to this mechanism.

[0102] Specifically, in step S105, the delay monitor 220 in the routing node 210 collects the level transitions of the request line and the response line in real time, and records the first timestamp of the request signal triggering. The second timestamp triggered by the response signal The single-hop handshake time difference is calculated by the internal subtractor circuit 221. The data header update circuit 214 accumulates the single-hop time difference and writes it into the data header of the asynchronous data packet. The single-hop delay is accumulated once every time the data packet passes through a routing node, and finally forms a time delay feature that characterizes the degree of congestion in the entire transmission process, which is transmitted to the next stage along with the data packet.

[0103] Specifically, step S106 includes the following sub-steps:

[0104] Step S106-1: The cross-domain reverse pressure physical feedback loop 400 obtains the single-hop handshake time difference within the asynchronous event-driven hardware logic routing network 200; the low-pass filter circuit 402 performs smoothing processing on the single-hop handshake time difference to eliminate high-frequency value jitter of the time difference; the reverse pressure bias voltage generator 403 receives the average delay time output by the low-pass filter circuit 402 and outputs the reverse bias voltage to the voltage-to-current converter 133 within the controlled dynamic impedance network 130.

[0105] In step S106-2, the voltage-to-current converter 133 receives the reverse bias voltage and outputs a dynamically adjustable current based on the amplitude of the reverse bias voltage; the amplitude of the dynamically adjustable current changes with the amplitude of the reverse bias voltage.

[0106] In step S106-3, the bias current source 131 in the controlled dynamic impedance network 130 outputs the static reference threshold current; the voltage-to-current converter 133 inputs the dynamically adjusted current to the superposition node 134; the bias current source 131 inputs the static reference threshold current to the superposition node 134; the dynamically adjusted current and the static reference threshold current converge at the superposition node 134.

[0107] In step S106-4, the controlled dynamic impedance network 130 outputs the adjusted cutoff threshold current at the superposition node 134; the adjusted cutoff threshold current is transmitted from the superposition node 134 to the differential comparator 140 in the analog impedance sensing mask unit 100; the differential comparator 140 receives the adjusted cutoff threshold current at the reference input terminal and receives multiple parallel characteristic input currents at the signal input terminal.

[0108] In step S106-5, when the communication link of the asynchronous event-driven hardware logic routing network 200 is congested, the amplitude of the reverse bias voltage output by the reverse bias voltage generator 403 increases; the voltage-to-current converter 133 responds to the increased reverse bias voltage and increases the output amplitude of the dynamically adjusted current; the amplitude of the cutoff threshold current converged at the superposition node 134 increases synchronously.

[0109] In step S106-6, the rising cutoff threshold current causes the differential comparator 140 to raise the comparison reference for level determination, and the screening threshold of the differential comparator 140 for the characteristic input current is raised accordingly; the number of input channels with amplitudes lower than the cutoff threshold current in the analog impedance sensing mask unit 100 increases.

[0110] In steps S106-7, the number of channels for the differential comparator 140 to output low-level control signals increases, and the low-level control signals are input to the corresponding channel's switching circuit 150; the number of switching circuits 150 in the high-impedance cutoff state increases, blocking the conduction path of the characteristic input current to the asynchronous pulse generator 120.

[0111] In steps S106-8, the number of valid physical signals received by the asynchronous pulse generator 120 decreases, and the number of asynchronous data packets encapsulated and output by the asynchronous pulse generator 120 decreases accordingly; the total amount of data injected into the asynchronous event-driven hardware logic routing network 200 decreases.

[0112] Steps S106-9: As the total amount of source data decreases, the buffer occupancy rate of routing nodes 210 within the asynchronous event-driven hardware logic routing network 200 decreases, and the queuing waiting time between routing nodes 210 is shortened; the cross-domain backpressure physical feedback loop 400 obtains the reduced single-hop handshake time difference.

[0113] In steps S106-10, as the average delay time decreases, the reverse bias voltage generator 403 correspondingly reduces the output amplitude of the reverse bias voltage; the voltage-to-current converter 133 in the controlled dynamic impedance network 130 reduces the dynamic adjustment current, and the cutoff threshold current decreases; the decrease in the cutoff threshold current increases the number of conduction channels in the analog impedance sensing mask unit 100, and the system tends to achieve a dynamic balance of adaptive negative feedback tuning.

[0114] Specifically, in step S107, asynchronous data packets transmitted at the end of the routing network are received through the asynchronous receiving interface 330. The internal data packet parsing circuit 331 performs packet unpacking processing, extracts the input channel identifier and the accumulated time delay feature from the data header, and extracts the digital feature from the payload segment. Then, the digital feature is transmitted to the feature digital-to-analog conversion network 332, and the time delay feature is transmitted to the voltage-controlled attenuator array 310, completing the separation and distribution of the data domain.

[0115] Specifically, in step S108, the time delay characteristic is received by the digital exponential mapping circuit 313 in the voltage-controlled attenuator array 310, and an exponential mapping operation is performed according to the hardware attenuation factor to output the attenuated digital quantity. The bias digital-to-analog converter 314 converts the attenuated digital quantity into an analog attenuated voltage and inputs it to the control terminal of the variable gain amplifier 312. At the same time, the characteristic digital-to-analog conversion network 332 converts the digital characteristic quantity into a characteristic reference voltage and inputs it to the signal terminal of the variable gain amplifier 312. Under the control of the analog attenuated voltage, the variable gain amplifier 312 performs amplitude attenuation on the characteristic reference voltage. The higher the congestion level and the greater the delay of the characteristic signal, the stronger its voltage amplitude attenuation, the lower the corresponding input amplitude, and the lower its contribution in subsequent in-memory calculations. Finally, the modulated characteristic voltage is output.

[0116] Specifically, in step S109, the streaming spatiotemporal data fusion and in-memory computing macro unit 300 performs timing alignment and rearrangement of the modulation characteristic voltages of each channel based on the arrival sequence of asynchronous data packets at the asynchronous receiving interface 330 and the timestamp information in the data packets. This reconstructs the discrete arriving asynchronous characteristic signals into a fused input vector that conforms to the multiply-accumulate array input format, providing a regular input signal for subsequent in-memory computing.

[0117] Specifically, in step S110, the voltage row driver 350 inputs the modulation characteristic voltage of each channel of the fused input vector to the word line corresponding to the analog cross-multiply-accumulate array 320 respectively; each resistive variable memory cell inside the array generates a branch current under the drive of the corresponding word line voltage according to its own conductance weight value. All branch currents in the same column converge at the bit line based on Kirchhoff's current law to form a converged current corresponding to the result of multiplying the input vector and the weight matrix, thus completing the multiply-accumulate operation in the analog domain.

[0118] Specifically, in step S111, the current sensing amplifier 340 collects the converged current of each column bit line, converts the current signal into a sensing voltage and amplifies it; the analog-to-digital converter 360 samples and quantizes the sensing voltage, outputs a tensor result in digital form, the timing alignment controller 370 controls the FIFO storage buffer array 371 to cache the tensor result, completes timing sorting according to the timestamp information in the data header, aligns the output protocol and outputs the final tensor result, after the quantization output is completed, the timing alignment controller 370 triggers the bit line reset circuit 380 to operate, injects a reset voltage into the bit line to discharge the residual charge in the array, so that the analog cross-multiply-accumulate array 320 returns to the initial state and prepares for the next cycle calculation.

Claims

1. An artificial intelligence chip processing system, characterized by, include: The system includes an analog impedance sensing mask unit (100), an asynchronous event-driven hardware logic routing network (200), a streaming spatiotemporal data fusion and in-memory computing macro unit (300), and a cross-domain backpressure physical feedback loop (400). The analog impedance sensing mask unit (100) is arranged on the input side of the artificial intelligence chip processing system, and its output is connected to an asynchronous pulse generator (120). The analog impedance sensing mask unit (100) is used to receive multi-source heterogeneous data streams, convert the discrete feature vectors in the multi-source heterogeneous data streams into physical current signals, and use the cutoff threshold current to physically truncate or allow the physical current signals. The asynchronous event-driven hardware logic routing network (200) is connected to the output of the asynchronous pulse generator (120); the asynchronous pulse generator (120) encapsulates the released physical current signal into an asynchronous data packet after amplitude quantization; the asynchronous event-driven hardware logic routing network (200) contains multiple routing nodes (210); the asynchronous data packet is transmitted between the routing nodes (210) according to the handshake protocol. The cross-domain reverse pressure physical feedback loop (400) is connected between the asynchronous event-driven hardware logic routing network (200) and the analog impedance sensing mask unit (100); the cross-domain reverse pressure physical feedback loop (400) is used to extract the handshake time difference of the routing node (210), convert the handshake time difference into a reverse bias voltage, and input the reverse bias voltage to the analog impedance sensing mask unit (100) to dynamically adjust the cutoff threshold current; The streaming spatiotemporal data fusion and in-memory computing macrocell (300) is connected to the output of the asynchronous event-driven hardware logic routing network (200) and is used to receive the asynchronous data packet containing the time delay feature, use the time delay feature to perform amplitude attenuation operation on the feature reference voltage corresponding to the asynchronous data packet, and inject the attenuated modulation feature voltage into the internal analog cross-multiply-accumulate array (320) to perform in-memory computing.

2. The artificial intelligence chip processing system of claim 1, wherein, The analog impedance sensing mask unit (100) includes a digital-to-analog conversion interface (110), a controlled dynamic impedance network (130), a differential comparator (140), and a switching circuit (150); The digital-to-analog converter interface (110) receives the multi-source heterogeneous data stream, converts the discrete feature vector into the physical current signal as the feature input current, and transmits the feature input current to the signal input terminal of the differential comparator (140). The controlled dynamic impedance network (130) is used to generate the cutoff threshold current and transmit the cutoff threshold current to the reference input of the differential comparator (140); The differential comparator (140) receives the characteristic input current and the cutoff threshold current in parallel, compares the amplitude of the characteristic input current and the amplitude of the cutoff threshold current in real time, and outputs the mask state parameter to the control terminal of the switching circuit (150) based on the comparison result. When the mask state parameter is 0, the differential comparator (140) outputs a low-level control signal, the switching circuit (150) is in the open state and switches to a high-impedance cutoff state, cutting off the conduction path of the characteristic input current; when the mask state parameter is 1, the differential comparator (140) outputs a high-level control signal, the switching circuit (150) is in the closed state and maintains a low-impedance conduction state, allowing the characteristic input current to be transmitted to the asynchronous pulse generator (120).

3. The artificial intelligence chip processing system according to claim 2, characterized in that, the mask state variable output by the differential comparator (140) the decision logic of the differential comparator (140) satisfies the following conditions: wherein, is the moment input channel a corresponding feature input current having an amplitude, is a cutoff threshold current output by the controlled dynamic impedance network (130) at the moment The dynamic modulation process of the cutoff threshold current satisfies the following calculation model: wherein, is the magnitude of the static reference threshold current, is the magnitude of the static reference threshold current, is the magnitude of the reverse bias voltage output by the cross-domain back pressure physical feedback loop (400) at the moment in time, is the transconductance conversion factor of the voltage-to-current converter (133).

4. The artificial intelligence chip processing system according to claim 2, characterized in that, The controlled dynamic impedance network (130) integrates a bias current source (131), a reference voltage source (132), a voltage-to-current converter (133), and a superposition node (134). The reference voltage source (132) is connected to the control terminal of the bias current source (131) and outputs a static constant voltage to make the bias current source (131) output a static reference threshold current. The voltage-to-current converter (133) receives the reverse bias voltage from the cross-domain reverse voltage physical feedback loop (400) and converts the reverse bias voltage into a dynamically regulated current. The output terminal of the voltage-to-current converter (133) and the output terminal of the bias current source (131) are connected in parallel at the superposition node (134). The dynamic adjustment current and the static reference threshold current are superimposed in the same direction at the superposition node (134) to generate the cutoff threshold current input to the differential comparator (140).

5. The artificial intelligence chip processing system according to claim 1, characterized in that, The asynchronous pulse generator (120) internally includes an analog-to-digital conversion module (121), a data packet encapsulation circuit (122), and a timestamp generator (123); The analog-to-digital conversion module (121) receives the released physical current signal and quantizes the amplitude of the physical current signal into a digital feature quantity. The timestamp generator (123) generates the initial timestamp for the current moment; The data packet encapsulation circuit (122) acquires the digital feature quantity, the input channel identifier of the corresponding feature signal, and the initial timestamp, and combines the three into an encapsulation to form the asynchronous data packet; wherein, the asynchronous data packet includes a data header and a payload segment, the data header records the input channel identifier and the initial timestamp, and the payload segment stores the digital feature quantity.

6. The artificial intelligence chip processing system according to claim 1, characterized in that, The routing node (210) is internally configured with an asynchronous controller (211) and a data buffer (212). Two adjacent routing nodes (210) on the communication link are divided into a front-end routing node and a back-end routing node. A data bus (213) and a handshake signal line containing a request line and an acknowledgment line are configured between the front-end routing node and the back-end routing node. The asynchronous controller (211) of the preceding routing node sends a logic high-level request signal to the following routing node through the request line; The asynchronous controller (211) of the downstream routing node detects the storage occupancy status of its own data buffer (212). When there is free storage space, it returns a logic high-level response signal to the upstream routing node through the response line. In response to the acknowledgment signal, the asynchronous controller (211) of the preceding routing node pushes the asynchronous data packet from the data buffer (212) of the preceding routing node to the data buffer (212) of the following routing node via the data bus (213). Upon detecting that the push is completed, the request signal is withdrawn on the request line, and the following routing node synchronously withdraws the acknowledgment signal.

7. The artificial intelligence chip processing system according to claim 6, characterized in that, The routing node (210) is equipped with a delay monitor (220), and the front-end routing node is equipped with a header update circuit (214) containing a hardware adder. The delay monitor (220) is physically connected in parallel to the request line and the response line. It uses the internal subtractor circuit (221) to subtract the second timestamp triggered by the recorded response signal from the first timestamp triggered by the request signal to generate a single-hop handshake time difference. The header update circuit (214) reads the single-hop handshake time difference and uses the hardware adder to accumulate the single-hop handshake time difference and write it into the header of the asynchronous data packet. The value accumulated by the multiple routing nodes (210) constitutes the time delay feature.

8. The artificial intelligence chip processing system according to claim 7, characterized in that, The cross-domain backpressure physical feedback loop (400) includes a congestion signal convergence bus (401), a low-pass filter circuit (402), a backpressure bias voltage generator (403), a congestion tolerance threshold register (404), a digital comparison circuit (405), and a digital-to-analog converter (406). The delay monitor (220) transmits the single-hop handshake time difference to the congestion signal aggregation bus (401). The low-pass filter circuit (402) receives the discrete single-hop handshake time difference sequence and performs an exponential moving average operation to output the average delay duration. The reverse bias voltage generator (403) is internally configured with a limiting amplifier circuit. The digital comparator circuit (405) receives the average delay duration and the congestion tolerance threshold output by the congestion tolerance threshold register (404) in parallel, performs a subtraction operation on the two, and outputs the digital difference. The digital-to-analog converter (406) converts the digital difference into an analog reference voltage and inputs it to the limiting amplifier circuit. The logic for generating the reverse bias voltage satisfies the following calculation formula: in, for The magnitude of the reverse bias voltage output by the reverse bias voltage generator (403) at that moment. for The average delay time of the output of the low-pass filter circuit (402) at the specified time. The congestion tolerance threshold is defined as follows. is the closed-loop voltage gain coefficient of the limiting amplifier circuit. This is the function for finding the maximum value.

9. The artificial intelligence chip processing system according to claim 1, characterized in that, The input side of the streaming spatiotemporal data fusion and in-memory computing macro unit (300) is equipped with an asynchronous receiving interface (330), which contains a voltage-controlled attenuator array (310). The asynchronous receiving interface (330) includes a data packet parsing circuit (331) and a feature digital-to-analog converter network (332); the data packet parsing circuit (331) extracts the time delay feature, input channel identifier and digital feature from the asynchronous data packet; the feature digital-to-analog converter network (332) converts the digital feature into a feature reference voltage; The voltage-controlled attenuator array (310) includes a delay voltage converter (311) and a variable gain amplifier (312); the delay voltage converter (311) converts the time delay characteristic into an analog attenuation voltage, which is input to the control input terminal of the variable gain amplifier (312); The variable gain amplifier (312) uses the analog attenuation voltage to perform an amplitude attenuation operation on the characteristic reference voltage at the input signal terminal, and outputs a modulation characteristic voltage for transmission to the analog cross-multiply-accumulate array (320).

10. The artificial intelligence chip processing system according to claim 9, characterized in that, The streaming spatiotemporal data fusion and in-memory computing macrocell (300) also includes an analog cross-multiply-accumulate array (320), a voltage row driver (350), a current sensing amplifier (340), an analog-to-digital converter (360), a timing alignment controller (370), a FIFO storage buffer array (371), and a bit line reset circuit (380). The voltage row driver (350) receives the modulation feature voltage and drives the word line input voltage of the analog cross-multiply-accumulate array (320). Each resistive variable memory cell inside the analog cross-multiply-accumulate array (320) generates a converged current on the bit line according to the conductance weight value and Kirchhoff's current law. The current sensing amplifier (340) converts the bit line converged current into a sensing voltage, and the analog-to-digital converter (360) samples and quantizes the sensing voltage to convert it into a tensor result in digital form; The timing alignment controller (370) controls the FIFO storage buffer array (371) to receive the tensor result, and performs buffering, sorting and alignment output on the tensor result according to the timestamp information in the data header; after the quantization output is completed, the bit line reset circuit (380) inputs a reset voltage to the bit line of the analog cross-multiply-accumulate array (320) to force the internal charge to be discharged.

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