Pin unit, chip, electronic device, and pin arrangement method

Abstract

The application discloses a pin unit, a chip, an electronic device and a pin arrangement method, and relates to the technical field of chip design. Since the pin unit comprises multiple pins, the pins in the pin unit are arranged in an array form, and the pin unit comprises two first pins, two second pins, four third pins, four fourth pins and multiple ground pins. The two first pins are a pair of differential signal pins, the two second pins are another pair of differential signal pins, the third pins and the fourth pins are single-ended signal pins. Therefore, the chip using the pin unit provided by the application can realize the transmission of double data rate signals. Since the rows and columns of the first pins and the second pins are different, that is, the rows and columns of different pairs of differential signal pins are different, compared with the same-row adjacent or same-column adjacent of different pairs of differential signal pins in the related art, the distance between different pairs of differential signal pins is increased, so that the electromagnetic crosstalk between different pairs of differential signal pins is reduced.

Description

Technical Field

[0001] This application belongs to the field of chip design technology, specifically relating to a pin unit, chip, electronic device, and pin arrangement method. Background Technology

[0002] In related technologies, in a set of pins corresponding to the 1-byte double data rate (DDR) channel of a chip, different pairs of differential signal pins are adjacent in the same row or column, resulting in large electromagnetic crosstalk between different pairs of differential signal pins. Summary of the Invention

[0003] This application aims to provide a pin unit, chip, electronic device, and pin arrangement method, which at least solves the problem in the related art that, in a group of pins corresponding to a 1-byte DDR channel of a chip, different pairs of differential signal pins are adjacent in the same row or column, resulting in large electromagnetic crosstalk between different pairs of differential signal pins.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, embodiments of this application provide a pin unit, the pin unit including a plurality of pins arranged in an array, the pin unit including two first pins, two second pins, four third pins and four fourth pins and a plurality of ground pins; the two first pins are a pair of differential signal pins, the two second pins are another pair of differential signal pins; the third pins and the fourth pins are both single-ended signal pins; The first pin and the second pin are different in both row and column.

[0005] Secondly, embodiments of this application also provide a chip including at least one row of pin units, each row of pin units including a plurality of pin units as described in the first aspect.

[0006] Thirdly, embodiments of this application also provide an electronic device, including the chip described in the second aspect.

[0007] Fourthly, embodiments of this application also provide a pin arrangement method, the method comprising: Two first pins, two second pins, four third pins, four fourth pins, and multiple ground pins are arranged in an array to obtain a pin unit; the two first pins are a pair of differential signal pins, and the two second pins are another pair of differential signal pins; the third pins and the fourth pins are both single-ended signal pins; the rows and columns of the first pins and the second pins are different; Arrange multiple pin units into a row to obtain a pin unit row; in the pin unit row, adjacent pin units have a common boundary, and the common boundary is composed of multiple ground pins; Arrange the multiple rows of pin units in an array to obtain the memory pin array of the chip.

[0008] In this embodiment, since the pin unit includes multiple pins arranged in an array, the pins in the pin unit include two first pins, two second pins, four third pins, four fourth pins, and multiple ground pins. The two first pins are a pair of differential signal pins, the two second pins are another pair of differential signal pins, and the third and fourth pins are single-ended signal pins. Therefore, the chip using the pin unit provided in this embodiment can achieve double data rate signal transmission. Furthermore, since the rows and columns of the first and second pins are different, that is, the rows and columns of different pairs of differential signal pins are different, compared with the related technology where different pairs of differential signal pins are adjacent in the same row or column, the distance between different pairs of differential signal pins is increased, thereby reducing electromagnetic crosstalk between different pairs of differential signal pins. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of a pin unit provided in an embodiment of this application; Figure 2 This is a schematic diagram of another pin unit structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of the motherboard wiring for a pin unit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the motherboard wiring for another pin unit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a pin unit row provided in an embodiment of this application; Figure 6 This is a schematic diagram of another pin unit row provided in an embodiment of this application; Figure 7 This is a schematic diagram of another pin unit row provided in the embodiments of this application; Figure 8 This is a flowchart of a pin arrangement method provided in an embodiment of this application.

[0010] Figure label: 10 - Pin unit; A1 - First pin; A2 - Second pin; A3 - Third pin; A4 - Fourth pin; B1 - Ground pin. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0013] Reference Figure 1 This application provides a pin unit 10, which includes a plurality of pins arranged in an array. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and a plurality of ground pins B1. The two first pins A1 are a pair of differential signal pins, and the two second pins A2 are another pair of differential signal pins. The third pins A3 and the fourth pins A4 are both single-ended signal pins. The rows and columns of the first pins A1 and the second pins A2 are different.

[0014] In some embodiments, the pins in pin unit 10 are memory pins (i.e., DDR pins) of the chip, the pins in pin unit 10 are disposed on the chip's packaging substrate, and all the pins in pin unit 10 are connected to the memory manager in the chip.

[0015] In some embodiments, the chip is a central processing unit (CPU) or a microcontroller unit (MCU). The memory manager includes a memory management unit (MMU), a DDR controller, and a physical layer transceiver (DDR PHY). The CPU core is connected to the CPU cache controller, the CPU cache controller is linked to the memory management unit, the memory management unit is connected to the DDR controller, the DDR controller is connected to the physical layer transceiver, the physical layer transceiver is connected to the pins in pin unit 10, the pins in pin unit 10 are connected to the memory traces on the motherboard, and the pins in pin unit 10 are connected to the corresponding pins in the dual in-line memory module socket (DIMM) through the memory traces on the motherboard. The DIMM is the memory module slot on the motherboard, and the pins in pin unit 10 are connected to the memory module through the DIMM.

[0016] In some embodiments, the DDR type of the pins in the pin unit 10 includes DDR3, DDR4, and DDR5, etc.

[0017] In some embodiments, pin unit 10 can realize signal transmission of a 1-byte double data rate channel. For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3 and four fourth pins A4, and multiple ground pins B1. Each third pin A3 can transmit 1 bit of data signal, each fourth pin A4 can transmit 1 bit of data signal, and the four third pins A3 and four fourth pins A4 can realize 8-bit data signal transmission.

[0018] In some embodiments, the third pin A3 is used to connect with the data signal pin corresponding to the third pin A3 of the motherboard's memory slot, and the fourth pin A4 is used to connect with the data signal pin corresponding to the fourth pin A4 of the motherboard's memory slot.

[0019] In some embodiments, ground pin B1 is used to connect to the ground plane of the motherboard.

[0020] In some embodiments, the two first pins A1 are used to transmit the differential data strobe signal (DQS) corresponding to the memory module of one motherboard, and the two second pins A2 are used to transmit the differential data strobe signal corresponding to the memory module of another motherboard.

[0021] In some embodiments, one first pin A1 is connected to a motherboard memory slot to transmit a first differential data strobe signal DQS0_P1, and the other first pin A1 is connected to a motherboard memory slot to transmit a second differential data strobe signal DQS0_N1. The first differential data strobe signal DQS0_P1 and the second differential data strobe signal DQS0_N1 are a pair of differential strobe signals.

[0022] In some embodiments, one second pin A2 is connected to the pin of the memory slot of another motherboard to transmit the third differential data strobe signal DQS0_P2, and the other second pin A2 is connected to the pin of the memory slot of another motherboard to transmit the fourth differential data strobe signal DQS0_N2. The third differential data strobe signal DQS0_P2 and the fourth differential data strobe signal DQS0_N2 are a pair of differential strobe signals.

[0023] In some embodiments, the pin unit 10 is an array consisting of two first pins A1, two second pins A2, four third pins A3 and four fourth pins A4, and a plurality of ground pins B1.

[0024] In some embodiments, the pins in pin unit 10 are arranged in a matrix.

[0025] In this embodiment, the pin unit 10 includes multiple pins arranged in an array. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. The two first pins A1 are a pair of differential signal pins, the two second pins A2 are another pair of differential signal pins, and the third pins A3 and fourth pins A4 are single-ended signal pins. Therefore, the chip containing the pin unit 10 provided in this embodiment can achieve double data rate signal transmission. Since the rows and columns of the first pins A1 and the second pins A2 are different, that is, the rows and columns of different pairs of differential signal pins are different, compared with the related technology where different pairs of differential signal pins are adjacent in the same row or column, the distance between different pairs of differential signal pins is increased, thereby reducing electromagnetic crosstalk between different pairs of differential signal pins.

[0026] Optionally, the two first pins A1 are located in the same column of the pin unit 10, the two second pins A2 are located in the same column of the pin unit 10, the four third pins A3 are located in the same column of the pin unit 10, and the four fourth pins A4 are located in the same column of the pin unit 10; wherein, the column containing the two first pins A1 is located between the column containing the four third pins A3 and the column containing the four fourth pins A4; and the column containing the two second pins A2 is located between the column containing the four third pins A3 and the column containing the four fourth pins A4.

[0027] For example, the two first pins A1 are located in the third column of the pin unit 10, the two second pins A2 are located in the fourth column of the pin unit 10, the four third pins A3 are located in the second column of the pin unit 10, and the four fourth pins A4 are located in the fifth column of the pin unit 10.

[0028] In this embodiment, since the two first pins A1 are located in the same column of the pin unit 10, the two second pins A2 are located in the same column of the pin unit 10, the four third pins A3 are located in the same column of the pin unit 10, and the four fourth pins A4 are located in the same column of the pin unit 10, and the column containing the two first pins A1 is located between the column containing the four third pins A3 and the column containing the four fourth pins A4, and the column containing the two second pins A2 is located between the column containing the four third pins A3 and the column containing the four fourth pins A4, and the data signal pins of the 1-byte channel of the motherboard's memory slot are located on both sides of the differential signal pins, the single-ended signal pins are located on both sides of the two pairs of differential signal pins, which is consistent with the pin arrangement of the motherboard's memory slot. This reduces the crossover of the pin unit 10 on the motherboard and shortens the trace length of the pin unit 10 on the motherboard, which is beneficial to the design of the motherboard traces of the pin unit 10.

[0029] Optionally, in some embodiments, the columns containing the two first pins A1 are adjacent to the columns containing the two second pins A2 and the columns containing the four third pins A3, respectively, and the columns containing the two second pins A2 are adjacent to the columns containing the four fourth pins A4.

[0030] For example, two first pins A1 are set in the third column of pin unit 10, two second pins A2 are set in the fourth column of pin unit 10, four third pins A3 are set in the second column of pin unit 10, and four fourth pins A4 are set in the fifth column of pin unit 10.

[0031] In this embodiment, since the columns containing the two first pins A1 are adjacent to the columns containing the two second pins A2 and the columns containing the four third pins A3, and the columns containing the two second pins A2 are adjacent to the columns containing the four fourth pins A4, that is, the columns containing the four third pins A3, the columns containing the two first pins A1, the columns containing the two second pins A2 and the columns containing the four fourth pins A4 are arranged sequentially adjacent to each other. Compared with the arrangement of the columns containing the four third pins A3, the columns containing the two first pins A1, the columns containing the two second pins A2 and the columns containing the four fourth pins A4 with the grounded pins B1 spaced apart, the number of pins in the pin unit 10 is reduced, thereby reducing the area occupied by the pin unit 10, which is beneficial to the miniaturization design of the chip package.

[0032] Optionally, in some embodiments, the four third pins A3 are arranged adjacent to each other in sequence; the four fourth pins A4 are arranged adjacent to each other in sequence; the two first pins A1 are adjacent to each other; and the two second pins A2 are adjacent to each other.

[0033] For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. Specifically, the first first pin A1 is located in the fourth row of pin unit 10, and the second first pin A1 is located in the fifth row of pin unit 10; the first second pin A2 is located in the second row of pin unit 10, and the second second second pin A2 is located in the third row of pin unit 10; the first third pin A3 is located in the fifth row of pin unit 10. In the second row of unit 10, the second third pin A3 is set in the third row of pin unit 10, the third third pin A3 is set in the fourth row of pin unit 10, and the fourth third pin A3 is set in the fifth row of pin unit 10; the first fourth pin A4 is set in the second row of pin unit 10, the second fourth pin A4 is set in the third row of pin unit 10, the third fourth pin A4 is set in the fourth row of pin unit 10, and the fourth fourth pin A4 is set in the fifth row of pin unit 10.

[0034] In this embodiment, since the four third pins A3 are arranged adjacent to each other, the four fourth pins A4 are arranged adjacent to each other, the two first pins A1 are adjacent to each other, and the two second pins A2 are adjacent to each other, the number of pins in the pin unit 10 is reduced compared with the arrangement of the grounded pins B1 between the pins in the same column, thereby reducing the area occupied by the pin unit 10, which is beneficial to the miniaturization design of the chip package.

[0035] Optionally, in some embodiments, each first pin A1 has a corresponding third pin A3 and a fourth pin A4, and each second pin A2 has a corresponding third pin A3 and a fourth pin A4; the first pin A1 and its corresponding third pin A3 and fourth pin A4 are arranged in the same row; the second pin A2 and its corresponding third pin A3 and fourth pin A4 are arranged in the same row.

[0036] For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. Specifically, the first first pin A1, the third third pin A3, and the third fourth pin A4 correspond to each other; the second first pin A1, the fourth third pin A3, and the fourth fourth pin A4 correspond to each other; the first second pin A2, the first third pin A3, and the first fourth pin A4 correspond to each other; and the second second pin A2, the second third pin A3, and the second fourth pin A4 correspond to each other. The first first pin A1 is set in the 4th row of pin unit 10, and the second first pin A1 is set in the 5th row of pin unit 10; the first second pin A2 is set in the 2nd row of pin unit 10, and the second second pin A2 is set in the 3rd row of pin unit 10; the first third pin A3 is set in the 2nd row of pin unit 10, the second third pin A3 is set in the 3rd row of pin unit 10, the third third pin A3 is set in the 4th row of pin unit 10, and the fourth third pin A3 is set in the 5th row of pin unit 10; the first fourth pin A4 is set in the 2nd row of pin unit 10, the second fourth pin A4 is set in the 3rd row of pin unit 10, the third fourth pin A4 is set in the 4th row of pin unit 10, and the fourth fourth pin A4 is set in the 5th row of pin unit 10.

[0037] In this embodiment, since the first pin A1 and the corresponding third pin A3 and fourth pin A4 are arranged in the same row, and the second pin A2 and the corresponding third pin A3 and fourth pin A4 are arranged in the same row, compared with single-ended signal pins and differential signal pins not being arranged in different rows, the number of pins in the pin unit 10 is reduced, thereby reducing the area occupied by the pin unit 10, which is beneficial to the miniaturization design of chip packaging.

[0038] Optionally, in some embodiments, a grounding pin B1 is provided between the first pin A1 and the fourth pin A4 corresponding to the first pin A1; a grounding pin B1 is provided between the second pin A2 and the third pin A3 corresponding to the second pin A2.

[0039] For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple grounding pins B1. Specifically, the first first pin A1, the third third pin A3, and the third fourth pin A4 correspond; the second first pin A1, the fourth third pin A3, and the fourth fourth pin A4 correspond; the first second pin A2, the first third pin A3, and the first fourth pin A4 correspond; the second second pin A2, the second third pin A3, and the second fourth pin A4 correspond; a grounding pin B1 is provided in the second row and third column of pin unit 10; a grounding pin B1 is provided in the third row and third column of pin unit 10; a grounding pin B1 is provided in the fourth row and fourth column of pin unit 10; and a grounding pin B1 is provided in the fifth row and fourth column of pin unit 10. The first pin A1 is located in the 4th row and 3rd column of pin unit 10; the second pin A1 is located in the 5th row and 3rd column of pin unit 10; the first pin A2 is located in the 2nd row and 4th column of pin unit 10; the second pin A2 is located in the 3rd row and 4th column of pin unit 10; the first pin A3 is located in the 2nd row and 2nd column of pin unit 10; the second pin A3 is located in the 3rd row and 2nd column of pin unit 10. The third third pin A3 is located in the 4th row and 2nd column of pin unit 10, and the fourth third pin A3 is located in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is located in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is located in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is located in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is located in the 5th row and 5th column of pin unit 10.

[0040] In this embodiment, a grounding pin B1 is provided between the first pin A1 and the fourth pin A4 corresponding to the first pin A1. This helps to reduce electromagnetic crosstalk between the first pin A1 and the fourth pin A4 corresponding to the first pin A1, and also provides a return reference ground for the first pin A1 or the fourth pin A4 corresponding to the first pin A1, thereby improving the signal quality of the first pin A1 and the fourth pin A4 corresponding to the first pin A1. Similarly, a grounding pin B1 is provided between the second pin A2 and the third pin A3 corresponding to the second pin A2. This helps to reduce electromagnetic crosstalk between the second pin A2 and the third pin A3 corresponding to the second pin A2, and also provides a return reference ground for the second pin A2 or the third pin A3 corresponding to the second pin A2, thereby improving the signal quality of the second pin A2 and the third pin A3 corresponding to the second pin A2.

[0041] Optionally, in some embodiments, a first pin A1, a third pin A3, a fourth pin A4, and a plurality of ground pins B1 constitute the boundary of the pin unit 10, wherein the first pin A1, the third pin A3, and the fourth pin A4 are disposed on the same side of the pin unit 10; or: a second pin A2, a third pin A3, a fourth pin A4, and a plurality of ground pins B1 constitute the boundary, wherein the second pin A2, the third pin A3, and the fourth pin A4 are disposed on the same side of the pin unit 10.

[0042] For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. Specifically, the pins in the first row, the first column, and the sixth column of pin unit 10 are all ground pins B1, and a ground pin B1 is located in the fifth row and fourth column of pin unit 10. The first first pin A1 is located in the fourth row and third column of pin unit 10, and the second first pin A1 is located in the fifth row and third column of pin unit 10. The first second pin A2 is located in the second row and fourth column of pin unit 10, and the second second pin A2 is located in the [missing information - likely a specific location or component]. The 3rd row and 4th column; the first third pin A3 is set in the 2nd row and 2nd column of pin unit 10, the second third pin A3 is set in the 3rd row and 2nd column of pin unit 10, the third third pin A3 is set in the 4th row and 2nd column of pin unit 10, the fourth third pin A3 is set in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is set in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is set in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is set in the 4th row and 5th column of pin unit 10, the fourth fourth pin A4 is set in the 5th row and 5th column of pin unit 10.

[0043] For example, the pins in pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. Specifically, the pins in the first row, first column, and sixth column of pin unit 10 are all ground pins B1, and a ground pin B1 is located in the fifth row and third column of pin unit 10. The first first pin A1 is located in the second row and third column of pin unit 10, and the second first pin A1 is located in the third row and third column of pin unit 10. The first second pin A2 is located in the fourth row and fourth column of pin unit 10, and the second second pin A2 is located in the fourth row and fourth column of pin unit 10. The 5th row and 4th column; the first third pin A3 is set in the 2nd row and 2nd column of pin unit 10, the second third pin A3 is set in the 3rd row and 2nd column of pin unit 10, the third third pin A3 is set in the 4th row and 2nd column of pin unit 10, the fourth third pin A3 is set in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is set in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is set in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is set in the 4th row and 5th column of pin unit 10, the fourth fourth pin A4 is set in the 5th row and 5th column of pin unit 10.

[0044] In this embodiment, since a first pin A1, a third pin A3, a fourth pin A4, and multiple ground pins B1 form the boundary of the pin unit 10, and the first pin A1, third pin A3, and fourth pin A4 are located on the same side of the pin unit 10, the boundaries of the remaining sides of the pin unit 10 are composed of multiple ground pins B1. This helps to prevent electromagnetic crosstalk between the pin units 10. The motherboard traces for data signal pins and differential signal pins can be routed from the pin units where the first pin A1, third pin A3, and fourth pin A4 are located. One side of pin 10 is led out; since a second pin A2, a third pin A3, a fourth pin A4 and multiple ground pins B1 form a boundary, and the second pin A2, the third pin A3 and the fourth pin A4 in the boundary are located on the same side of pin unit 10, the boundary of the other side of pin unit 10 is composed of multiple ground pins B1, which helps to prevent electromagnetic crosstalk between pin units 10, and the motherboard traces of data signal pins and differential signal pins can be led out from one side of pin unit 10 where the second pin A2, the third pin A3 and the fourth pin A4 are located in the boundary.

[0045] Reference Figure 1In some embodiments, the first array is a 5-row × 6-column matrix. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and eighteen ground pins B1. Specifically, the pins in the first row, the first column, and the sixth column of the pin unit 10 are all ground pins B1, and the pins in the fifth row and the fourth column of the pin unit 10 are ground pins B1. A ground pin B1 is provided in the second row and third column of the pin unit 10, a ground pin B1 is provided in the third row and third column of the pin unit 10, a ground pin B1 is provided in the fourth row and fourth column of the pin unit 10, and a ground pin B1 is provided in the fifth row and fourth column of the pin unit 10. The first pin A1 is located in the 4th row and 3rd column of pin unit 10; the second pin A1 is located in the 5th row and 3rd column of pin unit 10; the first pin A2 is located in the 2nd row and 4th column of pin unit 10; the second pin A2 is located in the 3rd row and 4th column of pin unit 10; the first pin A3 is located in the 2nd row and 2nd column of pin unit 10; the second pin A3 is located in the 3rd row and 2nd column of pin unit 10. The third third pin A3 is located in the 4th row and 2nd column of pin unit 10, and the fourth third pin A3 is located in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is located in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is located in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is located in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is located in the 5th row and 5th column of pin unit 10.

[0046] Reference Figure 2 In some embodiments, the first array is a 5-row × 6-column matrix. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and eighteen ground pins B1. Specifically, the pins in the first row, the first column, and the sixth column of the pin unit 10 are all ground pins B1, and the pins in the fifth row and the fourth column of the pin unit 10 are ground pins B1. A ground pin B1 is provided in the fourth row and third column of the pin unit 10, a ground pin B1 is provided in the fifth row and third column of the pin unit 10, a ground pin B1 is provided in the second row and fourth column of the pin unit 10, and a ground pin B1 is provided in the third row and fourth column of the pin unit 10. The first first pin A1 is located in the second row and third column of pin unit 10, and the second first pin A1 is located in the third row and third column of pin unit 10; the first second pin A2 is located in the fourth row and fourth column of pin unit 10, and the second second pin A2 is located in the fifth row and fourth column of pin unit 10; the first third pin A3 is located in the second row and second column of pin unit 10, and the second third pin A3 is located in the third row and second column of pin unit 10. The third third pin A3 is located in the 4th row and 2nd column of pin unit 10, and the fourth third pin A3 is located in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is located in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is located in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is located in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is located in the 5th row and 5th column of pin unit 10.

[0047] In related technologies, the number of pins in a group of pins corresponding to a 1-byte DDR channel of a chip is 35.

[0048] In this embodiment, the number of pins in the pin unit 10 corresponding to the 1-byte DDR channel is 30, which is 35 in a group of pins corresponding to the 1-byte DDR channel in the related technology. This reduces the number of pins in the pin unit 10, thereby reducing the area occupied by the pin unit 10, which is beneficial to the miniaturization design of the chip package.

[0049] Optionally, in some embodiments, when the boundary is composed of a first pin A1, a third pin A3, a fourth pin A4, and a plurality of ground pins B1: the motherboard trace of the first pin A1 in the boundary extends away from the pin unit 10, and the motherboard trace of another first pin A1 extends between the first pin A1 and the third pin A3 in the boundary; the motherboard trace of each second pin A2 extends from the ground pin B1 adjacent to the first pin A1 in the boundary and the first pin A1; the motherboard trace of the third pin A3 in the boundary extends away from the pin unit 10, and the other two third pins A3... All board traces originate from the boundary between the ground pin B1 adjacent to the third pin A3 and the third pin A3; the other motherboard trace of the third pin A3 originates from the boundary between the first pin A1 and the third pin A3; the motherboard trace of the fourth pin A4 in the boundary extends away from the pin unit 10; the other two motherboard traces of the fourth pin A4 originate from the boundary between the ground pin B1 adjacent to the fourth pin A4 and the fourth pin A4; the other motherboard trace of the fourth pin A4 originates from the boundary between the other ground pin B1 adjacent to the fourth pin A4 and the fourth pin A4.

[0050] In some embodiments, the motherboard trace of the first pin A1 is the memory trace of the motherboard connected to the first pin A1. The first pin A1 is connected to a memory slot and a corresponding pin for transmitting differential signals via the motherboard trace of the first pin A1; the motherboard trace of the second pin A2 is the memory trace of the motherboard connected to the second pin A2. The second pin A2 is connected to another memory slot and a corresponding pin for transmitting differential signals via the motherboard trace of the second pin A2; the motherboard trace of the third pin A3 is the memory trace of the motherboard connected to the third pin A3. The third pin A3 is connected to a memory slot and a corresponding pin for transmitting data signals via the motherboard trace of the third pin A3; the motherboard trace of the fourth pin A4 is the memory trace of the motherboard connected to the fourth pin A4. The fourth pin A4 is connected to a memory slot and a corresponding pin for transmitting data signals via the motherboard trace of the fourth pin A4.

[0051] In some embodiments, in pin unit 10: the first column and the sixth column are each composed of multiple ground pins B1; the motherboard trace of another first pin A1 in the third column is located between the second column and the third column; the motherboard trace of each second pin A2 is located between the third column and the fourth column; the motherboard traces of the other two third pins A3 in the second column are located between the second column and the first column; the motherboard trace of the other third pin A3 in the second column is located between the second column and the third column; the motherboard traces of the other two fourth pins A4 in the fifth column are located between the fifth column and the fourth column; the motherboard trace of the other fourth pin A4 in the fifth column is located between the fifth column and the sixth column.

[0052] Reference Figure 3 In some embodiments, the first array is a 5-row × 6-column matrix. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and eighteen ground pins B1. Specifically, the pins in the first row, the first column, and the sixth column of the pin unit 10 are all ground pins B1, and the pins in the fifth row and the fourth column of the pin unit 10 are ground pins B1. A ground pin B1 is provided in the second row and third column of the pin unit 10, a ground pin B1 is provided in the third row and third column of the pin unit 10, a ground pin B1 is provided in the fourth row and fourth column of the pin unit 10, and a ground pin B1 is provided in the fifth row and fourth column of the pin unit 10. The first pin A1 is located in the 4th row and 3rd column of pin unit 10; the second pin A1 is located in the 5th row and 3rd column of pin unit 10; the first pin A2 is located in the 2nd row and 4th column of pin unit 10; the second pin A2 is located in the 3rd row and 4th column of pin unit 10; the first pin A3 is located in the 2nd row and 2nd column of pin unit 10; the second pin A3 is located in the 3rd row and 2nd column of pin unit 10. The third third pin A3 is located in the 4th row and 2nd column of pin unit 10, and the fourth third pin A3 is located in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is located in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is located in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is located in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is located in the 5th row and 5th column of pin unit 10. The motherboard trace C5 of the first first pin A1 is located between the second and third columns of pin unit 10. The motherboard trace C5 of the first first pin A1 is led out from between the fourth third pin A3 and the second first pin A1. The motherboard trace C6 of the second first pin A1 is led out in a direction away from pin unit 10. The motherboard traces C7 and C8 of the first second pin A2 are both located between the third and fourth columns of pin unit 10. The motherboard traces C7 and C8 of the first second pin A2 are both led out from between the second first pin A1 and a grounding pin B1 located in the fifth row and fourth column of pin unit 10. The motherboard trace C4 of the first third pin A3 is located between the second and third columns of pin unit 10. The motherboard trace C4 of the first third pin A3 is led out from between the fourth third pin A3 and the second first pin A1. The motherboard trace C1 of the second third pin A3 and the motherboard trace C2 of the third third pin A3 are both located between the first and second columns of pin unit 10. The motherboard trace C1 of the second third pin A3 and the motherboard trace C2 of the third third pin A3 are both led out from between a ground pin B1 located in the fifth row and first column of pin unit 10 and the fourth third pin A3. The motherboard trace C3 of the fourth third pin A3 is led out in a direction away from pin unit 10. The motherboard trace C12 of the first fourth pin A4 is located between the 5th and 6th columns of pin unit 10. The motherboard trace C12 of the first fourth pin A4 is led out from between the fourth fourth pin A4 and a ground pin B1 located in the 5th row and 6th column of pin unit 10. The motherboard traces C9 of the second fourth pin A4 and C10 of the third fourth pin A4 are both located between the 4th and 5th columns of pin unit 10. The motherboard traces C9 of the second fourth pin A4 and C10 of the third fourth pin A4 are both led out from between a ground pin B1 located in the 5th row and 4th column of pin unit 10 and the fourth fourth pin A4. The motherboard trace C11 of the fourth fourth pin A4 is led out in a direction away from pin unit 10.

[0053] In this embodiment of the application, when a boundary is formed by a first pin A1, a third pin A3, a fourth pin A4, and multiple ground pins B1: the motherboard trace of the first pin A1 in the boundary is led out in a direction away from the pin unit 10, and the motherboard trace of another first pin A1 is led out between the first pin A1 and the third pin A3 in the boundary; the motherboard traces of the two second pins A2 are both led out between the ground pin B1 adjacent to the first pin A1 in the boundary and the first pin A1; the motherboard trace of the third pin A3 in the boundary is led out in a direction away from the pin unit 10; the motherboard traces of the other two third pins A3 are both led out between the ground pin B1 adjacent to the third pin A3 in the boundary and the third pin A3; and the third pin A1 is led out in a direction away from the pin unit 10. The motherboard trace of the other third pin A3 in pin 3 is led out from between the first pin A1 and the third pin A3 in the boundary, and the motherboard trace of the fourth pin A4 in the boundary is led out in a direction away from the pin unit 10. The motherboard traces of the other two fourth pins A4 in the fourth pin are led out from between a ground pin B1 adjacent to the fourth pin A4 in the boundary and the fourth pin A4. The motherboard trace of the other fourth pin A4 in the fourth pin is led out from between another ground pin B1 adjacent to the fourth pin A4 in the boundary and the fourth pin A4. This makes each differential signal pin and each data signal pin lead out from the same direction, reducing the crossover of the pin unit 10 on the motherboard traces and shortening the trace length of the pin unit 10 on the motherboard, which is beneficial to the design of the motherboard traces of the pin unit 10.

[0054] Optionally, in some embodiments, when the boundary is formed by a second pin A2, a third pin A3, a fourth pin A4, and a plurality of ground pins B1: the motherboard trace of each first pin A1 is led out from between the adjacent ground pin B1 and the second pin A2 in the boundary; the motherboard trace of the second pin A2 in the boundary is led out in a direction away from the pin unit 10, and the motherboard trace of another second pin A2 is led out from between the second pin A2 and the fourth pin A4 in the boundary; the motherboard trace of the third pin A3 in the boundary is led out in a direction away from the pin unit 10, and the other two third pins A3 are led out from between the second pin A2 and the fourth pin A4 in the boundary. All board traces originate from the boundary between a ground pin B1 adjacent to the third pin A3 and the third pin A3; another motherboard trace of the third pin A3 originates from the boundary between another ground pin B1 adjacent to the third pin A3 and the third pin A3; the motherboard trace of the fourth pin A4 in the boundary extends away from the pin unit 10; the other two motherboard traces of the fourth pin A4 originate from the boundary between a ground pin B1 adjacent to the fourth pin A4 and the fourth pin A4; the other motherboard trace of the fourth pin A4 originates from the boundary between the second pin A2 and the fourth pin A4.

[0055] In some embodiments, in pin unit 10: the first column and the sixth column are each composed of a plurality of ground pins B1, and the motherboard trace of each first pin A1 is disposed between the third column and the fourth column; the motherboard trace of another second pin A2 in the fourth column is disposed between the fourth column and the fifth column; the motherboard traces of the other two third pins A3 in the second column are disposed between the second column and the third column; the motherboard trace of the other third pin A3 in the second column is disposed between the second column and the first column; the motherboard traces of the other two fourth pins A4 in the fifth column are disposed between the fifth column and the sixth column; the motherboard trace of the other fourth pin A4 in the fifth column is disposed between the fourth column and the fifth column.

[0056] Reference Figure 4 In some embodiments, the first array is a 5-row × 6-column matrix. The pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and eighteen ground pins B1. The pins in the first row, the first column, and the sixth column of the pin unit 10 are all ground pins B1. A ground pin B1 is provided in the fourth row and third column of the pin unit 10, a ground pin B1 is provided in the fifth row and third column of the pin unit 10, a ground pin B1 is provided in the second row and fourth column of the pin unit 10, and a ground pin B1 is provided in the third row and fourth column of the pin unit 10. The first first pin A1 is located in the second row and third column of pin unit 10, and the second first pin A1 is located in the third row and third column of pin unit 10; the first second pin A2 is located in the fourth row and fourth column of pin unit 10, and the second second pin A2 is located in the fifth row and fourth column of pin unit 10; the first third pin A3 is located in the second row and second column of pin unit 10, and the second third pin A3 is located in the third row and second column of pin unit 10. The third third pin A3 is located in the 4th row and 2nd column of pin unit 10, and the fourth third pin A3 is located in the 5th row and 2nd column of pin unit 10; the first fourth pin A4 is located in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is located in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is located in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is located in the 5th row and 5th column of pin unit 10. The motherboard trace D5 of the first first pin A1 and the motherboard trace D6 of the second first pin A1 are both located between the 3rd and 4th columns of pin unit 10. The motherboard trace D5 of the first first pin A1 and the motherboard trace D6 of the second first pin A1 are both led out from between the second second pin A2 and a ground pin B1 located in the 5th row and 3rd column of pin unit 10. The motherboard trace D8 of the first second pin A2 is located between the 4th and 5th columns of pin unit 10. The motherboard trace D8 of the first second pin A2 is led out from between the fourth fourth pin A4 and the second second pin A2. The motherboard trace D7 of the second second pin A2 is led out in a direction away from pin unit 10. The motherboard trace D1 of the first third pin A3 is located between the first and second columns of pin unit 10. The motherboard trace D1 of the first third pin A3 is led out from between the fourth third pin A3 and a ground pin B1 located in the fifth row and first column of pin unit 10. The motherboard traces D4 and D3 of the second and third third pins A3 are both located between the second and third columns of pin unit 10. The motherboard traces D4 and D3 of the second and third third pins A3 are both led out from between a ground pin B1 located in the fifth row and third column of pin unit 10 and the fourth third pin A3. The motherboard trace D2 of the fourth third pin A3 is led out in a direction away from pin unit 10. The motherboard trace D9 of the first fourth pin A4 is located between the 4th and 5th columns of pin unit 10. The motherboard trace D9 of the first fourth pin A4 is led out from between the 4th fourth pin A4 and the 2nd second pin A2. The motherboard trace D12 of the 2nd fourth pin A4 and the motherboard trace D11 of the 3rd fourth pin A4 are both located between the 5th and 6th columns of pin unit 10. The motherboard trace D12 of the 2nd fourth pin A4 and the motherboard trace D11 of the 3rd fourth pin A4 are both led out from between a grounding pin B1 located in the 5th row and 6th column of pin unit 10 and the 4th fourth pin A4. The motherboard trace D10 of the 4th fourth pin A4 is led out in a direction away from pin unit 10.

[0057] In this embodiment of the application, when a boundary is formed by a second pin A2, a third pin A3, a fourth pin A4, and multiple ground pins B1, the motherboard traces of the two first pins A1 are led out from between the adjacent ground pin B1 and the second pin A2 in the boundary; the motherboard traces of the second pin A2 in the boundary are led out in a direction away from the pin unit 10; the motherboard trace of the other second pin A2 is led out from between the second pin A2 and the fourth pin A4 in the boundary; the motherboard traces of the third pin A3 in the boundary are led out in a direction away from the pin unit 10; the motherboard traces of the other two third pins A3 are led out from between the adjacent ground pin B1 and the third pin A3 in the boundary; and the third pin... The motherboard trace of the other third pin A3 in A3 is led out from the boundary between the adjacent ground pin B1 and the third pin A3. The motherboard trace of the fourth pin A4 in the boundary is led out in a direction away from the pin unit 10. The motherboard traces of the other two fourth pins A4 in the fourth pin A4 are led out from the boundary between the adjacent ground pin B1 and the fourth pin A4. The motherboard trace of the other fourth pin A4 in the fourth pin A4 is led out from the boundary between the second pin A2 and the fourth pin A4. This makes each differential signal pin and each data signal pin lead out from the same direction, reducing the crossover of the pin unit 10 on the motherboard and shortening the trace length of the pin unit 10 on the motherboard, which is beneficial to the design of the motherboard traces of the pin unit 10.

[0058] This application also provides a chip including at least one row of pin units, each row of pin units including a plurality of pin units 10 as described above. The specific implementation process of the pin units 10 in the chip is similar to the aforementioned implementation process of the pin units 10, and will not be repeated here.

[0059] For example, the chip includes two rows of pin cells, and each row of pin cells includes nine pin cells.

[0060] In some embodiments, a pin unit row corresponds to two memory slots on the motherboard, and the pin unit row is connected to each memory slot corresponding to the pin unit row.

[0061] In some embodiments, one memory slot corresponding to one pin row is located on the first side of the motherboard, and another memory slot corresponding to one pin row is located on the second side of the motherboard.

[0062] In some embodiments, a pin cell row including M pin cells 10 can achieve a data width of 8×M bits, where M is a positive integer. For example, a pin cell row including 4 pin cells 10 can achieve a data width of 32 bits, and a pin cell row including 8 pin cells 10 can achieve a data width of 64 bits.

[0063] In some embodiments, a pin cell row including M+1 pin cells 10 can implement an 8×M bit data width and an 8-bit error-correcting code (ECC). For example, a pin cell row including 5 pin cells 10 can implement a 32-bit data width and an 8-bit error-correcting code. Or, for example, a pin cell row including 9 pin cells 10 can implement a 64-bit data width and an 8-bit error-correcting code.

[0064] Optionally, in some embodiments, the pin units 10 in the pin unit row are arranged in a row; in the pin unit row, adjacent pin units 10 have a common boundary, which is composed of a plurality of ground pins B1.

[0065] For example, a pin cell row includes 9 pin cells 10, and each pin cell 10 includes 6 columns. For example, the first pin cell 10 and the second pin cell 10 have a common boundary, that is, the 6th column of the first pin cell 10 and the 1st column of the second pin cell 10 are the same column.

[0066] In this embodiment, since the pin units 10 in the pin unit row are arranged in a row, the crossover of different pin units 10 on the motherboard is reduced and the trace length of the pin units 10 on the motherboard is shortened, which is beneficial to the design of the motherboard traces of the pin units 10. Since adjacent pin units 10 in the pin unit row have a common boundary, and the common boundary is composed of multiple ground pins B1, the number of ground pins B1 in the boundary of the pin unit 10 is reduced, thereby reducing the area occupied by the pin unit row, which is beneficial to the miniaturization design of the chip package.

[0067] In some embodiments, in the pin unit row, the motherboard traces of the first pin A1, the second pin A2, the third pin A3, and the fourth pin A4 in each pin unit 10 are all in the same direction. This reduces the overlap of the motherboard traces of different pin units 10 in the pin unit row and shortens the trace length of the pin units 10 on the motherboard, which is beneficial to the design of the motherboard traces of the pin units 10.

[0068] In some embodiments, each pin unit 10 includes n rows of pins, and the first row of pins in each pin unit 10 consists of ground pins B1; the nth row of each pin unit 10 is composed of a first pin A1, a third pin A3, a fourth pin A4 and multiple ground pins B1, or is composed of a second pin A2, a third pin A3, a fourth pin A4 and multiple ground pins B1. Then, the motherboard traces for the first pin A1, the motherboard traces for the second pin A2, and the third pin A3 in each pin unit 10 are... Both the motherboard traces for pin A3 and the motherboard trace for pin A4 can be routed from the nth row of pin unit 10. In each pin unit 10, the single-ended signal pins are positioned on both sides of two pairs of differential signal pins, consistent with the pin arrangement of the motherboard's memory slots. This ensures that the pin arrangement of the pin unit row is consistent with the pin arrangement of the corresponding memory slot, reducing the overlap of different pin units 10 on the motherboard traces and shortening the trace length of pin units 10 on the motherboard, which is beneficial for the design of motherboard traces in the pin unit row; n is a positive integer.

[0069] Since each pin unit 10's nth row consists of a first pin A1, a third pin A3, a fourth pin A4, and multiple ground pins B1, or a second pin A2, a third pin A3, a fourth pin A4, and multiple ground pins B1, the motherboard traces for the first pin A1, second pin A2, third pin A3, and fourth pin A4 in each pin unit 10 can all be routed out from the nth row of pin unit 10. This allows the motherboard traces for the first pin A1, second pin A2, third pin A3, and fourth pin A4 in each pin unit 10 to be routed along the pin unit row on the motherboard's printed circuit board (PCB). The same layer of the motherboard allows for routing of a single pin unit row, which reduces the number of motherboard layers required compared to related technologies where a set of pins corresponding to a memory slot requires routing across multiple layers of the motherboard.

[0070] Optionally, in some embodiments, when there are multiple rows of pins in the chip, the rows of pins in the chip are arranged in an array.

[0071] For example, the chip includes two rows of pin units, which form a 2-row × 1-column array.

[0072] In this embodiment, since the pin unit rows of the chip are arranged in an array when there are multiple pin unit rows, the crossover of the pin units 10 on the motherboard is reduced and the trace length of the pin units 10 on the motherboard is shortened, which is beneficial to the design of the motherboard traces of the pin units 10.

[0073] Reference Figure 5 In some embodiments, each pin unit 10 in the pin unit row is identical, wherein each pin unit 10 has a ground pin B1 in the second row and third column, a ground pin B1 in the third row and third column, a ground pin B1 in the fourth row and fourth column, and a ground pin B1 in the fifth row and fourth column; a first first pin A1 is located in the fourth row and third column of the pin unit 10, a second first pin A1 is located in the fifth row and third column of the pin unit 10; a first second pin A2 is located in the second row and fourth column of the pin unit 10, and a second second pin A2 is located in the third row and fourth column of the pin unit 10.

[0074] Reference Figure 6 In some embodiments, each pin unit 10 in the pin unit row is identical, wherein a ground pin B1 is provided in the 4th row and 3rd column of the pin unit 10, a ground pin B1 is provided in the 5th row and 3rd column of the pin unit 10, a ground pin B1 is provided in the 2nd row and 4th column of the pin unit 10, and a ground pin B1 is provided in the 3rd row and 4th column of the pin unit 10; a first first pin A1 is provided in the 2nd row and 3rd column of the pin unit 10, a second first pin A1 is provided in the 3rd row and 3rd column of the pin unit 10; a first second pin A2 is provided in the 4th row and 4th column of the pin unit 10, and a second second pin A2 is provided in the 5th row and 4th column of the pin unit 10.

[0075] Reference Figure 7In some embodiments, at least a portion of the pin units 10 in a pin unit row are identical. For example, the first pin unit 10 is the same as the third pin unit 10, and the first pin unit 10 is different from the second pin unit 10. Specifically, in the first and third pin units 10, a ground pin B1 is provided in the fourth row and third column of the pin unit 10, and a ground pin B1 is provided in the fifth row and third column of the pin unit 10. Unit 10 has a grounding pin B1 in the second row and fourth column, and a grounding pin B1 in the third row and fourth column; the first pin A1 is located in the second row and third column of pin unit 10, and the second pin A1 is located in the third row and third column of pin unit 10; the first pin A2 is located in the fourth row and fourth column of pin unit 10, and the second pin A2 is located in the fifth row and fourth column of pin unit 10. In the second pin unit 10, a grounding pin B1 is provided in the second row and third column, the third row and third column, the fourth row and fourth column, and the fifth row and fourth column of the pin unit 10; the first first pin A1 is provided in the fourth row and third column of the pin unit 10, and the second first pin A1 is provided in the fifth row and third column of the pin unit 10; the first second pin A2 is provided in the second row and fourth column of the pin unit 10, and the second second pin A2 is provided in the third row and fourth column of the pin unit 10.

[0076] This application also provides an electronic device, including the chip as described above. The specific implementation process of the pin unit 10 in the chip of the electronic device is similar to the implementation process of the pin unit 10 described above, and will not be repeated here.

[0077] In the embodiments of this application, the signal pins in each pin unit 10 are symmetrical about the left and right sides. While ensuring that each DDR signal has a return reference ground, the arrangement area of ​​each pin unit 10 is effectively reduced. At the same time, the DDR signals between different pin units 10 are isolated, reducing electromagnetic crosstalk between different pin units 10.

[0078] In summary, in this embodiment, since the pin unit 10 includes multiple pins arranged in an array, the pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1. The two first pins A1 are a pair of differential signal pins, the two second pins A2 are another pair of differential signal pins, and the third pins A3 and fourth pins A4 are single-ended signal pins. Therefore, the chip using the pin unit 10 provided in this embodiment can achieve double data rate signal transmission. Furthermore, since the rows and columns of the first pins A1 and the second pins A2 are different, that is, the rows and columns of different pairs of differential signal pins are different, compared with the related technology where different pairs of differential signal pins are adjacent in the same row or column, the distance between different pairs of differential signal pins is increased, thereby reducing electromagnetic crosstalk between different pairs of differential signal pins.

[0079] Reference Figure 8 This application also provides a pin arrangement method, which includes the following steps: Step 101: Arrange two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1 in an array to obtain pin unit 10; the two first pins A1 are a pair of differential signal pins, and the two second pins A2 are another pair of differential signal pins; the third pins A3 and the fourth pins A4 are both single-ended signal pins; the rows and columns of the first pins A1 and the second pins A2 are different.

[0080] For example, the first array is set as a 5x6 matrix. The pins in the first row, first column, and sixth column of pin unit 10 are all ground pins B1. The pins in the fifth row and fourth column of pin unit 10 are also set as ground pins B1. A ground pin B1 is also set in the second row and third column, the third row and third column, the fourth row and fourth column, and the fifth row and fourth column of pin unit 10. Furthermore, the first first pin A1 is set in the fourth row and third column of pin unit 10, the second first pin A1 is set in the fifth row and third column of pin unit 10, the first second pin A2 is set in the second row and fourth column of pin unit 10, and the second second pin A2 is set in the fifth row and sixth column of pin unit 10. In the 3rd row and 4th column, the first third pin A3 is set in the 2nd row and 2nd column of pin unit 10, the second third pin A3 is set in the 3rd row and 2nd column of pin unit 10, the third third pin A3 is set in the 4th row and 2nd column of pin unit 10, the fourth third pin A3 is set in the 5th row and 2nd column of pin unit 10, the first fourth pin A4 is set in the 2nd row and 5th column of pin unit 10, the second fourth pin A4 is set in the 3rd row and 5th column of pin unit 10, the third fourth pin A4 is set in the 4th row and 5th column of pin unit 10, and the fourth fourth pin A4 is set in the 5th row and 5th column of pin unit 10 to form pin unit 10.

[0081] In this embodiment of the application, a pin unit 10 is obtained by arranging two first pins A1, two second pins A2, four third pins A3 and four fourth pins A4 and multiple ground pins B1 in an array, thereby forming a set of pins corresponding to a 1-byte DDR channel.

[0082] Step 102: Arrange the multiple pin units 10 into a row to obtain a pin unit row; in the pin unit row, adjacent pin units 10 have a common boundary, and the common boundary is composed of multiple ground pins B1.

[0083] For example, nine pin units 10 are arranged into a pin unit row. Each pin unit 10 includes m columns, where m is a positive integer. Specifically, the m-th column of the first pin unit 10 is the same as the first column of the second pin unit 10, the m-th column of the second pin unit 10 is the same as the first column of the third pin unit 10, the m-th column of the third pin unit 10 is the same as the first column of the fourth pin unit 10, and so on. Column m is the same column as column 1 of the 5th pin unit 10; column m of the 5th pin unit 10 is the same column as column 1 of the 6th pin unit 10; column m of the 6th pin unit 10 is the same column as column 1 of the 7th pin unit 10; column m of the 7th pin unit 10 is the same column as column 1 of the 8th pin unit 10; and column m of the 8th pin unit 10 is the same column as column 1 of the 9th pin unit 10.

[0084] In this embodiment of the application, a pin unit row is obtained by arranging multiple pin units 10 into a row to form a pin unit row corresponding to the memory module slot.

[0085] Step 103: Arrange the multiple pin units in an array to obtain the memory pin array of the chip.

[0086] For example, two pin units can be arranged vertically in a 2-row, 1-column array to form the chip's memory pin array.

[0087] In this embodiment of the application, the memory pin array of the chip is obtained by arranging the multiple pin unit rows in an array, so as to realize the memory pin arrangement of the chip.

[0088] In this embodiment, a pin unit 10 is obtained by arranging two first pins A1, two second pins A2, four third pins A3, four fourth pins A4, and multiple ground pins B1 in an array. Then, multiple pin units 10 are arranged in rows to form pin unit rows. Finally, multiple pin unit rows are arranged in an array to obtain the chip's memory pin array, thus realizing the chip's memory pin arrangement. Since each pin unit 10 includes multiple pins, and the pins in the pin unit 10 are arranged in an array, the pins in the pin unit 10 include two first pins A1, two second pins A2, four third pins A3, and four fourth pins A4. 4. The chip with pin unit 10 provided in this application embodiment can realize the transmission of double data rate signals by using the pin unit 10 and multiple ground pins B1. The two first pins A1 are a pair of differential signal pins, the two second pins A2 are another pair of differential signal pins, and the third pin A3 and the fourth pin A4 are single-ended signal pins. Since the first pins A1 and the second pins A2 are in different rows and columns, that is, the rows and columns of different pairs of differential signal pins are different, compared with the related technology where different pairs of differential signal pins are adjacent in the same row or column, the distance between different pairs of differential signal pins is increased, thereby reducing the electromagnetic crosstalk between different pairs of differential signal pins.

[0089] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0090] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A pin unit (10), characterized in that, The pin unit (10) includes multiple pins arranged in an array. The pins in the pin unit (10) include two first pins (A1), two second pins (A2), four third pins (A3), four fourth pins (A4), and multiple ground pins (B1). The two first pins (A1) are a pair of differential signal pins, and the two second pins (A2) are another pair of differential signal pins. The third pins (A3) and the fourth pins (A4) are both single-ended signal pins. The first pin (A1) and the second pin (A2) have different rows and columns.

2. The pin unit (10) according to claim 1, characterized in that, The two first pins (A1) are located in the same column of the pin unit (10), the two second pins (A2) are located in the same column of the pin unit (10), the four third pins (A3) are located in the same column of the pin unit (10), and the four fourth pins (A4) are located in the same column of the pin unit (10). The column containing the two first pins (A1) is located between the column containing the four third pins (A3) and the column containing the four fourth pins (A4); the column containing the two second pins (A2) is located between the column containing the four third pins (A3) and the column containing the four fourth pins (A4).

3. The pin unit (10) according to claim 2, characterized in that, The columns containing the two first pins (A1) are adjacent to the columns containing the two second pins (A2) and the columns containing the four third pins (A3), respectively. The columns containing the two second pins (A2) are adjacent to the columns containing the four fourth pins (A4).

4. The pin unit (10) according to claim 2, characterized in that, The four third pins (A3) are arranged adjacent to each other in sequence; The four fourth pins (A4) are arranged adjacent to each other in sequence; The two first pins (A1) are adjacent; The two second pins (A2) are adjacent.

5. The pin unit (10) according to claim 2, characterized in that, Each of the first pins (A1) has a corresponding third pin (A3) and a fourth pin (A4), and each of the second pins (A2) has a corresponding third pin (A3) and a fourth pin (A4). The first pin (A1) and the corresponding third pin (A3) and fourth pin (A4) are set in the same row; The second pin (A2) and the corresponding third pin (A3) and fourth pin (A4) are set in the same row.

6. The pin unit (10) according to claim 5, characterized in that, A grounding pin (B1) is provided in the same row between the first pin (A1) and the fourth pin (A4) corresponding to the first pin (A1). A grounding pin (B1) is provided between the second pin (A2) and the third pin (A3) corresponding to the second pin (A2).

7. The pin unit (10) according to claim 1, characterized in that, A first pin (A1), a third pin (A3), a fourth pin (A4), and a plurality of ground pins (B1) form the boundary of the pin unit (10), wherein the first pin (A1), the third pin (A3), and the fourth pin (A4) are disposed on the same side of the pin unit (10); or: The boundary is composed of a second pin (A2), a third pin (A3), a fourth pin (A4) and a plurality of ground pins (B1), wherein the second pin (A2), the third pin (A3) and the fourth pin (A4) are located on the same side of the pin unit (10).

8. The pin unit (10) according to claim 7, characterized in that, In the case where the boundary is composed of a first pin (A1), a third pin (A3), a fourth pin (A4), and a plurality of ground pins (B1): the motherboard trace of the first pin (A1) in the boundary is led out in a direction away from the pin unit (10), and the motherboard trace of the other first pin (A1) is led out between the first pin (A1) and the third pin (A3) in the boundary; The motherboard trace for each of the second pins (A2) is led out from the ground pin (B1) adjacent to the first pin (A1) in the boundary and the first pin (A1); The motherboard trace of the third pin (A3) in the boundary extends away from the pin unit (10). The motherboard traces of the other two third pins (A3) in the third pin (A3) are both led out from between the adjacent ground pin (B1) and the third pin (A3) in the boundary. The motherboard trace of the other third pin (A3) in the third pin (A3) is led out from between the first pin (A1) and the third pin (A3) in the boundary. The motherboard trace of the fourth pin (A4) in the boundary is led out in a direction away from the pin unit (10). The motherboard traces of the other two fourth pins (A4) are led out between a ground pin (B1) adjacent to the fourth pin (A4) in the boundary and the fourth pin (A4). The motherboard trace of the other fourth pin (A4) is led out between another ground pin (B1) adjacent to the fourth pin (A4) in the boundary and the fourth pin (A4).

9. The pin unit (10) according to claim 7, characterized in that, In the case where the boundary is formed by a second pin (A2), a third pin (A3), a fourth pin (A4), and a plurality of ground pins (B1): the motherboard trace of each first pin (A1) is led out from the ground pin (B1) adjacent to the second pin (A2) in the boundary and the second pin (A2); The motherboard trace of the second pin (A2) in the boundary is led out in a direction away from the pin unit (10), and the motherboard trace of the other second pin (A2) is led out between the second pin (A2) and the fourth pin (A4) in the boundary; The motherboard trace of the third pin (A3) in the boundary extends away from the pin unit (10). The motherboard traces of the other two fourth pins (A4) in the third pin (A3) are both led out from between a ground pin (B1) adjacent to the third pin (A3) in the boundary and the third pin (A3). The motherboard trace of the other third pin (A3) in the third pin (A3) is led out from between another ground pin (B1) adjacent to the third pin (A3) in the boundary and the third pin (A3). The motherboard trace of the fourth pin (A4) in the boundary is led out in a direction away from the pin unit (10). The motherboard traces of the other two fourth pins (A4) in the boundary are led out between the adjacent ground pin (B1) and the fourth pin (A4) in the boundary. The motherboard trace of the other fourth pin (A4) in the boundary is led out between the second pin (A2) and the fourth pin (A4) in the boundary.

10. A chip, characterized in that, It includes at least one row of pin units, each row of pin units including a plurality of pin units (10) as described in any one of claims 1 to 9.

11. The chip according to claim 10, characterized in that, The pin units (10) in the pin unit row are arranged in a row; In the pin unit row, adjacent pin units (10) have a common boundary, which is composed of a plurality of ground pins (B1).

12. The chip according to claim 10, characterized in that, When there are multiple rows of pins in the chip, the rows of pins are arranged in an array.

13. An electronic device, characterized in that, Includes the chip as described in any one of claims 10 to 12.

14. A pin arrangement method, characterized in that, The method includes: Two first pins (A1), two second pins (A2), four third pins (A3), four fourth pins (A4), and multiple ground pins (B1) are arranged in an array to obtain a pin unit (10); the two first pins (A1) are a pair of differential signal pins, and the two second pins (A2) are another pair of differential signal pins; the third pins (A3) and the fourth pins (A4) are both single-ended signal pins; the rows and columns of the first pins (A1) and the second pins (A2) are different; Arrange the multiple pin units (10) into a row to obtain a pin unit row; in the pin unit row, adjacent pin units (10) have a common boundary, which is composed of multiple ground pins (B1); Arrange the multiple rows of pin units in an array to obtain the memory pin array of the chip.

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