A wafer factory yield prediction method, system, device and medium based on multi-modal big data and causal learning

Abstract

The present application relates to the technical field of integrated circuit manufacturing, in particular to a wafer factory yield prediction method, system, device and medium based on multi-modal big data and causal learning; the method completes abnormal value processing, missing value hierarchical filling and data normalization through multi-strategy fusion; adaptive variational autoencoder VAE is used to realize sample balance according to three stages of research and development, mass production and transition; the multi-level feature screening is completed by recursive feature elimination RFE, mutual information MI and elastic network, so as to reduce feature redundancy; the stacking integrated architecture is used to construct LightGBM, random forest RF and deep neural network DNN fusion prediction model, so as to significantly improve yield prediction accuracy and generalization; the prediction error is effectively reduced, the root cause determination accuracy is improved, and the analysis cycle is shortened.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and more specifically, to a method, system, equipment, and medium for predicting wafer fab yield based on multimodal big data and causal learning. Background Technology

[0002] In the integrated circuit manufacturing process, yield directly determines the economic benefits of the production unit, and wafer test data (including WAT data and CP data) is the core basis for yield analysis. WAT data (wafer acceptance test data) contains 50-500 high-dimensional features such as transistor resistance (R), capacitance (C), inductance (L), threshold voltage (Vth), saturation current (Idsat), subthreshold current (Isub), and electrical parameters of the metal interconnect layer, which are used to monitor process fluctuations; CP data (wafer probe test data) covers the electrical functional test results and final yield label of each die, reflecting the actual failure status of the chip.

[0003] Existing technologies have significant limitations: First, the data preprocessing methods are simplistic, resulting in low outlier identification rates and failure to consider physical correlations when filling missing values, which can easily lead to data distortion. Second, sample augmentation does not differentiate between manufacturing stages and cannot adapt to different imbalanced distributions during the R&D, mass production, and transition periods. Third, feature selection focuses solely on correlation, leading to high redundancy and low model efficiency. Fourth, single prediction models have poor generalization capabilities and are susceptible to large errors due to process drift. Fifth, root cause analysis relies solely on correlations, which can easily misclassify spurious correlations as root causes, leading to errors in process adjustments.

[0004] Existing technologies have significant limitations: First, data preprocessing methods are simplistic. Traditional outlier handling (such as single box plot methods) has a low recognition rate for "peak-type anomalies" (such as instantaneous extreme values ​​caused by poor probe contact) in semiconductor testing; missing value handling (such as simple mean imputation) does not consider the physical correlation between features (such as the coupling relationship between Vth and Idsat), leading to data distortion. Second, sample augmentation has poor adaptability. Existing methods do not differentiate between different stages of semiconductor manufacturing—low-yield samples account for less than 5% in the R&D phase (extreme imbalance), high-yield samples account for over 90% in the mass production phase (reverse imbalance), and yield fluctuates greatly during the transition period (dynamic imbalance), making it difficult for a single strategy to achieve sample balance. Third, feature selection has high redundancy. Traditional strategies only focus on the correlation between features and yield, without eliminating redundancy between features (such as the linear correlation coefficient of 0.92 between metal interconnect layer capacitors C1 and C2), resulting in high model complexity and slow inference speed. Fourth, the prediction model has weak generalization ability. In advanced processes, single models suffer from several drawbacks. First, "process drift" (such as minute variations in film deposition thickness over time) leads to increased prediction errors, with MAE (mean absolute error) often exceeding 8%. Second, root cause analysis lacks causal consistency. Correlation analysis based solely on SHAP values ​​is prone to misidentifying "spurious correlation characteristics" (such as simultaneous fluctuations in ambient temperature and yield) as root causes, resulting in incorrect process adjustments and wasted production resources.

[0005] To address the aforementioned issues, this invention proposes a fully optimized yield prediction and improvement scheme that overcomes existing technical bottlenecks through multi-stage adaptive processing, multi-level feature optimization, integrated modeling, and causal inference. Summary of the Invention

[0006] This invention addresses the problems of high dimensionality, imbalance, strong coupling, and susceptibility to misjudgment in root cause analysis of WAT and CP data in wafer fabrication. It proposes a wafer fab yield prediction method, system, equipment, and medium based on multimodal big data and causal learning. The method employs multi-strategy fusion to handle outliers, fill missing values ​​hierarchically, and normalize data. It uses an adaptive variational autoencoder (VAE) to achieve sample balancing across the R&D, mass production, and transition phases. Multi-level feature filtering is performed through recursive feature elimination (RFE), mutual information (MI), and elastic networks to reduce feature redundancy. A stacking integrated architecture is used to construct a fusion prediction model of LightGBM, random forest (RF), and deep neural network (DNN), significantly improving yield prediction accuracy and generalization. Combining feature importance, SHAP value, and Do-Calculus root cause analysis, spurious correlations are eliminated, and the true root causes of yield loss are located, outputting feasible process parameter optimization solutions. This effectively reduces prediction errors, improves root cause identification accuracy, and shortens the analysis cycle.

[0007] The specific implementation details of this invention are as follows: A wafer fab yield prediction method based on multimodal big data and causal learning specifically includes the following steps: Step S1: Preprocess the acquired raw wafer data to obtain the preprocessed raw wafer dataset; Step S2: Using the wafer ID and timestamp as the association key, align and merge the preprocessed original wafer data line by line to obtain the wafer sample set; Step S3: Based on the sample imbalance status during the wafer fab R&D phase, wafer fab mass production phase, and wafer fab transition phase, perform multi-stage adaptive VAE to enhance the wafer sample set and generate a balanced sample set; Step S4: Perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature filtering using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminative power. Step S5: Input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict wafer yield; Step S6: Integrate the inherent importance and permutation importance of the model, calculate and rank the comprehensive importance of features, and analyze the marginal contribution of features to yield by combining SHAP values; Step S7: Based on the cause-effect graph and Do-Calculus intervention calculation, locate the root cause of yield loss and output the process adjustment plan.

[0008] To better realize the present invention, step S1 further includes the following steps: Step S11: Collect wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data to establish the original dataset; Step S12: Remove outliers from the original dataset according to the data structure; Step S13: Based on the field missing rate, perform hierarchical processing to remove outliers from the original data, and obtain the original data after missing value processing; Step S14: Normalize the original data after handling missing values ​​to obtain the normalized original dataset.

[0009] To better implement the present invention, the specific operation of step S12 is as follows: for electrical parameters that follow a normal distribution, the Z-score method is used to calculate the mean and standard deviation of the features, and those exceeding the confidence interval are identified as anomalies; for non-steady-state distributed parameters, the IQR interquartile range method is used to calculate the quartiles and interquartile ranges, and those exceeding the upper and lower limits are identified as anomalies; for coupled feature groups, the isolated forest method is used to calculate the anomaly score, and anomalies are identified according to the score threshold; and the original data that meet two or more anomalies are removed.

[0010] To better realize the present invention, step S2 further includes the following steps: Step S21: Using the wafer ID and timestamp as the association key, align and merge the wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data line by line to form a sample set containing complete features and yield labels; Step S22: Divide the dataset using stratified sampling. Group the sample set according to the yield interval. Randomly sample samples from each group at a ratio of 7:2:1 and assign them to the training set, test set, and validation set, respectively.

[0011] To better realize the present invention, step S3 further includes the following steps: Step S31: Based on the wafer fab's mass production period, for the reverse imbalance state where the proportion of high-yield samples is high during the wafer fab's mass production period, first perform reverse oversampling, calculate the Euclidean distance between the majority class samples and the minority class samples, retain the effective samples with closer inter-class distances, and remove redundant majority class samples that are far away from the minority class. Step S32: Construct a variational autoencoder (VAE) network with minority class samples as input. The encoder maps the input minority class samples to the latent space distribution. The decoder reconstructs new samples from the latent variables and verifies the range of physical parameters one by one, and removes invalid samples that do not conform to the process rules. Step S33: Based on the variational autoencoder (VAE) network used during the wafer fab's R&D phase, densely generate extremely sparse minority class samples; Step S34: Based on the wafer fab transition period and combined with the real-time sample ratio, dynamically adjust the weights of the loss function of the variational autoencoder (VAE) network to obtain a balanced sample set.

[0012] To better realize the present invention, step S4 further includes the following steps: Step S41: Perform recursive feature elimination (RFE) screening on the balanced sample set. Use the basic regression model as the evaluator, iteratively train and gradually remove the features with the lowest weights until a preset number of high-contribution features are retained. Step S42: Use mutual information (MI) to remove redundancy. Calculate the mutual information value between each feature and the yield label, retain features with mutual information higher than the threshold, and remove redundant features that are weakly correlated with the yield. Step S43: Introduce an elastic network to complete feature fine-tuning, and combine L1 regularization constraints and L2 regularization constraints to obtain the final feature set.

[0013] To better implement the present invention, step S5 is further defined as follows: Step S51: Build a Stacking two-layer modeling architecture and train the underlying LightGBM model using gradient unilateral sampling and mutual feature binding strategy; Step S52: Based on the Stacking two-layer modeling architecture, use a multi-decision-tree voting strategy to train the underlying random forest (RF) model; Step S53: Based on the Stacking two-layer modeling architecture, a fully connected structure is adopted and Dropout and batch normalization are added to train the underlying deep neural network (DNN) model; Step S54: Using K-fold cross-validation, the final feature set is input into the trained LightGBM model, Random Forest (RF) model, and Deep Neural Network (DNN) model to obtain the yield prediction probability; Step S55: Use the spliced ​​yield prediction probability as a new feature set, and use logistic regression as the top-level fusion model to input the new feature set to obtain the final yield prediction result.

[0014] To better realize the present invention, step S6 further includes the following steps: Step S61: Extract the gain importance of the underlying random forest (RF) model and the feature weights of the deep neural network (DNN) model, and normalize them to obtain the inherent importance of the model. Step S62: Perform random permutations on the features of the test set and calculate the permutation importance by calculating the change in model loss; Step S63: Combine the inherent importance and permutation importance of the model with fixed weights to obtain the comprehensive importance and sort them in descending order. At the same time, calculate the confidence interval of importance through Bootstrap sampling. Step S64: Based on the SHAP additivity interpretation theory, traverse the feature subsets to calculate the marginal contribution value of each feature to the sample prediction, obtain the global and local feature contribution results, and output the feature influence distribution and marginal effect curve.

[0015] To better realize the present invention, step S7 further includes the following steps: Step S71: Construct a causal graph of features and yield by combining the physical logic of semiconductor process, optimize the graph structure with Bayesian information criterion, and determine the causal path between features; Step S72: Perform intervention operations on high-importance features in sequence, and use the backdoor adjustment formula to calculate the expected yield under fixed feature values ​​to obtain the change in yield before and after feature intervention; Step S73: Features whose yield improvement exceeds the threshold are identified as true root causes, while the rest are identified as false correlation features; Step S74: Based on the process steps corresponding to the root cause characteristics, determine the adjustable process parameters and target values ​​to form a clear process adjustment technical solution.

[0016] Based on the aforementioned wafer fab yield prediction method based on multimodal big data and causal learning, in order to better realize this invention, a wafer fab yield prediction system based on multimodal big data and causal learning is further proposed to execute the aforementioned wafer fab yield prediction method based on multimodal big data and causal learning; including a preprocessing module, an alignment and merging module, a sample enhancement module, a feature filtering module, and a modeling and prediction module; The preprocessing module is used to preprocess the acquired raw wafer data to obtain a preprocessed raw wafer dataset. The alignment and merging unit is used to align and merge the preprocessed original wafer data line by line using wafer ID and timestamp as the association key to obtain a wafer sample set. The balancing unit is used to perform multi-stage adaptive VAE enhancement of wafer sample set and generate balanced sample set based on the sample imbalance status during the wafer fab R&D period, wafer fab mass production period and wafer fab transition period. The feature selection module is used to perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature selection using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminativeness. The modeling and prediction module is used to input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict the wafer yield.

[0017] Based on the aforementioned wafer fab yield prediction method based on multimodal big data and causal learning, and to better realize this invention, an electronic device is further proposed, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, the aforementioned wafer fab yield prediction method based on multimodal big data and causal learning is implemented.

[0018] Based on the aforementioned method for predicting wafer fab yield using multimodal big data and causal learning, and to better realize this invention, a computer-readable storage medium is further proposed, wherein computer instructions are stored on the computer-readable storage medium; when the computer instructions are executed on the aforementioned electronic device, the aforementioned method for predicting wafer fab yield using multimodal big data and causal learning is realized.

[0019] The present invention has the following beneficial effects: (1) The present invention adopts multi-strategy preprocessing to reduce the data distortion rate to <1%, multi-stage sample enhancement to adapt to the entire manufacturing cycle, and improves the sample balance to 1:1±10%.

[0020] (2) The Stacking integrated architecture of this invention combines three different underlying models, predicting ACC≥97% and MAE≤3%, which is better than a single model.

[0021] (3) This invention eliminates spurious associations through causal inference Do-Calculus, with a root cause hit rate of ≥90% and a false positive rate of ≤5%, avoiding the risk of misadjustment in traditional SHAP analysis.

[0022] (4) The analysis time of this invention is ≤2 hours, the yield improvement is ≥5%, it is compatible with advanced processes, and it can be directly integrated into the wafer fab MES system to achieve automated yield optimization. Attached Figure Description

[0023] Figure 1 The method flowchart provided by the present invention. Detailed Implementation

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Example 1: This embodiment proposes a wafer fab yield prediction method based on multimodal big data and causal learning, which specifically includes the following steps: Step S1: Preprocess the acquired raw wafer data to obtain the preprocessed raw wafer dataset; Step S1 specifically includes the following steps: Step S11: Collect wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data to establish the original dataset; Step S12: Remove outliers from the original dataset according to the data structure; The specific operations of step S12 are as follows: For electrical parameters that follow a normal distribution, the Z-score method is used to calculate the feature mean and standard deviation, and those exceeding the confidence interval are identified as anomalies; for non-steady-state distributed parameters, the IQR interquartile range method is used to calculate the quartiles and interquartile range, and those exceeding the upper and lower limits are identified as anomalies; for coupled feature groups, the isolated forest method is used to calculate anomaly scores, and anomalies are identified according to the score threshold; and original data that meet two or more anomaly criteria are removed.

[0027] Step S13: Based on the field missing rate, perform hierarchical processing to remove outliers from the original data, and obtain the original data after missing value processing; Step S14: Normalize the original data after handling missing values ​​to obtain the normalized original dataset.

[0028] Step S2: Using the wafer ID and timestamp as the association key, align and merge the preprocessed original wafer data line by line to obtain the wafer sample set; Step S2 specifically includes the following steps: Step S21: Using the wafer ID and timestamp as the association key, align and merge the wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data line by line to form a sample set containing complete features and yield labels; Step S22: Divide the dataset using stratified sampling. Group the sample set according to the yield interval. Randomly sample samples from each group at a ratio of 7:2:1 and assign them to the training set, test set, and validation set, respectively.

[0029] Step S3: Based on the sample imbalance status during the wafer fab R&D phase, wafer fab mass production phase, and wafer fab transition phase, perform multi-stage adaptive VAE to enhance the wafer sample set and generate a balanced sample set; Step S3 specifically includes the following steps: Step S31: Based on the wafer fab's mass production period, for the reverse imbalance state where the proportion of high-yield samples is high during the wafer fab's mass production period, first perform reverse oversampling, calculate the Euclidean distance between the majority class samples and the minority class samples, retain the effective samples with closer inter-class distances, and remove redundant majority class samples that are far away from the minority class. Step S32: Construct a variational autoencoder (VAE) network with minority class samples as input. The encoder maps the input minority class samples to the latent space distribution. The decoder reconstructs new samples from the latent variables and verifies the range of physical parameters one by one, and removes invalid samples that do not conform to the process rules. Step S33: Based on the variational autoencoder (VAE) network used during the wafer fab's R&D phase, densely generate extremely sparse minority class samples; Step S34: Based on the wafer fab transition period and combined with the real-time sample ratio, dynamically adjust the weights of the loss function of the variational autoencoder (VAE) network to obtain a balanced sample set.

[0030] Step S4: Perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature filtering using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminative power. Step S4 specifically includes the following steps: Step S41: Perform recursive feature elimination (RFE) screening on the balanced sample set. Use the basic regression model as the evaluator, iteratively train and gradually remove the features with the lowest weights until a preset number of high-contribution features are retained. Step S42: Use mutual information (MI) to remove redundancy. Calculate the mutual information value between each feature and the yield label, retain features with mutual information higher than the threshold, and remove redundant features that are weakly correlated with the yield. Step S43: Introduce an elastic network to complete feature fine-tuning, and combine L1 regularization constraints and L2 regularization constraints to obtain the final feature set.

[0031] Step S5: Input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict wafer yield; The specific operation of step S5 is as follows: Step S51: Build a Stacking two-layer modeling architecture and train the underlying LightGBM model using gradient unilateral sampling and mutual feature binding strategy; Step S52: Based on the Stacking two-layer modeling architecture, use a multi-decision-tree voting strategy to train the underlying random forest (RF) model; Step S53: Based on the Stacking two-layer modeling architecture, a fully connected structure is adopted and Dropout and batch normalization are added to train the underlying deep neural network (DNN) model; Step S54: Using K-fold cross-validation, the final feature set is input into the trained LightGBM model, Random Forest (RF) model, and Deep Neural Network (DNN) model to obtain the yield prediction probability; Step S55: Use the spliced ​​yield prediction probability as a new feature set, and use logistic regression as the top-level fusion model to input the new feature set to obtain the final yield prediction result.

[0032] Step S6: Integrate the inherent importance and permutation importance of the model, calculate and rank the comprehensive importance of features, and analyze the marginal contribution of features to yield by combining SHAP values; Step S6 specifically includes the following steps: Step S61: Extract the gain importance of the underlying random forest (RF) model and the feature weights of the deep neural network (DNN) model, and normalize them to obtain the inherent importance of the model. Step S62: Perform random permutations on the features of the test set and calculate the permutation importance by calculating the change in model loss; Step S63: Combine the inherent importance and permutation importance of the model with fixed weights to obtain the comprehensive importance and sort them in descending order. At the same time, calculate the confidence interval of importance through Bootstrap sampling. Step S64: Based on the SHAP additivity interpretation theory, traverse the feature subsets to calculate the marginal contribution value of each feature to the sample prediction, obtain the global and local feature contribution results, and output the feature influence distribution and marginal effect curve.

[0033] Step S7: Based on the cause-effect graph and Do-Calculus intervention calculation, locate the root cause of yield loss and output the process adjustment plan.

[0034] Step S7 specifically includes the following steps: Step S71: Construct a causal graph of features and yield by combining the physical logic of semiconductor process, optimize the graph structure with Bayesian information criterion, and determine the causal path between features; Step S72: Perform intervention operations on high-importance features in sequence, and use the backdoor adjustment formula to calculate the expected yield under fixed feature values ​​to obtain the change in yield before and after feature intervention; Step S73: Features whose yield improvement exceeds the threshold are identified as true root causes, while the rest are identified as false correlation features; Step S74: Based on the process steps corresponding to the root cause characteristics, determine the adjustable process parameters and target values ​​to form a clear process adjustment technical solution.

[0035] Working Principle: This embodiment addresses the issues of high dimensionality, imbalance, strong coupling, and susceptibility to misjudgment in root cause analysis of WAT and CP data in wafer manufacturing. It employs a multi-strategy fusion approach to handle outliers, graded filling of missing values, and data normalization. An adaptive variational autoencoder (VAE) is used to balance samples across the R&D, mass production, and transition phases. Multi-level feature filtering is achieved through recursive feature elimination (RFE), mutual information (MI), and elastic networks to reduce feature redundancy. A stacking integrated architecture is used to construct a fusion prediction model of LightGBM, random forest (RF), and deep neural network (DNN), significantly improving yield prediction accuracy and generalization. Combining feature importance, SHAP values, and Do-Calculus root cause analysis, spurious correlations are eliminated, and the true root causes of yield loss are located, outputting a feasible process parameter optimization solution. This invention effectively reduces prediction errors, improves root cause identification accuracy, and shortens the analysis cycle. It is applicable to the entire lifecycle yield management of advanced process wafer fabs and possesses strong engineering practicality and economic benefits.

[0036] Example 2: This embodiment is based on the above embodiment 1, such as... Figure 1 As shown, a specific embodiment will be described in detail, which includes the following steps.

[0037] The method in this embodiment is divided into seven core steps: data acquisition and preprocessing, data merging and partitioning, adaptive sample enhancement, multi-level feature screening, integrated modeling and prediction, multi-dimensional feature importance calculation and SHAP value analysis, and causal root cause analysis and optimization. The entire process revolves around the characteristics of wafer fab test data and process physical rules. The technical implementation process is as follows: Step 1: Multimodal test data collection and preprocessing WAT data, CP data, and process environment data are acquired according to the data acquisition specifications. WAT data includes transistor resistance, capacitance, threshold voltage, saturation current, and electrical parameters of the metal interconnect layer. CP data includes die electrical test items and yield labels. Auxiliary data includes parameters such as etching time, cavity temperature, and ambient temperature and humidity. Data is written to distributed storage using timestamp + wafer ID + test station as indexes, with a unified format and field specifications.

[0038] Outlier handling is performed as follows: For normally distributed electrical parameters, the Z-score method is used to calculate the feature mean and standard deviation, and samples exceeding the confidence interval are identified as outliers; for non-stationary distributed parameters, the IQR (Interquartile Range) method is used to calculate the quartiles and interquartile range, and samples exceeding the upper and lower limits are identified as outliers; for coupled feature groups, an isolation forest is used to calculate anomaly scores, and identification is completed according to the score threshold. The results of the three methods are fused according to a voting rule, and samples that meet at least two of the criteria are removed.

[0039] After outlier handling, missing value handling is performed, and the missing values ​​are handled in stages according to the field missing rate: for fields with a missing rate of less than 5%, nearest neighbor features are selected based on physical association, and weighted distance is calculated to complete KNN interpolation; for fields with a missing rate of 5% to 20%, multiple imputation is used to generate multiple sets of complete data, and the average result is taken later; batches with a missing rate of more than 20% are directly removed.

[0040] Finally, data normalization is performed. For process parameters with clear physical upper and lower limits, Min-Max normalization is used to map the values ​​to a fixed interval. For electrical parameters without a fixed range, mean-variance normalization is used to make them conform to a standard normal distribution. To adapt to subsequent sample enhancement model input, batch normalization is performed on some features, and a smoothing term is added to avoid the denominator being zero, thus ensuring numerical stability.

[0041] Step 2: Data Merging and Hierarchical Partitioning Methods Using wafer ID and timestamp as unique association keys, WAT data, CP data and auxiliary data are aligned and merged row by row to form a sample set containing complete features and yield labels, and samples without labels and those with failed association are removed.

[0042] Stratified sampling was used to partition the dataset, grouping samples according to yield intervals. Within each group, samples were randomly selected in a 7:2:1 ratio and assigned to the training, testing, and validation sets, respectively, ensuring that the yield distribution of the three subsets was consistent with the whole set. During the partitioning process, wafers from the same batch were constrained to not cross sets to avoid model evaluation bias caused by batch correlation.

[0043] Step 3: Multi-stage adaptive VAE sample augmentation To address the reverse imbalance state where a high proportion of high-yield samples are present during mass production, reverse oversampling is first performed to calculate the Euclidean distance between the majority class samples and the minority class samples. Effective samples with close inter-class distances are retained, while redundant majority class samples that are far from the minority class are removed.

[0044] A variational autoencoder (VAE) network is then constructed using minority class samples as input. The encoder maps the input samples to a latent space distribution, and the decoder reconstructs new samples from the latent variables. During training, the reconstruction loss and KL divergence are optimized simultaneously to make the distribution of generated samples closely resemble the real minority class samples. The physical parameter ranges of each generated sample are verified, and invalid samples that do not conform to the process rules are removed, ultimately achieving a balance between the number of samples from the two classes.

[0045] During the R&D phase, VAE was used to generate dense samples of extremely sparse minority classes; during the transition phase, the weights of the VAE loss function were dynamically adjusted according to the real-time sample ratio to ensure the continuous stability of the sample distribution.

[0046] Step 4: Multi-level feature selection First, a recursive feature elimination (RFE) screening is performed. The basic regression model is used as the evaluator. The model is iteratively trained and the features with the lowest weights are gradually removed until a preset number of high-contribution features are retained.

[0047] Subsequently, mutual information (MI) was used to remove redundancy. The mutual information value between each feature and the yield label was calculated. Features with mutual information higher than the threshold were retained, and redundant features with weak correlation to yield were removed.

[0048] Finally, an elastic network is introduced to complete feature fine-tuning. Combined with L1 and L2 regularization constraints, feature sparsity is achieved while ensuring model stability. Features with significant and stable weights are retained, resulting in a final feature set with reduced dimensions and adapted modeling.

[0049] Step 5: Integration and Modeling A stacking two-layer modeling architecture is constructed, with LightGBM, Random Forest (RF), and Deep Neural Network (DNN) models trained in the bottom layer respectively. LightGBM adopts gradient unilateral sampling and cross-feature binding strategies to improve training speed and generalization ability; Random Forest outputs stable probability results based on voting from multiple decision trees; DNN adopts a fully connected structure and incorporates Dropout and batch normalization to adapt to nonlinear fitting of high-dimensional features.

[0050] All three underlying models employ K-fold cross-validation, outputting yield prediction probabilities on the validation set. These three probability results are then concatenated into a new feature set. Logistic regression is used as the top-level fusion model, which is trained by inputting probabilistic features and outputting the final yield prediction result, thus achieving complementary advantages among multiple models.

[0051] Step 6: Feature Importance and SHAP Analysis The gain importance of the underlying tree model and the feature weights of the DNN model are extracted and normalized to obtain the inherent importance of the model. Then, random permutations are performed on the features of the test set, and the change in model loss is calculated to obtain the permutation importance. The two types of importance are fused with fixed weights to obtain the comprehensive importance and sorted in descending order. At the same time, the confidence interval of importance is calculated by Bootstrap sampling.

[0052] Based on the SHAP additivity interpretation theory, the marginal contribution value of each feature to the sample prediction is calculated by traversing the feature subset, and the global and local feature contribution results are obtained. The feature influence distribution and marginal effect curve are output to quantify the positive and negative impact of each feature on the yield.

[0053] Step 7: Cause and Effect Analysis and Process Optimization A causal graph between features and yield is constructed by combining the physical logic of semiconductor process. The graph structure is optimized using the Bayesian information criterion to determine the causal paths between features. Intervention operations are performed sequentially on highly important features, and the expected yield under fixed feature values ​​is calculated using a backdoor adjustment formula to obtain the yield change before and after feature intervention.

[0054] Features that improve yield by a margin exceeding a threshold are identified as true root causes, while the rest are considered spurious correlations. Based on the corresponding process steps of the root cause features, adjustable process parameters and target values ​​are determined, forming a clear process adjustment technical solution to achieve the full-process technical implementation of yield improvement.

[0055] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0056] Example 3: Based on any one of Embodiments 1-2 above, this embodiment takes a 7nm process logic chip manufacturing scenario (mass production period, current yield 88%) as an example to provide a detailed explanation of the implementation process.

[0057] Step 1: Data collection and preprocessing; Collect WAT data, CP data, and process environment auxiliary data from semiconductor production lines. Use timestamps, wafer IDs, and test stations as joint indexes to store the raw data in a unified distributed storage system, ensuring data traceability and efficient read / write.

[0058] Collected 1000 batches of multi-dimensional test data from wafers (120-dimensional WAT features, 30-dimensional CP features, and 8-dimensional auxiliary features), totaling 10,000 samples; formed the raw dataset and stored it in a distributed database (such as HBase). The storage design adopted a three-dimensional index of "timestamp + wafer ID + test station" to facilitate subsequent data traceability. The storage format was Parquet (compression ratio ≥3:1) to support efficient querying. Data categories and parameter definitions are as follows:

[0059] To address the characteristics of different data types, preprocessing is performed in three sub-steps, incorporating physical association constraints and multi-method fusion: Step 11: Combine the three methods for outlier handling; For outlier handling, Z-score (Vth), IQR (interquartile range) (Isub), and isolated forest (RCL) were combined to remove 450 outlier samples (outlier rate 4.5%).

[0060] Method 1: Applicable to normally distributed features, such as Vth, using the Z-score method to calculate the Z-value of feature x: in, The characteristic mean, The standard deviation is denoted as ; when hour, When this occurs, it is considered an outlier.

[0061] Method 2: Applicable to non-normally distributed characteristics, such as Isub. The IQR (interquartile range) method is used to sort the data for each characteristic variable (such as WAT parameters, CP test values) in ascending order, and calculate the first quartile Q1 (25th percentile) and the third quartile Q3 (75th percentile). The interquartile range IQR = Q3 - Q1; when... or When the value is not found, it is considered an outlier.

[0062] Method 3: Applicable to high-dimensional coupled features, such as RCL combinations, using an Isolation Forest to construct 100 isolated trees and calculate the "anomaly score S" of the samples: in, The average path length of the sample in the tree. The average path length for the sample size n; when When this occurs, it is considered an outlier.

[0063] Fusion rule: A sample is removed only if at least two of the three methods determine it as abnormal, thus reducing the false positive rate (false positive rate ≤ 0.5%).

[0064] Step 12: Handle missing values ​​based on physical correlation interpolation; For the missing value handling part, MICE imputation was used for C_int missing values ​​(missing rate 8%) to generate 5 complete datasets; Case 1: Missing rate <5% (e.g., Vout missing in individual numeric samples): Use KNN interpolation (K=5) and combine it with physical association to select nearest neighbor samples: for missing values ​​of feature x Select k features that are physically related to x (such as Vout and Iin), and calculate the weighted distance between samples: in, Physical weights (such as the weights of Vout and Iin) ),final , (The non-missing values ​​of the k nearest neighbors).

[0065] Scenario 2: Missing rate 5%-20% (e.g., missing C_int in a batch of WAT data): Use multiple imputation (MICE) to generate 5 complete datasets, and take the average of the results in subsequent modeling.

[0066] Case 3: Missing rate > 20%: Remove the data from this batch directly (to avoid data distortion).

[0067] Step 13: Data normalization; In the normalization process, the etching time is normalized using Min-Max (30-60s→[0,1]) and the mean-variance normalization is used for Idsat (μ=50μA, σ=15μA→N(0,1)).

[0068] If there are features with a clearly defined physical range, such as etch time t_etch, use Min-Max normalization: ,in , The physical limit value of the feature (such as t_etch) , After normalization .

[0069] If the feature does not have a clearly defined range, such as Idsat, use mean-variance normalization(): ,in , The mean and standard deviation of the training set are given. After normalization, the features follow an N(0,1) distribution.

[0070] If the features are input to the subsequent VAE model, batch normalization (BN) is used: for each feature x in batch B, the batch mean is calculated. Batch variance ,but , (To avoid the denominator being 0).

[0071] Step 2: Data merging and hierarchical partitioning; Using wafer ID and timestamp as the association key, WAT data, CP data and auxiliary data are merged into a complete sample set. Then, stratified sampling is performed according to the yield distribution, and the dataset is divided into training set, test set and validation set according to a fixed ratio to ensure that the yield distribution of each subset is consistent with the whole set and to avoid evaluation bias caused by batch correlation.

[0072] In the data merging step, using "Wafer ID + Timestamp" as the key, WAT data, CP data, and auxiliary data are merged into a single sample to form a fused dataset D. Each sample contains "feature set X (60-560 dimensions) + yield label Y (0-1)". In the stratified partitioning step, stratified sampling is used (to ensure consistent yield distributions across the training, test, and validation sets), with a partitioning ratio of 7:2:1, i.e.: Training set D_train: accounts for 70% and is used for model training; Test set D_test: accounts for 20% and is used for model generalization evaluation; Validation set D_val: accounting for 10%, used for model hyperparameter tuning.

[0073] Divide the constraint steps so that wafers from the same batch do not cross sets (to avoid evaluation bias caused by batch correlation).

[0074] Step 3: Sample enhancement and feature selection; Regarding sample augmentation, the original proportion of high-yield samples during mass production was 92%. In this embodiment, a combined optimization method of VAE and reverse oversampling was adopted to remove 30% of redundant high-yield samples. At the same time, low-yield samples were generated through the VAE model to supplement the data, and finally the number of the two types of samples was adjusted to a balanced ratio of 1:1, with 4775 samples in each type. Feature selection was optimized in three stages: First, the recursive feature elimination (RFE) algorithm was used to complete the initial screening, retaining 45 features that were strongly correlated with yield; then, the mutual information (MI) method was used to remove redundant feature information. After the mutual information evaluation function converged, 22 effective features were selected and retained; finally, the Elastic Net was used to complete the fine-tuning, and 15 core features with coefficients having an absolute value greater than 1e-4 were selected, mainly including key parameters such as Vth, Idsat, R_int, C_int, t_etch, and T.

[0075] Step 3.1: Multi-stage adaptive sample augmentation; Based on the sample imbalance characteristics during the semiconductor R&D, mass production, and transition periods, a differentiated enhancement strategy is adopted. During the R&D period, extreme imbalance is addressed by fusing VAE and SMOTE to generate minority class samples; during the mass production period, reverse imbalance is addressed by combining VAE with reverse oversampling to eliminate redundant majority class samples and enhance the minority class; during the transition period, dynamic imbalance is addressed by using an adaptive weighted VAE to adjust the loss function in real time to maintain sample balance. All generated samples undergo physical validity verification.

[0076] Based on the three stages of semiconductor manufacturing (R&D, transition, and mass production), differentiated sample enhancement strategies are designed, with the core being to balance sample distribution and preserve physical characteristics. Phase 1: Research and Development Period (Low-yield sample ratio <5%, extremely unbalanced) Adopting a VAE+SMOTE fusion strategy: SMOTE preprocessing (generating basic minority class samples): For minority class samples (Y=0, low yield), select k=5 nearest neighbor samples. Generate new samples: in, For the target minority class samples, Its neighbors, The random numbers are uniformly distributed in [0,1], and after generation, the number of minority class samples increases to 50% of the majority class samples.

[0077] VAE fine enhancement: Encoder E: Input real minority class samples The network outputs the mean μ and variance σ² of the latent variable z, satisfying z∼N(μ,σ²); Network structure: fully connected layer (128 dimensions) → BN → ReLU → fully connected layer (2×latent dimension).

[0078] Decoder D: Reconstructs the sample from the latent variable z and outputs... Network structure: Fully connected layer (128-dimensional) → Batch Normalization (BN) → ReLU → Fully connected layer (X-dimensional) → Tanh; Loss function:

[0079] Training iterations: until |L-VAE| < 0.01, the final ratio of minority class to majority class samples reaches 1:1.

[0080] Phase 2: Mass production (high yield sample ratio >90%, reverse imbalance); Employing a VAE+ inverse oversampling strategy: Reverse oversampling (filtering effective majority class samples): Calculate the Euclidean distance between the majority class samples (Y=1, high yield) and the minority class samples. ,reserve , The majority class samples (which are half the inter-class distance) are removed, and "redundant majority class samples" (accounting for about 30%) are discarded. VAE Enhancement Minority Class: Same as the VAE process during the R&D phase, with a final sample ratio of 1:1.

[0081] Phase 3: Transition period (yield fluctuates from 5% to 90%, with dynamic imbalance); Adaptive weighted VAE: Calculate the real-time sample balance coefficient , For a minority of classes, (Number of classes) Adjusting the weights of the VAE loss function: , To reconstruct the loss, Let KL divergence be denoted as KL divergence.

[0082] Dynamic iteration: Recalculate after each batch of data is updated. To ensure that the sample ratio is maintained at 1:1±10%.

[0083] Enhanced post-verification: "Physical rationality verification" is adopted - the generated samples are checked to see if their characteristics conform to the physical laws of semiconductors (such as Vth>0.3V, Idsat>10μA), and samples that do not conform are removed. The verification pass rate is ≥95%.

[0084] Step 3.2: Multi-level feature filtering; First, the recursive feature elimination (RFE) algorithm is used to perform initial screening, retaining features that are strongly correlated with yield. Then, mutual information (MI) is used to evaluate the correlation between features and labels and remove redundant features. Finally, an elastic network is introduced to fine-tune the feature set, resulting in a low-dimensional, high-discrimination final feature set, reducing modeling complexity.

[0085] The selection process is divided into three levels, taking into account relevance, redundancy, and model suitability: Level 1: RFE Recursive Feature Elimination (Retaining Features Strongly Correlated with Yield) Construct a random forest model (number of trees = 100, tree depth = 10) and calculate the importance of the original features. ; For each feature This generates its "shadow features". (randomly shuffled) The value of shadow features is used to calculate their importance. ; Define feature significance ,when , When the empirical threshold is reached, the feature is retained to obtain the initial screening feature set X1 (the dimension is reduced to 30-80 dimensions).

[0086] Level 2: Mutual Information MI Redundancy Removal; Fitness function. Combining mutual information entropy (correlation between features and yield) and redundancy coefficient (correlation between features): in, Features Mutual information entropy with yield Y ( ), Features and Pearson correlation coefficient, , As weight; The iteration terminates. The subset with MI above the threshold and low correlation between features is retained, and the redundant feature set X2 is output (dimension reduced to 15-40 dimensions).

[0087] Level 3: Elastic network fine-tuning (adapting to model input); Construct a linear regression model, introduce elastic network regularization (integrating L1+L2), with the objective function: in, For log loss ( ), , Here, is the regularization coefficient, and w is the feature weight; Preserving weights ( The features of the feature set X_final are obtained by reducing the dimension to 10-30.

[0088] Step 4: Integrate and combine yield prediction modeling (Stacking architecture); The prediction model is built using a stacking architecture. The bottom layer uses three different models: LightGBM, Random Forest, and Deep Neural Network (DNN) and outputs probability prediction results through cross-validation. The top layer uses logistic regression as a fusion model, takes the probability results of the bottom layer as input to complete the training, and outputs the final yield prediction value to improve the overall generalization ability.

[0089] Step 4.1 Training the underlying model; In the training of the underlying models, this embodiment used multiple models for experiments. The LightGBM model, with a learning rate of 0.05 and 200 trees, achieved an accuracy (ACC) of 96.5% on the validation set. The Random Forest (RF) model, with a learning rate of 0.03 and 300 trees, achieved an accuracy of 96.2% on the validation set. The Deep Neural Network (DNN) model, with parameters C set to 10 and γ set to 0.1, achieved an accuracy of 95.8% on the validation set. The specific design of the underlying models (3 differentiated models) is as follows:

[0090] Step 4.2 Training method; For each underlying model, 5-fold cross-validation is used for training, outputting the probability prediction results of the validation set (p1 (LightGBM prediction of pass probability), p2 (Random Forest RF prediction of pass probability), p3 (DNN prediction of pass probability)). The three sets of probability results are concatenated into a new feature set, which serves as the input features for the top-level model. Subsequently, logistic regression is used as the top-level fusion model, with the probability features as input to complete training, outputting the final yield prediction result, thus achieving complementary advantages among multiple models.

[0091] Step 4.3 Top-level model; Input features: Probabilistic prediction results from the underlying model ; Objective function: ,in These are the regression coefficients; Training and Prediction: The top-level model is trained using the low-level outputs of the training set, and the final output is the predicted wafer yield value. ( If and only if ).

[0092] The logistic regression model used at the top layer was trained using the probability features output by the underlying model. It achieved an accuracy of 97.8% on the test set, with a mean absolute error (MAE) of 2.2% and a root mean square error (RMSE) of 3.5%.

[0093] Step 5: Feature Importance and SHAP Analysis; In feature importance analysis, this embodiment first extracts the gain importance of the underlying tree model and the feature weights of the support vector machine, and obtains the inherent importance of the model through normalization. Simultaneously, a random permutation operation is performed on the test set features, and the change in model loss is calculated to determine the permutation importance. Subsequently, these two types of importance are fused according to fixed weights to obtain a comprehensive importance, which is then sorted in descending order. The top 5 features are: R_int (0.28), t_etch (0.22), Vth (0.18), C_int (0.15), and Idsat (0.12). Furthermore, the confidence interval for each feature importance is calculated using the Bootstrap sampling method. On the other hand, based on the SHAP additivity interpretation theory, the marginal contribution value of each feature to sample prediction is calculated by traversing the feature subsets, thereby obtaining the global and local feature contribution results and outputting the feature influence distribution and marginal effect curves to quantify the positive and negative impact of each feature on the yield. SHAPSummaryPlot shows that when R_int is greater than 5Ω, its SHAP value is negative, indicating that the yield will be reduced; while when t_etch is greater than 45s, the SHAP value decreases as t_etch increases.

[0094] Step 5.1: Calculate the importance of multi-dimensional features; The inherent importance and permutation importance of the fusion model are used to obtain the comprehensive importance of features, which are then sorted from largest to smallest. At the same time, the Bootstrap method is used to calculate the confidence interval of importance to ensure that the evaluation results are stable and reliable.

[0095] By combining "inherent importance of the model" and "permutation importance", a comprehensive assessment of the impact of features on yield is conducted. The inherent importance of the model: LightGBM / Random Forest RF: Extracting the built-in "gain importance" of the model (feature (The sum of the loss reductions contributed by all trees); DNN: Calculate the L2 norm of feature weights , These are the feature weights for the input layer of the DNN; Normalization: ( (For original importance).

[0096] Permutation Importance: Features Randomly shuffle the values ​​of the model on the test set and calculate the change in model loss before and after shuffling. ; Normalization: .

[0097] Overall Importance: ,according to Sort the features from largest to smallest and output the top 10 core features (e.g., Vth, Idsat, R_int).

[0098] Confidence interval: Calculated using the Bootstrap method (number of samples = 100). The 95% confidence interval ensures the stability of the importance assessment.

[0099] Step 5.2: In-depth analysis of SHAP values; Based on SHAP theory, the marginal contribution of each feature to the prediction results is calculated, and the feature impact analysis results are output. Then, combined with semiconductor process knowledge, a cause-effect graph is constructed. Through Do-Calculus intervention, the actual impact of feature adjustment on yield is calculated, distinguishing between true root causes and spurious correlation features, and finally outputting a feasible process adjustment solution.

[0100] Based on the SHAP (Shapley Additive exPlanations) theory, the marginal effect of each feature on yield prediction is quantified, and three types of analysis graphs are output: SHAP value calculation formula. Features of sample i Its SHAP value The contribution of this feature to the prediction result is expressed as follows: in, The average predicted value for all samples. The contribution is calculated iteratively using Shapley values ​​(by traversing all feature subsets).

[0101] There are three types of key analysis charts: Summary Plot. The horizontal axis represents the SHAP value (positive indicates improved yield, negative indicates decreased yield), and the vertical axis represents the features (sorted by importance). The color represents the magnitude of the feature value (e.g., red indicates high Vth, blue indicates low Vth), visually demonstrating the relationship between "feature value - SHAP value - yield". Partial Dependency Graph (PDP). With other features fixed, draw the "feature" graph. The curve “value → average SHAP value” reflects the global marginal effect of features on yield (e.g., when Vth is between 0.3 and 0.5V, the SHAP value increases with increasing Vth, and decreases after exceeding 0.5V). Individual Conditional Expectation Map (ICE). For each sample, plot the "features". The curve “value → SHAP value” reflects the individual effect of the feature on different samples (e.g., the SHAP value of some samples drops sharply when Vth=0.4V, corresponding to a specific process defect).

[0102] Step 6: Root cause analysis and optimization of causal reinforcement yield; Based on SHAP correlation analysis, Do-Calculus causal inference is introduced to eliminate spurious associations and locate the "true root cause": Step 6.1: Construct a cause-effect graph; Based on semiconductor process knowledge (e.g., etching time affects film thickness, and film thickness affects R_int), a causal graph G is constructed using a Bayesian network, where nodes represent "features + yield" and edges represent causal relationships (e.g., t_etch→R_int→Y). The graph structure is optimized using BIC scoring (Bayesian Information Criterion). (L is the likelihood function, k is the number of parameters, and n is the number of samples), select the causal graph with the smallest BIC.

[0103] Step 6.2: Do-Calculus intervention; The top 5 most important features selected in step 5.1 (such as...) =Vth, =Idsat, =R_int), and perform the intervention sequentially. ( For the target optimization value of the feature (e.g., Vth = 0.4V), calculate the change in yield before and after the intervention: in, These are the characteristic values ​​in the current production process. Calculated using the backdoor adjustment formula of the cause-effect graph (e.g.) z is (parent node).

[0104] Examples of Do-Calculus interventions: Intervention t_etch=40s (current 45s): E[Y|Do(t_etch=40s)]=94.2%, ΔY=6.2%; Intervention R_int=4Ω (current 5.5Ω): E[Y|Do(R_int=4Ω)]=93.8%, ΔY=5.8%.

[0105] Step 6.3: Root cause determination; when ( When the yield rate improves by more than 5% after intervention, it is considered... If it is a "true cause," then it is a "false correlation characteristic" (e.g., a high SHAP value between ambient temperature T and Y, but...). back (It was determined to be a false association).

[0106] Based on the previous calculations, the root cause determination results are that t_etch and R_int are true root causes (ΔY>5%), and Vth is a spurious association (ΔY=2.1%).

[0107] Step 6.4: Output the improved solution; For each root cause, adjustment suggestions are given in combination with process parameters (e.g., for the root cause of R_int, which is due to excessive etching time, it is recommended to adjust t_etch from 45s to 40s), and the yield improvement after adjustment is predicted (e.g., from 85% to 92%).

[0108] Step 7: Full lifecycle performance evaluation; The effectiveness of the solution is evaluated from three dimensions: prediction accuracy, root cause accuracy, and engineering value. The indicators and formulas are as follows:

[0109] In summary, regarding the verification of the implementation effect, after optimization, 50 batches of wafers were produced, with an actual yield of 93.8% (close to the predicted value of 94.2%), an improvement of 5.8%; the analysis time was 1.5 hours, and the root cause hit rate was 92% (2 true root causes and 0 false root causes), meeting the evaluation target.

[0110] Example 4: This embodiment is based on any one of the embodiments 1 to 3 above, but removes a wafer fab yield prediction system based on multimodal big data and causal learning, and is used to execute the above-mentioned wafer fab yield prediction method based on multimodal big data and causal learning; it includes a preprocessing module, an alignment and merging module, a sample enhancement module, a feature screening module, and a modeling and prediction module; The preprocessing module is used to preprocess the acquired raw wafer data to obtain a preprocessed raw wafer dataset. The alignment and merging unit is used to align and merge the preprocessed original wafer data line by line using wafer ID and timestamp as the association key to obtain a wafer sample set. The balancing unit is used to perform multi-stage adaptive VAE enhancement of wafer sample set and generate balanced sample set based on the sample imbalance status during the wafer fab R&D period, wafer fab mass production period and wafer fab transition period. The feature selection module is used to perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature selection using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminativeness. The modeling and prediction module is used to input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict the wafer yield.

[0111] This embodiment also proposes an electronic device, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the above-mentioned wafer fab yield prediction method based on multimodal big data and causal learning.

[0112] This embodiment also proposes a computer-readable storage medium storing computer instructions; when the computer instructions are executed on the aforementioned electronic device, the aforementioned wafer fab yield prediction method based on multimodal big data and causal learning is implemented.

[0113] The other parts of this embodiment are the same as any one of the above embodiments 1-3, so they will not be described again.

[0114] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for yield prediction of a wafer fab based on multi-modal big data and causal learning, characterized in that, Specifically, the following steps are included: Step S1: Preprocess the acquired raw wafer data to obtain the preprocessed raw wafer dataset; Step S2: Using the wafer ID and timestamp as the association key, align and merge the preprocessed original wafer data line by line to obtain the wafer sample set; Step S3: Based on the sample imbalance status during the wafer fab R&D phase, wafer fab mass production phase, and wafer fab transition phase, perform multi-stage adaptive VAE to enhance the wafer sample set and generate a balanced sample set; Step S4: Perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature filtering using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminative power. Step S5: Input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict wafer yield.

2. The base according to claim 1, characterized in that, Step S1 specifically includes the following steps: Step S11: Collect wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data to establish the original dataset; Step S12: Remove outliers from the original dataset according to the data structure; Step S13: Based on the field missing rate, perform hierarchical processing to remove outliers from the original data, and obtain the original data after missing value processing; Step S14: Normalize the original data after handling missing values ​​to obtain the normalized original dataset.

3. The wafer fab yield prediction method based on multimodal big data and causal learning according to claim 2, characterized in that, The specific operations of step S12 are as follows: For electrical parameters that follow a normal distribution, the Z-score method is used to calculate the feature mean and standard deviation, and those exceeding the confidence interval are identified as anomalies; for non-steady-state distributed parameters, the IQR interquartile range method is used to calculate the quartiles and interquartile range, and those exceeding the upper and lower limits are identified as anomalies; for coupled feature groups, the isolated forest method is used to calculate anomaly scores, and anomalies are identified according to the score threshold; and original data that meet two or more anomaly criteria are removed.

4. A base according to claim 1, characterized in that, Step S2 specifically includes the following steps: Step S21: Using the wafer ID and timestamp as the association key, align and merge the wafer acceptance test (WAT) data, wafer probe test (CP) data, and process environment auxiliary data line by line to form a sample set containing complete features and yield labels; Step S22: Divide the dataset using stratified sampling. Group the sample set according to the yield interval. Randomly sample samples from each group at a ratio of 7:2:1 and assign them to the training set, test set, and validation set, respectively.

5. The one according to claim 1, characterized in that, Step S3 specifically includes the following steps: Step S31: Based on the wafer fab's mass production period, for the reverse imbalance state where the proportion of high-yield samples is high during the wafer fab's mass production period, first perform reverse oversampling, calculate the Euclidean distance between the majority class samples and the minority class samples, retain the effective samples with closer inter-class distances, and remove redundant majority class samples that are far away from the minority class. Step S32: Construct a variational autoencoder (VAE) network with minority class samples as input. The encoder maps the input minority class samples to the latent space distribution. The decoder reconstructs new samples from the latent variables and verifies the range of physical parameters one by one, and removes invalid samples that do not conform to the process rules. Step S33: Based on the variational autoencoder (VAE) network used during the wafer fab's R&D phase, densely generate extremely sparse minority class samples; Step S34: Based on the wafer fab transition period and combined with the real-time sample ratio, dynamically adjust the weights of the loss function of the variational autoencoder (VAE) network to obtain a balanced sample set.

6. The one according to claim 4, characterized in that, Step S4 specifically includes the following steps: Step S41: Perform recursive feature elimination (RFE) screening on the balanced sample set. Use the basic regression model as the evaluator, iteratively train and gradually remove the features with the lowest weights until a preset number of high-contribution features are retained. Step S42: Use mutual information (MI) to remove redundancy. Calculate the mutual information value between each feature and the yield label, retain features with mutual information higher than the threshold, and remove redundant features that are weakly correlated with the yield. Step S43: Introduce an elastic network to complete feature fine-tuning, and combine L1 regularization constraints and L2 regularization constraints to obtain the final feature set.

7. The one according to claim 6, characterized in that, The specific operation of step S5 is as follows: Step S51: Build a Stacking two-layer modeling architecture and train the underlying LightGBM model using gradient unilateral sampling and mutual feature binding strategy; Step S52: Based on the Stacking two-layer modeling architecture, use a multi-decision-tree voting strategy to train the underlying random forest (RF) model; Step S53: Based on the Stacking two-layer modeling architecture, a fully connected structure is adopted and Dropout and batch normalization are added to train the underlying deep neural network (DNN) model; Step S54: Using K-fold cross-validation, the final feature set is input into the trained LightGBM model, Random Forest (RF) model, and Deep Neural Network (DNN) model to obtain the yield prediction probability; Step S55: Use the spliced ​​yield prediction probability as a new feature set, and use logistic regression as the top-level fusion model to input the new feature set to obtain the final yield prediction result.

8. A wafer fab yield prediction system based on multimodal big data and causal learning, used to execute the wafer fab yield prediction method based on multimodal big data and causal learning as described in claim 1; characterized in that, It includes a preprocessing module, an alignment and merging module, a sample augmentation module, a feature selection module, and a modeling and prediction module; The preprocessing module is used to preprocess the acquired raw wafer data to obtain a preprocessed raw wafer dataset. The alignment and merging unit is used to align and merge the preprocessed original wafer data line by line using wafer ID and timestamp as the association key to obtain a wafer sample set. The balancing unit is used to perform multi-stage adaptive VAE enhancement of wafer sample set and generate balanced sample set based on the sample imbalance status during the wafer fab R&D period, wafer fab mass production period and wafer fab transition period. The feature selection module is used to perform recursive feature elimination (RFE), mutual information (MI), and multi-level feature selection using elastic networks on the balanced sample set to obtain a final feature set with low redundancy and high discriminativeness. The modeling and prediction module is used to input the final feature set into the fusion prediction model built using the Stacking integrated architecture to predict the wafer yield.

9. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements a wafer fab yield prediction method based on multimodal big data and causal learning as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; when the computer instructions are executed on the electronic device as described in claim 9, they implement a wafer fab yield prediction method based on multimodal big data and causal learning as described in any one of claims 1-7.

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