Detection circuit and detection method, detection device and preparation method thereof, display panel

Abstract

The application discloses a detection circuit and a detection method, a detection device and a preparation method thereof, and a display panel, relates to the technical field of detection, and aims to improve the detection precision of the detection circuit. The detection circuit comprises a piezoelectric transducer, a signal amplification sub-circuit and a driving sub-circuit. The piezoelectric transducer is configured to output a first detection signal. The signal amplification sub-circuit is connected with the piezoelectric transducer. The signal amplification sub-circuit is configured to receive the first detection signal and output a second detection signal. The voltage value of the second detection signal is greater than the voltage value of the first detection signal. The driving sub-circuit is connected with the signal amplification sub-circuit. The driving sub-circuit is configured to receive the second detection signal. The detection device comprising the above detection circuit can be used for identifying fingerprints.

Description

Technical Field

[0001] This disclosure relates to the field of detection technology, and in particular to a detection circuit and detection method, a detection device and its preparation method, and a display panel. Background Technology

[0002] With the advancement of biometric technology, electronic devices with biometric functions have gradually entered people's lives and work. Fingerprints, including ridges and valleys on the surface of the skin of the fingertip, are inherent biological characteristics of the human body. Because fingerprints are unique and remain unchanged throughout life, fingerprint recognition technology has become an important means of personal identification and has received increasing attention. However, the fingerprint recognition accuracy of existing detection circuits needs improvement. Summary of the Invention

[0003] The embodiments of this disclosure provide a detection circuit and detection method, a detection device and its preparation method, and a display panel for improving the detection accuracy of the detection circuit.

[0004] On one hand, a detection circuit is provided. The detection circuit includes a piezoelectric transducer, a signal amplification subcircuit, and a driving subcircuit. The piezoelectric transducer is configured to output a first detection signal. The signal amplification subcircuit is connected to the piezoelectric transducer. The signal amplification subcircuit is configured to receive the first detection signal and output a second detection signal. The voltage value of the second detection signal is greater than the voltage value of the first detection signal. The driving subcircuit is connected to the signal amplification subcircuit. The driving subcircuit is configured to receive the second detection signal.

[0005] In the above detection circuit, the first detection signal is transmitted to the signal amplification sub-circuit. After the signal amplification sub-circuit amplifies the first detection signal, it is converted into a second detection signal, so that the voltage value of the second detection signal is greater than the voltage value of the first detection signal. This results in a larger voltage value of the second detection signal received by the driving sub-circuit, which helps to improve the detection accuracy of the detection circuit.

[0006] For example, when the detection circuit is used to identify fingerprints, since the voltage values ​​of the first detection signal corresponding to the valleys and ridges on the surface of the fingertip skin are different, the voltage values ​​of the second detection signal corresponding to the valleys and ridges on the surface of the fingertip skin are also different. Because the voltage value of the second detection signal is greater than the voltage value of the first detection signal, the difference between the voltage values ​​of the second detection signal corresponding to the valleys and ridges on the surface of the fingertip skin (hereinafter referred to as the second difference for ease of description) can be greater than the difference between the voltage values ​​of the first detection signal corresponding to the valleys and ridges on the surface of the fingertip skin (hereinafter referred to as the first difference for ease of description). This improves the detection accuracy of the detection circuit in identifying the valleys and ridges on the surface of the fingertip skin, thereby improving the fingerprint recognition accuracy of the detection circuit.

[0007] In some embodiments, the signal amplification sub-circuit is also connected to a first voltage signal terminal and a second voltage signal terminal, respectively. The voltage value of the first voltage signal provided by the first voltage signal terminal is different from the voltage value of the second voltage signal provided by the second voltage signal terminal.

[0008] In some embodiments, the signal amplification subcircuit includes a first transistor. The control electrode of the first transistor is connected to a piezoelectric transducer, the first electrode of the first transistor is connected to a first voltage signal terminal, and the second electrode of the first transistor is connected to a second voltage signal terminal.

[0009] In some embodiments, the signal amplification subcircuit further includes a first resistor, one end of which is connected to a first voltage signal terminal and the other end of which is connected to the first electrode of a first transistor.

[0010] In some embodiments, the common terminal of the first transistor and the first resistor is the first node. The driving sub-circuit is connected to the first node.

[0011] In some embodiments, the first transistor is an N-type transistor. The voltage value of the first voltage signal provided at the first voltage signal terminal is greater than the voltage value of the second voltage signal provided at the second voltage signal terminal.

[0012] In some embodiments, the resistance value of the first resistor is greater than or equal to 100 kΩ and less than or equal to 400 kΩ.

[0013] In some embodiments, the common terminal of the signal amplification subcircuit and the piezoelectric transducer is the second node. The detection circuit further includes a first reset subcircuit, which is connected to the first control signal terminal, the first bias voltage signal terminal, and the second node, respectively. The first reset subcircuit is configured to, in response to the first control signal provided by the first control signal terminal being at an active level, conduct the current path between the first bias voltage signal terminal and the second node to transmit the first bias voltage signal provided by the first bias voltage signal terminal to the second node.

[0014] In some embodiments, the first reset circuit includes a second transistor. The control electrode of the second transistor is connected to a first control signal terminal, the first electrode of the second transistor is connected to a first bias voltage signal terminal, and the second electrode of the second transistor is connected to a second node.

[0015] In some embodiments, the common terminal of the signal amplification subcircuit and the driving subcircuit is the third node. The detection circuit further includes a second reset subcircuit, which is connected to the second control signal terminal, the second bias voltage signal terminal, and the third node, respectively. The second reset subcircuit is configured to, in response to the second control signal provided at the second control signal terminal being at an active level, conduct the current path between the second bias voltage signal terminal and the third node to transmit the second bias voltage signal provided at the second bias voltage signal terminal to the third node.

[0016] In some embodiments, the second reset circuit includes a third transistor. The control electrode of the third transistor is connected to the second control signal terminal, the first electrode of the third transistor is connected to the second bias voltage signal terminal, and the second electrode of the third transistor is connected to the third node.

[0017] In some embodiments, the detection circuit further includes a first reset sub-circuit, which is connected to a first control signal terminal and a first bias voltage signal terminal, respectively. The first control signal terminal and the second control signal terminal are connected to the same first control signal line. And / or, the first bias voltage signal terminal and the second bias voltage signal terminal are connected to the same bias voltage signal line.

[0018] In some embodiments, the detection circuit further includes a first control sub-circuit, which is connected to the third control signal terminal, the signal amplification sub-circuit, and the third node, respectively. Alternatively, the detection circuit further includes a first control sub-circuit, which is connected to the third control signal terminal, the third node, and the driving sub-circuit, respectively.

[0019] On the other hand, a detection method for a detection circuit is provided. The detection method is applied to the detection circuit as described in any of the above embodiments. The detection method includes: The piezoelectric transducer outputs the first detection signal.

[0020] The signal amplification sub-circuit receives the first detection signal and outputs the second detection signal. The voltage value of the second detection signal is greater than the voltage value of the first detection signal.

[0021] The driver circuit receives the second detection signal.

[0022] In some embodiments, the signal amplification subcircuit includes a first transistor and a first resistor. One end of the first resistor is connected to a first voltage signal terminal, and the other end is connected to a first electrode of the first transistor. The control electrode of the first transistor is connected to a piezoelectric transducer, and the second electrode of the first transistor is connected to a second voltage signal terminal. The common terminal of the first transistor and the first resistor is a first node. The driving subcircuit is connected to the first node.

[0023] The signal amplification sub-circuit receives the first detection signal and outputs the second detection signal, including: In response to a first detection signal, the first transistor turns on the current path between the first voltage signal terminal and the second voltage signal terminal.

[0024] The second detection signal is generated at the first node and output to the driver sub-circuit.

[0025] In another aspect, a detection device is provided. The detection device includes a substrate and a plurality of detection units, the plurality of detection units being located on one side of the substrate along a first direction, the first direction being the thickness direction of the substrate. The detection units include the detection circuit as described in any of the above embodiments.

[0026] In some embodiments, the detection unit includes a piezoelectric transducer and a first transistor. The first transistor includes a first gate, which is connected to the piezoelectric transducer.

[0027] In some embodiments, the piezoelectric transducer includes a first electrode connected to a first gate. The first electrode is located on the side of the film layer containing the first gate that is away from the substrate.

[0028] In some embodiments, the detection unit further includes a first transition pattern located between the film layer containing the first electrode and the film layer containing the first gate. The first gate is connected to the first electrode via the first transition pattern.

[0029] In some embodiments, the detection device further includes a first voltage signal line. The first transistor further includes a first active pattern, the orthographic projection of the first active pattern onto the substrate and the orthographic projection of the first gate onto the substrate overlapping. The detection unit further includes a first resistor, one end of which is connected to the first voltage signal line and the other end of which is connected to the first active pattern.

[0030] In some embodiments, the first resistor is arranged in a serpentine pattern.

[0031] In some embodiments, in a projection onto the substrate, the first resistor is located on one side of the first active pattern along a second direction, which is perpendicular to the first direction.

[0032] In some embodiments, the first resistor and the first active pattern are disposed on the same layer, and the first resistor and the first active pattern are interconnected to form an integral structure.

[0033] In some embodiments, the first voltage signal line extends along a second direction, which is perpendicular to the first direction. In a projection onto the substrate, the first voltage signal line and the first resistor overlap.

[0034] In some embodiments, in the orthographic projection onto the substrate, the first active pattern is located on one side of the first resistor along the second direction, and the first active pattern and the first voltage signal line are spaced apart along a third direction, which is perpendicular to the first direction and intersects the second direction.

[0035] In some embodiments, the first voltage signal line extends along a second direction, which is perpendicular to the first direction. The detection device further includes a signal readout line. The detection unit also includes a fourth transistor, which includes a fourth active pattern connected to the signal readout line. In a projection onto the substrate, along a third direction, the first voltage signal line is located between the first and fourth active patterns, the third direction being perpendicular to the first direction and intersecting the second direction.

[0036] In some embodiments, the detection device further includes a second voltage signal line extending along a second direction perpendicular to the first direction. In an orthographic projection onto the substrate, the second voltage signal line is located on one side of the first active pattern along a third direction perpendicular to the first direction, and the third direction intersects the second direction. The first active pattern is also connected to the second voltage signal line.

[0037] In some embodiments, the first voltage signal line extends along a second direction. In a projection onto the substrate, along a third direction, the first voltage signal line is located between the first active pattern and the second voltage signal line. The detection unit further includes a second transition pattern, through which the first active pattern is connected to the second voltage signal line. In a projection onto the substrate, the second transition pattern and the first voltage signal line overlap.

[0038] In some embodiments, the second transition pattern is located between the film layer containing the first active pattern and the film layer containing the second voltage signal line.

[0039] In some embodiments, the detection device further includes a signal readout line. The detection unit also includes a fourth transistor, which includes a fourth active pattern connected to the signal readout line. In a normal projection onto the substrate, along a third direction, the second voltage signal line is located between the first active pattern and the fourth active pattern.

[0040] In some embodiments, the detection device further includes a first bias voltage signal line. The detection unit further includes a second transistor, the second transistor including a second active pattern, the second active pattern being connected to the first bias voltage signal line and the first gate, respectively.

[0041] In some embodiments, the first transistor further includes a first active pattern. In an orthographic projection onto the substrate, the second active pattern is located on one side of the first active pattern along a third direction perpendicular to the first direction.

[0042] In some embodiments, the detection device further includes a second bias voltage signal line. The first transistor further includes a first active pattern. The detection unit further includes a third transistor, which includes a third active pattern, and the third active pattern is connected to both the second bias voltage signal line and the first active pattern.

[0043] In some embodiments, the first active pattern and the third active pattern are disposed on the same layer, and the first active pattern and the third active pattern are interconnected to form an integral structure.

[0044] In some embodiments, in orthographic projection onto the substrate, the third active pattern is located on one side of the first active pattern along a third direction, which is perpendicular to the first direction.

[0045] In some embodiments, the detection unit further includes a second transistor, the second transistor including a second active pattern. In a normal projection onto the substrate, along a third direction, the second active pattern is located between the first active pattern and the third active pattern.

[0046] In some embodiments, the detection device further includes a first bias voltage signal line. Both the first bias voltage signal line and the second bias voltage signal line extend along a third direction, and are spaced apart along a second direction. Both the second direction and the third direction are perpendicular to the first direction, and the second direction and the third direction intersect.

[0047] The first bias voltage signal line and the second bias voltage signal line are located on one side of the detection unit along the second direction.

[0048] In another aspect, a method for fabricating a detection device is provided. The method includes forming a plurality of detection units on one side of a substrate along a first direction, where the first direction is the thickness direction of the substrate. Each detection unit includes a detection circuit as described in any of the above embodiments.

[0049] The detection unit includes: A first transistor is formed. The first transistor includes a first gate.

[0050] A piezoelectric transducer is formed. The piezoelectric transducer is connected to the first gate.

[0051] In another aspect, a display panel is provided. The display panel includes a display substrate and a detection device as described in any of the above embodiments. The detection device is located on the non-display side of the display substrate.

[0052] It is understood that the beneficial effects of the detection circuit, detection device, and preparation method and display panel provided in the above embodiments of this disclosure can be referred to the beneficial effects of the detection circuit described above, and will not be repeated here. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0054] Figure 1 This is a plan view of a display device according to some embodiments; Figure 2 This is a cross-sectional view of a partial area within a display panel according to some embodiments; Figure 3 This is a plan view of a local area within a detection device according to some embodiments; Figure 4 This is another plan view of a local area within a detection device according to some embodiments; Figure 5 This is a block diagram of a detection circuit within a detection unit according to some embodiments; Figure 6 This is another block diagram of the detection circuit within a detection unit according to some embodiments; Figures 7-10 , Figures 13-28 , Figure 32 and Figure 33 Various plan views of local regions of the film layer within the detection device 20 according to some embodiments; Figure 11 and Figure 12 , Figures 34-44Various equivalent circuit diagrams of the detection circuit according to some embodiments; Figure 29 A waveform diagram of a first signal provided by a transmitting signal terminal according to some embodiments; Figure 30 A waveform diagram of the first detection signal according to some embodiments; Figure 31 A waveform diagram of the second detection signal according to some embodiments; Figure 45 for Figure 11 , Figure 12 , Figures 34-44 The driving timing diagram of the detection circuit is shown. Detailed Implementation

[0055] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0056] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0057] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0058] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0059] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0060] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0061] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0062] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0063] For ease of description below, an XYZ coordinate system is established. The first direction Z is the thickness direction of the substrate, and the second direction Y and the third direction X are both perpendicular to the first direction Z, and the second direction Y and the third direction X intersect. For example, the second direction Y and the third direction X can be perpendicular to each other.

[0064] It should be noted that, for example, 11(1) in the accompanying drawings of this disclosure indicates that component 11 belongs to component 1, and for example, T22 / T32 indicates that the component can be either T22 or T32. Other similar reference numerals in the accompanying drawings also follow the above description.

[0065] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000.

[0066] Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether it is text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The following is an illustration using a mobile phone as an example, with display device 1000 as an example.

[0067] For example, the display device 1000 may be an electroluminescent display device.

[0068] Alternatively, the display device 1000 may be a photoluminescent display device.

[0069] Alternatively, the display device 1000 can be a micro light-emitting diode (Micro LED) display device.

[0070] Alternatively, the display device 1000 can be a sub-millimeter light-emitting diode (Mini LED) display device.

[0071] Alternatively, the display device 1000 can be a thin film transistor liquid crystal display (TFT-LCD) device, etc.

[0072] For example, if the display device 1000 is an electroluminescent display device, the display device 1000 may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device, etc.

[0073] For example, if the display device 1000 is a photoluminescent display device, the display device 1000 may be a quantum dot photoluminescent display device.

[0074] In some embodiments, please continue reading Figure 1 The display device 1000 may include a display panel 100 and a driver chip (not shown in the figure), with the driver chip connected to the display panel 100.

[0075] In the aforementioned display device 1000, the driver chip is connected to the display panel 100, so that the driver chip can be configured to drive the display panel 100 to display images.

[0076] It should be noted that, from the perspective of connection medium and signal transmission principle, the above-mentioned "connection" can be electrical connection, etc.

[0077] For example, the connection between the driver chip and the display panel 100 can be an electrical connection.

[0078] When the connection between the driver chip and the display panel 100 is an electrical connection, an electrical path can be established between the driver chip and the display panel 100 through a conductive material, so that electrical signals can be effectively transmitted between the driver chip and the display panel 100.

[0079] From the perspective of the connection path, the above "connection" can be a direct connection or an indirect connection, etc.

[0080] For example, the connection between the driver chip and the display panel 100 can be a direct connection.

[0081] When the connection between the driver chip and the display panel 100 is a direct connection, the driver chip and the display panel 100 can communicate directly through a dedicated channel to achieve fast data signal transmission.

[0082] For example, the connection between the driver chip and the display panel 100 can be an indirect connection.

[0083] When the connection between the driver chip and the display panel 100 is indirect, the driver chip and the display panel 100 can transfer data signals through an intermediate component to enhance the flexibility of the display device 1000.

[0084] The following description of "connection" will follow this explanation and will not be repeated.

[0085] For example, when the display device 1000 is an organic light-emitting diode (OLED) display device, the display panel 100 within the display device 1000 can be an organic light-emitting diode (OLED) display panel.

[0086] When the display device 1000 is a quantum dot light-emitting diode display device, the display panel 100 within the display device 1000 can be a quantum dot light-emitting diode display panel.

[0087] When the display device 1000 is a quantum dot photoluminescent diode display device, the display panel 100 within the display device 1000 can be a quantum dot photoluminescent diode display panel.

[0088] When the display device 1000 is a micro-light-emitting diode display device, the display panel 100 inside the display device 1000 can be a micro-light-emitting diode display panel.

[0089] When the display device 1000 is a sub-millimeter light-emitting diode display device, the display panel 100 within the display device 1000 can be a sub-millimeter light-emitting diode display panel.

[0090] When the display device 1000 is a thin-film transistor liquid crystal display device, the display panel 100 within the display device 1000 can be a thin-film transistor liquid crystal display panel.

[0091] For example, the driver chip may include a display driver integrated circuit (DDIC), etc.

[0092] For example, the driver chip can be packaged in a way that uses chip on film (COF), chip on glass (COG), or chip on flexible material (COP) and bonded to the display panel 100.

[0093] The structure of the above-mentioned display panel 100 will be described in detail below.

[0094] In some embodiments, such as Figure 2 As shown, Figure 2 This is a cross-sectional view of a partial area within a display panel 100 according to some embodiments. The display panel 100 may include a display substrate 10 and a detection device 20. The detection device 20 may be located on the non-display side 10b of the display substrate 10.

[0095] It should be noted that the display side 10a of the display substrate 10 refers to the side of the display substrate 10 where the image can be displayed. The aforementioned "non-display side 10b of the display substrate 10" refers to the side opposite to the display side 10a of the display substrate 10.

[0096] For example, the detection device 20 can be used to identify biometric features.

[0097] For example, the detection device 20 can be used to identify biometric features such as fingerprints.

[0098] For example, the detection device 20 can be an ultrasonic detection device.

[0099] In the aforementioned display panel 100, when the display substrate 10 within the display panel 100 includes a black pixel definition layer (BPDL) and / or a black matrix (BM) layer, since the detection device 20 within the display panel 100 is an ultrasonic detection device, the detection device 20 can perform detection (e.g., fingerprint detection) via ultrasonic waves. Therefore, there is no need for the black pixel definition layer and / or black matrix layer to optically avoid the detection device 20, which is beneficial to improving the display uniformity of the display substrate 10 and thus improving the display effect of the display panel 100.

[0100] In some embodiments, please continue reading Figure 2 The display panel 100 may include a color filter 30.

[0101] In the aforementioned display panel 100, the color filter 30 can absorb or reflect light of non-target wavelengths, thereby reducing stray light interference and improving the display effect of the display panel 100.

[0102] For example, please continue reading Figure 2 The color filter 30 can be directly integrated into the encapsulation layer within the display substrate 10. On the one hand, this shortens the optical path and improves the luminous efficiency of the display panel 100. On the other hand, it eliminates the need for a polarizer within the display panel 100, thereby avoiding interference with black purity and improving the display effect of the display panel 100.

[0103] For example, please continue reading Figure 2 In the case where the display panel 100 also includes a display substrate 10 and a detection device 20, and the detection device 20 is located on the non-display side 10b of the display substrate 10, the color filter 30 may be located on the side of the display substrate 10 away from the detection device 20.

[0104] The structure of the above-mentioned detection device 20 will be described in detail below.

[0105] In some embodiments, such as Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 These are all plan views of a local area within the detection device 20 according to some embodiments. The detection device 20 may include a substrate 201.

[0106] For example, please continue reading Figure 3 and Figure 4 The material of the substrate 201 may include at least one of glass, polyimide (PI), and semiconductor materials.

[0107] For example, if the material of the substrate 201 includes a semiconductor material, the material of the substrate 201 may include silicon (Si) and the like.

[0108] In some embodiments, please continue reading Figure 3 and Figure 4 The detection device 20 may include multiple detection units 1.

[0109] When the detection device 20 also includes a substrate 201, the plurality of detection units 1 in the detection device 20 may be located on one side of the substrate 201 along the first direction Z, where the first direction Z is the thickness direction of the substrate 201.

[0110] For example, please continue reading Figure 3 and Figure 4 Multiple detection units 1 within the detection device 20 can be arranged in an array.

[0111] For example, please continue reading Figure 3 and Figure 4 Multiple detection units 1 within the detection device 20 can be arranged at intervals along the third direction X and the second direction Y, respectively. The third direction X and the second direction Y are both perpendicular to the first direction Z, and the third direction X and the second direction Y intersect.

[0112] The third direction X can be the row direction in which multiple detection units 1 are arranged in an array. That is, a row of detection units 1 can include multiple detection units 1 arranged at intervals along the third direction X.

[0113] The second direction Y can be the column direction in which multiple detection units 1 are arranged in an array. That is, a column of detection units 1 can include multiple detection units 1 arranged at intervals along the second direction Y.

[0114] For example, please continue reading Figure 3 and Figure 4When multiple detection units 1 in the detection device 20 are arranged at intervals along the third direction X and the second direction Y, along the third direction X, two adjacent detection units 1 can be symmetrically arranged with respect to the virtual line N1 extending along the second direction Y.

[0115] And / or, along the second direction Y, two adjacent detection units 1 can be symmetrically arranged relative to the virtual line N2 extending along the third direction X.

[0116] For example, such as Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 These are all block diagrams of a detection circuit 11 within a detection unit 1 according to some embodiments. The detection unit 1 may include the detection circuit 11 (the structure of the detection circuit 11 will be described in detail below).

[0117] In some embodiments, such as Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 These are all plan views of a partial region of the second conductive layer 204 within the detection device 20 according to some embodiments. The detection device 20 may include a first voltage signal line 2.

[0118] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the first voltage signal line 2 can be connected to the detection unit 1.

[0119] For example, please continue reading Figure 7 and Figure 8 The first voltage signal line 2 can extend along the second direction Y.

[0120] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple first voltage signal lines 2, and the multiple first voltage signal lines 2 may be arranged at intervals along a third direction X.

[0121] For example, please continue reading Figure 3 and Figure 4 When the first voltage signal line 2 extends along the second direction Y, one first voltage signal line 2 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0122] In some embodiments, please continue reading Figure 7 and Figure 8 The detection device 20 may include a second voltage signal line 3.

[0123] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the second voltage signal line 3 can be connected to the detection unit 1.

[0124] For example, please continue reading Figure 7 and Figure 8 The second voltage signal line 3 can extend along the second direction Y.

[0125] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple second voltage signal lines 3, and the multiple second voltage signal lines 3 may be arranged at intervals along a third direction X.

[0126] For example, please continue reading Figure 3 and Figure 4 When the second voltage signal line 3 extends along the second direction Y, one second voltage signal line 3 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0127] For example, please continue reading Figure 7 and Figure 8 When the detection device 20 also includes a first voltage signal line 2, and both the first voltage signal line 2 and the second voltage signal line 3 extend along the second direction Y, the first voltage signal line 2 and the second voltage signal line 3 can be arranged at intervals along the third direction X.

[0128] In some embodiments, please continue reading Figure 7 and Figure 8 The detection device 20 may include a first control signal line 4.

[0129] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the first control signal line 4 can be connected to the detection unit 1.

[0130] For example, please continue reading Figure 7 and Figure 8 The first control signal line 4 can extend along the second direction Y.

[0131] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple first control signal lines 4, and the multiple first control signal lines 4 may be arranged at intervals along a third direction X.

[0132] For example, please continue reading Figure 3 and Figure 4When the first control signal line 4 extends along the second direction Y, one first control signal line 4 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0133] For example, please continue reading Figure 3 and Figure 4 When the first control signal line 4 extends along the second direction Y, the first control signal line 4 can be located on one side of the detection unit 1 along the third direction X.

[0134] For example, along a third direction X, a first control signal line 4 can be located between two adjacent detection units 1.

[0135] For example, please continue reading Figure 3 and Figure 4 Along the third direction X, the two first control signal lines 4 can be located between two adjacent detection units 1.

[0136] For example, please continue reading Figure 7 and Figure 8 In the case that the detection device 20 also includes a first voltage signal line 2 and a second voltage signal line 3, and the first voltage signal line 2, the second voltage signal line 3 and the first control signal line 4 all extend along the second direction Y, the first voltage signal line 2, the second voltage signal line 3 and the first control signal line 4 can be arranged at intervals along the third direction X.

[0137] In some embodiments, please continue reading Figure 7 and Figure 8 The detection device 20 may include a third control signal line 5.

[0138] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the third control signal line 5 can be connected to the detection unit 1.

[0139] For example, please continue reading Figure 7 and Figure 8 The third control signal line 5 can extend along the second direction Y.

[0140] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple third control signal lines 5, and the multiple third control signal lines 5 may be arranged at intervals along a third direction X.

[0141] For example, when the third control signal line 5 extends along the second direction Y, one third control signal line 5 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0142] Alternatively, please continue reading Figure 3 and Figure 4 When the third control signal line 5 extends along the second direction Y, one third control signal line 5 can be connected to two adjacent detection units 1.

[0143] For example, please continue reading Figure 3 and Figure 4 When the third control signal line 5 extends along the second direction Y, the third control signal line 5 can be located on one side of the detection unit 1 along the third direction X.

[0144] For example, please continue reading Figure 3 and Figure 4 Along the third direction X, a third control signal line 5 can be located between two adjacent detection units 1.

[0145] For example, please continue reading Figure 3 and Figure 4 and combined Figure 7 and Figure 8 In the case where the detection device 20 also includes a first control signal line 4, and both the first control signal line 4 and the third control signal line 5 extend along the second direction Y and along the third direction X, and the two first control signal lines 4 are located between two adjacent detection units 1, along the third direction X, a third control signal line 5 can be located between two adjacent detection units 1 and can be located between two first control signal lines 4.

[0146] For example, please continue reading Figure 7 and Figure 8 In the case that the detection device 20 also includes a first voltage signal line 2, a second voltage signal line 3 and a first control signal line 4, and the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4 and the third control signal line 5 all extend along the second direction Y, the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4 and the third control signal line 5 can be arranged at intervals along the third direction X.

[0147] In some embodiments, please continue reading Figure 7 and Figure 8 The detection device 20 may include a fourth control signal line 6.

[0148] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the fourth control signal line 6 can be connected to the detection unit 1.

[0149] For example, please continue reading Figure 7 and Figure 8 The fourth control signal line 6 can extend along the second direction Y.

[0150] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple fourth control signal lines 6, and the multiple fourth control signal lines 6 may be arranged at intervals along a third direction X.

[0151] For example, please continue reading Figure 3 and Figure 4 When the fourth control signal line 6 extends along the second direction Y, one fourth control signal line 6 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0152] For example, please continue reading Figure 7 and Figure 8 When the detection device 20 further includes a first voltage signal line 2, a second voltage signal line 3, a first control signal line 4, and a third control signal line 5, and the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4, the third control signal line 5, and the fourth control signal line 6 all extend along the second direction Y, the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4, the third control signal line 5, and the fourth control signal line 6 can be arranged at intervals along the third direction X.

[0153] In some embodiments, please continue reading Figure 7 and Figure 8 The detection device 20 may include a third bias voltage signal line 73.

[0154] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the third bias voltage signal line 73 can be connected to the detection unit 1.

[0155] For example, please continue reading Figure 7 and Figure 8 The third bias voltage signal line 73 can extend along the second direction Y.

[0156] For example, please continue reading Figure 7 and Figure 8 The detection device 20 may include multiple third bias voltage signal lines 73, and the multiple third bias voltage signal lines 73 may be arranged at intervals along the third direction X.

[0157] For example, please continue reading Figure 3 and Figure 4 When the third bias voltage signal line 73 extends along the second direction Y, one third bias voltage signal line 73 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the second direction Y).

[0158] For example, please continue reading Figure 3 and Figure 4 When the third bias voltage signal line 73 extends along the second direction Y, the third bias voltage signal line 73 can be located on one side of the detection unit 1 along the third direction X.

[0159] For example, please continue reading Figure 3 and Figure 4 Along the third direction X, the third bias voltage signal line 73 can be located between two adjacent detection units 1.

[0160] For example, please continue reading Figure 3 and Figure 4 In the case that the detection device 20 also includes a third control signal line 5, and both the third control signal line 5 and the third bias voltage signal line 73 extend along the second direction Y, the third control signal line 5 and the third bias voltage signal line 73 can be located on opposite sides of the detection unit 1 along the third direction X.

[0161] For example, please continue reading Figure 7 and Figure 8 When the detection device 20 further includes a first voltage signal line 2, a second voltage signal line 3, a first control signal line 4, a third control signal line 5, and a fourth control signal line 6, and the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4, the third control signal line 5, the fourth control signal line 6, and the third bias voltage signal line 73 all extend along the second direction Y, the first voltage signal line 2, the second voltage signal line 3, the first control signal line 4, the third control signal line 5, the fourth control signal line 6, and the third bias voltage signal line 73 can be arranged at intervals along the third direction X.

[0162] In some embodiments, such as Figure 9 and Figure 10 As shown, Figure 9 and Figure 10 These are all plan views of a partial region of the first conductive layer 203 within the detection device 20 according to some embodiments. The detection device 20 may include a first bias voltage signal line 71.

[0163] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the first bias voltage signal line 71 can be connected to the detection unit 1.

[0164] For example, please continue reading Figure 9 and Figure 10 The first bias voltage signal line 71 can extend along the third direction X.

[0165] For example, please continue reading Figure 9 and Figure 10 The detection device 20 may include multiple first bias voltage signal lines 71, and the multiple first bias voltage signal lines 71 may be arranged at intervals along the second direction Y.

[0166] For example, please continue reading Figure 3 and Figure 4 When the first bias voltage signal line 71 extends along the third direction X, one first bias voltage signal line 71 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the third direction X).

[0167] Alternatively, if the first bias voltage signal line 71 extends along a third direction X, one first bias voltage signal line 71 can be connected to two adjacent rows of detection units 1.

[0168] For example, please continue reading Figure 3 and Figure 4 When the first bias voltage signal line 71 extends along the third direction X, the first bias voltage signal line 71 can be located on one side of the detection unit 1 along the second direction Y.

[0169] For example, please continue reading Figure 3 and Figure 4 Along the second direction Y, the first bias voltage signal line 71 can be located between two adjacent detection units 1.

[0170] For example, please continue reading Figure 3 In the case where the detection device 20 also includes a third bias voltage signal line 73, the first bias voltage signal line 71 can be connected to the third bias voltage signal line 73.

[0171] In the aforementioned detection device 20, when the first bias voltage signal line 71 extends along the third direction X and the third bias voltage signal line 73 extends along the second direction Y, since the third direction X and the second direction Y intersect, the first bias voltage signal line 71 extending along the third direction X and the third bias voltage signal line 73 extending along the second direction Y together form a mesh structure. This can reduce the attenuation of the first bias voltage signal transmitted in the first bias voltage signal line 71 and the third bias voltage signal line 73 during transmission, thereby improving the consistency of the first bias voltage signal received by the multiple detection units 1 in the detection device 20, and thus improving the detection accuracy of the detection device 20.

[0172] In some embodiments, please continue reading Figure 10 The detection device 20 may include a second bias voltage signal line 72.

[0173] Please continue reading. Figure 4If the detection device 20 also includes a detection unit 1, the second bias voltage signal line 72 can be connected to the detection unit 1.

[0174] For example, please continue reading Figure 10 The second bias voltage signal line 72 can extend along the third direction X.

[0175] For example, please continue reading Figure 10 The detection device 20 may include multiple second bias voltage signal lines 72, and the multiple second bias voltage signal lines 72 may be arranged at intervals along the second direction Y.

[0176] For example, please continue reading Figure 4 When the second bias voltage signal line 72 extends along the third direction X, one second bias voltage signal line 72 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the third direction X).

[0177] Alternatively, if the second bias voltage signal line 72 extends along the third direction X, one second bias voltage signal line 72 can be connected to two adjacent rows of detection units 1.

[0178] For example, please continue reading Figure 4 When the second bias voltage signal line 72 extends along the third direction X, the second bias voltage signal line 72 can be located on one side of the detection unit 1 along the second direction Y.

[0179] For example, please continue reading Figure 4 Along the second direction Y, the second bias voltage signal line 72 can be located between two adjacent detection units 1.

[0180] For example, please continue reading Figure 10 In the case that the detection device 20 also includes a first bias voltage signal line 71, and both the first bias voltage signal line 71 and the second bias voltage signal line 72 extend along the third direction X, the first bias voltage signal line 71 and the second bias voltage signal line 72 can be arranged at intervals along the second direction Y.

[0181] For example, please continue reading Figure 4 In the case where the detection device 20 also includes a third bias voltage signal line 73, the second bias voltage signal line 72 can be connected to the third bias voltage signal line 73.

[0182] In the aforementioned detection device 20, when the second bias voltage signal line 72 extends along the third direction X and the third bias voltage signal line 73 extends along the second direction Y, since the third direction X and the second direction Y intersect, the second bias voltage signal line 72 extending along the third direction X and the third bias voltage signal line 73 extending along the second direction Y together form a mesh structure. This can reduce the attenuation of the second bias voltage signal transmitted in the second bias voltage signal line 72 and the third bias voltage signal line 73 during transmission, thereby improving the consistency of the second bias voltage signal received by the multiple detection units 1 in the detection device 20, and thus improving the detection accuracy of the detection device 20.

[0183] In some embodiments, please continue reading Figure 9 and Figure 10 The detection device 20 may include a signal reading line 81.

[0184] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the signal reading line 81 can be connected to the detection unit 1.

[0185] For example, please continue reading Figure 9 and Figure 10 The signal reading line 81 can extend along a third direction X.

[0186] For example, please continue reading Figure 9 and Figure 10 The detection device 20 may include multiple signal reading lines 81, and the multiple signal reading lines 81 may be arranged at intervals along the second direction Y.

[0187] For example, please continue reading Figure 3 and Figure 4 When the signal reading line 81 extends along the third direction X, one signal reading line 81 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the third direction X).

[0188] For example, please continue reading Figure 3 and Figure 4 When the signal reading line 81 extends along the third direction X, the signal reading line 81 can be located on one side of the detection unit 1 along the second direction Y.

[0189] For example, please continue reading Figure 3 and Figure 4 Along the second direction Y, the signal reading line 81 can be located between two adjacent detection units 1.

[0190] For example, please continue reading Figure 9 and Figure 10In the case that the detection device 20 also includes a first bias voltage signal line 71, and both the first bias voltage signal line 71 and the signal reading line 81 extend along the third direction X, the first bias voltage signal line 71 and the signal reading line 81 can be arranged at intervals along the second direction Y.

[0191] For example, please continue reading Figure 10 When the detection device 20 also includes a second bias voltage signal line 72, and both the second bias voltage signal line 72 and the signal reading line 81 extend along the third direction X, the second bias voltage signal line 72 and the signal reading line 81 can be arranged at intervals along the second direction Y.

[0192] In some embodiments, please continue reading Figure 9 and Figure 10 The detection device 20 may include a third voltage signal line 82.

[0193] Please continue reading. Figure 3 and Figure 4 If the detection device 20 also includes a detection unit 1, the third voltage signal line 82 can be connected to the detection unit 1.

[0194] For example, please continue reading Figure 9 and Figure 10 The third voltage signal line 82 can extend along the third direction X.

[0195] For example, please continue reading Figure 9 and Figure 10 The detection device 20 may include multiple third voltage signal lines 82, and the multiple third voltage signal lines 82 may be arranged at intervals along the second direction Y.

[0196] For example, when the third voltage signal line 82 extends along the third direction X, one third voltage signal line 82 can be connected to a row of detection units 1 (i.e., multiple detection units 1 arranged at intervals along the third direction X).

[0197] Alternatively, please continue reading Figure 3 and Figure 4 When the third voltage signal line 82 extends along the third direction X, one third voltage signal line 82 can be connected to two adjacent rows of detection units 1.

[0198] For example, please continue reading Figure 3 and Figure 4 When the third voltage signal line 82 extends along the third direction X, the third voltage signal line 82 can be located on one side of the detection unit 1 along the second direction Y.

[0199] For example, please continue reading Figure 3 and Figure 4Along the second direction Y, the third voltage signal line 82 can be located between two adjacent detection units 1.

[0200] For example, please continue reading Figure 9 and Figure 10 In the case that the detection device 20 also includes a first bias voltage signal line 71 and a signal reading line 81, and the first bias voltage signal line 71, the signal reading line 81 and the third voltage signal line 82 all extend along the third direction X, the first bias voltage signal line 71, the signal reading line 81 and the third voltage signal line 82 can be arranged at intervals along the second direction Y.

[0201] For example, please continue reading Figure 10 When the detection device 20 also includes a first bias voltage signal line 71, a second bias voltage signal line 72, and a signal reading line 81, and the first bias voltage signal line 71, the second bias voltage signal line 72, the signal reading line 81, and the third voltage signal line 82 all extend along the third direction X, the first bias voltage signal line 71, the second bias voltage signal line 72, the signal reading line 81, and the third voltage signal line 82 can be arranged at intervals along the second direction Y.

[0202] For example, please continue reading Figure 3 and Figure 4 In the case where the detection device 20 also includes a first bias voltage signal line 71 and a signal reading line 81, and the first bias voltage signal line 71, the signal reading line 81 and the third voltage signal line 82 all extend along the third direction X, among the first bias voltage signal line 71, the signal reading line 81 and the third voltage signal line 82 connected to the same detection unit 1, along the second direction Y, the first bias voltage signal line 71 and the signal reading line 81 can be located on one side of the detection unit 1, and the third voltage signal line 82 can be located on the other side of the detection unit 1.

[0203] For example, please continue reading Figure 4 In the case where the detection device 20 also includes a first bias voltage signal line 71, a second bias voltage signal line 72, and a signal reading line 81, and the first bias voltage signal line 71, the second bias voltage signal line 72, the signal reading line 81, and the third voltage signal line 82 all extend along the third direction X, among the first bias voltage signal line 71, the second bias voltage signal line 72, the signal reading line 81, and the third voltage signal line 82 connected to the same detection unit 1, along the second direction Y, the first bias voltage signal line 71, the second bias voltage signal line 72, and the signal reading line 81 can be located on one side of the detection unit 1, and the third voltage signal line 82 can be located on the other side of the detection unit 1.

[0204] The detection circuit 11 within the detection unit 1 described above will be explained in detail below.

[0205] In some embodiments, please continue reading Figure 5 and Figure 6 The detection circuit 11 may include a piezoelectric transducer C1, which is configured to output a first detection signal.

[0206] For example, please continue reading Figure 5 and Figure 6 The piezoelectric transducer C1 may include a first electrode C11, a second electrode C12, and a piezoelectric material layer C13, with the piezoelectric material layer C13 located between the first electrode C11 and the second electrode C12.

[0207] For example, please continue reading Figure 5 and Figure 6 When the detection device 20 is used to identify fingerprints, since the surface of the fingertip skin has valleys and ridges, the working principle of the piezoelectric transducer C1 can be as follows: after ultrasonic waves (e.g., ultrasonic waves emitted by an ultrasonic transmitter) come into contact with the surface of the fingertip skin, they are either reflected or absorbed (e.g., most of the ultrasonic waves that come into contact with the valleys of the fingertip skin surface can be reflected; most of the ultrasonic waves that come into contact with the ridges of the fingertip skin surface can be absorbed, and a small portion can be reflected), the vibration intensity of the ultrasonic waves reflected from different locations (e.g., valleys and ridges within the fingertip skin surface) varies.

[0208] The piezoelectric material layer C13 inside the piezoelectric transducer C1 is deformed by the reflected ultrasonic waves, which allows the piezoelectric transducer C1 to output the first detection signal.

[0209] Because the vibration intensity of the ultrasonic waves reflected from the valleys and ridges on the surface of the fingertip skin differs, the deformation of the piezoelectric material layer C13 caused by receiving ultrasonic waves reflected from the valleys on the surface of the fingertip skin can be different from the deformation caused by receiving ultrasonic waves reflected from the ridges on the surface of the fingertip skin. Consequently, the voltage value of the first detection signal corresponding to the valleys on the surface of the fingertip skin can be different from the voltage value of the first detection signal corresponding to the ridges on the surface of the fingertip skin.

[0210] For example, please continue reading Figure 5 and Figure 6 The second electrode C12 inside the piezoelectric transducer C1 can be connected to the transmitting signal terminal Tx.

[0211] For example, please continue reading Figure 5 and Figure 6 The materials of the first electrode C11 and the second electrode C12 in the piezoelectric transducer C1 can both include at least one of metals and metal oxides.

[0212] For example, if the materials of the first electrode C11 and the second electrode C12 in the piezoelectric transducer C1 both include metals, the materials of the first electrode C11 and the second electrode C12 in the piezoelectric transducer C1 can each include one or more (two or more) of platinum (Pt), iridium (Ir), gold (Au), aluminum (Al), copper (Cu), titanium (Ti) and stainless steel.

[0213] For example, if the materials of the first electrode C11 and the second electrode C12 in the piezoelectric transducer C1 both include metal oxides, the materials of the first electrode C11 and the second electrode C12 in the piezoelectric transducer C1 can both include one or a combination of indium tin oxide (ITO) and fluorine-doped tin oxide.

[0214] For example, please continue reading Figure 5 and Figure 6 The material of the piezoelectric material layer C13 in the piezoelectric transducer C1 may include one or a combination of polyvinylidene fluoride (PVDF) and aluminum nitride (AlN).

[0215] In some embodiments, please continue reading Figure 5 and Figure 6 The detection circuit 11 may include a signal amplification sub-circuit 111.

[0216] When the detection circuit 11 also includes a piezoelectric transducer C1, and the piezoelectric transducer C1 is configured to output a first detection signal, the signal amplification sub-circuit 111 can be connected to the piezoelectric transducer C1. The signal amplification sub-circuit 111 can be configured to receive the first detection signal and output a second detection signal. The voltage value of the second detection signal is greater than the voltage value of the first detection signal.

[0217] For example, please continue reading Figure 5 and Figure 6 The signal amplification sub-circuit 111 is configured to receive a first detection signal and output a second detection signal. When the detection device 20 is used to identify fingerprints, since the voltage value of the first detection signal corresponding to the valleys in the skin surface of the fingertip is different from the voltage value of the first detection signal corresponding to the ridges in the skin surface of the fingertip, the voltage value of the second detection signal corresponding to the valleys in the skin surface of the fingertip is also different from the voltage value of the second detection signal corresponding to the ridges in the skin surface of the fingertip.

[0218] Since the voltage value of the second detection signal is greater than the voltage value of the first detection signal, the difference between the voltage value of the second detection signal corresponding to the valley in the skin surface of the fingertip and the voltage value of the second detection signal corresponding to the ridge in the skin surface of the fingertip (hereinafter referred to as the second difference for ease of description) can be greater than the difference between the voltage value of the first detection signal corresponding to the valley in the skin surface of the fingertip and the voltage value of the first detection signal corresponding to the ridge in the skin surface of the fingertip (hereinafter referred to as the first difference for ease of description).

[0219] For example, the ratio between the second difference and the first difference can be greater than or equal to 1.5 and less than or equal to 3.5.

[0220] Specifically, the ratio between the second difference and the first difference can be 1.5, 1.8, 2, 2.1, 2.3, 2.5, 2.8, 3, 3.3, or 3.5, etc.

[0221] For example, please continue reading Figure 5 and Figure 6 When the piezoelectric transducer C1 includes a first electrode C11, the signal amplification sub-circuit 111 can be connected to the first electrode C11 in the piezoelectric transducer C1.

[0222] For example, please continue reading Figure 5 and Figure 6 The signal amplification sub-circuit 111 can also be connected to the first voltage signal terminal V1 and the second voltage signal terminal V2 respectively. The voltage value of the first voltage signal provided by the first voltage signal terminal V1 is different from the voltage value of the second voltage signal provided by the second voltage signal terminal V2.

[0223] For example, please continue reading Figure 5 and Figure 6 The voltage value of the first voltage signal provided by the first voltage signal terminal V1 can be greater than the voltage value of the second voltage signal provided by the second voltage signal terminal V2.

[0224] For example, such as Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 These are all equivalent circuit diagrams of the detection circuit 11 according to some embodiments. The signal amplification sub-circuit 111 may include a first transistor T1.

[0225] The first transistor T1 includes a control electrode, a first electrode, and a second electrode. The control electrode of the first transistor T1 can be connected to the piezoelectric transducer C1, the first electrode of the first transistor T1 can be connected to the first voltage signal terminal V1, and the second electrode of the first transistor T1 can be connected to the second voltage signal terminal V2.

[0226] For example, please continue reading Figure 11 and Figure 12 When the piezoelectric transducer C1 includes a first electrode C11, the control electrode of the first transistor T1 can be connected to the first electrode C11 inside the piezoelectric transducer C1.

[0227] For example, please continue reading Figure 11 and Figure 12 The first transistor T1 in the signal amplification sub-circuit 111 can be a thin film transistor (TFT), etc.

[0228] Please continue reading. Figure 11 and Figure 12 When the first transistor T1 is a thin-film transistor, the control electrode of the first transistor T1 can be the gate, the first electrode of the first transistor T1 can be the source, and the second electrode of the first transistor T1 can be the drain. Alternatively, the control electrode of the first transistor T1 can be the gate, the first electrode of the first transistor T1 can be the drain, and the second electrode of the first transistor T1 can be the source.

[0229] For example, please continue reading Figure 11 and Figure 12 The first transistor T1 in the signal amplification sub-circuit 111 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. LTPS thin-film transistors have advantages such as high mobility and fast charging.

[0230] For example, please continue reading Figure 11 and Figure 12 The first transistor T1 in the signal amplification sub-circuit 111 can be an oxide thin-film transistor. Oxide thin-film transistors have advantages such as low leakage current.

[0231] For example, please continue reading Figure 11 and Figure 12 The first transistor T1 in the signal amplification sub-circuit 111 can be an N-type transistor.

[0232] Alternatively, the first transistor T1 in the signal amplification sub-circuit 111 can be a P-type transistor.

[0233] For example, please continue reading Figure 11 and Figure 12In the case that the first transistor T1 in the signal amplification sub-circuit 111 is an N-type transistor, and the first terminal of the first transistor T1 is connected to the first voltage signal terminal V1, and the second terminal of the first transistor T1 is connected to the second voltage signal terminal V2, the voltage value of the first voltage signal provided by the first voltage signal terminal V1 can be greater than the voltage value of the second voltage signal provided by the second voltage signal terminal V2.

[0234] The following uses an N-type transistor as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the first transistor T1 can also be other suitable types of transistors.

[0235] For example, please continue reading Figure 11 and Figure 12 The first transistor T1 in the signal amplification sub-circuit 111 can be a single-gate transistor.

[0236] Alternatively, the first transistor T1 in the signal amplification sub-circuit 111 can be a dual-gate transistor.

[0237] The following uses a single-gate transistor as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the first transistor T1 can also be other suitable types of transistors.

[0238] For example, such as Figure 13 , Figure 14 , Figure 15 and Figure 16 As shown, and in combination Figure 9 , Figure 10 , Figure 11 and Figure 12 , Figure 13 and Figure 14 These are all plan views of a local region of the first active layer 202 within the detection device 20 according to some embodiments. Figure 15 and Figure 16 These are all plan views of partial regions of the substrate 201, the first active layer 202, and the first conductive layer 203 within the detection device 20 according to some embodiments. The first transistor T1 within the signal amplification sub-circuit 111 may include a first active pattern T11 and a first gate T12, wherein the orthographic projection of the first active pattern T11 onto the substrate 201 within the detection device 20 and the orthographic projection of the first gate T12 onto the substrate 201 overlap.

[0239] For example, such as Figure 17 , Figure 18 and Figure 19 As shown, and in combination Figure 9 , Figure 10 , Figure 11 and Figure 12 , Figure 17 This is a plan view of a partial region of the first electrode layer 206 within the detection device 20 according to some embodiments. Figure 18 and Figure 19 These are all plan views of partial regions of the substrate 201, the first conductive layer 203, and the first electrode layer 206 within the detection device 20 according to some embodiments. In the case where the first transistor T1 within the signal amplification sub-circuit 111 includes a first gate T12, the first gate T12 within the first transistor T1 can be connected to the piezoelectric transducer C1.

[0240] For example, please continue reading Figure 18 and Figure 19 When the piezoelectric transducer C1 includes a first electrode C11, the first gate T12 in the first transistor T1 can be connected to the first electrode C11 in the piezoelectric transducer C1.

[0241] For example, please continue reading Figure 18 and Figure 19 and combined Figure 11 and Figure 12 When the piezoelectric transducer C1 includes a first electrode C11, the first transistor T1 in the signal amplification sub-circuit 111 includes a first gate T12, and the first gate T12 in the first transistor T1 is connected to the first electrode C11 in the piezoelectric transducer C1, the first electrode C11 in the piezoelectric transducer C1 can be located on the side of the film layer where the first gate T12 in the first transistor T1 is located away from the substrate 201.

[0242] For example, such as Figure 20 and Figure 21 As shown, and in combination Figure 18 and Figure 19 , Figure 20 and Figure 21 These are all plan views of partial regions of the substrate 201, first conductive layer 203, second conductive layer 204, and first electrode layer 206 within the detection device 20 according to some embodiments. The detection unit 1 may further include a first transition pattern 91, located between the film layer containing the first electrode C11 within the piezoelectric transducer C1 and the film layer containing the first gate T12 within the first transistor T1. The first gate T12 within the first transistor T1 can be connected to the first electrode C11 within the piezoelectric transducer C1 through the first transition pattern 91.

[0243] For example, such as Figure 22 , Figure 23 and Figure 24 As shown, and in combination Figure 20 and Figure 21 , Figure 22This is a plan view of a partial region of the third conductive layer 205 within the detection device 20 according to some embodiments. Figure 23 and Figure 24 These are all plan views of partial regions of the substrate 201, first conductive layer 203, second conductive layer 204, third conductive layer 205, and first electrode layer 206 within the detection device 20 according to some embodiments. When the detection unit 1 further includes a first transition pattern 91, the detection unit 1 may also include a third transition pattern 93, located between the film layer containing the first transition pattern 91 and the film layer containing the first electrode C11 within the piezoelectric transducer C1. The first transition pattern 91 can be connected to the first electrode C11 within the piezoelectric transducer C1 via the third transition pattern 93.

[0244] In other words, the first gate T12 in the first transistor T1 can be connected to the first electrode C11 in the piezoelectric transducer C1 in sequence through the first transition pattern 91 and the third transition pattern 93.

[0245] For example, such as Figure 25 and Figure 26 As shown, and in combination Figure 11 and Figure 12 , Figure 25 and Figure 26 These are all plan views of partial regions of the substrate 201, the first active layer 202, and the second conductive layer 204 within the detection device 20 according to some embodiments. When the detection device 20 further includes a first voltage signal line 2, and the first transistor T1 within the signal amplification sub-circuit 111 includes a first active pattern T11, the first active pattern T11 within the first transistor T1 and the first voltage signal line 2 can be arranged at intervals along a third direction X.

[0246] For example, please continue reading Figure 25 and Figure 26 and combined Figure 11 and Figure 12 In the case where the detection device 20 also includes a second voltage signal line 3, and the first transistor T1 in the signal amplification sub-circuit 111 includes a first active pattern T11, the first active pattern T11 in the first transistor T1 can be connected to the second voltage signal line 3.

[0247] For example, please continue reading Figure 25 and Figure 26 In the orthographic projection onto the substrate 201, the second voltage signal line 3 can be located on one side of the first active pattern T11 within the first transistor T1 along the third direction X.

[0248] For example, please continue reading Figure 25 and Figure 26 and combined Figure 11and Figure 12 In the case where the detection device 20 also includes a first voltage signal line 2 and a second voltage signal line 3, both of which extend along the second direction Y, and the first transistor T1 in the signal amplification sub-circuit 111 includes a first active pattern T11, and the first active pattern T11 in the first transistor T1 is connected to the second voltage signal line 3, in the orthogonal projection onto the substrate 201, along the third direction X, the first voltage signal line 2 can be located between the first active pattern T11 and the second voltage signal line 3 in the first transistor T1.

[0249] like Figure 27 and Figure 28 As shown, Figure 27 and Figure 28 These are all plan views of partial regions of the substrate 201, the first active layer 202, the first conductive layer 203, and the second conductive layer 204 within the detection device 20 according to some embodiments. The detection unit 1 may also include a second transition pattern 92, through which the first active pattern T11 within the first transistor T1 can be connected to the second voltage signal line 3.

[0250] In the orthographic projection onto the substrate 201, the second transition pattern 92 can overlap with the first voltage signal line 2.

[0251] For example, please continue reading Figure 27 and Figure 28 The second transition pattern 92 can be located between the film layer containing the first active pattern T11 within the first transistor T1 and the film layer containing the second voltage signal line 3.

[0252] For example, please continue reading Figure 11 and Figure 12 When the signal amplification sub-circuit 111 includes the first transistor T1, the signal amplification sub-circuit 111 may also include the first resistor R1. One end of the first resistor R1 may be connected to the first voltage signal terminal V1, and the other end of the first resistor R1 may be connected to the first terminal of the first transistor T1.

[0253] For example, please continue reading Figure 25 and Figure 26 If the detection device 20 also includes a first voltage signal line 2, one end of the first resistor R1 can be connected to the first voltage signal line 2.

[0254] Please continue reading. Figure 13 and Figure 14 When the first transistor T1 includes a first active pattern T11, the other end of the first resistor R1 can be connected to the first active pattern T11 within the first transistor T1.

[0255] For example, please continue reading Figure 25 and Figure 26 and combined Figure 11 and Figure 12 When the detection device 20 also includes a first voltage signal line 2, and one end of the first resistor R1 in the signal amplification sub-circuit 111 is connected to the first voltage signal line 2, the first voltage signal line 2 can overlap with the first resistor R1 in the orthogonal projection onto the substrate 201.

[0256] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the first transistor T1 in the signal amplification sub-circuit 111 includes a first active pattern T11, and the other end of the first resistor R1 is connected to the first active pattern T11 in the first transistor T1, in the orthogonal projection onto the substrate 201, the first resistor R1 may be located on one side of the first active pattern T11 in the first transistor T1 along the second direction Y.

[0257] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the first transistor T1 in the signal amplification sub-circuit 111 includes a first active pattern T11, and the other end of the first resistor R1 is connected to the first active pattern T11 in the first transistor T1, the first resistor R1 and the first active pattern T11 in the first transistor T1 can be arranged on the same layer, and the first resistor R1 and the first active pattern T11 in the first transistor T1 can be connected to each other to form an integral structure.

[0258] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 The first resistor R1 in the signal amplification sub-circuit 111 can be arranged in a serpentine pattern.

[0259] It should be noted that the above statement "the first resistor R1 can be arranged in a serpentine pattern" means that the first resistor R1 can be arranged in a serpentine pattern through multiple bends and turns.

[0260] For example, please continue reading Figure 11 and Figure 12 The resistance value of the first resistor R1 in the signal amplification sub-circuit 111 can be greater than or equal to 100 kΩ and less than or equal to 400 kΩ.

[0261] For example, the resistance value of the first resistor R1 can be 100 kΩ, 120 kΩ, 130 kΩ, 150 kΩ, 180 kΩ, 200 kΩ, 230 kΩ, 250 kΩ, 280 kΩ, 300 kΩ, 330 kΩ, 350 kΩ, 380 kΩ, or 400 kΩ, etc.

[0262] In some embodiments, please continue reading Figure 5 and Figure 6 The detection circuit 11 may include a driving sub-circuit 112.

[0263] The detection circuit 11 further includes a signal amplification sub-circuit 111, which is configured to receive a first detection signal and output a second detection signal. If the voltage value of the second detection signal is greater than the voltage value of the first detection signal, a driving sub-circuit 112 can be connected to the signal amplification sub-circuit 111. The driving sub-circuit 112 can be configured to receive the second detection signal.

[0264] like Figure 29 , Figure 30 and Figure 31 As shown, and in combination Figure 5 and Figure 6 , Figure 29 This is a waveform diagram of the first signal provided by the transmitting signal terminal Tx according to some embodiments. Figure 30 The waveform of the first detection signal M1 according to some embodiments is shown below. Figure 31 The diagram shows the waveform of the second detection signal M2 according to some embodiments. In the detection circuit 11 described above, the first detection signal M1 is transmitted to the signal amplification sub-circuit 111. After the signal amplification sub-circuit 111 amplifies the first detection signal M1, it is converted into the second detection signal M2, such that the voltage value of the second detection signal M2 is greater than the voltage value of the first detection signal M1. Consequently, the voltage value of the second detection signal M2 received by the driving sub-circuit 112 is larger, which helps to improve the detection accuracy of the detection circuit 11.

[0265] For example, when the detection circuit 11 is used to identify fingerprints, the detection accuracy of the detection circuit 11 in detecting valleys and ridges in the skin surface of the fingertip can be improved, thereby improving the fingerprint recognition accuracy of the detection circuit 11.

[0266] For example, please continue reading Figure 11 and Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, and the first terminal of the first transistor T1 is connected to the first resistor R1, the common terminal of the first transistor T1 and the first resistor R1 is the first node N1. The driving sub-circuit 112 can be connected to the first node N1.

[0267] It should be noted that the first node N1 mentioned above does not represent an actual existing component, but rather the junction point of related connections in the equivalent circuit diagram of the detection circuit 11. In other words, the first node N1 is a node equivalent to the junction point of related connections in the equivalent circuit diagram of the detection circuit 11.

[0268] In the detection circuit 11 described above, the control electrode of the first transistor T1 receives the first detection signal, which enables the first detection signal to control the degree of activation of the first transistor T1. This, in turn, enables the first detection signal to control the magnitude of the current in the conductive path formed by the first voltage signal terminal V1, the first resistor R1, the first transistor T1, and the second voltage signal terminal V2. Consequently, the first detection signal can control the magnitude of the voltage value of the second detection signal transmitted in the conductive path formed by the first voltage signal terminal V1, the first resistor R1, the first transistor T1, and the second voltage signal terminal V2.

[0269] On the one hand, the voltage value of the second detection signal changes with the voltage value of the first detection signal, thereby making the voltage value of the second detection signal correspond to the voltage value of the first detection signal (for example, when the detection device 20 is used to identify fingerprints, the first detection signal corresponding to the valley in the skin surface of the fingertip corresponds to the second detection signal corresponding to the valley in the skin surface of the fingertip; the first detection signal corresponding to the ridge in the skin surface of the fingertip corresponds to the second detection signal corresponding to the ridge in the skin surface of the fingertip).

[0270] On the other hand, the signal amplification sub-circuit 111 can receive the first detection signal M1, amplify the first detection signal M1, convert it into the second detection signal M2, and transmit it to the drive sub-circuit 112.

[0271] For example, please continue reading Figure 11 and Figure 12 The driving sub-circuit 112 may include a sixth transistor T6.

[0272] The sixth transistor T6 includes a control electrode, a first electrode, and a second electrode. The control electrode of the sixth transistor T6 can be connected to the signal amplification sub-circuit 111, the first electrode of the sixth transistor T6 can be connected to the third voltage signal terminal V3, and the second electrode of the sixth transistor T6 can be connected to the signal reading terminal Re1.

[0273] In the detection circuit 11 described above, the control electrode of the sixth transistor T6 is connected to the signal amplification sub-circuit 111, so that the control electrode of the sixth transistor T6 can receive the second detection signal output by the signal amplification sub-circuit 111, thereby enabling the second detection signal to control the degree of opening of the sixth transistor T6, and thus enabling the second detection signal to control the strength of the current in the sixth transistor T6.

[0274] For example, when the detection circuit 11 is used to identify fingerprints, the signal reading terminal Re1 can detect the strength of the current in the sixth transistor T6, and determine the valleys and ridges in the skin surface of the fingertip based on the strength of the current, thereby generating a fingerprint pattern and realizing fingerprint recognition.

[0275] By setting up a signal amplification sub-circuit 111, and amplifying the first detection signal M1 and converting it into a second detection signal M2, the voltage values ​​of the second detection signal M2 corresponding to the valleys and ridges on the skin surface of the fingertip are both relatively large. This results in different current values ​​corresponding to the valleys and ridges detected by the signal reading terminal Re1, and the difference between the current values ​​corresponding to the valleys and ridges increases, which helps to improve the fingerprint recognition accuracy of the detection circuit 11.

[0276] For example, please continue reading Figure 11 and Figure 12 In the case that the signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, the common terminal of the first transistor T1 and the first resistor R1 is the first node N1, and the driving sub-circuit 112 is connected to the first node N1, the control electrode of the sixth transistor T6 can be connected to the first node N1.

[0277] For example, please continue reading Figure 11 and Figure 12 The sixth transistor T6 in the driver sub-circuit 112 can be a thin-film transistor, etc.

[0278] Please continue reading. Figure 11 and Figure 12 When the sixth transistor T6 is a thin-film transistor, the control electrode of the sixth transistor T6 can be the gate, the first electrode of the sixth transistor T6 can be the source, and the second electrode of the sixth transistor T6 can be the drain. Alternatively, the control electrode of the sixth transistor T6 can be the gate, the first electrode of the sixth transistor T6 can be the drain, and the second electrode of the sixth transistor T6 can be the source.

[0279] For example, please continue reading Figure 11 and Figure 12 The sixth transistor T6 in the driver sub-circuit 112 can be a low-temperature polycrystalline silicon thin-film transistor.

[0280] For example, please continue reading Figure 11 and Figure 12 The sixth transistor T6 in the driver sub-circuit 112 can be an oxide thin-film transistor.

[0281] For example, please continue reading Figure 11 and Figure 12 The sixth transistor T6 in the driver sub-circuit 112 can be an N-type transistor.

[0282] Alternatively, the sixth transistor T6 in the driver sub-circuit 112 can be a P-type transistor.

[0283] The following uses the sixth transistor T6 as an example of an N-type transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the sixth transistor T6 can also be other suitable types of transistors.

[0284] For example, please continue reading Figure 11 and Figure 12 The sixth transistor T6 in the driver sub-circuit 112 can be a single-gate transistor.

[0285] Alternatively, the sixth transistor T6 in the driver sub-circuit 112 can be a dual-gate transistor.

[0286] The following uses the sixth transistor T6 as an example of a single-gate transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the sixth transistor T6 can also be other suitable types of transistors.

[0287] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 The sixth transistor T6 in the driving sub-circuit 112 may include a sixth active pattern T61 and a sixth gate T62. The orthographic projection of the sixth active pattern T61 onto the substrate 201 in the detection device 20 and the orthographic projection of the sixth gate T62 onto the substrate 201 overlap.

[0288] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 When the signal amplification sub-circuit 111 includes the first resistor R1, in the orthogonal projection onto the substrate 201, the sixth active pattern T61 within the sixth transistor T6 can be located on one side of the first resistor R1 along the third direction X.

[0289] For example, please continue reading Figure 25 and Figure 26 In the case where the detection device 20 also includes a second voltage signal line 3 and a fourth control signal line 6, and both the second voltage signal line 3 and the fourth control signal line 6 extend along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the second voltage signal line 3 and the fourth control signal line 6 can be located between the first resistor R1 and the sixth active pattern T61 within the sixth transistor T6.

[0290] For example, please continue reading Figure 15 and Figure 16and combined Figure 11 and Figure 12 In the case where the detection device 20 also includes a third voltage signal line 82, and the sixth transistor T6 in the drive sub-circuit 112 includes a sixth active pattern T61, the sixth active pattern T61 in the sixth transistor T6 can be connected to the third voltage signal line 82.

[0291] For example, please continue reading Figure 27 and Figure 28 The detection unit 1 may also include an eighth transition pattern 98, through which the third voltage signal line 82 can be connected to the sixth active pattern T61 in the sixth transistor T6 via the eighth transition pattern 98.

[0292] In some embodiments, please continue reading Figure 5 and Figure 6 When the detection circuit 11 includes a signal amplification sub-circuit 111 and a piezoelectric transducer C1, and the signal amplification sub-circuit 111 is connected to the piezoelectric transducer C1, the common terminal of the signal amplification sub-circuit 111 and the piezoelectric transducer C1 is the second node N2.

[0293] The detection circuit 11 may also include a first reset circuit 113, which is connected to the first control signal terminal G1, the first bias voltage signal terminal B1, and the second node N2.

[0294] The first reset circuit 113 can be configured to: when the first control signal provided by the first control signal terminal G1 is at an effective level, in response to the first control signal, conduct the current path between the first bias voltage signal terminal B1 and the second node N2 to transmit the first bias voltage signal provided by the first bias voltage signal terminal B1 to the second node N2.

[0295] It should be noted that the second node N2 mentioned above does not represent an actual existing component, but rather the junction point of relevant connections in the equivalent circuit diagram of the detection circuit 11. In other words, the second node N2 is a node equivalent to the junction point of relevant connections in the equivalent circuit diagram of the detection circuit 11.

[0296] In the detection circuit 11 described above, when the first control signal provided by the first control signal terminal G1 is at an effective level, the first reset sub-circuit 113 responds to the first control signal, conducts the current path between the first bias voltage signal terminal B1 and the second node N2, and transmits the first bias voltage signal provided by the first bias voltage signal terminal B1 to the second node N2 to reset the potential of the second node N2, which is beneficial to improving the detection accuracy of the detection circuit 11.

[0297] For example, when the detection circuit 11 is used to identify fingerprints, the detection accuracy of the detection circuit 11 in detecting valleys and ridges in the skin surface of the fingertip can be improved, thereby improving the fingerprint recognition accuracy of the detection circuit 11.

[0298] For example, please continue reading Figure 11 and Figure 12 In the case that the signal amplification sub-circuit 111 includes a first transistor T1, the piezoelectric transducer C1 includes a first electrode C11, and the control electrode of the first transistor T1 is connected to the first electrode C11 in the piezoelectric transducer C1, the second node N2 can be the common terminal of the control electrode of the first transistor T1 and the first electrode C11 in the piezoelectric transducer C1.

[0299] For example, please continue reading Figure 11 and Figure 12 The first reset circuit 113 may include a second transistor T2.

[0300] The second transistor T2 includes a control electrode, a first electrode, and a second electrode. The control electrode of the second transistor T2 can be connected to the first control signal terminal G1, the first electrode of the second transistor T2 can be connected to the first bias voltage signal terminal B1, and the second electrode of the second transistor T2 can be connected to the second node N2.

[0301] For example, please continue reading Figure 11 and Figure 12 The second transistor T2 in the first reset circuit 113 can be a thin-film transistor or the like.

[0302] Please continue reading. Figure 11 and Figure 12 When the second transistor T2 is a thin-film transistor, the control electrode of the second transistor T2 can be the gate, the first electrode of the second transistor T2 can be the source, and the second electrode of the second transistor T2 can be the drain. Alternatively, the control electrode of the second transistor T2 can be the gate, the first electrode of the second transistor T2 can be the drain, and the second electrode of the second transistor T2 can be the source.

[0303] For example, please continue reading Figure 11 and Figure 12 The second transistor T2 in the first reset circuit 113 can be a low-temperature polycrystalline silicon thin-film transistor.

[0304] For example, please continue reading Figure 11 and Figure 12 The second transistor T2 in the first reset circuit 113 can be an oxide thin film transistor.

[0305] For example, please continue reading Figure 11 and Figure 12The second transistor T2 in the first reset circuit 113 can be an N-type transistor.

[0306] Alternatively, the second transistor T2 within the first reset circuit 113 can be a P-type transistor.

[0307] The following uses an N-type transistor as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the second transistor T2 can also be other suitable types of transistors.

[0308] For example, please continue reading Figure 11 and Figure 12 The second transistor T2 in the first reset circuit 113 can be a single-gate transistor.

[0309] Alternatively, the second transistor T2 within the first reset circuit 113 can be a dual-gate transistor.

[0310] The following uses a single-gate transistor as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the second transistor T2 may also be other suitable types of transistors.

[0311] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 The second transistor T2 in the first reset circuit 113 may include a second active pattern T21 and a second gate T22. The second active pattern T21 is projected onto the substrate 201 in the detection device 20 and the second gate T22 is projected onto the substrate 201.

[0312] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1, the first transistor T1 includes a first active pattern T11, and the second transistor T2 in the first reset sub-circuit 113 includes a second active pattern T21, in the orthogonal projection onto the substrate 201, the second active pattern T21 in the second transistor T2 may be located on the side of the first active pattern T11 in the first transistor T1 along the third direction X.

[0313] For example, please continue reading Figure 25 and Figure 26In the case where the detection device 20 also includes a first voltage signal line 2 and the first voltage signal line 2 extends along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the first active pattern T11 in the first transistor T1 can be located between the first voltage signal line 2 and the second active pattern T21 in the second transistor T2.

[0314] For example, please continue reading Figure 25 and Figure 26 In the case where the detection device 20 also includes a second voltage signal line 3 and the second voltage signal line 3 extends along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the first active pattern T11 in the first transistor T1 can be located between the second voltage signal line 3 and the second active pattern T21 in the second transistor T2.

[0315] For example, please continue reading Figure 25 and Figure 26 In the case that the detection device 20 also includes a fourth control signal line 6 and the fourth control signal line 6 extends along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the first active pattern T11 in the first transistor T1 can be located between the fourth control signal line 6 and the second active pattern T21 in the second transistor T2.

[0316] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1, the first transistor T1 includes a first gate T12, and the second transistor T2 in the first reset sub-circuit 113 includes a second active pattern T21, the second active pattern T21 in the second transistor T2 can be connected to the first gate T12 in the first transistor T1.

[0317] For example, please continue reading Figure 27 and Figure 28 If the detection unit 1 also includes a first transition pattern 91, the second active pattern T21 in the second transistor T2 can be connected to the first gate T12 in the first transistor T1 through the first transition pattern 91.

[0318] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12In the case where the detection device 20 also includes a first bias voltage signal line 71, and the second transistor T2 in the first reset sub-circuit 113 includes a second active pattern T21, the second active pattern T21 in the second transistor T2 can be connected to the first bias voltage signal line 71.

[0319] For example, please continue reading Figure 27 and Figure 28 The detection device 20 may further include a fourth transition pattern 94. The second active pattern T21 within the second transistor T2 and the first bias voltage signal line 71 are both located between the substrate 201 and the film layer containing the fourth transition pattern 94. The first bias voltage signal line 71 can be connected to the second active pattern T21 within the second transistor T2 through the fourth transition pattern 94.

[0320] For example, please continue reading Figure 27 and Figure 28 and combined Figure 11 and Figure 12 In the case where the detection device 20 also includes a first control signal line 4, and the second transistor T2 in the first reset sub-circuit 113 includes a second gate T22, the second gate T22 in the second transistor T2 can be connected to the first control signal line 4.

[0321] In some embodiments, please continue reading Figure 5 and Figure 6 In the case where the detection circuit 11 includes a signal amplification sub-circuit 111 and a driving sub-circuit 112, the detection circuit 11 may also include a first control sub-circuit 115, which is connected to the third control signal terminal G3, the signal amplification sub-circuit 111 and the driving sub-circuit 112 respectively.

[0322] The first control sub-circuit 115 can be configured to, in response to the third control signal provided by the third control signal terminal G3 at an effective level, conduct the current path between the signal amplification sub-circuit 111 and the drive sub-circuit 112.

[0323] For example, please continue reading Figure 11 and Figure 12 In the case that the signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, the first terminal of the first transistor T1 is connected to the first resistor R1, and the common terminal of the first transistor T1 and the first resistor R1 is the first node N1, the first control sub-circuit 115 can be connected to the first node N1.

[0324] For example, please continue reading Figure 11 and Figure 12When the driving sub-circuit 112 includes the sixth transistor T6, the first control sub-circuit 115 can be connected to the control electrode of the sixth transistor T6.

[0325] For example, please continue reading Figure 11 and Figure 12 The first control sub-circuit 115 may include a fifth transistor T5.

[0326] The fifth transistor T5 includes a control electrode, a first electrode, and a second electrode. The control electrode of the fifth transistor T5 can be connected to the third control signal terminal G3, the first electrode of the fifth transistor T5 can be connected to the signal amplification sub-circuit 111, and the second electrode of the fifth transistor T5 can be connected to the driving sub-circuit 112.

[0327] For example, please continue reading Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 can be a thin-film transistor, etc.

[0328] Please continue reading. Figure 11 and Figure 12 When the fifth transistor T5 is a thin-film transistor, the control electrode of the fifth transistor T5 can be the gate, the first electrode of the fifth transistor T5 can be the source, and the second electrode of the fifth transistor T5 can be the drain. Alternatively, the control electrode of the fifth transistor T5 can be the gate, the first electrode of the fifth transistor T5 can be the drain, and the second electrode of the fifth transistor T5 can be the source.

[0329] For example, please continue reading Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 can be a low-temperature polycrystalline silicon thin-film transistor.

[0330] For example, please continue reading Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 can be an oxide thin-film transistor.

[0331] For example, please continue reading Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 can be an N-type transistor.

[0332] Alternatively, the fifth transistor T5 within the first control sub-circuit 115 can be a P-type transistor.

[0333] The following uses the fifth transistor T5 as an example of an N-type transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the fifth transistor T5 can also be other suitable types of transistors.

[0334] For example, please continue reading Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 can be a single-gate transistor.

[0335] Alternatively, the fifth transistor T5 within the first control sub-circuit 115 can be a dual-gate transistor.

[0336] The following uses the fifth transistor T5 as an example of a single-gate transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the fifth transistor T5 can also be other suitable types of transistors.

[0337] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 The fifth transistor T5 in the first control sub-circuit 115 may include a fifth active pattern T51 and a fifth gate T52. The orthographic projection of the fifth active pattern T51 onto the substrate 201 in the detection device 20 and the orthographic projection of the fifth gate T52 onto the substrate 201 overlap.

[0338] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the signal amplification sub-circuit 111 includes a first resistor R1 and the fifth transistor T5 in the first control sub-circuit 115 includes a fifth active pattern T51, in the orthogonal projection onto the substrate 201, the fifth active pattern T51 in the fifth transistor T5 can be located on one side of the first resistor R1 along the third direction X.

[0339] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, the first transistor T1 includes a first active pattern T11, and the fifth transistor T5 in the first control sub-circuit 115 includes a fifth active pattern T51, the fifth active pattern T51 in the fifth transistor T5 can be connected to the first resistor R1 and the first active pattern T11 in the first transistor T1.

[0340] For example, please continue reading Figure 13 and Figure 14The fifth active pattern T51 in the fifth transistor T5, the first active pattern T11 in the first transistor T1 and the first resistor R1 can be arranged in the same layer, and the fifth active pattern T51 in the fifth transistor T5, the first active pattern T11 in the first transistor T1 and the first resistor R1 can be connected to each other to form an integral structure.

[0341] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 In the case where the driving sub-circuit 112 includes a sixth transistor T6, the sixth transistor T6 includes a sixth gate T62, and the fifth transistor T5 in the first control sub-circuit 115 includes a fifth active pattern T51, the fifth active pattern T51 in the fifth transistor T5 can be connected to the sixth gate T62 in the sixth transistor T6.

[0342] For example, please continue reading Figure 27 and Figure 28 The detection unit 1 may further include a fifth transition pattern 95, a fifth active pattern T51 in the fifth transistor T5, and a sixth gate T62 in the sixth transistor T6, both located between the substrate 201 and the film layer containing the fifth transition pattern 95. The fifth active pattern T51 in the fifth transistor T5 can be connected to the sixth gate T62 in the sixth transistor T6 through the fifth transition pattern 95.

[0343] For example, such as Figure 32 and Figure 33 As shown, and in combination Figure 11 and Figure 12 , Figure 32 and Figure 33 All are plan views of partial regions of the substrate 201, the first conductive layer 203, and the second conductive layer 204 within the detection device 20 according to some embodiments. In the case where the detection device 20 further includes a third control signal line 5, and the fifth transistor T5 within the first control sub-circuit 115 includes a fifth gate T52, the fifth gate T52 within the fifth transistor T5 can be connected to the third control signal line 5.

[0344] In some embodiments, please continue reading Figure 6 When the detection circuit 11 includes a signal amplification sub-circuit 111 and a driving sub-circuit 112, and the signal amplification sub-circuit 111 and the driving sub-circuit 112 are connected, the common terminal of the signal amplification sub-circuit 111 and the driving sub-circuit 112 is the third node N3.

[0345] The detection circuit 11 may also include a second reset circuit 114, which is connected to the second control signal terminal G2, the second bias voltage signal terminal B2 and the third node N3 respectively.

[0346] The second reset circuit 114 can be configured to, in response to the second control signal provided by the second control signal terminal G2 being at an effective level, conduct the current path between the second bias voltage signal terminal B2 and the third node N3 to transmit the second bias voltage signal provided by the second bias voltage signal terminal B2 to the third node N3.

[0347] It should be noted that the third node N3 mentioned above does not represent an actual existing component, but rather the junction point of relevant connections in the equivalent circuit diagram of the detection circuit 11. In other words, the third node N3 is a node equivalent to the junction point of relevant connections in the equivalent circuit diagram of the detection circuit 11.

[0348] In the detection circuit 11 described above, when the second control signal provided by the second control signal terminal G2 is at an effective level, the second reset sub-circuit 114 responds to the second control signal, conducts the current path between the second bias voltage signal terminal B2 and the third node N3, and transmits the second bias voltage signal provided by the second bias voltage signal terminal B2 to the third node N3 to reset the potential of the third node N3, which is beneficial to improving the detection accuracy of the detection circuit 11.

[0349] For example, when the detection circuit 11 is used to identify fingerprints, the detection accuracy of the detection circuit 11 in detecting valleys and ridges in the skin surface of the fingertip can be improved, thereby improving the fingerprint recognition accuracy of the detection circuit 11.

[0350] For example, please continue reading Figure 6 In the case where the detection circuit 11 also includes a first reset circuit 113 and the first reset circuit 113 is connected to the first bias voltage signal terminal B1, the first bias voltage signal terminal B1 and the second bias voltage signal terminal B2 can be connected to the same bias voltage signal line.

[0351] Alternatively, if the detection circuit 11 further includes a first reset circuit 113, and the first reset circuit 113 is connected to the first bias voltage signal terminal B1, the first bias voltage signal terminal B1 and the second bias voltage signal terminal B2 can be connected to different bias voltage signal lines respectively.

[0352] In the detection circuit 11 described above, when the first bias voltage signal terminal B1 and the second bias voltage signal terminal B2 are connected to the same bias voltage signal line, the number of bias voltage signal lines in the detection device 20 can be reduced, thereby reducing the wiring complexity in the detection device 20, which in turn reduces the manufacturing cost of the detection device 20 and improves the manufacturing yield of the detection device 20.

[0353] For example, please continue reading Figure 6and combined Figure 33 In the case where the detection circuit 11 also includes a first reset sub-circuit 113 and the first reset sub-circuit 113 is connected to the first control signal terminal G1, the first control signal terminal G1 and the second control signal terminal G2 can be connected to the same first control signal line 4.

[0354] Alternatively, if the detection circuit 11 further includes a first reset sub-circuit 113, and the first reset sub-circuit 113 is connected to the first control signal terminal G1, the first control signal terminal G1 and the second control signal terminal G2 can be connected to different first control signal lines 4 respectively.

[0355] In the detection circuit 11 described above, when the first control signal terminal G1 and the second control signal terminal G2 are connected to the same first control signal line 4, the number of first control signal lines 4 in the detection device 20 can be reduced, thereby reducing the wiring complexity in the detection device 20, which in turn reduces the manufacturing cost of the detection device 20 and improves the manufacturing yield of the detection device 20.

[0356] For example, please continue reading Figure 12 The second reset circuit 114 may include a third transistor T3.

[0357] The third transistor T3 includes a control electrode, a first electrode, and a second electrode. The control electrode of the third transistor T3 can be connected to the second control signal terminal G2, the first electrode of the third transistor T3 can be connected to the second bias voltage signal terminal B2, and the second electrode of the third transistor T3 can be connected to the third node N3.

[0358] For example, please continue reading Figure 12 The third transistor T3 in the second reset circuit 114 can be a thin-film transistor or the like.

[0359] Please continue reading. Figure 12 When the third transistor T3 is a thin-film transistor, the control electrode of the third transistor T3 can be the gate, the first electrode of the third transistor T3 can be the source, and the second electrode of the third transistor T3 can be the drain. Alternatively, the control electrode of the third transistor T3 can be the gate, the first electrode of the third transistor T3 can be the drain, and the second electrode of the third transistor T3 can be the source.

[0360] For example, please continue reading Figure 12 The third transistor T3 in the second reset circuit 114 can be a low-temperature polycrystalline silicon thin-film transistor.

[0361] For example, please continue reading Figure 12 The third transistor T3 in the second reset circuit 114 can be an oxide thin film transistor.

[0362] For example, please continue reading Figure 12 The third transistor T3 in the second reset circuit 114 can be an N-type transistor.

[0363] Alternatively, the third transistor T3 in the second reset circuit 114 can be a P-type transistor.

[0364] The following uses an N-type transistor as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the third transistor T3 can also be other suitable types of transistors.

[0365] For example, please continue reading Figure 12 The third transistor T3 in the second reset circuit 114 can be a single-gate transistor.

[0366] Alternatively, the third transistor T3 in the second reset circuit 114 can be a dual-gate transistor.

[0367] The following uses a single-gate transistor as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the third transistor T3 can also be other suitable types of transistors.

[0368] For example, please continue reading Figure 16 The third transistor T3 in the second reset circuit 114 may include a third active pattern T31 and a third gate T32. The orthographic projection of the third active pattern T31 onto the substrate 201 in the detection device 20 and the orthographic projection of the third gate T32 onto the substrate 201 overlap.

[0369] For example, please continue reading Figure 16 and combined Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1 and the first transistor T1 includes a first active pattern T11, and the third transistor T3 in the second reset sub-circuit 114 includes a third active pattern T31, in the orthogonal projection onto the substrate 201, the third active pattern T31 in the third transistor T3 may be located on the side of the first active pattern T11 in the first transistor T1 along the third direction X.

[0370] For example, please continue reading Figure 16 and combined Figure 12In the case where the detection circuit 11 also includes a first reset circuit 113, the first reset circuit 113 includes a second transistor T2, and the second transistor T2 includes a second active pattern T21, in the orthogonal projection onto the substrate 201, along the third direction X, the second active pattern T21 in the second transistor T2 can be located between the first active pattern T11 in the first transistor T1 and the third active pattern T31 in the third transistor T3.

[0371] For example, please continue reading Figure 14 and combined Figure 12 In the case where the signal amplification sub-circuit 111 includes a first transistor T1 and the first transistor T1 includes a first active pattern T11, and the third transistor T3 in the second reset sub-circuit 114 includes a third active pattern T31, the third active pattern T31 in the third transistor T3 can be connected to the first active pattern T11 in the first transistor T1.

[0372] For example, please continue reading Figure 14 The third active pattern T31 in the third transistor T3 and the first active pattern T11 in the first transistor T1 can be arranged on the same layer, and the third active pattern T31 in the third transistor T3 and the first active pattern T11 in the first transistor T1 can be connected to each other to form an integral structure.

[0373] For example, please continue reading Figure 14 and combined Figure 12 The detection circuit 11 also includes a first control sub-circuit 115, which includes a fifth transistor T5 and a fifth active pattern T51. The signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, which includes a first active pattern T11. In the case that the third transistor T3 in the second reset sub-circuit 114 includes a third active pattern T31, the third active pattern T31 in the third transistor T3, the fifth active pattern T51 in the fifth transistor T5, the first active pattern T11 in the first transistor T1, and the first resistor R1 can be arranged on the same layer, and the third active pattern T31 in the third transistor T3, the fifth active pattern T51 in the fifth transistor T5, the first active pattern T11 in the first transistor T1, and the first resistor R1 can be interconnected to form an integral structure.

[0374] For example, please continue reading Figure 16 and combined Figure 12 In the case that the detection device 20 also includes a second bias voltage signal line 72, and the third transistor T3 in the second reset circuit 114 includes a third active pattern T31, the third active pattern T31 in the third transistor T3 can be connected to the second bias voltage signal line 72.

[0375] For example, please continue reading Figure 28 The detection device 20 may further include a seventh transition pattern 97. The third active pattern T31 and the second bias voltage signal line 72 in the third transistor T3 are both located between the substrate 201 and the film layer where the seventh transition pattern 97 is located. The second bias voltage signal line 72 can be connected to the third active pattern T31 in the third transistor T3 through the seventh transition pattern 97.

[0376] For example, please continue reading Figure 33 and combined Figure 12 In the case that the detection device 20 also includes a first control signal line 4, and the third transistor T3 in the second reset sub-circuit 114 includes a third gate T32, the third gate T32 in the third transistor T3 can be connected to the first control signal line 4.

[0377] For example, please continue reading Figure 10 and combined Figure 12 In the case where the detection circuit 11 also includes a first reset circuit 113, the first reset circuit 113 includes a second transistor T2, the second transistor T2 includes a second gate T22, and the third transistor T3 in the second reset circuit 114 includes a third gate T32, the third gate T32 in the third transistor T3 and the second gate T22 in the second transistor T2 can be arranged on the same layer, and the third gate T32 in the third transistor T3 and the second gate T22 in the second transistor T2 can be connected to each other to form an integral structure.

[0378] In some embodiments, please continue reading Figure 6 In the case where the detection circuit 11 includes a signal amplification sub-circuit 111, a drive sub-circuit 112, a second reset sub-circuit 114, and a first control sub-circuit 115, and the signal amplification sub-circuit 111 is connected to the drive sub-circuit 112, the common terminal of the signal amplification sub-circuit 111 and the drive sub-circuit 112 is the third node N3, the first control sub-circuit 115 is connected to the third control signal terminal G3, the signal amplification sub-circuit 111 and the drive sub-circuit 112 respectively, and the second reset sub-circuit 114 is connected to the second control signal terminal G2, the second bias voltage signal terminal B2 and the third node N3 respectively, the first control sub-circuit 115 can be connected to the third control signal terminal G3, the third node N3 and the drive sub-circuit 112 respectively.

[0379] For example, please continue reading Figure 12When the first control sub-circuit 115 includes a fifth transistor T5, the first terminal of the fifth transistor T5 can be connected to the third node N3, and the second terminal of the fifth transistor T5 can be connected to the drive sub-circuit 112. That is, the first terminal of the fifth transistor T5 can be connected to the signal amplification sub-circuit 111 and the second reset sub-circuit 114.

[0380] For example, please continue reading Figure 12 In the case that the signal amplification sub-circuit 111 includes a first transistor T1 and a first resistor R1, and the second reset sub-circuit 114 includes a third transistor T3, the first terminal of the fifth transistor T5 can be connected to the first terminal of the first transistor T1, the first resistor R1, and the second terminal of the third transistor T3.

[0381] When the driver sub-circuit 112 includes a sixth transistor T6, the second terminal of the fifth transistor T5 can be connected to the control terminal of the sixth transistor T6.

[0382] In other embodiments, such as Figure 34 As shown, Figure 34 This is an equivalent circuit diagram of a detection circuit 11 according to some embodiments. In a detection circuit 11 comprising a signal amplification subcircuit 111, a drive subcircuit 112, a second reset subcircuit 114, and a first control subcircuit 115, where the signal amplification subcircuit 111 is connected to the drive subcircuit 112, the common terminal of the signal amplification subcircuit 111 and the drive subcircuit 112 is the third node N3, the first control subcircuit 115 is connected to the third control signal terminal G3, the signal amplification subcircuit 111, and the drive subcircuit 112 respectively, and the second reset subcircuit 114 is connected to the second control signal terminal G2, the second bias voltage signal terminal B2, and the third node N3 respectively, the first control subcircuit 115 can be connected to the third control signal terminal G3, the signal amplification subcircuit 111, and the third node N3 respectively.

[0383] For example, please continue reading Figure 34 When the first control sub-circuit 115 includes a fifth transistor T5, the first terminal of the fifth transistor T5 can be connected to the signal amplification sub-circuit 111, and the second terminal of the fifth transistor T5 can be connected to the third node N3. That is, the second terminal of the fifth transistor T5 can be connected to the drive sub-circuit 112 and the second reset sub-circuit 114.

[0384] For example, please continue reading Figure 34 In the case where the signal amplification sub-circuit 111 includes the first transistor T1 and the first resistor R1, the first terminal of the fifth transistor T5 can be connected to the first terminal of the first transistor T1 and the first resistor R1.

[0385] When the driving sub-circuit 112 includes a sixth transistor T6 and the second reset sub-circuit 114 includes a third transistor T3, the second terminal of the fifth transistor T5 can be connected to the control terminal of the sixth transistor T6 and the second terminal of the third transistor T3.

[0386] In some embodiments, please continue reading Figure 5 and Figure 6 In the case where the detection circuit 11 includes the driving sub-circuit 112, the detection circuit 11 may also include the signal reading sub-circuit 116, which is connected to the fourth control signal terminal G4, the driving sub-circuit 112 and the signal reading terminal Re1 respectively.

[0387] For example, please continue reading Figure 11 and Figure 12 When the driving sub-circuit 112 includes a sixth transistor T6, the signal reading sub-circuit 116 can be connected to the second terminal of the sixth transistor T6.

[0388] For example, please continue reading Figure 11 and Figure 12 The signal reading sub-circuit 116 may include a fourth transistor T4.

[0389] The fourth transistor T4 includes a control electrode, a first electrode, and a second electrode. The control electrode of the fourth transistor T4 can be connected to the fourth control signal terminal G4, the first electrode of the fourth transistor T4 can be connected to the driver sub-circuit 112, and the second electrode of the fourth transistor T4 can be connected to the signal reading terminal Re1.

[0390] For example, please continue reading Figure 11 and Figure 12 The fourth transistor T4 in the signal reading sub-circuit 116 can be a thin-film transistor, etc.

[0391] Please continue reading. Figure 11 and Figure 12 When the fourth transistor T4 is a thin-film transistor, the control electrode of the fourth transistor T4 can be the gate, the first electrode of the fourth transistor T4 can be the source, and the second electrode of the fourth transistor T4 can be the drain. Alternatively, the control electrode of the fourth transistor T4 can be the gate, the first electrode of the fourth transistor T4 can be the drain, and the second electrode of the fourth transistor T4 can be the source.

[0392] For example, please continue reading Figure 11 and Figure 12 The fourth transistor T4 in the signal reading sub-circuit 116 can be a low-temperature polycrystalline silicon thin-film transistor.

[0393] For example, please continue reading Figure 11 and Figure 12The fourth transistor T4 in the signal reading sub-circuit 116 can be an oxide thin-film transistor.

[0394] For example, please continue reading Figure 11 and Figure 12 The fourth transistor T4 in the signal reading sub-circuit 116 can be an N-type transistor.

[0395] Alternatively, the fourth transistor T4 in the signal reading sub-circuit 116 can be a P-type transistor.

[0396] The following uses an N-type transistor as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the fourth transistor T4 can also be other suitable types of transistors.

[0397] For example, please continue reading Figure 11 and Figure 12 The fourth transistor T4 in the signal reading sub-circuit 116 can be a single-gate transistor.

[0398] Alternatively, the fourth transistor T4 in the signal readout sub-circuit 116 can be a dual-gate transistor.

[0399] The following uses the fourth transistor T4 as an example of a single-gate transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this, and the fourth transistor T4 can also be other suitable types of transistors.

[0400] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 The fourth transistor T4 in the signal reading sub-circuit 116 may include a fourth active pattern T41 and a fourth gate T42. The orthographic projection of the fourth active pattern T41 onto the substrate 201 in the detection device 20 and the orthographic projection of the fourth gate T42 onto the substrate 201 overlap.

[0401] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the driving sub-circuit 112 includes a sixth transistor T6, the sixth transistor T6 includes a sixth active pattern T61, and the fourth transistor T4 in the signal reading sub-circuit 116 includes a fourth active pattern T41, the fourth active pattern T41 in the fourth transistor T4 can be connected to the sixth active pattern T61 in the sixth transistor T6.

[0402] For example, please continue reading Figure 13 and Figure 14The fourth active pattern T41 in the fourth transistor T4 and the sixth active pattern T61 in the sixth transistor T6 can be arranged on the same layer, and the fourth active pattern T41 in the fourth transistor T4 and the sixth active pattern T6 in the sixth transistor T6 can be connected to each other to form an integrated structure.

[0403] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 In the case where the driving sub-circuit 112 includes a sixth transistor T6, the sixth transistor T6 includes a sixth active pattern T61, and the fourth transistor T4 in the signal reading sub-circuit 116 includes a fourth active pattern T41, the fourth active pattern T41 in the fourth transistor T4 may be located on one side of the sixth active pattern T61 in the sixth transistor T6 along the second direction Y.

[0404] For example, please continue reading Figure 15 and Figure 16 and combined Figure 11 and Figure 12 In the case where the detection device 20 also includes a signal readout line 81, and the fourth transistor T4 in the signal readout sub-circuit 116 includes a fourth active pattern T41, the fourth active pattern T41 in the fourth transistor T4 can be connected to the signal readout line 81.

[0405] For example, please continue reading Figure 27 and Figure 28 The detection device 20 may further include a sixth transition pattern 96, a fourth active pattern T41 within the fourth transistor T4, and a signal readout line 81, all located between the substrate 201 and the film layer containing the sixth transition pattern 96. The fourth active pattern T41 within the fourth transistor T4 can be connected to the signal readout line 81 via the sixth transition pattern 96.

[0406] For example, please continue reading Figure 32 and Figure 33 and combined Figure 11 and Figure 12 In the case where the detection device 20 also includes a fourth control signal line 6, and the fourth transistor T4 in the signal reading sub-circuit 116 includes a fourth gate T42, the fourth gate T42 in the fourth transistor T4 can be connected to the fourth control signal line 6.

[0407] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12In the case where the detection circuit 11 further includes a signal amplification sub-circuit 111, the signal amplification sub-circuit 111 includes a first transistor T1, and the first transistor T1 includes a first active pattern T11, and the fourth transistor T4 in the signal reading sub-circuit 116 includes a fourth active pattern T41, in the orthogonal projection onto the substrate 201, the fourth active pattern T41 in the fourth transistor T4 may be located on the side of the first active pattern T11 in the first transistor T1 along the third direction X.

[0408] For example, please continue reading Figure 25 and Figure 26 In the case where the detection device 20 also includes a first voltage signal line 2 and the first voltage signal line 2 extends along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the first voltage signal line 2 can be located between the first active pattern T11 in the first transistor T1 and the fourth active pattern T41 in the fourth transistor T4.

[0409] For example, please continue reading Figure 25 and Figure 26 In the case where the detection device 20 also includes a second voltage signal line 3 and the second voltage signal line 3 extends along the second direction Y, in the orthogonal projection onto the substrate 201, along the third direction X, the second voltage signal line 3 may be located between the first active pattern T11 in the first transistor T1 and the fourth active pattern T41 in the fourth transistor T4.

[0410] In some embodiments, please continue reading Figure 5 and Figure 6 In the case where the detection circuit 11 includes a driving sub-circuit 112, the detection circuit 11 may also include a voltage regulator sub-circuit 117, which is connected to the driving sub-circuit 112.

[0411] For example, please continue reading Figure 11 and Figure 12 When the driving sub-circuit 112 includes the sixth transistor T6, the voltage regulator sub-circuit 117 can be connected to the control electrode of the sixth transistor T6.

[0412] In the detection circuit 11 described above, the voltage regulator circuit 117 is connected to the control electrode of the sixth transistor T6, which can improve the stability of the voltage of the control electrode of the sixth transistor T6, thereby improving the detection accuracy of the detection circuit 11, which in turn can improve the recognition accuracy of the detection device 20 (e.g., the fingerprint recognition accuracy of the detection device 20), and is beneficial to improving the reliability of the detection device 20.

[0413] For example, please continue reading Figure 11 The voltage regulator circuit 117 can also be connected to the first bias voltage signal terminal B1.

[0414] Or, such as Figure 35 As shown, and in combination Figure 12 and Figure 34 , Figure 35 This is an equivalent circuit diagram of the detection circuit 11 according to some embodiments. The voltage regulator circuit 117 can also be connected to the second bias voltage signal terminal B2.

[0415] Or, as Figure 36 , Figure 37 and Figure 38 As shown, Figure 36 , Figure 37 and Figure 38 These are all equivalent circuit diagrams of the detection circuit 11 according to some embodiments. The voltage regulator circuit 117 can also be connected to the third voltage signal terminal V3.

[0416] Or, for example Figures 39-44 As shown, Figures 39-44 These are all equivalent circuit diagrams of the detection circuit 11 according to some embodiments. The voltage regulator circuit 117 can also be connected to the fourth control signal terminal G4.

[0417] In some embodiments, please continue reading Figure 11 , Figure 12 , Figures 34-41 and combined Figure 9 and Figure 10 In the case where the detection circuit 11 includes a voltage regulator sub-circuit 117 and a drive sub-circuit 112, and the voltage regulator sub-circuit 117 is connected to the drive sub-circuit 112, the voltage regulator sub-circuit 117 may include a second capacitor C2. The second capacitor C2 may include a first plate C21, and the first plate C21 is connected to the drive sub-circuit 112.

[0418] For example, please continue reading Figure 9 and Figure 10 and combined Figure 11 , Figure 12 , Figures 34-41 When the driving sub-circuit 112 includes a sixth transistor T6 and the sixth transistor T6 includes a sixth gate T62, the first plate C21 in the second capacitor C2 can be connected to the sixth gate T62 in the sixth transistor T6.

[0419] For example, please continue reading Figure 9 and Figure 10 The first electrode plate C21 in the second capacitor C2 and the sixth gate T62 in the sixth transistor T6 can be arranged in the same layer, and the first electrode plate C21 in the second capacitor C2 and the sixth gate T62 in the sixth transistor T6 can be connected to each other to form an integral structure.

[0420] For example, please continue reading Figure 11 , Figure 12 , Figures 34-41 The second capacitor C2 may also include a second plate.

[0421] For example, please continue reading Figure 11 The second plate inside the second capacitor C2 can be connected to the first bias voltage signal terminal B1.

[0422] For example, please continue reading Figure 12 , Figure 34 and Figure 35 The second plate inside the second capacitor C2 can be connected to the second bias voltage signal terminal B2.

[0423] For example, please continue reading Figure 36 , Figure 37 and Figure 38 The second plate inside the second capacitor C2 can be connected to the third voltage signal terminal V3.

[0424] For example, please continue reading Figure 39 , Figure 40 and Figure 41 The second plate inside the second capacitor C2 can be connected to the fourth control signal terminal G4.

[0425] For example, please continue reading Figure 32 and Figure 33 When the detection device 20 also includes a third bias voltage signal line 73, in the orthogonal projection onto the substrate 201, the first electrode C21 in the second capacitor C2 can overlap with the third bias voltage signal line 73, and the portion of the third bias voltage signal line 73 that overlaps with the first electrode C21 in the second capacitor C2 can be used to form the second electrode C22 in the second capacitor C2.

[0426] In the aforementioned detection device 20, the portion of the third bias voltage signal line 73 that overlaps with the first plate C21 in the second capacitor C2 is used to form the second plate C22 in the second capacitor C2. This reduces the wiring density of the detection device 20, thereby reducing the risk of crosstalk between adjacent signal lines in the detection device 20, which in turn helps to improve the stability and reliability of the detection device 20.

[0427] In other embodiments, please continue to refer to Figures 42-44 In the case where the detection circuit 11 includes a voltage regulator circuit 117, the voltage regulator circuit 117 may include a seventh transistor T7.

[0428] The first and second terminals of the seventh transistor T7 can be shorted together, forming an equivalent capacitor together with the control terminal of the seventh transistor T7.

[0429] In the aforementioned detection circuit 11, the voltage regulator circuit 117 includes a seventh transistor T7. The first and second terminals of the seventh transistor T7 are shorted together and together with the control terminal of the seventh transistor T7 form an equivalent capacitor. On the one hand, this can improve the stability of the voltage at the control terminal of the sixth transistor T6, thereby improving the detection accuracy of the detection circuit 11, which in turn can improve the recognition accuracy of the detection device 20 (e.g., the fingerprint recognition accuracy of the detection device 20), and is beneficial to improving the reliability of the detection device 20.

[0430] On the other hand, during the information acquisition phase, the capacitance of the seventh transistor T7 is close to 0, which can reduce the voltage division of the effective signal and help improve the acquisition rate of the effective signal.

[0431] For example, please continue reading Figures 42-44 In the case that the detection circuit 11 also includes a driving sub-circuit 112 and the voltage regulator sub-circuit 117 is connected to the driving sub-circuit 112, the control electrode of the seventh transistor T7 can be connected to the driving sub-circuit 112.

[0432] For example, please continue reading Figures 42-44 In the case where the driving sub-circuit 112 includes the sixth transistor T6, the control electrode of the seventh transistor T7 can be connected to the control electrode of the sixth transistor T6.

[0433] For example, please continue reading Figures 42-44 The first and second terminals of the seventh transistor T7 can be shorted to connect to the fourth control signal terminal G4.

[0434] For example, please continue reading Figures 42-44 The seventh transistor T7 can be a thin-film transistor, etc.

[0435] When the seventh transistor T7 is a thin-film transistor, the control electrode of the seventh transistor T7 can be the gate, the first electrode of the seventh transistor T7 can be the source, and the second electrode of the seventh transistor T7 can be the drain. Alternatively, the control electrode of the seventh transistor T7 can be the gate, the first electrode of the seventh transistor T7 can be the drain, and the second electrode of the seventh transistor T7 can be the source.

[0436] The detection method of the above detection circuit 11 will be described in detail below.

[0437] In some embodiments, such as Figure 45 As shown, Figure 45 for Figure 11 , Figure 12 , Figures 34-44 The driving timing diagram of the detection circuit 11 shown is shown. Figure 45In this diagram, V3 represents the timing of the third voltage signal provided by the third voltage signal terminal V3, Tx represents the timing of the first signal provided by the transmit signal terminal Tx, G1 represents the timing of the first control signal provided by the first control signal terminal G1, G2 represents the timing of the second control signal provided by the second control signal terminal G2, G3 represents the timing of the third control signal provided by the third control signal terminal G3, G4 represents the timing of the fourth control signal provided by the fourth control signal terminal G4, N1 represents the signal timing of the first node N1, N2 represents the signal timing of the second node N2, T62 represents the timing of the signal applied to the control electrode of the sixth transistor T6, and Re1 represents the intensity of the drive current input from the sixth transistor T6 and the fourth transistor T4 to the signal readout terminal Re1.

[0438] Please continue reading. Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44 The detection method of the detection circuit 11 may include a reset stage S1, an information acquisition stage S2, and an information reading stage S3.

[0439] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figure 34 , Figure 36 , Figure 38 , Figure 39 , Figure 41 , Figure 42 and Figure 44 When the detection circuit 11 includes the second transistor T2, during the reset phase S1: the first control signal provided by the first control signal terminal G1 is at an active level, and the second transistor T2 responds to the first control signal by conducting the current path between the first bias voltage signal terminal B1 and the second node N2, transmitting the first bias voltage signal provided by the first bias voltage signal terminal B1 to the second node N2 to reset the potential of the second node N2.

[0440] Please continue reading. Figure 45 and combined Figure 11 , Figure 36 , Figure 39 and Figure 42 During the reset phase S1: the first transistor T1 can respond to the potential of the second node N2 and conduct the current path of the first voltage signal terminal V1 and the second voltage signal terminal V2. At the same time, the fifth transistor T5 can respond to the third control signal provided by the third control signal terminal G3 and conduct the current path between the first transistor T1 and the sixth transistor T6 to reset the potential of the control electrode of the sixth transistor T6.

[0441] For example, please continue reading Figure 35 , Figure 37 , Figure 40 and Figure 43 In the absence of the second transistor T2 in the detection circuit 11, the first signal provided by the transmitting signal terminal Tx can be a sine wave with an adjustable center value.

[0442] For example, please continue reading Figure 45 and combined Figure 12 , Figure 34 , Figure 35 , Figure 37 , Figure 38 , Figure 40 , Figure 41 , Figure 43 and Figure 44 When the detection circuit 11 includes the third transistor T3, during the reset phase S1: the second control signal provided by the second control signal terminal G2 is at an active level, and the third transistor T3 responds to the second control signal by conducting the current path between the second bias voltage signal terminal B2 and the third node N3, transmitting the second bias voltage signal provided by the second bias voltage signal terminal B2 to the third node N3 to reset the potential of the third node N3.

[0443] Please continue reading. Figure 45 and combined Figure 12 , Figure 35 , Figure 37 , Figure 38 , Figure 40 , Figure 41 , Figure 43 and Figure 44 During the reset phase S1: the fifth transistor T5 can respond to the third control signal provided by the third control signal terminal G3, and conduct the current path between the third node N3 and the sixth transistor T6 to reset the potential of the control electrode of the sixth transistor T6.

[0444] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44 In the information collection phase S2: The piezoelectric transducer C1 outputs the first detection signal. At this time, the voltage value of the first detection signal is written into the second node N2.

[0445] The signal amplification sub-circuit 111 receives the first detection signal and outputs the second detection signal. The voltage value of the second detection signal is greater than the voltage value of the first detection signal. At this time, the potential of the first node N1 and the potential of the third node N3 are both the voltage value of the second detection signal, and the potentials of the first node N1 and the third node N3 are both higher than the potential of the second node N2.

[0446] The driver sub-circuit 112 receives the second detection signal.

[0447] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44 In a signal amplification subcircuit 111, which includes a first transistor T1 and a first resistor R1, with one end of the first resistor R1 connected to a first voltage signal terminal V1 and the other end connected to the first electrode of the first transistor T1, the control electrode of the first transistor T1 connected to a piezoelectric transducer C1, and the second electrode of the first transistor T1 connected to a second voltage signal terminal V2, and the common terminal of the first transistor T1 and the first resistor R1 being a first node N1, and the driving subcircuit 112 connected to the first node N1, the signal amplification subcircuit 111 receives a first detection signal and outputs a second detection signal, which may include: In response to the first detection signal, the first transistor T1 turns on the current path between the first voltage signal terminal V1 and the second voltage signal terminal V2.

[0448] The second detection signal is generated at the first node N1 and output to the driver sub-circuit 112.

[0449] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44 In the information acquisition stage S2: the ultrasonic signal reflected from the skin surface of the fingertip is transmitted to the piezoelectric material layer C13 in the piezoelectric transducer C1. The piezoelectric material layer C13 generates a first detection signal when impacted by the ultrasonic wave (because the fingerprint valleys and ridges reflect and scatter the ultrasonic signal respectively, the voltage value of the first detection signal corresponding to the valley is different from the voltage value of the first detection signal corresponding to the ridge), and is transmitted to the signal amplification sub-circuit 111. The signal amplification sub-circuit 111 converts the first detection signal into a second detection signal and transmits it to the fifth transistor T5. The third control signal provided by the third control signal terminal G3 is at an active level. The fifth transistor T5 responds to the third control signal provided by the third control signal terminal G3 and conducts the current path between the third node N3 and the sixth transistor T6 to transmit the second detection signal to the control electrode of the sixth transistor T6.

[0450] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44During the information reading phase S3: the sixth transistor T6 responds to the third detection signal and is in the on state. The fourth control signal provided by the fourth control signal terminal G4 is at an active level, and the fourth transistor T4 responds to the fourth control signal provided by the fourth control signal terminal G4, thus turning on the current path between the sixth transistor T6 and the signal reading terminal Re1.

[0451] For example, please continue reading Figure 45 and combined Figure 11 , Figure 12 , Figures 34-44 In the information reading stage S3: the chip can generate a fingerprint image based on the current magnitude of the signal reading terminal Re1 to complete fingerprint recognition.

[0452] The detection unit 1, signal lines, and adapter patterns in the detection device 20 can be located within the film structure of the detection device 20. The film structure of the detection device 20 will be described in detail below.

[0453] In some embodiments, please continue reading Figure 13 and Figure 14 and combined Figure 3 and Figure 4 The detection device 20 may include a first active layer 202, which is located on one side of the substrate 201 along the first direction Z.

[0454] For example, please continue reading Figure 13 and Figure 14 The first active pattern T11 within the first transistor T1 can be located in the first active layer 202.

[0455] For example, please continue reading Figure 13 and Figure 14 The second active pattern T21 within the second transistor T2 can be located in the first active layer 202.

[0456] For example, please continue reading Figure 14 The third active pattern T31 within the third transistor T3 can be located in the first active layer 202.

[0457] For example, please continue reading Figure 13 and Figure 14 The fourth active pattern T41 within the fourth transistor T4 can be located in the first active layer 202.

[0458] For example, please continue reading Figure 13 and Figure 14 The fifth active pattern T51 within the fifth transistor T5 can be located in the first active layer 202.

[0459] For example, please continue reading Figure 13 and Figure 14 The sixth active pattern T61 within the sixth transistor T6 can be located in the first active layer 202.

[0460] For example, please continue reading Figure 13 and Figure 14 The first resistor R1 can be located in the first active layer 202.

[0461] For example, please continue reading Figure 13 and Figure 14 The material of the first active layer 202 may include one or more of amorphous silicon (a-Si), low temperature poly-silicon (LTPS), amorphous oxide semiconductor (a-Oxide), and low temperature polycrystalline oxide (LTPO).

[0462] In some embodiments, please continue reading Figure 9 and Figure 10 and combined Figure 3 and Figure 4 The detection device 20 may also include a first conductive layer 203, which is located on the side of the first active layer 202 away from the substrate 201.

[0463] For example, please continue reading Figure 9 and Figure 10 The first bias voltage signal line 71 can be located in the first conductive layer 203.

[0464] For example, please continue reading Figure 10 The second bias voltage signal line 72 can be located in the first conductive layer 203.

[0465] For example, please continue reading Figure 9 and Figure 10 The signal reading line 81 can be located in the first conductive layer 203.

[0466] For example, please continue reading Figure 9 and Figure 10 The third voltage signal line 82 can be located in the first conductive layer 203.

[0467] For example, please continue reading Figure 9 and Figure 10 The first gate T12 in the first transistor T1 can be located in the first conductive layer 203.

[0468] For example, please continue reading Figure 9and Figure 10 The second gate T22 within the second transistor T2 can be located in the first conductive layer 203.

[0469] For example, please continue reading Figure 10 The third gate T32 in the third transistor T3 can be located in the first conductive layer 203.

[0470] For example, please continue reading Figure 9 and Figure 10 The fourth gate T42 in the fourth transistor T4 can be located in the first conductive layer 203.

[0471] For example, please continue reading Figure 9 and Figure 10 The fifth gate T52 in the fifth transistor T5 can be located in the first conductive layer 203.

[0472] For example, please continue reading Figure 9 and Figure 10 The sixth gate T62 in the sixth transistor T6 can be located in the first conductive layer 203.

[0473] For example, please continue reading Figure 9 and Figure 10 The first plate C21 inside the second capacitor C2 can be located in the first conductive layer 203.

[0474] For example, please continue reading Figure 9 and Figure 10 The second transition pattern 92 can be located in the first conductive layer 203.

[0475] For example, please continue reading Figure 9 and Figure 10 The material of the first conductive layer 203 may include one or more of molybdenum (MO), titanium (Ti), aluminum (Al) and copper (Cu).

[0476] In some embodiments, please continue reading Figure 7 and Figure 8 and combined Figure 3 and Figure 4 The detection device 20 may also include a second conductive layer 204, which is located on the side of the first conductive layer 203 away from the substrate 201.

[0477] For example, please continue reading Figure 7 and Figure 8 The first voltage signal line 2 can be located in the second conductive layer 204.

[0478] For example, please continue reading Figure 7 and Figure 8The second voltage signal line 3 can be located in the second conductive layer 204.

[0479] For example, please continue reading Figure 7 and Figure 8 The first control signal line 4 can be located in the second conductive layer 204.

[0480] For example, please continue reading Figure 7 and Figure 8 The third control signal line 5 can be located in the second conductive layer 204.

[0481] For example, please continue reading Figure 7 and Figure 8 The fourth control signal line 6 can be located in the second conductive layer 204.

[0482] For example, please continue reading Figure 7 and Figure 8 The third bias voltage signal line 73 can be located in the second conductive layer 204.

[0483] For example, please continue reading Figure 7 and Figure 8 The first transition pattern 91 can be located in the second conductive layer 204.

[0484] For example, please continue reading Figure 7 and Figure 8 The fourth transition pattern 94 can be located in the second conductive layer 204.

[0485] For example, please continue reading Figure 7 and Figure 8 The fifth transition pattern 95 can be located in the second conductive layer 204.

[0486] For example, please continue reading Figure 7 and Figure 8 The sixth transition pattern 96 can be located in the second conductive layer 204.

[0487] For example, please continue reading Figure 8 The seventh transition pattern 97 can be located in the second conductive layer 204.

[0488] For example, please continue reading Figure 7 and Figure 8 The eighth transition pattern 98 can be located in the second conductive layer 204.

[0489] For example, please continue reading Figure 7 and Figure 8 The material of the second conductive layer 204 may include one or more of molybdenum, titanium, aluminum and copper.

[0490] In some embodiments, please continue reading Figure 22 and combined Figure 3 and Figure 4 The detection device 20 may also include a third conductive layer 205, which is located on the side of the second conductive layer 204 away from the substrate 201.

[0491] For example, please continue reading Figure 22 The third transition pattern 93 can be located in the third conductive layer 205.

[0492] For example, please continue reading Figure 22 The material of the third conductive layer 205 may include one or more of molybdenum, titanium, aluminum and copper.

[0493] In some embodiments, please continue reading Figure 17 and combined Figure 3 and Figure 4 The detection device 20 may also include a first electrode layer 206, which is located on the side of the third conductive layer 205 away from the substrate 201.

[0494] For example, please continue reading Figure 17 The first electrode C11 in the piezoelectric transducer C1 can be located in the first electrode layer 206.

[0495] For example, the detection device 20 may also include a second electrode layer located on the side of the first electrode layer 206 away from the substrate 201, and the second electrode C12 in the piezoelectric transducer C1 may be located in the second electrode layer.

[0496] The piezoelectric material layer C13 in the piezoelectric transducer C1 is located between the first electrode layer 206 and the second electrode layer.

[0497] It should be noted that the above description only refers to the conductive film layer within the detection device 20, but the detection device 20 may also include an inorganic insulating layer and / or an organic insulating layer located between two adjacent conductive film layers. When two interconnected conductive structures are located on different conductive film layers, the connection can be achieved through vias penetrating the insulating layers.

[0498] The preparation method of the above-mentioned detection device 20 is described below.

[0499] In some embodiments, please continue reading Figure 3 and Figure 4 and combined Figure 5 and Figure 6 The fabrication method of the detection device 20 may include forming a plurality of detection units 1 on one side of the substrate 201 along the first direction Z. The detection unit 1 may include a detection circuit 11.

[0500] For example, please continue reading Figure 15, Figure 16 , Figure 18 and Figure 19 and combined Figure 3 and Figure 4 The aforementioned detection unit 1 may include: A first transistor T1 is formed. The first transistor T1 includes a first gate T12.

[0501] A piezoelectric transducer C1 is formed. The piezoelectric transducer C1 can be connected to the first gate T12 in the first transistor T1.

[0502] For example, please continue reading Figure 2 In the case where the display panel 100 includes a display substrate 10 and a detection device 20, after the detection device 20 is formed, the detection device 20 can be disposed on the non-display side 10b of the display substrate 10.

[0503] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A detection circuit, characterized in that, include: The piezoelectric transducer is configured to output a first detection signal; A signal amplification subcircuit is connected to the piezoelectric transducer; the signal amplification subcircuit is configured to receive the first detection signal and output a second detection signal; the voltage value of the second detection signal is greater than the voltage value of the first detection signal. A driving sub-circuit is connected to the signal amplification sub-circuit; the driving sub-circuit is configured to receive the second detection signal.

2. The detection circuit according to claim 1, characterized in that, The signal amplification sub-circuit is also connected to a first voltage signal terminal and a second voltage signal terminal respectively. The voltage value of the first voltage signal provided by the first voltage signal terminal is different from the voltage value of the second voltage signal provided by the second voltage signal terminal.

3. The detection circuit according to claim 2, characterized in that, The signal amplification sub-circuit includes a first transistor; The control electrode of the first transistor is connected to the piezoelectric transducer, the first electrode of the first transistor is connected to the first voltage signal terminal, and the second electrode of the first transistor is connected to the second voltage signal terminal.

4. The detection circuit according to claim 3, characterized in that, The signal amplification sub-circuit further includes a first resistor, one end of which is connected to the first voltage signal terminal, and the other end of which is connected to the first electrode of the first transistor.

5. The detection circuit according to claim 4, characterized in that, The common terminal of the first transistor and the first resistor is the first node; The driving sub-circuit is connected to the first node.

6. The detection circuit according to claim 5, characterized in that, The first transistor is an N-type transistor; The voltage value of the first voltage signal provided by the first voltage signal terminal is greater than the voltage value of the second voltage signal provided by the second voltage signal terminal.

7. The detection circuit according to claim 4, characterized in that, The resistance value of the first resistor is greater than or equal to 100 kΩ and less than or equal to 400 kΩ.

8. The detection circuit according to claim 1, characterized in that, The common terminal of the signal amplification subcircuit and the piezoelectric transducer is the second node; The detection circuit further includes a first reset circuit, which is connected to a first control signal terminal, a first bias voltage signal terminal, and the second node, respectively. The first reset sub-circuit is configured to: when the first control signal provided by the first control signal terminal is at an active level, in response to the first control signal, conduct the current path between the first bias voltage signal terminal and the second node to transmit the first bias voltage signal provided by the first bias voltage signal terminal to the second node.

9. The detection circuit according to claim 8, characterized in that, The first reset circuit includes a second transistor; The control electrode of the second transistor is connected to the first control signal terminal, the first electrode of the second transistor is connected to the first bias voltage signal terminal, and the second electrode of the second transistor is connected to the second node.

10. The detection circuit according to any one of claims 1-9, characterized in that, The common terminal of the signal amplification sub-circuit and the driving sub-circuit is the third node; The detection circuit further includes a second reset circuit, which is connected to the second control signal terminal, the second bias voltage signal terminal and the third node respectively; The second reset sub-circuit is configured to, in response to the second control signal provided by the second control signal terminal being at an active level, conduct the current path between the second bias voltage signal terminal and the third node to transmit the second bias voltage signal provided by the second bias voltage signal terminal to the third node.

11. The detection circuit according to claim 10, characterized in that, The second reset circuit includes a third transistor; The control electrode of the third transistor is connected to the second control signal terminal, the first electrode of the third transistor is connected to the second bias voltage signal terminal, and the second electrode of the third transistor is connected to the third node.

12. The detection circuit according to claim 10, characterized in that, The detection circuit further includes a first reset circuit, which is connected to a first control signal terminal and a first bias voltage signal terminal respectively. The first control signal terminal and the second control signal terminal are connected to the same first control signal line; And / or, The first bias voltage signal terminal and the second bias voltage signal terminal are connected to the same bias voltage signal line.

13. The detection circuit according to claim 10, characterized in that, The detection circuit further includes a first control sub-circuit, which is connected to the third control signal terminal, the signal amplification sub-circuit, and the third node; or... The detection circuit further includes a first control sub-circuit, which is connected to the third control signal terminal, the third node, and the driving sub-circuit.

14. A detection method for a detection circuit, characterized in that, Applied to the detection circuit as described in any one of claims 1-13; The detection method includes: The piezoelectric transducer outputs the first detection signal; The signal amplification sub-circuit receives the first detection signal and outputs the second detection signal; the voltage value of the second detection signal is greater than the voltage value of the first detection signal. The driver sub-circuit receives the second detection signal.

15. The detection method according to claim 14, characterized in that, The signal amplification sub-circuit includes a first transistor and a first resistor; one end of the first resistor is connected to a first voltage signal terminal, and the other end is connected to a first electrode of the first transistor; the control electrode of the first transistor is connected to the piezoelectric transducer, and the second electrode of the first transistor is connected to a second voltage signal terminal. The common terminal of the first transistor and the first resistor is the first node; The driving sub-circuit is connected to the first node; The signal amplification sub-circuit receives the first detection signal and outputs the second detection signal, including: In response to the first detection signal, the first transistor turns on the current path between the first voltage signal terminal and the second voltage signal terminal. A second detection signal is generated at the first node and output to the driving sub-circuit.

16. A detection device, characterized in that, include: Substrate; Multiple detection units are located on one side of the substrate along a first direction, the first direction being the thickness direction of the substrate; the detection unit includes a detection circuit as described in any one of claims 1-13.

17. The detection device according to claim 16, characterized in that, The detection unit includes: piezoelectric transducers; The first transistor includes a first gate; the first gate is connected to the piezoelectric transducer.

18. The detection device according to claim 17, characterized in that, The piezoelectric transducer includes a first electrode, which is connected to the first gate. The first electrode is located on the side of the film layer containing the first gate that is away from the substrate.

19. The detection device according to claim 18, characterized in that, The detection unit further includes a first transition pattern, which is located between the film layer where the first electrode is located and the film layer where the first gate is located; the first gate is connected to the first electrode through the first transition pattern.

20. The detection device according to claim 17, characterized in that, The detection device further includes a first voltage signal line; The first transistor further includes a first active pattern, the orthographic projection of the first active pattern onto the substrate and the orthographic projection of the first gate onto the substrate overlapping; The detection unit further includes a first resistor, one end of which is connected to the first voltage signal line and the other end of which is connected to the first active pattern.

21. The detection device according to claim 20, characterized in that, The first resistor is arranged in a serpentine pattern.

22. The detection device according to claim 20, characterized in that, In a projection onto the substrate, the first resistor is located on one side of the first active pattern along a second direction, which is perpendicular to the first direction.

23. The detection device according to claim 20, characterized in that, The first resistor and the first active pattern are disposed on the same layer, and the first resistor and the first active pattern are interconnected to form an integral structure.

24. The detection device according to claim 20, characterized in that, The first voltage signal line extends along a second direction, which is perpendicular to the first direction; In a projection onto the substrate, the first voltage signal line and the first resistor overlap.

25. The detection device according to claim 24, characterized in that, In the orthographic projection onto the substrate, the first active pattern is located on one side of the first resistor along the second direction, and the first active pattern and the first voltage signal line are spaced apart along a third direction, which is perpendicular to the first direction and intersects the second direction.

26. The detection device according to claim 20, characterized in that, The first voltage signal line extends along a second direction, which is perpendicular to the first direction; The detection device also includes a signal readout line; The detection unit further includes a fourth transistor, which includes a fourth active pattern and is connected to the signal readout line. In a projection onto the substrate, along a third direction, the first voltage signal line is located between the first active pattern and the fourth active pattern, the third direction being perpendicular to the first direction and intersecting the second direction.

27. The detection device according to claim 20, characterized in that, The detection device further includes a second voltage signal line, which extends along a second direction, the second direction being perpendicular to the first direction; In the orthographic projection onto the substrate, the second voltage signal line is located on one side of the first active pattern along a third direction, which is perpendicular to the first direction and intersects with the second direction; the first active pattern is also connected to the second voltage signal line.

28. The detection device according to claim 27, characterized in that, The first voltage signal line extends along the second direction; In a projection onto the substrate, along the third direction, the first voltage signal line is located between the first active pattern and the second voltage signal line; The detection unit further includes a second adapter pattern, wherein the first active pattern is connected to the second voltage signal line through the second adapter pattern; In the orthographic projection onto the substrate, the second transition pattern and the first voltage signal line overlap.

29. The detection device according to claim 28, characterized in that, The second transition pattern is located between the film layer containing the first active pattern and the film layer containing the second voltage signal line.

30. The detection device according to claim 27, characterized in that, The detection device also includes a signal readout line; The detection unit further includes a fourth transistor, which includes a fourth active pattern and is connected to the signal readout line. In a projection onto the substrate, along the third direction, the second voltage signal line is located between the first active pattern and the fourth active pattern.

31. The detection device according to claim 17, characterized in that, The detection device further includes a first bias voltage signal line; The detection unit further includes a second transistor, which includes a second active pattern, and the second active pattern is connected to the first bias voltage signal line and the first gate, respectively.

32. The detection device according to claim 31, characterized in that, The first transistor further includes a first active pattern; In a projection onto the substrate, the second active pattern is located on one side of the first active pattern along a third direction, which is perpendicular to the first direction.

33. The detection device according to any one of claims 17-32, characterized in that, The detection device also includes a second bias voltage signal line; The first transistor further includes a first active pattern; The detection unit further includes a third transistor, which includes a third active pattern, and the third active pattern is connected to the second bias voltage signal line and the first active pattern respectively.

34. The detection device according to claim 33, characterized in that, The first active pattern and the third active pattern are disposed on the same layer, and the first active pattern and the third active pattern are interconnected to form an integral structure.

35. The detection device according to claim 33, characterized in that, In a projection onto the substrate, the third active pattern is located on one side of the first active pattern along a third direction, which is perpendicular to the first direction.

36. The detection device according to claim 35, characterized in that, The detection unit further includes a second transistor, the second transistor including a second active pattern; In a projection onto the substrate, along the third direction, the second active pattern is located between the first active pattern and the third active pattern.

37. The detection device according to claim 33, characterized in that, The detection device further includes a first bias voltage signal line; Both the first bias voltage signal line and the second bias voltage signal line extend along a third direction, and the first bias voltage signal line and the second bias voltage signal line are arranged at intervals along a second direction. Both the second direction and the third direction are perpendicular to the first direction, and the second direction and the third direction intersect. The first bias voltage signal line and the second bias voltage signal line are located on one side of the detection unit along the second direction.

38. A method for preparing a detection device, characterized in that, include: Multiple detection units are formed on one side of the substrate along a first direction, where the first direction is the thickness direction of the substrate; The detection unit includes the detection circuit as described in any one of claims 1-13; The detection unit comprises: A first transistor is formed; the first transistor includes a first gate; A piezoelectric transducer is formed; the piezoelectric transducer is connected to the first gate.

39. A display panel, characterized in that, include: Display substrate; The detection device as described in any one of claims 16-37 is located on the non-display side of the display substrate.

Images