A gate driving circuit, a display panel and a display device

Abstract

The application discloses a gate driving circuit, a display panel and a display device. The circuit comprises an input unit, a first node, a second node, a first output unit, a second output unit, a first control unit and a second control unit. The control end of the first output unit is electrically connected with the first node, the control end of the second output unit is electrically connected with the second node, and the output end of the shift register outputs a gate driving signal under the control of the first node or the second node. The control end of the second control unit is electrically connected with a control signal end, the input end is electrically connected with a first voltage end, and the output end is electrically connected with the second node. When the output end of the shift register outputs a valid gate driving signal, the control signal provided by the control signal end controls the second control unit to input the voltage of the first voltage end into the second node. The application avoids the influence of the voltage of the second node on the output signal when the gate driving circuit outputs a valid gate driving signal, and improves the stability of the output signal of the gate driving circuit.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] In the display field, Gate-on-Array (GOA) technology is widely used to reduce costs and achieve integration of gate drive circuits. For automotive display products, with the increasing reliability requirements of automotive electronic systems, the industry has introduced Reliability Assessment (RA) testing, requiring display panels to be tested under conditions such as high temperature, high humidity, low temperature, and temperature variations. After RA testing, the characteristics of traditional GOA circuits drift, potentially leading to a significant reduction in circuit output capability. Furthermore, in the circuit's two critical control nodes, the potential of the first node is clamped by the potential of the second node. When the gate drive circuit is operating, the first node controls the output of the effective gate drive signal, while noise at the second node affects normal output. Summary of the Invention

[0003] This invention provides a gate driving circuit, a display panel, and a display device to reduce the clamping effect of the second node on the first node, avoid the influence of the second node voltage on the output signal when the gate driving circuit outputs a valid gate driving signal, and improve the stability of the output signal of the gate driving circuit.

[0004] In a first aspect, embodiments of the present invention provide a gate driving circuit, including an input unit, a first node, a second node, a first output unit, a second output unit, a first control unit, and a second control unit; The first terminal of the first output unit is electrically connected to the first clock signal terminal and the second terminal is electrically connected to the output terminal of the shift register. The first terminal of the second output unit is electrically connected to the first voltage terminal and the second terminal is electrically connected to the output terminal of the shift register. The control terminal of the first output unit is electrically connected to the first node and the control terminal of the second output unit is electrically connected to the second node. The output terminal of the shift register outputs a gate drive signal under the control of the first node or the second node. The first terminal of the first control unit is electrically connected to the first clock signal terminal, the second terminal of the first control unit is electrically connected to the second node, the control terminal of the second control unit is electrically connected to the control signal terminal, the input terminal of the second control unit is electrically connected to the first voltage terminal, and the output terminal of the second control unit is electrically connected to the second node. When the output terminal of the shift register outputs a valid gate drive signal, the control signal provided by the control signal terminal controls the second control unit to input the voltage of the first voltage terminal to the second node. The control terminal of the input unit is electrically connected to the first signal terminal, the input terminal of the input unit is electrically connected to the second voltage terminal, and the output terminal of the input unit is electrically connected to the first node.

[0005] Secondly, embodiments of the present invention also provide a display panel, including the gate driving circuit described in the first aspect.

[0006] Thirdly, embodiments of the present invention also provide a display device, including the display panel described in the second aspect.

[0007] The gate driving circuit provided in this embodiment of the invention includes an input unit, a first node, a second node, a first output unit, a second output unit, a first control unit, and a second control unit. The input terminal of the input unit receives an input signal, and the output signal is output to the first node. The first node and the second node are the control nodes of the first output unit and the second output unit, respectively. The first control unit and the second control unit are used to control the voltage of the second node. When the first node controls the gate driving circuit to output a valid gate driving signal, the first control unit causes noise in the second node due to the influence of the signal provided by the first clock signal terminal, which weakens the ability of the first node to control the output signal (i.e., the clamping effect of the second node on the first node). By setting the second control unit, when the gate driving circuit outputs a valid gate driving signal, the voltage of the first voltage terminal is input to the second node through the second control unit, thereby maintaining the voltage stability of the second node, eliminating the influence of noise, and improving the output signal stability of the gate driving circuit. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a gate drive circuit in related technologies; Figure 2 for Figure 1 The timing diagram of the drive signals for the gate drive circuit shown is as follows; Figure 3 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of the circuit structure of a gate driving circuit provided in an embodiment of the present invention; Figure 5A schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 6 A schematic diagram of a partial cascaded structure of a gate driving circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention; Figure 8 A schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 10 A schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0010] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "upper" or "lower" of another element, it can be formed not only directly "upper" or "lower" of the other element, but also indirectly "upper" or "lower" of the other element through an intermediate element. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0011] Figure 1 This is a schematic diagram of a gate drive circuit in related technologies. Figure 2 for Figure 1 The timing diagram of the drive signal for the gate drive circuit shown is for reference. Figure 1In related technologies, the gate drive circuit includes an input unit 1, a first node PU, a second node PD, an output unit 2, and a second node control unit 3. The output unit 2 includes a first output transistor M21 and a second output transistor M22. The second node control unit 3 includes a capacitor C31. The first node PU is a pull-up node, and the second node PD is a pull-down node. The gate of the first output transistor M21 is electrically connected to the first node PU. The first terminal (e.g., the source) of the first output transistor M21 is electrically connected to the first clock signal terminal CKB, which provides an alternating high and low level clock signal. The second terminal (e.g., the drain) of the first output transistor M21 is electrically connected to the output terminal GOUT of the shift register. The gate of the second output transistor M22 is electrically connected to the second node PD. The first terminal of the second output transistor M22 is electrically connected to the voltage terminal VGL, which provides a low-level signal. The second terminal of the second output transistor M22 is electrically connected to the output terminal GOUT of the shift register. The output terminal GOUT of the shift register outputs a gate drive signal under the control of the first node PU or the second node PD. The first terminal of capacitor C31 is electrically connected to the first clock signal terminal CKB, and the second terminal of capacitor C31 is electrically connected to the second node PD.

[0012] Figure 1 Taking the first output transistor M21 and the second output transistor M22 as N-type transistors as an example, the transistors are turned on when the control signal is high, and when the first node PU is high to control the first output transistor M21 to turn on, the second node PD should be low. However, the inventors discovered in their research that in this gate drive circuit, when the output terminal GOUT of the shift register outputs a valid gate drive signal (high level), the first node PU controls the first output transistor M21 to turn on, and at this time CKB is high. (Refer to...) Figure 2 Due to the bootstrap effect of capacitor C31, the voltage of the second node PD will be affected by CKB and generate a small spike (noise signal). When the second node PD jumps to a high level, it will briefly pull down the voltage of the GOUT signal, affecting the stability of the gate drive signal.

[0013] To address the aforementioned problems, this invention provides a gate driving circuit, including an input unit, a first node, a second node, a first output unit, a second output unit, a first control unit, and a second control unit. The input unit receives an input signal at its input terminal and outputs a signal to the first node. The first node and the second node are control nodes for the first output unit and the second output unit, respectively. The first control unit and the second control unit are used to control the voltage of the second node. When the first node controls the gate driving circuit to output a valid gate driving signal, the first control unit generates noise in the second node due to the influence of the signal provided by the first clock signal terminal, weakening the ability of the first node to control the output signal (i.e., the clamping effect of the second node on the first node). This invention addresses this by providing a second control unit. When the gate driving circuit outputs a valid gate driving signal, the voltage at the first voltage terminal is input to the second node through the second control unit, thereby maintaining the voltage stability of the second node, eliminating the influence of noise, and improving the stability of the output signal of the gate driving circuit.

[0014] The above is the core idea of ​​the embodiments of the present invention. The specific embodiments of the present invention are described below with reference to the accompanying drawings. Figure 3 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 3 The gate drive circuit includes an input unit 10, a first node PU, a second node PD, a first output unit 20, a second output unit 30, a first control unit 40, and a second control unit 50. The first terminal of the first output unit 20 is electrically connected to the first clock signal terminal CKB, and the second terminal is electrically connected to the output terminal GOUT of the shift register. The first terminal of the second output unit 30 is electrically connected to the first voltage terminal V1, and the second terminal is electrically connected to the output terminal GOUT of the shift register. The control terminal of the first output unit 20 is electrically connected to the first node PU, and the control terminal of the second output unit 30 is electrically connected to the second node PD. The output terminal GOUT of the shift register outputs a gate drive signal under the control of the first node PU and the second node PD. The first terminal of the control unit 40 is electrically connected to the first clock signal terminal CKB, the second terminal of the first control unit 40 is electrically connected to the second node PD, the control terminal of the second control unit 50 is electrically connected to the control signal terminal K, the input terminal of the second control unit 50 is electrically connected to the first voltage terminal V1, and the output terminal of the second control unit 50 is electrically connected to the second node PD. When the output terminal GOUT of the shift register outputs a valid gate drive signal, the control signal provided by the control signal terminal K controls the second control unit 50 to input the voltage of the first voltage terminal V1 to the second node PD. The control terminal of the input unit 10 is electrically connected to the first signal terminal S1, the input terminal of the input unit 10 is electrically connected to the second voltage terminal V2, and the output terminal of the input unit 10 is electrically connected to the first node PU.

[0015] The gate drive circuit includes multiple cascaded shift registers. Figure 3 The diagram illustrates the structure of a single-stage shift register. Input unit 10, first output unit 20, second output unit 30, first control unit 40, and second control unit 50 can all include transistors. Optionally, the first control unit 40 includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the first clock signal terminal CKB, and the second terminal of the first capacitor C1 is electrically connected to the second node PD. The first control unit 40 achieves voltage regulation of the second node PD through capacitive coupling. The transistor type can be P-type or N-type; this embodiment uses an N-type transistor as an example, which is not intended to limit the scope of the invention. The basic working process of the gate drive circuit is as follows: the first node PU is a pull-up node. When the gate drive circuit is working, the second voltage terminal V2 can always provide a high-level signal, and the first voltage terminal V1 always provides a low-level signal. When the first signal terminal S1 provides a high level, the transistor in the control input unit 10 is turned on. The high level provided by the second voltage terminal V2 is input to the first node PU. The first node PU controls the first output unit 20 to be turned on. The first clock signal terminal CKB provides a clock signal with alternating high and low levels. When the clock signal is high, the gate drive circuit outputs a valid gate drive signal (high level). In order to avoid the second node PD from interfering with the output signal, this embodiment sets in the circuit... A second control unit 50 is provided. The control terminal of the second control unit 50 is electrically connected to the control signal terminal K. The input terminal of the second control unit 50 is electrically connected to the first voltage terminal V1. The output terminal of the second control unit 50 is electrically connected to the second node PD. When the gate drive circuit outputs a valid gate drive signal, the control signal terminal K outputs a high-level signal to turn on the transistor of the second control unit 50. The low-level signal provided by the first voltage terminal V1 is input to the second node PD through the second control unit 50, so that when the gate drive circuit outputs a valid gate drive signal, the voltage of the second node PD is always maintained at a low level, eliminating the influence of the voltage jump of the second node PD on the output signal and improving the stability of the output signal.

[0016] Figure 4 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 4 Optionally, the input unit 10 includes a first transistor M1, the control terminal of the first transistor M1 is electrically connected to the first signal terminal S1, the first terminal of the first transistor M1 is electrically connected to the second voltage terminal V2, and the second terminal of the first transistor M1 is electrically connected to the first node PU.

[0017] In this circuit diagram, the control terminal of the first transistor M1 is its gate. The first terminal of the first transistor M1 can be its source (or drain), serving as the input terminal of the input unit 10 and electrically connected to the second voltage terminal V2. The second terminal of the first transistor M1 can be its drain (or source), serving as the output terminal of the input unit 10. The second voltage terminal V2 can provide a high-level signal. When the control signal provided by the first signal terminal S1 controls the first transistor M1 to conduct, the input unit 10 transmits the high-level signal provided by the second voltage terminal V2 to the first node PU. It should also be noted that in the circuit diagram of this embodiment, solid dots represent electrical connections at intersections, while intersections without solid dots indicate no connection.

[0018] Continue to refer to Figure 4 Optionally, the second control unit 50 includes a third transistor M3, the control terminal of the third transistor M3 is electrically connected to the control signal terminal K, the first terminal of the third transistor M3 is electrically connected to the first voltage terminal V1, and the second terminal of the third transistor M3 is electrically connected to the second node PD.

[0019] Similarly, the control terminal of the third transistor M3 is its gate, and the first terminal of the third transistor M3 can be its source (or drain), serving as the input terminal of the second control unit 50 and electrically connected to the first voltage terminal V1. The second terminal of the third transistor M3 can be its drain (or source), serving as the output terminal of the second control unit 50. In this embodiment of the invention, the transistor control terminal, the first terminal, and the second terminal are the same. The first voltage terminal V1 can provide a low-level signal. When the control signal provided by the control signal terminal K controls the third transistor M3 to conduct, the second control unit 50 transmits the low-level signal provided by the first voltage terminal V1 to the second node PD, maintaining the stability of the second node PD and eliminating the influence of noise on the output signal.

[0020] In another embodiment, the gate drive circuit can be a bidirectional scanning circuit, for example, Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, the input unit 10 includes a forward scan subunit 11 and a reverse scan subunit 12; the control terminal of the forward scan subunit 11 is electrically connected to the first signal terminal S1, the input terminal of the forward scan subunit 11 is electrically connected to the second voltage terminal V2, and the output terminal of the forward scan subunit 11 is electrically connected to the first node PU; the control terminal of the reverse scan subunit 12 is electrically connected to the second signal terminal S2, the input terminal of the reverse scan subunit 12 is electrically connected to the third voltage terminal V3, and the output terminal of the reverse scan subunit 12 is electrically connected to the first node PU.

[0021] Both the second voltage terminal V2 and the third voltage terminal V3 can provide high-level signals. During forward scanning, the control signal provided by the first signal terminal S1 controls the forward scanning subunit 11 to work, and the high-level signal provided by the second voltage terminal V2 is transmitted to the first node PU. During reverse scanning, the control signal provided by the second signal terminal S2 controls the reverse scanning subunit 12 to work, and the high-level signal provided by the third voltage terminal V3 is transmitted to the first node PU.

[0022] Continue to refer to Figure 5 Optionally, the second control unit 50 includes a first sub-control unit 51 and a second sub-control unit 52, and the control signal terminals include a first control signal terminal K1 and a second control signal terminal K2; the control terminal of the first sub-control unit 51 is electrically connected to the first control signal terminal K1, the input terminal of the first sub-control unit 51 is electrically connected to the first voltage terminal V1, and the output terminal of the first sub-control unit 51 is electrically connected to the second node PD; the control terminal of the second sub-control unit 52 is electrically connected to the second control signal terminal K2, the input terminal of the second sub-control unit 52 is electrically connected to the first voltage terminal V1, and the output terminal of the second sub-control unit 52 is electrically connected to the second node PD; the first sub-control unit 51 operates during forward scanning of the forward scanning sub-unit 11, and the second sub-control unit 52 operates during reverse scanning of the reverse scanning sub-unit 12.

[0023] In this embodiment, when the gate drive circuit is a bidirectional scanning circuit, noise signals may appear in the second node PD during both the forward scan sub-unit 11 and the reverse scan sub-unit 12. In order to simplify the control timing of the control signal terminal, the second control unit 50 is provided to include a first sub-control unit 51 and a second sub-control unit 52. The first sub-control unit 51 works during the forward scan of the forward scan sub-unit 11, and the second sub-control unit 52 works during the reverse scan of the reverse scan sub-unit 12. This allows a certain gate drive signal to be multiplexed as the control signal of the first control signal terminal K1, and another gate drive signal to be multiplexed as the control signal of the second control signal terminal K2, which helps to reduce the number of control signals. Optionally, the gate drive circuit includes multiple cascaded shift registers. The effective gate drive signal output by the nth shift register is Gn. The first signal terminal S1 is electrically connected to the output terminal of the (n-4)th shift register, the second signal terminal S2 is electrically connected to the output terminal of the (n+4)th shift register, the first control signal terminal K1 is electrically connected to the output terminal of the (n-2)th shift register, and the second control signal terminal K2 is electrically connected to the output terminal of the (n+2)th shift register, where n is an integer greater than 4.

[0024] The inventors discovered in their research that, for a dual-scan gate drive circuit, during forward scan, the time period during which the (n-2)th stage shift register outputs the effective gate signal Gn-2 overlaps with the time period during which the second node PD generates noise when the nth stage shift register outputs the effective gate signal Gn. Similarly, during reverse scan, the time period during which the (n+2)th stage shift register outputs the effective gate signal Gn+2 overlaps with the time period during which the second node PD generates noise when the nth stage shift register outputs the effective gate signal Gn. Therefore, the input signal of the first control signal terminal K1 can be set to Gn-2, and the input signal of the second control signal terminal K2 can be set to Gn+2. In this embodiment, the timing of the first signal terminal S1 is the same as Gn-4 during forward scan, and the timing of the second signal terminal S2 is the same as Gn+4 during reverse scan. Therefore, setting the input signal of the first signal terminal S1 to Gn-4 and the input signal of the second signal terminal S2 to Gn+4 helps reduce the number of control signals, simplify the structure, and lower costs.

[0025] It is understood that in other embodiments, similar approaches may also be used. Figure 3 A second control unit 50 is set up, which only needs to output the corresponding control signal at the control signal terminal during forward and reverse scanning.

[0026] For example, Figure 6 This is a schematic diagram of a partial cascaded structure of a gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 6 , Figure 6 Each rectangle (such as ASG1, ASG3, etc.) represents a shift register unit, whose core ports include: CK / CKB: clock inputs with different phases (complementary phases or phases differing by a specific angle), which toggle the state of the control unit; Reset: reset input, which pulls the unit output low; Set: set input, which pulls the unit output high; Gn+1: trigger signal for the next stage unit (the output of this stage serves as the Set signal for the next stage, realizing cascading); Gout: gate output signal of this stage, which directly drives a row of pixel gate lines on the display panel.

[0027] Dummy units are typically used to provide stable start and end reset / set signals, balance circuit load, eliminate static electricity, or act as edge buffers. Start and end dummy units can also be used for bidirectional scanning signal switching to achieve reverse scanning from left to right or from right to left.

[0028] The operation of the entire circuit can be divided into the following stages: Phase 1: Reset initialization. The Reset signal pulls the output of all cells low, ensuring that all gate lines are initially at a low level and the pixel diodes are in the off state.

[0029] Phase 2: Start-up pulse injection. STV1 and STV2 are used as start signals to inject into the first active unit (the dummy unit is triggered first, and then the signal is passed to the first display unit), setting the output of the first unit to a high level.

[0030] Phase 3: Shifting and line-by-line scanning. Driven by the CK / CKB multiphase clock, the output of each unit will trigger the next level unit through the Gn+1 port when the clock transitions: The first unit outputs a high level, driving the first row of pixels, and simultaneously transmits the signal to the Set pin of the second unit. In the next clock cycle, the second unit is set, outputting a high level to drive the second row, and simultaneously triggering the third unit; and so on. The signal is transmitted sequentially from one end to the other like a "shift", realizing line-by-line scanning. The output of each unit is high for only one clock cycle, ensuring that only one row of pixels is selected, thus avoiding display crosstalk.

[0031] Phase 4: Bidirectional scan design. The left and right chains in the diagram (left chain: Gout1, Gout3...Gout7; right chain: Gout847, Gout849...) adopt an alternating odd and even rows / bidirectional scan design. The left chain drives odd-numbered rows, and the right chain drives even-numbered rows. By controlling different clock phases, a more uniform load distribution can be achieved. In some designs, STV1 and STV2 can also be used as the start signals for reverse scanning, enabling reverse scanning from the last row to the first row for displaying flipped or special display modes.

[0032] Figure 7 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention, wherein... Figure 7 Corresponding to the timing during forward scanning, when the nth stage shift register outputs a valid gate signal Gn, the time period during which the second node PD generates noise overlaps with the time period during which the (n-2)th stage shift register outputs a valid gate signal Gn-2. By pulling down the voltage of the second node PD through Gn-2, the influence on the shift register output is eliminated.

[0033] Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 8 Optionally, the forward scan subunit 11 includes a first transistor M1, and the reverse scan subunit 12 includes a second transistor M2. The control terminal of the first transistor M1 is electrically connected to the first signal terminal S1, the first terminal of the first transistor M1 is electrically connected to the second voltage terminal V2, and the second terminal of the first transistor M1 is electrically connected to the first node PU. The control terminal of the second transistor M2 is electrically connected to the second signal terminal S2, the first terminal of the second transistor M2 is electrically connected to the third voltage terminal V3, and the second terminal of the second transistor M2 is electrically connected to the first node PU.

[0034] Optionally, the first sub-control unit 51 includes a third transistor M3, and the second sub-control unit 52 includes a fourth transistor M4. The control terminal of the third transistor M3 is electrically connected to the first control signal terminal K1, the first terminal of the third transistor M3 is electrically connected to the first voltage terminal V1, and the second terminal of the third transistor M3 is electrically connected to the second node PD. The control terminal of the fourth transistor M4 is electrically connected to the second control signal terminal K2, the first terminal of the fourth transistor M4 is electrically connected to the first voltage terminal V1, and the second terminal of the fourth transistor M4 is electrically connected to the second node PD.

[0035] Figure 9 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 9 Optionally, the gate drive circuit also includes a reset unit 60. The control terminal of the reset unit 60 is electrically connected to the reset signal terminal R, the input terminal of the reset unit 60 is electrically connected to the first voltage terminal V1, the first output terminal of the reset unit 60 is electrically connected to the output terminal GOUT of the shift register, and the second output terminal of the reset unit 60 is electrically connected to the first node PU. The reset unit 60 is used to reset the output terminal GOUT of the shift register and the first node PU.

[0036] In this circuit, after one working cycle, the state of the first node PU and the output terminal GOUT of the first-stage shift register of the gate drive circuit may not be completely restored to the initial state, thus affecting the next working cycle. Therefore, the gate drive circuit also includes a reset unit 60. The reset unit 60 is used to reset the voltage of the first node PU and the output terminal GOUT of the shift register. Specifically, the reset unit 60 operates under the control of the reset signal terminal R and writes the low-level signal provided by the first voltage terminal V1 into the output terminal GOUT of the first node PU and the shift register, thereby eliminating the influence of the previous working cycle on the next working cycle.

[0037] Optional, continue to refer to Figure 9 The gate drive circuit also includes a node pull-down unit 70, which is used to provide the voltage of the first voltage terminal V1 to the first node PU and the second node PD.

[0038] The first output unit 20 and the second output unit 30 control the output signal under the control of the first node PU and the second node PD, respectively. When the first node PU controls the first output unit 20 to output, the node pull-down unit 70 pulls down the voltage of the second node PD. When the second node PD controls the second output unit 30 to output, the node pull-down unit 70 pulls down the voltage of the first node PU, thereby ensuring the normal operation of the gate drive circuit.

[0039] Optional, continue to refer to Figure 9The gate drive circuit also includes a second capacitor C2. The first end of the second capacitor C2 is electrically connected to the first node PU, and the second end of the second capacitor C2 is electrically connected to the output terminal GOUT of the shift register.

[0040] By setting a second capacitor C2, the voltage of the first node PU can be further increased when the output terminal GOUT of the shift register outputs a valid gate signal, thereby improving output stability.

[0041] Figure 10 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 10 Optionally, the reset unit 60 includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the fifth transistor M5 is electrically connected to the reset signal terminal R, the first terminal of the fifth transistor M5 is electrically connected to the first voltage terminal V1, and the second terminal of the fifth transistor M5 is electrically connected to the output terminal GOUT of the shift register. The control terminal of the sixth transistor M6 is electrically connected to the reset signal terminal R, the first terminal of the sixth transistor M6 is electrically connected to the first voltage terminal V1, and the second terminal of the sixth transistor M6 is electrically connected to the first node PU.

[0042] In this embodiment, when the reset signal terminal R controls the fifth transistor M5 to turn on, the output terminal GOUT of the shift register outputs a low-level signal provided by the first voltage terminal V1. When the reset signal terminal R controls the sixth transistor M6 to turn on, the low-level signal provided by the first voltage terminal V1 is written to the first node PU. It can be understood that in the gate drive circuit provided by this embodiment, the effective gate drive signal (high level) output by the output terminal GOUT of the shift register is output when the first node PU is high. Therefore, when GOUT outputs a low level, the first node PU is also low, meaning that the control signals for the fifth transistor M5 and the sixth transistor M6 are the same. The gates of the fifth transistor M5 and the sixth transistor M6 are electrically connected and jointly connected to the reset signal terminal R.

[0043] Continue to refer to Figure 10 Optionally, the first output unit 11 includes a seventh transistor M7, and the second output unit 12 includes an eighth transistor M8. The control terminal of the seventh transistor M7 is electrically connected to the first node PU, and the first terminal of the seventh transistor M7 is electrically connected to the first clock signal terminal CKB. The control terminal of the eighth transistor M8 is electrically connected to the second node PD, and the first terminal of the eighth transistor M8 is electrically connected to the first voltage terminal V1. The second terminals of both the seventh transistor M7 and the eighth transistor M8 are electrically connected to the output terminal GOUT of the shift register.

[0044] In this process, when the first node PU controls the seventh transistor M7 to turn on and the first clock signal terminal CKB provides a high-level signal, the gate drive circuit outputs a valid gate drive signal. When the second node PD controls the eighth transistor M8 to turn on, it outputs a low-level signal. Its operation process is the same as that in related technologies and will not be described in detail here.

[0045] Optional, continue to refer to Figure 10 The second output unit 12 also includes a ninth transistor M9. The control terminal of the ninth transistor M9 is electrically connected to the second clock signal terminal CK. The first terminal of the ninth transistor M9 is electrically connected to the first voltage terminal V1. The second terminal of the ninth transistor M9 is electrically connected to the second terminal of the eighth transistor M8. The clock signal output by the first clock signal terminal CKB is out of phase with the clock signal output by the second clock signal terminal CK.

[0046] In this embodiment of the invention, the voltage of the second node PD follows the change of the first clock signal terminal CKB. When the first clock signal terminal CKB provides a low level, the second node PD is also at a low level. At this time, the eighth transistor M8 is turned off. Since the clock signal output by the first clock signal terminal CKB is out of phase with the clock signal output by the second clock signal terminal CK, when the first clock signal terminal CKB provides a low level, the second clock signal terminal CK provides a high level, controlling the ninth transistor M9 to be turned on, maintaining the output terminal GOUTA at a low level, realizing the alternating control of the eighth transistor M8 and the ninth transistor M9, and maintaining the stability of the output signal.

[0047] Optional, continue to refer to Figure 10 The node pull-down unit 70 includes a tenth transistor M10 and an eleventh transistor M11. The control terminal of the tenth transistor M10 is electrically connected to the second node PD. The first terminal of the tenth transistor M10 is electrically connected to the first voltage terminal V1. The second terminal of the tenth transistor M10 is electrically connected to the first node PU. The control terminal of the eleventh transistor M11 is electrically connected to the first node PU. The first terminal of the eleventh transistor M11 is electrically connected to the first voltage terminal V1. The second terminal of the eleventh transistor M11 is electrically connected to the second node PD.

[0048] Since the seventh transistor M7 and the eighth transistor M8 will not be turned on at the same time, when the first node PU is high, the eleventh transistor M11 is turned on, and the low level provided by the first voltage terminal V1 is written to the second node PD, thereby pulling down the voltage of the second node PD. When the second node PD is high, the tenth transistor M10 is turned on, and the low level provided by the first voltage terminal V1 is written to the first node PU, thereby pulling down the voltage of the first node PU.

[0049] This invention also provides a display panel, including any of the gate driving circuits provided in the above embodiments.

[0050] Since the display panel provided in the embodiments of the present invention includes any of the gate driving circuits provided in the above embodiments, and has the same or corresponding technical effects as the gate driving circuit, it will not be described in detail here.

[0051] Figure 11 This is a schematic diagram of a display device provided in an embodiment of the present invention. (Reference) Figure 11 The display device 100 includes any of the display panels 200 provided in the embodiments of the present invention. Specifically, the display device 100 can be a mobile phone, a computer, or a smart wearable device, etc.

[0052] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A gate driving circuit, characterized in that, It includes an input unit, a first node, a second node, a first output unit, a second output unit, a first control unit, and a second control unit; The first terminal of the first output unit is electrically connected to the first clock signal terminal and the second terminal is electrically connected to the output terminal of the shift register. The first terminal of the second output unit is electrically connected to the first voltage terminal and the second terminal is electrically connected to the output terminal of the shift register. The control terminal of the first output unit is electrically connected to the first node and the control terminal of the second output unit is electrically connected to the second node. The output terminal of the shift register outputs a gate drive signal under the control of the first node or the second node. The first terminal of the first control unit is electrically connected to the first clock signal terminal, the second terminal of the first control unit is electrically connected to the second node, the control terminal of the second control unit is electrically connected to the control signal terminal, the input terminal of the second control unit is electrically connected to the first voltage terminal, and the output terminal of the second control unit is electrically connected to the second node. When the output terminal of the shift register outputs a valid gate drive signal, the control signal provided by the control signal terminal controls the second control unit to input the voltage of the first voltage terminal to the second node. The control terminal of the input unit is electrically connected to the first signal terminal, the input terminal of the input unit is electrically connected to the second voltage terminal, and the output terminal of the input unit is electrically connected to the first node.

2. The gate driving circuit according to claim 1, characterized in that, The first control unit includes a first capacitor, a first terminal of which is electrically connected to the first clock signal terminal, and a second terminal of which is electrically connected to the second node.

3. The gate driving circuit according to claim 2, characterized in that, The input unit includes a first transistor, the control terminal of the first transistor is electrically connected to the first signal terminal, the first terminal of the first transistor is electrically connected to the second voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

4. The gate driving circuit according to claim 3, characterized in that, The second control unit includes a third transistor, the control terminal of which is electrically connected to the control signal terminal, the first terminal of which is electrically connected to the first voltage terminal, and the second terminal of which is electrically connected to the second node.

5. The gate driving circuit according to claim 1, characterized in that, The input unit includes a forward scan subunit and a reverse scan subunit; The control terminal of the forward scan subunit is electrically connected to the first signal terminal, the input terminal of the forward scan subunit is electrically connected to the second voltage terminal, and the output terminal of the forward scan subunit is electrically connected to the first node. The control terminal of the backscan subunit is electrically connected to the second signal terminal, the input terminal of the backscan subunit is electrically connected to the third voltage terminal, and the output terminal of the backscan subunit is electrically connected to the first node.

6. The gate driving circuit according to claim 5, characterized in that, The forward scan subunit includes a first transistor, and the reverse scan subunit includes a second transistor. The control terminal of the first transistor is electrically connected to the first signal terminal, the first terminal of the first transistor is electrically connected to the second voltage terminal, and the second terminal of the first transistor is electrically connected to the first node. The control terminal of the second transistor is electrically connected to the second signal terminal, the first terminal of the second transistor is electrically connected to the third voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.

7. The gate driving circuit according to claim 5, characterized in that, The second control unit includes a first sub-control unit and a second sub-control unit, and the control signal terminal includes a first control signal terminal and a second control signal terminal; The control terminal of the first sub-control unit is electrically connected to the first control signal terminal, the input terminal of the first sub-control unit is electrically connected to the first voltage terminal, and the output terminal of the first sub-control unit is electrically connected to the second node. The control terminal of the second sub-control unit is electrically connected to the second control signal terminal, the input terminal of the second sub-control unit is electrically connected to the first voltage terminal, and the output terminal of the second sub-control unit is electrically connected to the second node. The first sub-control unit operates during the forward scanning sub-unit's forward scanning, and the second sub-control unit operates during the reverse scanning sub-unit's reverse scanning.

8. The gate driving circuit according to claim 7, characterized in that, The first sub-control unit includes a third transistor, and the second sub-control unit includes a fourth transistor. The control terminal of the third transistor is electrically connected to the first control signal terminal, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the second node. The control terminal of the fourth transistor is electrically connected to the second control signal terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

9. The gate driving circuit according to claim 8, characterized in that, The gate drive circuit includes multiple cascaded shift registers. The effective gate drive signal output by the nth stage shift register is Gn. The first signal terminal is electrically connected to the output terminal of the (n-4)th stage shift register, the second signal terminal is electrically connected to the output terminal of the (n+4)th stage shift register, the first control signal terminal is electrically connected to the output terminal of the (n-2)th stage shift register, and the second control signal terminal is electrically connected to the output terminal of the (n+2)th stage shift register, where n is an integer greater than 4.

10. The gate driving circuit according to claim 1, characterized in that, It also includes a reset unit, wherein the control terminal of the reset unit is electrically connected to the reset signal terminal, the input terminal of the reset unit is electrically connected to the first voltage terminal, the first output terminal of the reset unit is electrically connected to the output terminal of the shift register, and the second output terminal of the reset unit is electrically connected to the first node. The reset unit is used to reset the output terminal of the shift register and the first node.

11. The gate driving circuit according to claim 10, characterized in that, The reset unit includes a fifth transistor and a sixth transistor. The control terminal of the fifth transistor is electrically connected to the reset signal terminal, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the output terminal of the shift register. The control terminal of the sixth transistor is electrically connected to the reset signal terminal, the first terminal of the sixth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixth transistor is electrically connected to the first node.

12. The gate driving circuit according to claim 1, characterized in that, The first output unit includes a seventh transistor, and the second output unit includes an eighth transistor. The control terminal of the seventh transistor is electrically connected to the first node, and the first terminal of the seventh transistor is electrically connected to the first clock signal terminal. The control terminal of the eighth transistor is electrically connected to the second node, and the first terminal of the eighth transistor is electrically connected to the first voltage terminal. The second terminals of both the seventh and eighth transistors are electrically connected to the output terminal of the shift register.

13. The gate driving circuit according to claim 12, characterized in that, The second output unit further includes a ninth transistor, the control terminal of which is electrically connected to a second clock signal terminal, the first terminal of which is electrically connected to the first voltage terminal, and the second terminal of which is electrically connected to the second terminal of the eighth transistor. The clock signal output from the first clock signal terminal and the clock signal output from the second clock signal terminal are out of phase.

14. The gate driving circuit according to claim 1, characterized in that, It also includes a node pull-down unit, which is used to provide the voltage of the first voltage terminal to the first node and the second node.

15. The gate driving circuit according to claim 14, characterized in that, The node pull-down unit includes a tenth transistor and an eleventh transistor. The control terminal of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first node. The control terminal of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the second node.

16. The gate driving circuit according to claim 1, characterized in that, It also includes a second capacitor, the first end of which is electrically connected to the first node, and the second end of which is electrically connected to the output of the shift register.

17. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1 to 16.

18. A display device, characterized in that, Includes the display panel as described in claim 17.

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