Robust design method and system for isolated stage cllc of solid state transformer

Abstract

The application discloses an isolation stage CLLC robust design method and system for a solid-state transformer, and belongs to the technical field of power electronics and electric energy conversion. The technical problem to be solved by the application is that the existing CLLC design method ignores non-ideal factors such as dead time and parasitic capacitance, and does not fully consider the component tolerance, so that the actual circuit faces the risk of voltage gain deviation and soft switch loss when the parameters drift. The application establishes a full-cycle non-ideal time-domain mathematical model by taking into account the parasitic capacitance of the switching device and the dead zone commutation process; combined with the parameter tolerance of the resonant components, the multi-dimensional extreme working condition data leading to the worst CLLC performance is extracted; with the extreme working condition data as the constraint boundary, the optimized parameter operation area that can meet the soft switch condition and the voltage gain condition is solved, and the parameter optimization output is carried out in the area. The application can ensure constant voltage gain and zero voltage opening in the full tolerance range, and significantly improves the engineering robustness of the isolation stage CLLC of the solid-state transformer.

Description

Technical Field

[0001] This application relates to the field of power electronics and power conversion technology, specifically to a robust design method for the isolation stage CLLC of a solid-state transformer. Background Technology

[0002] Solid-state transformers (SSTs) have become core components in applications such as fast charging for electric vehicles, data center power supply systems, and new energy DC microgrids due to their high-frequency electrical isolation, power routing, and flexible multi-voltage level conversion capabilities. As a core component of SSTs, the isolated-stage CLLC resonant converter can achieve quasi-constant voltage gain with high efficiency without complex closed-loop control when operating near its resonant frequency. Currently, for the parameter design of isolated-stage CLLCs, existing technologies generally employ the fundamental equivalent analysis method to construct its frequency domain mathematical model and design component parameters based on ideal nominal operating conditions. The theoretical voltage gain boundary derived from this frequency domain model is then used as a constraint to limit the parameter boundary design.

[0003] However, the aforementioned existing design methods generally rely on highly simplified frequency domain models, failing to quantitatively account for the impact of key non-ideal parameters such as dead time and parasitic capacitance of switching devices. This leads to significant errors between theoretically calculated voltage gain and soft-switching characteristics and actual circuits. Furthermore, in industrial mass production and long-term field operation, resonant inductors and capacitors not only suffer from unavoidable initial manufacturing tolerances due to process limitations, but are also subject to complex nonlinear parameter drifts caused by the combined effects of device temperature rise and aging under operating conditions. Existing technologies do not adequately consider the risks of these parameter tolerances and drifts. Therefore, when facing extreme and harsh tolerance boundary conditions where process tolerances and aging intertwine, CLLC circuits designed using existing methods still face the risk of hardware failure, including significant deviations from design targets in steady-state gain and loss of zero-voltage turn-on soft switching. Summary of the Invention

[0004] This application discloses a robust design method and system for isolation stage CLLCs used in solid-state transformers. The technical problem to be solved by this application is that existing CLLC design methods rely on simplified frequency domain models, fail to quantitatively account for the influence of key non-ideal parameters such as dead time and parasitic capacitance of switching devices, and do not fully consider component tolerances. As a result, under the extreme and harsh tolerance boundary conditions where process tolerances and operational aging are intertwined, CLLCs face the risk of hardware failure, such as steady-state gain deviating significantly from the design target and loss of zero-voltage turn-on soft switching.

[0005] To achieve the above objectives, this application provides the following technical solution: In a first aspect, this application provides a robust design method for the isolation stage CLLC of a solid-state transformer, comprising the following steps: Step S1: Model building step, taking into account the parasitic capacitance parameters of the switching devices and the preset dead time parameters, to build a non-ideal time-domain mathematical model to describe the electrical behavior of the CLLC circuit during the entire switching cycle; Step S2: Boundary determination step, input the parameter tolerance range of the inductor and capacitor in the resonant circuit into the non-ideal time domain mathematical model, obtain the parameter combination that causes multiple performance indicators of the CLLC circuit to be in the worst state through ergonomic analysis, and determine the parameter combination as multi-dimensional extreme working condition data; Step S3: Parameter planning step, using the multidimensional extreme operating condition data as the constraint boundary, using the non-ideal time domain mathematical model to solve for the optimized parameter operating range that can simultaneously satisfy the preset soft switching conditions and voltage gain conditions, and selecting and outputting the nominal parameters of the CLLC circuit within the optimized parameter operating range.

[0006] Preferably, the construction of the non-ideal time-domain mathematical model in step S1 specifically includes: defining three independent operating modes, namely P mode, N mode and O mode, according to the on / off state of each switch in the primary-side full bridge and the secondary-side full bridge, and orthogonally combining the primary-side operating modes and the secondary-side operating modes to generate nine segmented operating modes that cover the entire switching cycle of the CLLC circuit; establishing the time-domain analytical expression corresponding to each segmented operating mode, and splicing the segmented operating modes according to the time sequence through mode switching logic.

[0007] Preferably, the P-mode, N-mode, and O-mode are defined as follows: P-mode: In the same full-bridge, the upper transistor of the first half-bridge and the lower transistor of the second half-bridge are simultaneously turned on, or their body diodes are simultaneously turned on, so that the voltage between the midpoints of the full-bridge is clamped to the positive DC bus voltage; N-mode: In the same full-bridge, the lower transistor of the first half-bridge and the upper transistor of the second half-bridge are simultaneously turned on, or their body diodes are simultaneously turned on, so that the voltage between the midpoints of the full-bridge is clamped to the negative DC bus voltage; O-mode: The same full-bridge is in the dead zone stage, all switching transistors and their body diodes are turned off, the parasitic capacitance of the switching transistors of the full-bridge participates in resonant charging and discharging, and the voltage between its midpoints changes dynamically.

[0008] Preferably, the mode switching logic is a hybrid step-size iterative method based on event triggering, including: solving the P mode or N mode in a single step with a large step size during the non-dead time; switching to micro-step size for iterative calculation during the dead time, and triggering the entry and exit of the corresponding segmented operating mode according to the active turn-off event of the switch, the natural zero-crossing event of the resonant current, or the voltage clamping event.

[0009] Preferably, the multi-dimensional extreme operating condition data in step S2 specifically refers to a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum positive tolerance value, or a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum negative tolerance value.

[0010] Preferably, the determination of the optimized parameter operating region in step S3 specifically includes: substituting the multidimensional extreme operating condition data into the non-ideal time-domain mathematical model, mapping out a first feasible region that satisfies the preset soft-switching condition and a second feasible region that satisfies the voltage gain condition on a plane with the nominal parameter as the coordinate axis, and performing a logical intersection operation on the first feasible region and the second feasible region to extract the optimized parameter operating region.

[0011] Preferably, the preset soft-switching conditions and voltage gain conditions specifically include: a first constraint: under the multi-dimensional extreme operating conditions, before each switch in the primary-side full bridge and the secondary-side full bridge is turned on, its corresponding parasitic capacitance voltage has been completely discharged to zero; a second constraint: under the multi-dimensional extreme operating conditions, the steady-state voltage gain of the CLLC circuit is limited to the preset design allowable upper and lower limits.

[0012] Preferably, in step S3, selecting and outputting the nominal parameters of the CLLC circuit within the optimized parameter operating range specifically includes: using the measured leakage inductance value of the high-frequency transformer in the CLLC circuit as the nominal resonant inductance value, and selecting the excitation inductance value that meets the performance requirements and has the largest value within the optimized parameter operating range as the nominal excitation inductance value.

[0013] Preferably, when selecting the nominal excitation inductance value, the optimization objective is to minimize the reactive circulating current of the circuit.

[0014] Preferably, after determining the nominal resonant inductance value and the nominal excitation inductance value, the nominal resonant capacitance value is also calculated and output by reverse calculation using the resonant frequency formula based on the nominal resonant frequency preset by the system.

[0015] Secondly, this application provides a robust design system for the isolation stage CLLC of a solid-state transformer, comprising: The model building module is used to construct a non-ideal time-domain mathematical model that describes the electrical behavior of the CLLC circuit throughout the entire switching cycle, taking into account the parasitic capacitance parameters of the switching devices and the preset dead time parameters. The boundary determination module is used to input the parameter tolerance ranges of the inductor and capacitor elements in the resonant circuit into the non-ideal time-domain mathematical model, obtain the parameter combinations that cause multiple performance indicators of the CLLC circuit to be in the worst state through ergonomic analysis, and determine the parameter combinations as multi-dimensional extreme operating condition data. The parameter planning module is used to use the multi-dimensional extreme operating condition data as the constraint boundary, use the non-ideal time-domain mathematical model to solve for the optimized parameter operating region that can simultaneously satisfy the preset soft switching conditions and voltage gain conditions, and select and output the nominal parameters of the CLLC circuit within the optimized parameter operating region.

[0016] Compared with the prior art, this application has at least the following beneficial effects: This application overcomes the shortcomings of existing fundamental equivalent analysis methods in quantitatively characterizing the dead-zone process by establishing a full-cycle non-ideal time-domain mathematical model that takes into account the parasitic capacitance of switching devices and the dead-zone commutation process. It can accurately characterize the transient current and voltage discharge trajectory caused by the charging and discharging of parasitic capacitance during the dead-zone time, thereby accurately assessing and identifying whether the circuit has the risk of hard turn-on due to incomplete discharge of parasitic capacitance and the risk of stress exceeding the standard due to dead-zone current distortion, thus ensuring the efficient and safe operation of the solid-state transformer isolation stage CLLC.

[0017] Furthermore, this application overcomes the shortcomings of existing technologies that rely solely on ideal nominal parameters for design and are detached from actual engineering by extracting the tolerance value that induces the worst performance of CLLC through traversal. It fundamentally eliminates the problem of voltage gain deviating significantly from the design target and zero-voltage turn-on loss caused by component parameter drift during industrial mass production and full life cycle operation of CLLC, greatly improving the yield and operational robustness of solid-state transformer engineering mass production.

[0018] Furthermore, this application locks the operating region of the optimization parameters by logically intersecting multi-dimensional conditional constraints. On the parameter design plane, it delineates a clear feasible region for the design of the leakage inductance and magnetizing inductance of the CLLC high-frequency transformer, effectively guiding the transformer design and verifying parameter feasibility. Compared to existing parameter design methods that only yield a fixed set of unique parameters, the feasible region of parameters in this application broadens the actual tolerance space of the parameters, thereby significantly reducing the processing accuracy requirements and manufacturing difficulty of the high-frequency transformer. Attached Figure Description

[0019] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. In the drawings: Figure 1 This is a diagram of the basic circuit topology of the CLLC involved in this application; Figure 2 This is the equivalent circuit diagram of the CLLC involved in this application in PP mode; Figure 3 This is the equivalent circuit diagram of the CLLC involved in this application in OP mode; Figure 4 This is a simplified equivalent circuit diagram of the CLLC involved in this application in OP mode; Figure 5 This is the equivalent circuit diagram of the CLLC involved in this application in OO mode; Figure 6 This is a measured voltage gain curve of an embodiment of this application; Figure 7 The following are ZVS waveforms under the nominal parameters of the embodiments of this application; (a) is the ZVS waveform of the primary-side switching device; (b) is the ZVS waveform of the secondary-side switching device; Figure 8 (a) is the ZVS waveform of the primary-side switching device under the lower limit of parameter deviation in the embodiments of this application; (b) is the ZVS waveform of the secondary-side switching device. Figure 9 (a) is the ZVS waveform of the parameter deviation upper limit in the embodiment of this application; (b) is the ZVS waveform of the primary-side switching device; (c) is the ZVS waveform of the secondary-side switching device. Detailed Implementation

[0020] To make the objectives and technical solutions of this application clearer and easier to understand, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. It should be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Terminology Explanation Solid-state transformers (SSTs) are a new type of transformer based on power electronics technology. They have the ability to provide high-frequency electrical isolation, power routing, and flexible conversion of multiple voltage levels. Unlike traditional power frequency transformers, SSTs are core equipment for applications such as fast charging of electric vehicles, power supply systems for data centers, and new energy DC microgrids.

[0023] CLLC (Clear-Loop Cell-Loop) refers to the core power conversion stage in a solid-state transformer. It is an isolated DC-DC converter that uses a CLLC resonant topology. "CLLC" indicates that the circuit contains two resonant capacitors and two resonant inductors, with a symmetrical primary and secondary structure.

[0024] Quasi-constant voltage gain refers to the fact that when a CLLC circuit operates near its resonant frequency, the ratio of its output voltage to its input voltage remains essentially constant and does not fluctuate significantly with changes in load. Therefore, a relatively stable voltage output can be achieved without the need for complex closed-loop control.

[0025] Open-loop operation mode refers to the operating mode of a CLLC circuit that does not rely on feedback control and instead relies solely on the resonant characteristics of the circuit itself for energy transfer. In this mode, the steady-state performance of the circuit is extremely sensitive to the matching degree of component parameters.

[0026] Parameter drift refers to the phenomenon where the actual values ​​of resonant inductance and resonant capacitance deviate from their initial nominal values ​​due to factors such as temperature changes and increased operating time. This drift is non-linear and difficult to predict accurately.

[0027] Zero-voltage switching (ZVS) is a type of soft-switching technology that refers to the process where the voltage across the switching transistor has already been discharged to zero through circuit resonance before it is turned on, thus achieving zero-voltage turn-on. ZVS can significantly reduce switching losses and improve circuit efficiency.

[0028] ZVS loss refers to a circuit originally designed for ZVS operation where, due to parameter deviations, changes in operating conditions, or other reasons, the parasitic capacitance of the switching transistor fails to fully discharge to zero before turn-on, resulting in a hard turn-on and causing a sharp increase in switching losses and thermal safety hazards.

[0029] Dead time is a time interval artificially set in the drive signal during which both switches are off, to prevent a shoot-through short circuit caused by the simultaneous conduction of the upper and lower switches on the same half-bridge. During the dead time, the commutation behavior of the circuit is completely different from when the switches are on.

[0030] Parasitic capacitance refers to the inherent capacitance of the switching transistor itself, mainly including the output capacitance Coss. This capacitance participates in resonant commutation during high-frequency switching, and its charging and discharging behavior, especially during the dead time, directly affects whether ZVS can be achieved.

[0031] The fundamental equivalent analysis (FHA) method is a commonly used frequency domain analysis method for resonant converters. It approximates the analysis of non-sinusoidal voltage and current by retaining only the fundamental component, ignoring the influence of higher harmonics. This method is computationally simple but has limited accuracy and is difficult to characterize nonlinear processes such as dead zones.

[0032] P-mode is an independent operating mode of the full bridge as defined in this application. In this mode, the upper transistor of the first half-bridge and the lower transistor of the second half-bridge are turned on simultaneously, or their body diodes are turned on simultaneously, so that the voltage between the midpoints of the full bridge is clamped to the positive DC bus voltage, and the parasitic capacitance of the switching devices does not participate in resonant commutation.

[0033] N-mode is an independent operating mode of the full bridge as defined in this application. In this mode, the lower transistor of the first half-bridge and the upper transistor of the second half-bridge are turned on simultaneously, or their body diodes are turned on simultaneously, so that the voltage between the midpoints of the full bridge is clamped to the negative DC bus voltage, and the parasitic capacitance of the switching devices does not participate in resonant commutation.

[0034] Mode 0 is an independent operating mode of the full-bridge as defined in this application. In this mode, the full-bridge is in the dead zone, all switching transistors and their anti-parallel diodes are in the off state, the parasitic capacitance of the switching devices participates in the circuit resonance for charging or discharging, and the voltage between the midpoints changes dynamically.

[0035] The event-triggered hybrid step-size iterative method is the time-domain mathematical model solution proposed in this application. Its core idea is to use a large step size for fast solution during non-dead time, and switch to micro-step size for precise iteration during dead time, with the switching between modes driven by specific events.

[0036] Active shutdown triggering is one type of event triggering. When the positive or negative half-cycle drive signal ends and the circuit is turned off, the trigger circuit switches to the corresponding initial commutation operation mode, which includes the zero mode, based on the instantaneous polarity of the primary and secondary resonant currents at the moment of shutdown.

[0037] Resonant current natural zero-crossing triggering is the second type of event triggering. During the dead time, when a full bridge on one side is in P mode or N mode, if the resonant current on that side undergoes polarity reversal and crosses zero, it triggers the full bridge on that side to switch to O mode.

[0038] Voltage clamping triggering is the third type of event triggering. When the circuit is in an operating state that includes the O mode, if the absolute value of the voltage between the midpoints of the primary or secondary side reaches the corresponding DC bus voltage due to charging and discharging, the full bridge on that side is forcibly triggered to switch to the corresponding P mode or N mode, and the corresponding body diode will naturally conduct.

[0039] Multidimensional extreme operating condition data are the design boundary conditions defined in this application. They refer to the parameter combinations that cause multiple performance indicators of the CLLC to be in the worst state, extracted from the parameter tolerance range of the resonant inductor and resonant capacitor through ergonomic analysis. That is, the operating conditions in which the inductor and capacitor simultaneously have the largest positive deviation or the largest negative deviation.

[0040] The optimized parameter operating region is the feasible region of parameters defined in this application. It is the range of nominal parameters that simultaneously satisfies soft-switching and voltage gain conditions, obtained using a non-ideal time-domain mathematical model and constrained by multi-dimensional extreme operating condition data. Any set of parameters within this region can guarantee that the circuit still meets the design requirements under extreme tolerance conditions.

[0041] Reactive circulating current refers to the current component in a circuit that does not participate in the transfer of active power but is only used to establish a magnetic field or exchange energy with an electric field. In a CLLC (Clear-Loop Circuit), the excitation current is the main reactive circulating current; the larger its value, the greater the conduction loss and the lower the efficiency of the circuit.

[0042] Hard switching is the opposite of soft switching. It refers to the situation where the voltage across the switching transistor has not yet discharged to zero when the transistor is turned on, resulting in overlapping voltage and current waveforms, which in turn causes greater switching losses and electromagnetic interference.

[0043] Commutation refers to the process by which current in a circuit switches from one conduction path to another. In a CLLC (Clear-Loop Circuit), the commutation process mainly occurs during the dead time and involves the charging and discharging of parasitic capacitance and the conduction of the body diode.

[0044] Voltage clamping refers to the phenomenon where the voltage at a certain point in a circuit is forcibly limited to a fixed potential (such as the DC bus voltage). In this application, when the body diode of the switching transistor is turned on, the corresponding voltage between the midpoints of the full bridge is clamped to the DC bus voltage.

[0045] First, in order to facilitate understanding of the technical solution of this application, the basic topology of CLLC and the definition of its key parameters involved in this application are explained.

[0046] like Figure 1 As shown, the isolation-level CLLC topology described in this application includes a primary-side full-bridge, a secondary-side full-bridge, and a high-frequency transformer (transformer turns ratio n:1, magnetizing inductance L). m ) and LC series resonant cavities symmetrically distributed on the primary and secondary sides.

[0047] Primary-side full-bridge structure: This includes a first half-bridge composed of switching transistors Q1 and Q2, and a second half-bridge composed of switching transistors Q3 and Q4; Q1 and Q3 are the upper transistors, and Q2 and Q4 are the lower transistors. All primary-side switching devices have the same parasitic capacitance C. oss1 .

[0048] Secondary-side full-bridge structure: This includes a first half-bridge composed of switching transistors S1 and S2, and a second half-bridge composed of switching transistors S3 and S4; S1 and S3 are the upper transistors, and S2 and S4 are the lower transistors. Each switching device on the secondary side has the same parasitic capacitance C. oss2 .

[0049] Resonant cavity components: including primary resonant inductor L r1 Primary resonant capacitor C r1 Secondary resonant inductor L r2 and secondary resonant capacitor C r2 In a preferred embodiment of this application, the CLLC adopts a symmetrical structure design, and the main circuit parameters satisfy: L r1 =n 2 L r2 =L r C r1 =C r2 / n 2 =C r .

[0050] Based on the above topology, the robust design method of CLLC isolation stage for solid-state transformers proposed in this application is implemented as follows: Step S1: Model Building Steps In this step, the parasitic capacitance parameters and the preset dead time parameters of the switching devices must first be considered. The parasitic capacitance parameter refers to the inherent output capacitance Coss of the switching transistor (such as a MOSFET). This capacitance participates in resonant commutation during high-frequency switching; neglecting this will lead to a significant deviation between the theoretical model and the actual circuit behavior. The dead time parameter refers to the artificially set period during which both switching transistors are in the off state to prevent shoot-through of the upper and lower transistors of the same half-bridge. During this period, the commutation behavior of the circuit is completely different from when the switching transistors are on.

[0051] Specifically, establishing a full-cycle non-ideal time-domain mathematical model includes: Time-domain analytical expressions for nine operating modes of CLLC are established; an event-triggered hybrid step-size iterative method is adopted, and the nine operating modes are combined in a time sequence through three mode switching logics: active shutdown triggering, resonant current natural zero-crossing triggering, and voltage clamping triggering.

[0052] The nine operating modes are formed by combining three independent operating modes of the primary-side full-bridge and three independent operating modes of the secondary-side full-bridge; wherein, both the primary-side full-bridge and the secondary-side full-bridge include a first half-bridge and a second half-bridge, and both the first half-bridge and the second half-bridge include an upper pipe and a lower pipe; the three independent operating modes of the primary-side or secondary-side full-bridge include: P-mode: The upper diode of the first half-bridge and the lower diode of the second half-bridge, or the upper diode of the first half-bridge and the lower diode of the second half-bridge, are simultaneously turned on. The voltage between the midpoints of the first half-bridge and the second half-bridge is clamped to the DC bus voltage, and the parasitic capacitance of the switching devices does not participate in the resonant commutation. N-mode: The lower diode of the first half-bridge and the upper diode of the second half-bridge, or the lower diode of the first half-bridge and the upper diode of the second half-bridge, are simultaneously turned on. The voltage between the midpoints of the first half-bridge and the second half-bridge is clamped to the negative DC bus voltage, and the parasitic capacitance of the switching devices does not participate in the resonant commutation. O-mode: In the dead zone stage, all switching devices and their anti-parallel diodes on the same side of the full bridge are in the off state. The parasitic capacitance of the switching devices participates in the circuit resonance for charging or discharging. The voltage between the midpoints of the first half-bridge and the second half-bridge changes dynamically. The nine operating modes are: PP mode, PN mode, NP mode, NN mode, OP mode, ON mode, PO mode, NO mode, and OO mode.

[0053] Furthermore, the establishment of the time-domain analytical expressions for the nine operating modes specifically includes: For the operation phase with O-mode, the parasitic capacitances of the four switching transistors on the same side of the full bridge are simplified and equivalent to a single parasitic capacitance. The equivalent single parasitic capacitance is connected in series with the resonant capacitor on the same side to form an equivalent resonant cavity. The corresponding state differential equations are established and solved.

[0054] This step, by introducing the aforementioned parameters, constructs a non-ideal time-domain mathematical model to describe the electrical behavior of a CLLC circuit throughout the entire switching cycle. This model differs from the commonly used fundamental equivalent analysis (FHA) and other frequency-domain simplified models in the prior art, and can accurately characterize the transient waveforms of the resonant current, resonant capacitor voltage, magnetizing current, and the charging and discharging process of the switching transistor's parasitic capacitance in the time domain.

[0055] From a technical perspective, this step, by constructing a non-ideal time-domain mathematical model, overcomes the fundamental deficiency of existing frequency-domain models in being unable to quantitatively characterize dead-zone processes and the effects of parasitic capacitance, thus laying an accurate physical foundation for subsequent precise design and robustness evaluation. The model outputs a set of differential equations and their analytical or numerical solutions that describe the changes in electrical quantities in the CLLC circuit at various switching stages.

[0056] Furthermore, the event-triggered hybrid step-size iterative method specifically includes: During the non-dead time of the positive and negative half-cycles, the circuit operates in PP mode or NN mode, and a single solution is performed using a large step size, where the large step size is T. s / 2-t d T s For the switching period, t d Dead time; During the dead time, the circuit switches to microstep iteration for calculation. During the microstep iteration, the switching between modes is triggered by specific events.

[0057] Furthermore, the specific events specifically include: 1) Active turn-off triggering of switching devices: When the positive or negative half-cycle drive signal ends and the device is turned off, the trigger circuit switches to the corresponding operating mode according to the instantaneous polarity of the primary side resonant current and the secondary side resonant current at the moment of turn-off. 2) Resonant current natural zero-crossing trigger: During the dead time, when a certain side of the full bridge is in P mode or N mode, if the resonant current on that side reverses polarity and crosses zero, it will trigger the full bridge on that side to switch to O mode. 3) Voltage clamping trigger: When the circuit is in an operating state including O mode, if the absolute value of the voltage between the midpoint of the first half bridge and the second half bridge on the primary or secondary side reaches the corresponding DC bus voltage, the full bridge on that side will be triggered to switch to the corresponding P mode or N mode.

[0058] Step S2: Boundary Determination Step After completing the construction of the non-ideal time-domain mathematical model in step S1, this step further considers the uncertainties in actual engineering, namely the inductor element (L) in the resonant circuit. r ) and capacitor element (C r The parameter tolerance range of the device. In industrial mass production, due to processing limitations, the actual values ​​of inductance and capacitance cannot be exactly equal to the nominal values, but are distributed within a tolerance band (e.g., ±5%, ±10%). In addition, the parameters will drift further due to temperature rise and aging during long-term operation.

[0059] This step inputs the aforementioned parameter tolerance range into the non-ideal time-domain mathematical model constructed in step S1. Through traversal analysis—that is, systematically simulating or calculating all possible combinations of values ​​within the parameter tolerance range—the parameter combination that causes multiple performance indicators of the CLLC circuit (such as voltage gain accuracy, ZVS implementation conditions, etc.) to be in the worst state is obtained. This parameter combination is determined as the "multidimensional extreme operating condition data" referred to in this application.

[0060] From a technical perspective, this step, by introducing parameter tolerances and using extreme operating conditions as design boundaries, fundamentally overcomes the shortcomings of existing technologies that rely solely on ideal nominal parameters and are detached from actual engineering practice. The multi-dimensional extreme operating condition data output by this step represents the limit of parameter deviations that components may experience throughout their entire lifespan, ensuring that subsequent designs can cover the most severe operating conditions.

[0061] Specifically, the multidimensional extreme operating condition data refers to the operating condition where the resonant inductor and resonant capacitor simultaneously exhibit the largest positive or negative deviation.

[0062] Furthermore, the determination of the optimized parameter operating area specifically includes: The multidimensional extreme working condition data is substituted into the full-cycle non-ideal time-domain mathematical model, and several independent feasible regions that satisfy the CLLC performance constraints are mapped onto the nominal parameter plane. Logical intersection operation is performed on each of the independent feasible regions to extract the operating region of the optimization parameters.

[0063] Step S3: Parameter Programming Step After determining the multidimensional extreme operating condition data in step S2, this step uses this extreme operating condition data as the most stringent constraint boundary and performs inverse solution using the non-ideal time-domain mathematical model constructed in step S1. The goal of the solution is to find one or more sets of circuit parameters (such as Lr, Lm, Cr, etc.) such that the circuit can still simultaneously meet the preset soft-switching condition and voltage gain condition under this extreme operating condition.

[0064] Among them, soft switching condition usually refers to zero voltage turn-on (ZVS), that is, the parasitic capacitance voltage across the switch has been completely discharged to zero before the switch is turned on; voltage gain condition refers to the ratio of actual output voltage to input voltage being limited to the preset design allowable upper and lower limits.

[0065] The performance constraints specifically include: 1) Primary-side ZVS constraint: Under the aforementioned multidimensional extreme operating conditions, the parasitic capacitance voltage of all primary-side switching devices must be completely discharged to zero before they are turned on. 2) Secondary-side ZVS constraint: Under the aforementioned multidimensional extreme operating conditions, the parasitic capacitance voltage of all secondary-side switching devices must be completely discharged to zero before they are turned on. 3) Voltage gain constraint: Under the multi-dimensional extreme operating conditions, the steady-state voltage gain of the system is limited to the preset design allowable upper and lower limits.

[0066] Furthermore, the parameter optimization output within the optimized parameter operating area specifically includes: Using the measured leakage inductance value of the transformer as the nominal resonant inductance value, the maximum excitation inductance value is obtained within the optimized parameter operating range to minimize the reactive circulating current of the circuit; subsequently, the nominal resonant capacitance value is directly calculated using the resonant frequency formula based on the system's preset nominal resonant frequency.

[0067] By performing the reverse solution described above, a parameter range, known as the "optimized parameter operating range," can be determined. Any set of parameters within this range can guarantee that the circuit will still meet design requirements even under the most severe component deviation conditions. Finally, a specific set of nominal parameters (e.g., selecting the center or optimal value) is chosen within this optimized parameter operating range and output as the final design result.

[0068] From a technical perspective, this step, by expanding the design from a traditional "single parameter point" to a "parameter feasible domain," not only ensures robustness across the entire tolerance range but also significantly reduces the processing precision requirements of key components such as high-frequency transformers, thereby improving mass production yield. The nominal parameters output from this step can be directly used in the actual engineering design and production of solid-state transformer isolation stage CLLCs.

[0069] The technical solution of this application will be described in more detail and in a more complete manner below.

[0070] Step 1: Considering the parasitic capacitance and dead-time commutation process of the switching devices, a full-cycle non-ideal time-domain mathematical model is established. First, based on the actual on / off states of the switching transistors and anti-parallel diodes, three independent operating modes—P-mode, N-mode, and O-mode—are independently defined for both the primary and secondary full-bridge circuits. Through orthogonal combinations of the primary and secondary operating modes, nine segmented operating modes are formed: PP mode, PN mode, NP mode, NN mode, OP mode, ON mode, PO mode, NO mode, and OO mode.

[0071] The nine operating modes are formed by combining three independent operating modes of the primary-side full-bridge and three independent operating modes of the secondary-side full-bridge; wherein, both the primary-side full-bridge and the secondary-side full-bridge include a first half-bridge and a second half-bridge, and both the first half-bridge and the second half-bridge include an upper pipe and a lower pipe; the three independent operating modes of the primary-side or secondary-side full-bridge include: P-mode: The upper diode of the first half-bridge and the lower diode of the second half-bridge, or the upper diode of the first half-bridge and the lower diode of the second half-bridge, are simultaneously turned on. The voltage between the midpoints of the first half-bridge and the second half-bridge is clamped to the DC bus voltage, and the parasitic capacitance of the switching devices does not participate in the resonant commutation. N-mode: The lower diode of the first half-bridge and the upper diode of the second half-bridge, or the lower diode of the first half-bridge and the upper diode of the second half-bridge, are simultaneously turned on. The voltage between the midpoints of the first half-bridge and the second half-bridge is clamped to the negative DC bus voltage, and the parasitic capacitance of the switching devices does not participate in the resonant commutation. O-mode: In the dead zone stage, all switching devices and their anti-parallel diodes on the same side of the full bridge are in the off state. The parasitic capacitance of the switching devices participates in the circuit resonance for charging or discharging. The voltage between the midpoints of the first half-bridge and the second half-bridge changes dynamically. The nine operating modes are: PP mode, PN mode, NP mode, NN mode, OP mode, ON mode, PO mode, NO mode, and OO mode.

[0072] by Figure 2 Taking the PP mode as an example, at this time, the primary-side switches Q1 and Q4 are turned on, and the secondary-side switches S1 and S4 are turned on. The voltage v between the midpoints of the first and second half-bridges on the primary side is... AB Clamped to DC bus voltage V in The voltage v between the midpoints of the first and second half-bridges on the secondary side CD Clamped to the secondary DC bus voltage V o The parasitic capacitance of the switching device does not participate in resonant commutation because it is short-circuited by the conduction channel. After uniformly converting the secondary side parameters to the primary side, the corresponding state differential equations are written using Kirchhoff's laws as shown in equation (1): (1) In the formula, u c1 and u' c2 These are the primary resonant capacitor voltage and the reduced secondary resonant capacitor voltage, respectively; i p 、i' s and i m These are the primary resonant current, the converted secondary resonant current, and the transformer magnetizing current, Vin and V', respectively. o These are the input voltage and the converted output voltage, respectively. By performing an algebraic solution on equation (1) and substituting the initial values ​​of the state variables at the start of the mode, the time-domain expression of the variable in the PP mode can be obtained as equation (2).

[0073] (2).

[0074] The specific expressions for the coefficients in the formula are as follows: (3) In the formula, u c1 ( t 0), u ' c2 ( t 0), i p ( t 0), i’ s ( t 0) represents the start time of the PP mode. t The initial values ​​of each state variable are 0.

[0075] When the circuit reaches the dead time and enters a stage containing the 0-mode, the analysis will focus on the OP mode. Looking from the midpoint between the first and second half-bridges on the primary side, as shown... Figure 3 As shown, the parasitic capacitances of the four switching transistors exhibit a symmetrical topology, with each transistor connected in series and then in parallel. Therefore, the four parasitic capacitances of the primary-side full-bridge can be simplified and equivalent to a single parasitic capacitance, with a total equivalent capacitance value still being C. oss1 Because the magnitude of the parasitic capacitance is much smaller than the resonant capacitance C on the same side. r1 Therefore, the total equivalent capacitance formed by the single parasitic capacitance and the resonant capacitor on the same side connected in series is approximately equal to C. oss1 Based on this simplification criterion, the equivalent circuit diagram of the OP mode is as follows: Figure 4 As shown, the corresponding system of state differential equations is listed as shown in equation (4): (4).

[0076] In the formula, u 1 represents the sum of the voltage between the midpoints of the first and second half-bridges on the primary side and the voltage of the primary resonant capacitor.

[0077] Similarly, for the OO mode where both the primary and secondary sides are in a dead-zone cutoff state, its equivalent circuit is shown in [reference needed]. Figure 5 The corresponding system of state differential equations is shown in equation (5): (5).

[0078] In the formula, u '2 is the sum of the voltage between the midpoints of the first and second half-bridges on the secondary side and the voltage of the secondary resonant capacitor after conversion. C ' oss2 This is the converted secondary-side parasitic capacitance.

[0079] To concatenate the above piecewise non-ideal expressions into a continuous waveform with a full cycle, this application employs an event-triggered hybrid step-size iterative method for time series combination: 1. Large Step Size Solution Stage: During the non-dead time of the positive and negative half-cycles, the circuit operates in the stable PP mode or NN mode. The algorithm directly performs a single solution with a large step size, where the large step size is T. s / 2-t d .

[0080] 2. Micro-step event triggering phase: During the dead time, the circuit switches to micro-step for precise iterative calculations. The switching between modes is driven by trigger events generated when the circuit's internal state variables reach specific thresholds. The specific triggering logic includes: 1) Active turn-off triggering of switching devices: When the positive or negative half-cycle drive signal ends and the device is turned off, the trigger circuit switches to the corresponding initial commutation operation mode containing the O mode according to the instantaneous polarity of the primary side resonant current and the secondary side resonant current at the moment of turn-off.

[0081] 2) Resonant current natural zero-crossing trigger: During the dead time, when a certain side of the full bridge is in P mode or N mode, if the resonant current on that side reverses polarity and crosses zero, it will trigger the full bridge on that side to switch to O mode.

[0082] 3) Voltage clamping trigger: When the circuit is operating in a state including the O mode, if the absolute value of the voltage between the midpoint of the first half-bridge and the second half-bridge on the primary or secondary side reaches the corresponding DC bus voltage due to charging and discharging, the full bridge on that side is forcibly triggered to switch to the corresponding P mode or N mode, and the corresponding body diode naturally conducts. Through the above mixed step-size iteration, the full-cycle non-ideal time-domain mathematical model is established.

[0083] Step 2: Combining the full-cycle non-ideal time-domain mathematical model, considering the tolerance of the resonant components, extract the worst tolerance value that induces the multidimensional performance of the CLLC as multidimensional extreme operating condition data.

[0084] Let the nominal values ​​of the resonant inductor and resonant capacitor be Lr and Cr, respectively, and their actual values ​​be LrA and CrA. These values ​​can be expressed as: (6) Where, α min ,β min These represent the lower tolerance limits of the inductor and capacitor, respectively, α max ,β max This represents the upper limit of tolerance. The multi-dimensional extreme operating condition data represents the operating condition where the resonant inductor and resonant capacitor simultaneously exhibit the largest positive or negative deviation.

[0085] Step 3: Based on the multidimensional extreme operating condition data and the full-cycle non-ideal time-domain mathematical model, determine the operating region of the optimized parameters, and perform parameter optimization output within the operating region. On a two-dimensional nominal parameter plane graph with the nominal excitation inductance Lm and the nominal resonant inductance Lr as coordinate axes, deduce and map the following three dimensions of independent performance constraint feasible regions: Primary-side ZVS constraint: Under the aforementioned multidimensional extreme operating conditions, the parasitic capacitance voltage of all primary-side switching devices must be completely discharged to zero before they are turned on. Secondary-side ZVS constraint: Under the aforementioned multidimensional extreme operating conditions, the parasitic capacitance voltage of all secondary-side switching devices must be completely discharged to zero before they are turned on. Voltage gain constraint: Under the multi-dimensional extreme operating conditions, the steady-state voltage gain of the system is limited to the preset design allowable upper and lower limits.

[0086] In nominal parameters (L) r ,L m On the plane, a logical intersection operation is performed on the three independent feasible regions mapped above: the primary side ZVS, the secondary side ZVS, and the voltage gain, to extract the optimized parameter operating region that takes into account parameter tolerance.

[0087] This application introduces the following specific optimization design criteria: The system's nominal resonant inductance value L... r The size constraint is limited to the measured leakage inductance value of the high-frequency transformer. Within the extracted optimized parameter operating range, the maximum allowable excitation inductance value L within this range is obtained through optimization. m Finally, based on the system's preset nominal operating frequency f... r The required nominal resonant capacitance value C can be directly calculated using the resonant frequency formula (7). r The final nominal parameters of the system are obtained and output. The resonant frequency formula (7) is as follows: (7).

[0088] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0089] This embodiment designs a CLLC with an input voltage of 400V, an output voltage of 400V, a rated transmission power of 2kW, a high-frequency transformer ratio of 1:1, and a switching frequency of 50kHz. The parasitic capacitance of the selected switching devices on the primary and secondary sides is 540pF.

[0090] Step 1: Taking into account the parasitic capacitance and dead-zone commutation process of the switching devices, establish a full-cycle non-ideal time-domain mathematical model: Establish a mathematical model based on the circuit parameters of this embodiment.

[0091] Step 2: Combining the full-cycle non-ideal time-domain mathematical model, considering the tolerance of the resonant components, the tolerance values ​​that induce the worst multidimensional performance of the CLLC are extracted as multidimensional extreme operating condition data: the maximum positive deviation of 10% for both inductor and capacitor parameters, and the maximum negative deviation of -10% for both parameters.

[0092] Step 3: Based on the multidimensional extreme operating condition data and the full-cycle non-ideal time-domain mathematical model, determine the optimized parameter operating region, and perform parameter optimization within the optimized parameter operating region: On the nominal parameter plane, perform a logical intersection operation on the three independent feasible regions mapped above—primary-side ZVS, secondary-side ZVS, and voltage gain—to extract the optimized parameter operating region. The measured transformer leakage inductance is 3.38uH; therefore, within the optimized parameter operating region, the maximum excitation inductance value is obtained as 500uH, and the required nominal resonant capacitance value is calculated as 3uF.

[0093] Using the design parameters described in this embodiment, an experimental setup was constructed for testing. The measured voltage gain and soft-switching waveform under parameter deviations of the experimental setup are as follows: Figure 6-9 As shown, an experimental setup was built using the design parameters described above in this embodiment for testing. The measured voltage gain and soft-switching waveform of the experimental setup under parameter deviations are shown below. Figures 6 to 9 As shown. Among them, Figure 6 The measured voltage gain curve shows that the voltage gain remains constant and meets design expectations within the full tolerance range; Figure 7 The ZVS waveform under nominal parameters; Figure 8 The ZVS waveform is for the lower limit of parameter deviation (inductor and capacitor are simultaneously negatively biased by 10%). Figure 9 This is the ZVS waveform under the maximum parameter deviation condition (inductor and capacitor simultaneously forward biased by 10%). The waveform shows that the primary and secondary switching devices are under gate drive signal v GS Before its arrival, its drain-source voltage v DS The voltage drop has completely decreased to zero, proving that both the primary and secondary switching devices have achieved ZVS turn-on. Therefore, it can be concluded that even under extreme tolerance conditions, the ZVS soft-switching characteristics of the switching transistors are maintained, verifying the effectiveness of the parameter design method proposed in this application. This demonstrates that the proposed parameter design method can achieve constant voltage gain and ZVS operation across the entire tolerance range.

[0094] Secondly, this application provides a robust design system for the isolation stage CLLC of a solid-state transformer, comprising: a model building module, used to construct a non-ideal time-domain mathematical model describing the electrical behavior of the CLLC circuit throughout the entire switching cycle, taking into account the parasitic capacitance parameters of the switching devices and preset dead-time parameters; a boundary determination module, used to input the parameter tolerance ranges of the inductor and capacitor elements in the resonant circuit into the non-ideal time-domain mathematical model, obtain the parameter combinations that cause multiple performance indicators of the CLLC circuit to be in the worst state through ergonomic analysis, and determine the parameter combinations as multi-dimensional extreme operating condition data; and a parameter planning module, used to use the multi-dimensional extreme operating condition data as constraint boundaries, use the non-ideal time-domain mathematical model to solve for the optimized parameter operating region that can simultaneously satisfy preset soft-switching conditions and voltage gain conditions, and select and output the nominal parameters of the CLLC circuit within the optimized parameter operating region.

[0095] Preferably, the specific method by which the model building module constructs the non-ideal time-domain mathematical model includes: defining three independent operating modes—P mode, N mode, and O mode—based on the on / off states of each switch in the primary and secondary full-bridge circuits, and orthogonally combining the primary and secondary operating modes to generate nine segmented operating modes that cover the entire switching cycle of the CLLC circuit; establishing time-domain analytical expressions for each segmented operating mode, and splicing the segmented operating modes according to a time sequence through mode switching logic.

[0096] Preferably, the P-mode, N-mode, and O-mode are defined as follows: P-mode: In the same full-bridge, the upper transistor of the first half-bridge and the lower transistor of the second half-bridge are simultaneously turned on, or their body diodes are simultaneously turned on, so that the voltage between the midpoints of the full-bridge is clamped to the positive DC bus voltage; N-mode: In the same full-bridge, the lower transistor of the first half-bridge and the upper transistor of the second half-bridge are simultaneously turned on, or their body diodes are simultaneously turned on, so that the voltage between the midpoints of the full-bridge is clamped to the negative DC bus voltage; O-mode: The same full-bridge is in the dead zone stage, all switching transistors and their body diodes are turned off, the parasitic capacitance of the switching transistors of the full-bridge participates in resonant charging and discharging, and the voltage between its midpoints changes dynamically.

[0097] Preferably, the mode switching logic is a hybrid step-size iterative method based on event triggering, including: solving the P mode or N mode in a single step with a large step size during the non-dead time; switching to micro-step size for iterative calculation during the dead time, and triggering the entry and exit of the corresponding segmented operating mode according to the active turn-off event of the switch, the natural zero-crossing event of the resonant current, or the voltage clamping event.

[0098] Preferably, the multi-dimensional extreme operating condition data determined by the boundary determination module is specifically: a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum positive tolerance value, or a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum negative tolerance value.

[0099] Preferably, the parameter planning module determines the optimized parameter operating region in the following ways: substituting the multidimensional extreme operating condition data into the non-ideal time-domain mathematical model, mapping a first feasible region that satisfies the preset soft-switching condition and a second feasible region that satisfies the voltage gain condition on a plane with the nominal parameter as the coordinate axis, and performing a logical intersection operation on the first feasible region and the second feasible region to extract the optimized parameter operating region.

[0100] Preferably, the preset soft-switching conditions and voltage gain conditions specifically include: a first constraint: under the multi-dimensional extreme operating conditions, before each switch in the primary-side full bridge and the secondary-side full bridge is turned on, its corresponding parasitic capacitance voltage has been completely discharged to zero; a second constraint: under the multi-dimensional extreme operating conditions, the steady-state voltage gain of the CLLC circuit is limited to the preset design allowable upper and lower limits.

[0101] Preferably, the specific method by which the parameter planning module selects and outputs the nominal parameters of the CLLC circuit within the optimized parameter operating area includes: using the measured leakage inductance value of the high-frequency transformer in the CLLC circuit as the nominal resonant inductance value, and selecting the excitation inductance value that meets the performance requirements and has the largest value within the optimized parameter operating area as the nominal excitation inductance value.

[0102] Preferably, when selecting the nominal excitation inductance value, the optimization objective is to minimize the reactive circulating current of the circuit.

[0103] Preferably, after determining the nominal resonant inductance value and the nominal excitation inductance value, the nominal resonant capacitance value is also calculated and output by reverse calculation using the resonant frequency formula based on the nominal resonant frequency preset by the system.

[0104] Thirdly, this application provides a controller characterized in that it is configured to execute the described robust design method for isolation stage CLLC of solid-state transformers.

[0105] Fourthly, this application provides an electronic device, characterized in that it includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the robust design method of the isolation stage CLLC for solid-state transformers.

[0106] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when the program is executed by a processor, it implements the robust design method for the isolation stage CLLC of a solid-state transformer.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0109] This application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0111] Obviously, the described embodiments are only some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort should fall within the scope of protection of this application.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A robust design method for the isolation stage CLLC of a solid-state transformer, characterized in that, Includes the following steps: S1: Taking into account the parasitic capacitance parameters of the switching devices and the preset dead time parameters, a non-ideal time-domain mathematical model is constructed to describe the electrical behavior of the CLLC circuit throughout the entire switching cycle. S2: Input the parameter tolerance range of the inductor and capacitor in the resonant circuit into the non-ideal time-domain mathematical model, obtain the parameter combination that causes multiple performance indicators of the CLLC circuit to be in the worst state through ergonomic analysis, and determine the parameter combination as multi-dimensional extreme working condition data. S3: Using the multidimensional extreme operating condition data as the constraint boundary, the optimized parameter operating range that can simultaneously satisfy the preset soft switching conditions and voltage gain conditions is solved using the non-ideal time-domain mathematical model, and the nominal parameters of the CLLC circuit are selected and output within the optimized parameter operating range.

2. The robust design method for the isolation stage CLLC of a solid-state transformer according to claim 1, characterized in that, Taking into account the parasitic capacitance parameters of the switching devices and the preset dead time parameters, a non-ideal time-domain mathematical model is constructed to describe the electrical behavior of the CLLC circuit throughout the entire switching cycle, specifically including: Based on the on / off states of each switch in the primary and secondary full-bridge circuits, three independent operating modes—P mode, N mode, and O mode—are defined. The primary and secondary operating modes are orthogonally combined to generate nine segmented operating modes that cover the entire switching cycle of the CLLC circuit. Time-domain analytical expressions for each segmented operating mode are established, and the segmented operating modes are spliced ​​together in a timing sequence using mode switching logic.

3. The robust design method for the isolation stage CLLC of a solid-state transformer according to claim 2, characterized in that, The P-mode, N-mode, and O-mode are specifically defined as follows: P-mode: In the same full bridge, the upper transistor of the first half bridge and the lower transistor of the second half bridge are turned on at the same time, or the body diodes of the two are turned on at the same time, so that the voltage between the midpoints of the full bridge is clamped to the positive DC bus voltage. N-mode: In the same full bridge, the lower transistor of the first half bridge and the upper transistor of the second half bridge are turned on at the same time, or the body diodes of the two are turned on at the same time, so that the voltage between the midpoints of the full bridge is clamped to the negative DC bus voltage. O-mode: When the same full bridge is in the dead zone, all switching transistors and their body diodes are turned off. The parasitic capacitance of the switching transistors in this full bridge participates in resonant charging and discharging, and the voltage between its midpoints changes dynamically.

4. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 2, characterized in that, The mode switching logic is specifically an event-triggered hybrid step-size iterative method, including: Within the non-dead time, the P-mode or N-mode is solved in a single pass with a large step size; the large step size is T. s / 2-t d T s For the switching period, t d Dead time; During the dead time, it switches to micro-step size for iterative calculation, and triggers the entry and exit of the corresponding segmented operation mode based on the active turn-off event of the switch, the natural zero-crossing event of the resonant current, or the voltage clamping event.

5. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 1, characterized in that, The multidimensional extreme operating condition data in step S2 specifically refers to: a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum positive tolerance value, or a parameter combination in which the resonant inductor and resonant capacitor simultaneously take the maximum negative tolerance value.

6. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 1, characterized in that, The step of using the multidimensional extreme operating condition data as a constraint boundary and employing the non-ideal time-domain mathematical model to solve for the optimized parameter operating range that can simultaneously satisfy the preset soft-switching conditions and voltage gain conditions specifically includes: Substituting the multidimensional extreme operating condition data into the non-ideal time-domain mathematical model, a first feasible region satisfying the preset soft-switching condition and a second feasible region satisfying the voltage gain condition are mapped onto a plane with the nominal parameters as coordinate axes. Logical intersection operations are then performed on the first feasible region and the second feasible region to extract the operating region of the optimized parameters.

7. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 6, characterized in that, The preset soft-switching conditions and voltage gain conditions specifically include: First constraint: Under the aforementioned multidimensional extreme operating conditions, before each switch in the primary-side full bridge and the secondary-side full bridge is turned on, its corresponding parasitic capacitance voltage has been completely discharged to zero. Second constraint: Under the aforementioned multidimensional extreme operating conditions, the steady-state voltage gain of the CLLC circuit is limited to the preset design allowable upper and lower limits.

8. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 1, characterized in that, Step S3, which involves selecting and outputting the nominal parameters of the CLLC circuit within the optimized parameter operating area, specifically includes: The measured leakage inductance value of the high-frequency transformer in the CLLC circuit is used as the nominal resonant inductance value, and the excitation inductance value that meets the performance requirements and has the largest value is selected as the nominal excitation inductance value within the operating range of the optimized parameters. When selecting the nominal excitation inductance value, the optimization objective is to minimize the reactive circulating current of the circuit.

9. A robust design method for the isolation stage CLLC of a solid-state transformer according to claim 8, characterized in that, After determining the nominal resonant inductance value and the nominal excitation inductance value, the nominal resonant capacitance value is calculated and output by reverse calculation using the resonant frequency formula based on the system's preset nominal resonant frequency.

10. A robust design system for the isolation stage CLLC of a solid-state transformer, characterized in that, include: The model building module is used to construct a non-ideal time-domain mathematical model to describe the electrical behavior of the CLLC circuit throughout the entire switching cycle, taking into account the parasitic capacitance parameters of the switching devices and the preset dead time parameters. The boundary determination module is used to input the parameter tolerance range of the inductor and capacitor elements in the resonant circuit into the non-ideal time-domain mathematical model, obtain the parameter combination that causes multiple performance indicators of the CLLC circuit to be in the worst state through ergonomic analysis, and determine the parameter combination as multi-dimensional extreme operating condition data. The parameter planning module is used to solve the optimized parameter operating range that can simultaneously meet the preset soft switching conditions and voltage gain conditions using the multi-dimensional extreme operating condition data as the constraint boundary and the non-ideal time domain mathematical model, and select and output the nominal parameters of the CLLC circuit within the optimized parameter operating range.

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