A simplified method of virtual space vector pulse width modulation for T-type three-level inverters

Abstract

The application provides a T-type three-level inverter virtual space vector pulse width modulation simplification method, and belongs to the technical field of power electronic multilevel inverter modulation. The application comprises the following steps: S1: converting given axis and axis reference voltage to a coordinate system through coordinate transformation; S2: calculating and comparing intermediate variables in register configuration; S3: using the same sector judgment method as traditional two-level SVPWM modulation to judge the large sector where the target synthetic voltage vector is located; S4: according to the sector judgment result obtained in step S3 and the intermediate variables obtained in step S2, calculating the duty cycle by using the pre-calculated switch tube action time duty cycle expression; S5: according to the switch tube action time duty cycle obtained in step S4, completing ePWM comparison register configuration and outputting PWM waveform. The application directly uses the expression obtained through offline calculation to realize the calculation of the duty cycle of the action time of each switch tube, reduces the calculation amount of the algorithm and improves the calculation accuracy.

Description

Technical Field

[0001] This invention relates to a simplified method for virtual space vector pulse width modulation of a T-type three-level inverter, belonging to the field of power electronic multilevel inverter modulation technology. Background Technology

[0002] The T-type Neutral Point Clamped (T-NPC) three-level topology is widely used in high-voltage, high-power applications due to its low output voltage harmonics and low switching voltage withstand capability. However, due to the presence of neutral point current, this topology inherently suffers from neutral point voltage fluctuations. The Virtual Space Vector Pulse Width Modulation (SVPWM) strategy is a modulation strategy proposed to address this inherent problem of the NPC three-level topology. This strategy rewrites the vector space of traditional three-level space vector pulse width modulation (SVPWM) into a vector space composed of virtual vectors that have no effect on neutral point voltage fluctuations, and uses these virtual vectors to synthesize the target voltage vector.

[0003] Traditional virtual space vector pulse width modulation (VSP) methods for three-level inverters require first determining the large sector where a given target voltage vector resides, and then, based on geometric relationships, further determining the small sector where the target voltage vector resides. After sector determination, a basic voltage vector is selected based on the sector where the voltage vector resides, and the duration of each voltage vector is calculated. Subsequently, the duty cycle of each switch can be calculated. This process involves determining the large and small sectors of the voltage vector and calculating the duration of each voltage vector individually. This involves numerous calculations and judgments, resulting in a heavy computational burden and complex program steps. Therefore, designing a simplified VSP method for three-level inverters is of significant value. Summary of the Invention

[0004] The purpose of this invention is to address the problems existing in the prior art and provide a simplified method for virtual space vector pulse width modulation (VSPWM) in a T-type three-level inverter. The core idea of ​​this method is to pre-calculate the expression for the duty cycle of each switch offline and directly apply it to the program, thereby bypassing the judgment of small sectors and the online calculation of the action time of each voltage vector in the traditional three-level inverter's Virtual Space Vector Pulse Width Modulation (VSPWM) method. This invention first synthesizes the actual voltage vector into a virtual voltage vector, then establishes a system of linear equations based on the synthesis conditions of the target voltage vector and other constraints. By solving this system of equations, the action time of the virtual vector is obtained, and then the action time and duty cycle of the corresponding actual voltage vector can be deduced, thus obtaining the duty cycle expression. Using the pre-calculated duty cycle expression and its inherent mathematical laws for program writing can significantly simplify the program calculation process and improve the calculation speed of the VSVPWM method in the program.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A simplified method for virtual space vector pulse width modulation in a T-type three-level inverter includes the following steps:

[0007] S1: Given shaft and The axis reference voltage is transformed to... Coordinate system;

[0008] S2: Calculate intermediate variables for the comparison register configuration. ;

[0009] S3: The same sector determination method as traditional two-level SVPWM modulation is used to determine the large sector where the target synthesized voltage vector is located;

[0010] S4: Based on the sector judgment result obtained in step S3 and the intermediate variable obtained in step S2, calculate the duty cycle using the pre-calculated duty cycle expression of the switching transistor's operating time.

[0011] S5: Based on the duty cycle of the switching transistor obtained in step S4, complete the configuration of the ePWM comparator register and output the PWM waveform.

[0012] Preferably, the coordinate transformation described in step S1 is performed to... The formula for the coordinate system is as follows:

[0013]

[0014] in, For voltage vector in shaft and Components on the axis, For voltage vector in shaft and Components on the axis, This refers to the DC bus voltage in the motor system.

[0015] Preferably, the intermediate variable for calculating the comparison register configuration in step S2 is... The formula is as follows:

[0016]

[0017] in, and The target composite vector at this time is respectively shaft and Components on the axis.

[0018] Preferably, the method for synthesizing the target synthesized voltage vector in step S3 is as follows:

[0019] The spatial vector diagram is divided into 6 large sectors according to the SVPWM modulation method of the three-level topology. The voltage vector is synthesized into a virtual vector. Each large sector contains 1 virtual zero vector, 2 virtual small vectors, 1 virtual medium vector and 2 virtual large vectors.

[0020] Two virtual small vectors are each synthesized from a pair of adjacent small vectors in the basic vector, wherein the positive and negative vectors in the pair of small vectors each account for half and have the same duration of action; one virtual medium vector is synthesized from one medium vector in the basic vector and two different adjacent small vectors; two virtual large vectors are directly taken from the two large vectors in the basic vector; one virtual zero vector is directly taken from the zero vector in the basic vector.

[0021] For a given target voltage vector, the sector in which it is located is determined first, using the same sector determination method as traditional SVPWM. Then, based on the sector determination result, a virtual vector is selected for synthesizing the target voltage vector. Finally, based on geometric relationships, the selected virtual vector is synthesized into the target synthesized voltage vector.

[0022] Preferably, the expression for the pre-calculated duty cycle of the switching transistor in step S4 is as follows:

[0023] when When =1, ;

[0024] when When =2, ;

[0025] when When =3, ;

[0026] when When =4, ;

[0027] when When =5, ;

[0028] when When =6, ;

[0029] in, For sector determination results, These are the on-time duty cycles of the 1 and 2 switching transistors in phases A, B, and C of a T-type three-level inverter.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] This invention discloses a simplified method for virtual space vector pulse width modulation (VVM) of a T-type three-level inverter. This method bypasses the small sector judgment and voltage vector action time calculation steps in traditional modulation methods, avoids the complex geometric calculation process in traditional methods, and directly uses the expression obtained from offline calculation to calculate the duty cycle of each switching transistor. This significantly reduces the computational load of the algorithm and improves the accuracy of the calculation.

[0032] Compared to the traditional VSVPWM algorithm, the simplified algorithm proposed in this invention utilizes a pre-calculated duty cycle expression and is based on its inherent mathematical principles for program writing. This significantly simplifies the program calculation process, requiring far fewer steps and less online computation than traditional algorithms, thus improving the calculation speed of the VSVPWM method in the program. The execution efficiency of this algorithm is far higher than that of traditional algorithms, and the amount of code is significantly less, contributing to the lightweight improvement of the algorithm's program space.

[0033] Furthermore, the method used in this invention is also effective for other three-level circuit topologies and can be extended to VSVPWM modulation strategies for other three-level circuit topologies. Attached Figure Description

[0034] Figure 1 This is a topology diagram of the T-type midpoint clamped three-level inverter of the present invention.

[0035] Figure 2This is a schematic diagram of the basic vector space structure of the three-level inverter of the present invention.

[0036] Figure 3 This is a schematic diagram of the sector division structure of the I sector of the present invention; wherein:

[0037] Figure 3 (a) is a schematic diagram of the first sector of a three-level SVPWM;

[0038] Figure 3 (b) is a schematic diagram of the first sector of the three-level VSVPWM.

[0039] Figure 4 This is a schematic diagram of the virtual vector space structure of the three-level inverter of the present invention.

[0040] Figure 5 This is a flowchart of a traditional algorithm.

[0041] Figure 6 This is a flowchart of a simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to the present invention. Detailed Implementation

[0042] The present invention will be further described in detail below with reference to the accompanying drawings: This embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation methods are given, but the protection scope of the present invention is not limited to the following embodiments.

[0043] like Figure 6 As shown in the figure, the simplified virtual space vector pulse width modulation method for a T-type three-level inverter involved in this embodiment includes the following steps:

[0044] S1: Given shaft and The axis reference voltage is transformed to... Coordinate system;

[0045] S2: Calculate the intermediate variables for configuring the comparison register;

[0046] S3: The same sector determination method as traditional two-level SVPWM modulation is used to determine the large sector where the target synthesized voltage vector is located;

[0047] The target synthesized voltage vector is the voltage vector required by the motor system at this time, that is, the voltage vector that the VSVPWM module wants to synthesize at this time. The target synthesized voltage vector is given by the motor dual closed-loop control system, and the process of giving it is completely consistent with the traditional PMSM dual closed-loop control.

[0048] S4: Based on the sector judgment result obtained in step S3 and the intermediate variable obtained in step S2, calculate the duty cycle using the pre-calculated duty cycle expression of the switching transistor's operating time.

[0049] S5: Based on the duty cycle of the switching transistor obtained in step S4, complete the configuration of the ePWM comparator register and output the PWM waveform.

[0050] The core idea of ​​this invention lies in pre-calculating the expression for the duty cycle of each switch offline and directly applying it to the program, thereby bypassing the online calculation process for small sectors and the duration of each voltage vector in the traditional three-level VSVPWM method. This invention first synthesizes the actual voltage vector into a virtual voltage vector, then establishes a system of linear equations based on the synthesis conditions of the target voltage vector and other constraints. By solving this system of equations, the duration of the virtual vector is obtained, and then the duration and duty cycle of the corresponding actual voltage vector can be deduced, thus obtaining the duty cycle expression. Using the pre-calculated duty cycle expression and its inherent mathematical laws in program writing significantly simplifies the program calculation process and improves the calculation speed of the VSVPWM method in the program.

[0051] The technical problem solved by this invention and the derivation process of the formula are as follows:

[0052] The circuit topology of the T-type midpoint clamped three-level inverter is shown in Figure 1, and its basic vector space is shown in Figure 2.

[0053] Taking phase A as an example, when the switching transistor S... A1 ,S A2 When the circuit is on, the potential at the midpoint of the bridge arm is This is represented by the switching state P; when the switching transistor S... A2 ,S A3 When the circuit is on, the potential at the midpoint of the bridge arm is 0, indicating a switching state O; when the switching transistor S... A3 ,S A4 When the circuit is on, the potential at the midpoint of the bridge arm is This represents the switching state N. Generally speaking, the switching transistor S... A1 ,S A3 Complementary conduction, switching transistor S A2 ,S A4 Complementary conduction, therefore only the switching transistor S needs to be calculated. A1 ,S A2 The duty cycle of the transistor can be used to obtain the duty cycle of all the switching transistors.

[0054] To simplify the calculation, the coordinate transformation given in equation (1) is chosen to transform the rectangular coordinate system ( Transform all voltage vectors in the coordinate system to the 60° coordinate system. In a coordinate system, all voltage vectors are normalized. The outer boundary of the spatial vector diagram is then a regular hexagon with a circumscribed circle of radius 2. Using geometric relationships, the coordinates of the points corresponding to each voltage vector can be obtained.

[0055] (1)

[0056] in, For voltage vector in shaft and Components on the axis, For voltage vector in shaft and Components on the axis, This refers to the DC bus voltage in the motor system.

[0057] For the VSVPWM strategy, the basic vectors need to be synthesized into virtual vectors that have no effect on the midpoint voltage fluctuation. Taking sector I shown in Figure 3(a) as an example, the voltage vectors contained therein will be synthesized into virtual vectors as shown in Figure 3(b), which includes 1 virtual zero vector, 2 virtual small vectors, 1 virtual medium vector and 2 virtual large vectors.

[0058] Among them, virtual small vectors A pair of smaller vectors from the fundamental vectors and The composite vectors, with each occupying half the space and acting for the same duration, are:

[0059] (2)

[0060] Virtual vector One of the fundamental vectors and its two adjacent distinct small vectors and Synthesis, the synthesis method is as follows:

[0061] (3)

[0062] Since neither the large vector nor the zero vector in the fundamental vectors affects the midpoint current, the virtual large vector... and You can directly take the larger vector from the basic vectors. and The virtual zero vector can also be directly taken as the zero vector among the basic vectors, that is:

[0063] (4)

[0064] (5)

[0065] By synthesizing the basic vectors according to the above method and corresponding formula, the virtual vector space of the three-level inverter shown in Figure 4 can be obtained.

[0066] Taking sector 1 of sector I in Figure 3(b) as an example, the virtual vector used is: and Based on the requirements for synthesizing the target voltage vector and the constraint that the sum of the duty cycles of all switching states is 1, the following system of linear equations can be established.

[0067] (6)

[0068] In the formula, Representing virtual vectors respectively The duty cycle corresponding to the state, and This indicates that the target composite vector is at this time. shaft and The components on the axis. The solution to equation (6) can be obtained as:

[0069] (7)

[0070] According to the virtual vector synthesis method described above, the duty cycle of the switching state can be calculated according to equation (8):

[0071] (8)

[0072] in, They represent voltage vectors, These represent the duty cycles of the corresponding switch states;

[0073] Calculate the duty cycle of the switching device by establishing a system of linear equations based on the switching state:

[0074] (9)

[0075] In the formula Let be the duty cycle of the conduction time of switches 1 and 2 in phases A, B, and C. Generally, the conduction times of switches 1 and 3 in each phase are complementary, and the conduction times of switches 2 and 4 in each phase are complementary. Thus, the duty cycle of the conduction time of all switches can be obtained. The solution to equation (9) can be obtained as follows:

[0076] (10)

[0077] By applying the same calculation process to other sectors, the expressions for the duty cycle of the switching transistors in all sectors can be obtained. Based on the calculated expressions, the ePWM module can be configured. After normalization using the maximum value of the ePWM period register as a reference, the configurations of the Sx1 and Sx2 compare registers as shown in Table 1 can be obtained.

[0078] Table 1. Configuration of Three-Level VSVPWM Comparator Register

[0079] To simplify program writing, intermediate variables are defined as follows:

[0080] (11)

[0081] in, As an intermediate variable;

[0082] Using predefined intermediate variables makes expressions more concise and readable. Combining the above calculation process and results, and following the flowchart shown in Figure 6, it is possible to configure the comparison register directly without performing small sector judgment and vector action time calculation. For example... Figure 5 The flowchart of the traditional VSVPWM algorithm shown below and as follows Figure 6 The simplified algorithm flowchart shown demonstrates that the simplified algorithm proposed in this invention requires significantly fewer steps and less online computation than traditional algorithms. This algorithm boasts significantly higher execution efficiency than traditional algorithms, while its code size is considerably smaller, contributing to a lighter program space.

[0083] Example 1

[0084] This invention consists of the following steps:

[0085] S1. Given shaft and The axis reference voltage is transformed to... Coordinate system;

[0086]

[0087] S2. Calculate intermediate variables ;

[0088]

[0089] in, and They are respectively shaft and Shaft reference voltage;

[0090] S3. The same sector determination method as traditional two-level SVPWM modulation is used to determine the large sector where the target synthesized voltage vector is located;

[0091] S4. Based on the sector judgment result, calculate the duty cycle using the pre-calculated duty cycle expression for the switching transistor's operating time;

[0092] when When =1, ;

[0093] when When =2, ;

[0094] when When =3, ;

[0095] when When =4, ;

[0096] when When =5, ;

[0097] when When =6, ;

[0098] in, For sector determination results, The duty cycle of the conduction time of each phase 1 and 2 switch transistor;

[0099] S5. Based on the obtained duty cycle of the switching transistor, configure the ePWM comparator register and output the PWM waveform.

[0100] Figure 6 shows a flowchart of a simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to the present invention.

[0101] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A simplified method for virtual space vector pulse width modulation in a T-type three-level inverter, characterized in that, Includes the following steps: S1: Given shaft and The axis reference voltage is transformed to... Coordinate system; S2: Calculate intermediate variables for the comparison register configuration. ; S3: The same sector determination method as traditional two-level SVPWM modulation is used to determine the large sector where the target synthesized voltage vector is located; S4: Based on the sector judgment result obtained in step S3 and the intermediate variable obtained in step S2, calculate the duty cycle using the pre-calculated duty cycle expression of the switching transistor's operating time. S5: Based on the duty cycle of the switching transistor obtained in step S4, complete the configuration of the ePWM comparator register and output the PWM waveform.

2. The simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to claim 1, characterized in that, The transformation to coordinates described in step S1 The formula for the coordinate system is as follows: in, For voltage vector in shaft and Components on the axis, For voltage vector in shaft and Components on the axis, This refers to the DC bus voltage in the motor system.

3. The simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to claim 2, characterized in that, The intermediate variable for calculating the comparison register configuration in step S2 is... The formula is as follows: in, and The target composite vector at this time is respectively shaft and Components on the axis.

4. The simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to claim 3, characterized in that, The method for synthesizing the target synthesized voltage vector in step S3 is as follows: The spatial vector diagram is divided into 6 large sectors according to the SVPWM modulation method of the three-level topology. The voltage vector is synthesized into a virtual vector. Each large sector contains 1 virtual zero vector, 2 virtual small vectors, 1 virtual medium vector and 2 virtual large vectors. Two virtual small vectors are each synthesized from a pair of adjacent small vectors in the basic vector, wherein the positive and negative vectors in the pair of small vectors each account for half and have the same duration of action; one virtual medium vector is synthesized from one medium vector in the basic vector and two different adjacent small vectors; two virtual large vectors are directly taken from the two large vectors in the basic vector; one virtual zero vector is directly taken from the zero vector in the basic vector. For a given target voltage vector, the sector in which it is located is determined first, using the same sector determination method as traditional SVPWM. Then, based on the sector determination result, a virtual vector is selected for synthesizing the target voltage vector. Finally, based on geometric relationships, the selected virtual vector is synthesized into the target synthesized voltage vector.

5. The simplified method for virtual space vector pulse width modulation of a T-type three-level inverter according to claim 4, characterized in that, The expression for the pre-calculated duty cycle of the switching transistor in step S4 is as follows: when When =1, ; when When =2, ; when When =3, ; when When =4, ; when When =5, ; when When =6, ; in, For sector determination results, These are the on-time duty cycles of the 1 and 2 switching transistors in phases A, B, and C of a T-type three-level inverter.

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