A low-power low-noise analog front-end circuit applied to a sensor and a signal processing method

Abstract

The application provides a low-power and low-noise analog front-end circuit applied to a sensor and a signal processing method, and belongs to the field of CMOS integrated circuit design.The circuit comprises a capacitive coupling chopping instrument amplifier, a fully differential switched capacitor low-pass filter and a successive approximation analog-to-digital converter.The capacitive coupling chopping instrument amplifier adopts a quadrature time sequence mismatch averaging technology to suppress passive device mismatch of an input and feedback network, and is used for amplifying a weak differential signal output by the sensor.The differential input end of the fully differential switched capacitor low-pass filter is connected with the differential output end of the capacitive coupling chopping instrument amplifier, and is used for filtering high-frequency noise in the amplified signal.The successive approximation analog-to-digital converter is used for converting the filtered analog signal into a digital signal output.The application has low power consumption and low noise, can accurately complete amplification, filtering and conversion of the weak signal output by the sensor, and guarantees high-precision monitoring performance of the sensor.

Description

Technical Field

[0001] This invention belongs to the field of CMOS integrated circuit design, specifically relating to a low-power, low-noise analog front-end circuit and signal processing method for use in sensors. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), portable electronic devices, and industrial automation technologies, sensors, as core components for information acquisition, play an indispensable role in numerous fields such as healthcare, environmental monitoring, smart wearables, industrial control, and aerospace. Analog front-end circuits, serving as a crucial bridge between sensors and back-end signal processing modules, are primarily responsible for amplifying, filtering, and conditioning the weak signals output by the sensors, directly determining the measurement accuracy, stability, and reliability of the entire sensing system. Among these, low-power, low-noise analog front-end circuits, with their core advantages of adapting to the battery life requirements of portable devices and ensuring accurate extraction of weak signals, have become one of the core technologies in modern sensing system design.

[0003] However, low-power, low-noise analog front-end circuits used in sensors face numerous severe challenges in practical design and application. On the one hand, sensor output signals typically have weak amplitudes and low signal-to-noise ratios, making them highly susceptible to external electromagnetic interference, power supply noise, and the circuit's own thermal noise. This necessitates excellent noise suppression capabilities from the analog front-end circuit. On the other hand, in portable, wearable, and wireless sensing node scenarios, devices often rely on battery power, imposing stringent limitations on the power consumption of the analog front-end circuit. How to reduce power consumption while maintaining low noise performance becomes a core challenge in circuit design. Especially in miniaturized sensing systems, traditional analog front-end circuits struggle to simultaneously meet the multiple requirements of low power consumption, low noise, and high integration due to limitations in chip area, power supply voltage, and heat dissipation.

[0004] Noise in the analog front-end circuit of a sensor mainly originates from amplifier input noise, resistor thermal noise, and switching noise of switched capacitor circuits. This noise can severely overwhelm the weak effective signal output by the sensor, leading to signal distortion and decreased measurement accuracy. Currently, existing analog front-end circuits typically employ low-noise operational amplifiers, precision resistors and capacitors, and complex filter topologies to suppress noise, while reducing circuit power consumption by using low-power transistors, dynamic biasing techniques, and power management modules. However, these design solutions often present irreconcilable contradictions: for example, increasing transistor size or bias current to reduce noise directly leads to increased power consumption; while using complex filter circuits can improve noise suppression, it increases chip area and design complexity, and may introduce additional signal delay and nonlinear distortion. In miniaturized sensing systems, due to high integration requirements and low supply voltage, traditional low-power design methods easily lead to decreased circuit gain stability, while noise suppression measures further exacerbate power consumption pressure, making it difficult to achieve a balanced performance optimization. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned technical problems and provide a low-power, low-noise analog front-end circuit and signal processing method for use in sensors.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A low-power, low-noise analog front-end circuit for sensors includes: a capacitively coupled chopper instrumentation amplifier, a fully differential switched-capacitor low-pass filter, and a successive approximation analog-to-digital converter.

[0008] The capacitively coupled chopper instrumentation amplifier employs orthogonal timing mismatch averaging technology to suppress passive component mismatch between the input and feedback networks, and is used to amplify the weak differential signal output by the sensor.

[0009] The differential input terminal of the fully differential switched capacitor low-pass filter is connected to the differential output terminal of the capacitively coupled chopper instrumentation amplifier, and is used to filter out high-frequency noise in the amplified signal.

[0010] The input terminal of the successive approximation analog-to-digital converter is connected to the differential output terminal of the fully differential switched-capacitor low-pass filter, and is used to convert the filtered analog signal into a digital signal output.

[0011] Furthermore, the capacitively coupled chopper instrumentation amplifier includes a fully symmetrical differential upper half circuit and a differential lower half circuit, wherein the upper half circuit includes:

[0012] The first chopper CH1 is connected between the differential negative input terminal VIN and the first node A;

[0013] The second chopper CH2 is connected between the first node A and the second node B;

[0014] The first capacitor C1 is connected between the second node B and the third node C;

[0015] The third chopper CH3 is connected between the third node C and the fourth node D;

[0016] The first bias resistor Rb is connected between the fourth node D and the common-mode level VCM;

[0017] The operational amplifier OPA has its non-inverting input connected to the fourth node D.

[0018] The fourth chopper CH4 is connected between the inverting output terminal E and the differential positive output terminal VOP of the operational amplifier;

[0019] The fifth chopper CH5 is connected between the first node A and the fifth node F;

[0020] The second capacitor C2 is connected between the fifth node F and the sixth node G;

[0021] The sixth chopper CH6 is connected between the sixth node G and the inverting output terminal E of the operational amplifier;

[0022] The seventh chopper CH7 is connected between the fourth node D and the seventh node H;

[0023] The third capacitor C3 is connected between the seventh node H and the eighth node I;

[0024] The eighth chopper CH8 is connected between the eighth node I and the inverting output terminal E of the operational amplifier.

[0025] The operational amplifier OPA also has an inverting input terminal and a non-inverting output terminal. The inverting input terminal is connected to the corresponding node of the differential lower half circuit, and the non-inverting output terminal is connected to the differential negative output terminal VON.

[0026] Furthermore, the orthogonal timing mismatch averaging technique performs the following operations sequentially in four orthogonal phases using the second chopper CH2, the third chopper CH3, the fifth chopper CH5, the sixth chopper CH6, the seventh chopper CH7, and the eighth chopper CH8:

[0027] In the first phase, the connections of the input network capacitor and the feedback network capacitor remain unchanged;

[0028] The second phase is the path for the switching feedback network capacitor;

[0029] The third phase switches the path of the input network capacitor.

[0030] The fourth phase simultaneously swaps the paths of the input network capacitor and the feedback network capacitor.

[0031] Furthermore, the first bias resistor Rb adopts a segmented duty cycle resistor structure, and achieves an equivalent ultra-high impedance through segmented cascading.

[0032] Furthermore, the fully differential switched-capacitor low-pass filter includes a completely symmetrical differential upper half circuit and a differential lower half circuit, wherein the upper half circuit includes:

[0033] The first switch S1 is connected between the differential negative input terminal VIN and the first node A;

[0034] The second switch S2 is connected between the first node A and the common-mode level VCM;

[0035] The first sampling capacitor C1 is connected between the first node A and the second node B;

[0036] The third switch S3 is connected between the second node B and the common-mode level VCM;

[0037] The fourth switch S4 is connected between the second node B and the third node C;

[0038] The second compensation capacitor C2 is connected between the second node B and the fourth node D;

[0039] The third integrating capacitor C3 is connected between the third node C and the fifth node E;

[0040] The fifth switch S5 is connected between the fourth node D and the common-mode level VCM;

[0041] The sixth switch S6 is connected between the fourth node D and the fifth node E;

[0042] An operational amplifier (OPA) has its non-inverting input connected to the third node C and its inverting output connected to the fifth node E.

[0043] The inverting input of the operational amplifier OPA is connected to the corresponding node of the differential lower half circuit, and its non-inverting output is connected to the differential negative output VON.

[0044] Furthermore, the successive approximation analog-to-digital converter includes a gate-voltage bootstrap sampling switch, a differential capacitor analog-to-digital converter, a comparator, and a successive approximation logic circuit. The gate-voltage bootstrap sampling switch is used for linear sampling of the differential input signal. The differential capacitor analog-to-digital converter is connected to the output terminal of the gate-voltage bootstrap sampling switch. The differential input terminal of the comparator is connected to the differential output terminal of the differential capacitor analog-to-digital converter. The input terminal of the successive approximation logic circuit is connected to the output terminal of the comparator, and its output terminal is the digital output terminal of the successive approximation analog-to-digital converter. The control terminal of the successive approximation logic circuit is connected to the control terminal of the differential capacitor analog-to-digital converter.

[0045] Furthermore, the differential capacitor-type digital-to-analog converter adopts Vcm-based capacitor switching timing; the comparator adopts a clock-controlled fully differential two-stage dynamic comparator structure.

[0046] The present invention may also include:

[0047] A method for processing weak sensor signals based on the above-mentioned analog front-end circuit includes the following steps:

[0048] The weak differential signal output by the sensor is input to a capacitively coupled chopper instrumentation amplifier. The passive component mismatch is suppressed by the orthogonal timing mismatch averaging technique, and the signal is amplified.

[0049] The amplified differential signal is input to a fully differential switched-capacitor low-pass filter to filter out high-frequency noise components.

[0050] The filtered analog signal is input to a successive approximation analog-to-digital converter and converted into a digital signal.

[0051] The digital signal is output as the final detection result.

[0052] Furthermore, the capacitor-coupled chopper instrumentation amplifier amplifies the signal by chopping modulation to modulate the offset voltage and flicker noise of the operational amplifier to the high-frequency region; through orthogonal timing mismatch averaging technology, the input network capacitor and feedback network capacitor are sequentially maintained, the feedback capacitor path is swapped, the input capacitor path is swapped, and the input and feedback capacitor paths are swapped in four orthogonal phases to dynamically average the capacitor mismatch.

[0053] Furthermore, the fully differential switched-capacitor low-pass filter filters out high-frequency noise components including:

[0054] During the sampling phase, the input signal charges the first sampling capacitor C1, the compensation capacitor is reset to the common-mode voltage, and the integrating capacitor keeps the output level stable.

[0055] During the integration phase, the first sampling capacitor C1 is reset to the common-mode voltage, and the charge stored on it is transferred to the integrating capacitor. The second compensation capacitor C2 provides charge compensation, and a new voltage level is established at the output.

[0056] The beneficial effects of this invention are as follows:

[0057] This invention realizes the amplification, conditioning and conversion technology of weak signals from sensors, with low input noise, low power consumption and high common-mode rejection ratio, and is suitable for sensor applications in complex environments.

[0058] This invention employs orthogonal timing mismatch averaging technology to effectively suppress passive device mismatch between the input and feedback networks, significantly improving the common-mode rejection ratio.

[0059] This invention modulates the offset voltage and flicker noise of the operational amplifier to the high-frequency region through chopper modulation, and then filters them out by combining the subsequent switched capacitor low-pass filter, thereby achieving lower input noise.

[0060] This invention uses a segmented duty cycle resistor structure to achieve ultra-high impedance bias, avoiding the use of large-size resistors and thus reducing chip area.

[0061] The successive approximation analog-to-digital converter of this invention employs gate voltage bootstrap sampling, Vcm-based capacitor switching timing, and a dynamic comparator, which effectively reduces overall power consumption while ensuring sampling linearity and conversion accuracy.

[0062] The overall circuit architecture of this invention achieves efficient noise suppression under strict power consumption control, breaking through the performance bottleneck of the difficulty in balancing low power consumption and low noise, and providing key technical support for high-precision, portable sensing systems. Attached Figure Description

[0063] Appendix Figure 1 The circuit structure block diagram of the invention;

[0064] Appendix Figure 2 Circuit diagram for the invention of a capacitor-coupled chopper instrumentation amplifier;

[0065] Appendix Figure 3 Circuit diagram for inventing a fully differential switched capacitor low-pass filter;

[0066] Appendix Figure 4 Circuit diagram for inventing a successive approximation analog-to-digital converter. Detailed Implementation

[0067] The present invention will now be further described with reference to the accompanying drawings.

[0068] This invention provides a low-power, low-noise analog front-end circuit for sensors, as shown in the attached figure. Figure 1As shown, it includes: a capacitor-coupled chopper instrumentation amplifier based on orthogonal timing mismatch averaging technology (OTMA-CCIA), a fully differential switched capacitor low-pass filter (SC-LPF), and a successive approximation analog-to-digital converter (SAR ADC).

[0069] The differential output of the capacitively coupled chopper instrumentation amplifier (OTMA-CCIA) is connected to the differential input of the SC-LPF; the differential output of the fully differential switched capacitor low-pass filter (SC-LPF) is connected to the differential input of the successive approximation analog-to-digital converter (SAR ADC); the digital output of the successive approximation analog-to-digital converter (SAR ADC) serves as the final output of the analog front-end circuit of this invention.

[0070] In the workflow, the weak differential signal input from the sensor is first amplified by a capacitively coupled chopper instrumentation amplifier (OTMA-CCIA) while suppressing common-mode interference and low-frequency noise. Then, a fully differential switched-capacitor low-pass filter (SC-LPF) performs low-pass filtering on the output signal of the capacitively coupled chopper instrumentation amplifier (OTMA-CCIA) to remove high-frequency switching noise and spike pulses introduced by chopper modulation. Finally, the analog signal output from the fully differential switched-capacitor low-pass filter (SC-LPF) is transmitted to a successive approximation analog-to-digital converter (SAR ADC) for conversion into a digital signal output.

[0071] Example 1:

[0072] As attached Figure 2 As shown, the capacitively coupled chopper instrumentation amplifier (OTMA-CCIA) includes:

[0073] The OTMA-CCIA has differential inputs VIN and VIP;

[0074] The OTMA-CCIA described above has a completely symmetrical structure. The connection method of the upper part of the OTMA-CCIA is described below.

[0075] There is a chopper CH1 between VIN and point A;

[0076] There is a chopper CH2 between points A and B;

[0077] There is a capacitor C1 between point B and point C;

[0078] There is a chopper CH3 between points C and D;

[0079] There is a bias resistor Rb between point D and the common-mode level (VCM);

[0080] Point D is connected to the non-inverting input terminal of the operational amplifier OPA;

[0081] Point E is connected to the inverting output terminal of the operational amplifier OPA;

[0082] There is a chopper CH4 between point E and the inverting output terminal VOP of OTMA-CCIA;

[0083] There is a chopper CH5 between points A and F;

[0084] There is a capacitor C2 between point F and point G;

[0085] There is a chopper CH6 between points G and E;

[0086] There is a chopper CH7 between point D and point H;

[0087] There is a capacitor C3 between point H and point I;

[0088] There is a chopper CH8 between point I and point E;

[0089] The connection method for the lower half of OTMA-CCIA is the same as that for the upper half of OTMA-CCIA.

[0090] The operational amplifier OPA also has an inverting input terminal and a non-inverting output terminal. Its inverting input terminal is connected to the corresponding node of the differential lower half circuit, and its non-inverting output terminal is connected to the differential negative output terminal VON.

[0091] Specifically, the OTMA-CCIA architecture employs two sets of synchronous clock choppers, CH1 and CH4, both driven by bi-phase non-overlapping clocks of the same frequency, to jointly perform chopping modulation and demodulation of the input signal. Through chopping modulation, the differential-mode component formed by the input common-mode interference can be shifted to near the chopping frequency, enabling the system to achieve high common-mode rejection within the baseband signal bandwidth. At the same time, the offset voltage and flicker noise of the operational amplifier are also modulated to the high-frequency band, thereby achieving low input noise system performance.

[0092] Since the chopper and the input coupling capacitor C1 together form an equivalent switched capacitor structure, the OTMA-CCIA input stage will exhibit a significant impedance change. Therefore, this design introduces a positive feedback loop to effectively improve the system's equivalent input impedance by constructing a controllable current enhancement mechanism in the signal path.

[0093] To further suppress passive component mismatch and improve overall common-mode rejection capability, the circuit employs quadrature timing mismatch averaging technology. Choppers CH2, CH3, CH5, CH6, CH7, and CH8 sequentially perform four operations within four quadrature phases: hold, swap feedback network capacitors, swap input network capacitors, and simultaneously swap input and feedback network capacitors. This dynamically averages the capacitor mismatch between the input and feedback networks, significantly reducing common-mode to differential-mode conversion caused by mismatch and further improving the system's common-mode rejection ratio.

[0094] Furthermore, OTMA-CCIA uses a capacitively coupled input method, which inherently exhibits high-pass filtering characteristics, requiring extremely high-resistance bias resistors in its branches. This necessitates implementation within a small chip area. To achieve ultra-high equivalent impedance, this design employs a segmented duty cycle resistor (S-DCR) structure. This technique effectively amplifies the base resistance by adjusting the duty cycle of the switching signal. Due to the limitation of the amplification capability of a single-stage duty cycle resistor, this design achieves the target high impedance characteristic through segmented cascading.

[0095] Example 2:

[0096] As attached Figure 3 As shown, the fully differential switched-capacitor low-pass filter (SC-LPF) includes:

[0097] The SC-LPF has differential inputs VIN and VIP;

[0098] The SC-LPF described above has a completely symmetrical structure. The connection method of the upper part of the SC-LPF is now described.

[0099] There is a switch S1 between VIN and point A;

[0100] There is a switch S2 between point A and VCM;

[0101] There is a capacitor C1 between points A and B;

[0102] There is a switch S3 between point B and VCM;

[0103] There is a switch S4 between point B and point C;

[0104] There is a capacitor C2 between points B and D;

[0105] There is a capacitor C3 between point C and point E;

[0106] There is a switch S5 between point D and VCM;

[0107] There is a switch S6 between points D and E;

[0108] Point C is connected to the non-inverting input of the operational amplifier OPA;

[0109] Point E is connected to the inverting output terminal of operational amplifier OPA;

[0110] The connection method for the lower half of the SC-LPF is the same as that for the upper half of the SC-LPF.

[0111] The operational amplifier OPA also has an inverting input terminal and a non-inverting output terminal. Its inverting input terminal is connected to the corresponding node of the differential lower half circuit, and its non-inverting output terminal is connected to the differential negative output terminal VON.

[0112] Specifically, because OTMA-CCIA employs chopper modulation technology, it modulates offset voltage and flicker noise into the high-frequency region, introducing spikes and glitches at the output caused by the chopper switch. To ensure the processing accuracy of subsequent circuits, it is necessary to design a low-pass filter to filter out these high-frequency interference components. The fully differential SC-LPF of this invention can simultaneously meet the signal processing requirements of large dynamic range and high linearity. Furthermore, it features low power consumption.

[0113] Example 3:

[0114] As attached Figure 4 As shown, the successive approximation analog-to-digital converter (SAR ADC) includes a gate-voltage bootstrap sampling switch, a differential capacitor analog-to-digital converter (CDAC), a comparator, and SAR logic circuitry.

[0115] VIN and VIP are the inputs to the SAR ADC;

[0116] The VIN and VIP are respectively connected to the differential inputs of the Bootstrapped Switch;

[0117] The differential output of the bootstrapped switch is connected to the differential input of the CDAC;

[0118] The differential output of the CDAC is connected to the differential input of the Comparator;

[0119] The differential output of the Comparator is connected to the differential input of the SAR Logic;

[0120] The output of the SAR Logic is the digital output of the SAR ADC;

[0121] In traditional sample-and-hold circuits, the on-resistance of the switching MOSFET is affected by the gate-source voltage, which in turn varies with the input signal, leading to a decrease in circuit linearity. To improve performance, this invention introduces gate voltage bootstrapping technology, which effectively suppresses changes in on-resistance by fixing the gate-source voltage during the switching transistor's conduction period, thereby significantly improving sampling linearity.

[0122] Compared to other DAC architectures, the CDAC structure used in this invention employs a charge redistribution mechanism, which not only eliminates static current loss but also offers the advantages of high-speed response and high precision. Furthermore, the Vcm-based capacitor switching timing used in this invention exhibits lower dynamic power consumption compared to other traditional switching timings.

[0123] The Comparator of this invention employs a two-stage dynamic comparator with a fully differential structure. This comparator uses a clock-controlled dual-phase operating mechanism to achieve signal comparison. Through precise timing control and a positive feedback structure, it achieves fast response characteristics while ensuring comparison accuracy. Furthermore, the comparator uses a clock-controlled signal to control its operating time, effectively reducing quiescent current consumption and resulting in low overall power consumption.

[0124] SAR Logic implements a binary search algorithm. By judging the output of the comparator, it sequentially determines the output of each bit of the digital code from the high bit to the low bit, while controlling the voltage selection of the lower stage board of the CDAC capacitor, thereby realizing the successive approximation process and finally outputting the converted complete digital code.

[0125] The objective of this embodiment is achieved as follows: This embodiment consists of a capacitor-coupled chopper instrumentation amplifier (OTMA-CCIA) based on orthogonal timing mismatch averaging technology, a fully differential switched-capacitor low-pass filter (SC-LPF), and a successive approximation analog-to-digital converter (SAR ADC). In terms of workflow, the weak input signal is first initially amplified by the OTMA-CCIA. Then, the SC-LPF filters the output signal of the OTMA-CCIA to remove high-frequency noise. Finally, the signal output from the SC-LPF is transmitted to the SAR ADC to convert the analog signal into a digital signal.

[0126] Specifically, the OTMA-CCIA of this invention employs quadrature timing mismatch averaging technology to improve the overall common-mode rejection ratio (CMRR) of the circuit by suppressing passive component mismatches in the input and feedback networks. The quadrature timing averaging technology utilizes four different quadrature phases, which can be divided into four stages: First stage, keeping the capacitance of the input and feedback networks constant; second stage, swapping the capacitor path of the feedback network; third stage, swapping the capacitor path of the input network; fourth stage, simultaneously swapping the capacitor paths of both the input and feedback networks. Through these four operations, dynamic averaging of the capacitance mismatch between the input and feedback networks is achieved, thereby suppressing common-mode to differential-mode switching caused by mismatch and ultimately improving the overall CMRR of the circuit.

[0127] In this embodiment, the relationship between the capacitance values ​​is as follows:

[0128] , (1)

[0129] The OTMA-CCIA transfer function is:

[0130] (2)

[0131] To reduce low-frequency noise and interference in the operational amplifier, the OTMA-CCIA designed in this invention employs chopper modulation technology, which modulates the operational amplifier's offset voltage and flicker noise to the high-frequency region to reduce overall input noise.

[0132] OTMA-CCIA employs chopper modulation technology, which inevitably introduces some high-frequency switching noise and interference signals into the output signal. To accurately detect the voltage signal, it is necessary to add an LPF after OTMA-CCIA to filter out high-frequency noise and provide appropriate amplification. SC-LPF can simultaneously meet the signal processing requirements of large dynamic range and high linearity.

[0133] The SC-LPF uses a two-phase non-overlapping clock signal to control the charge transfer process. Its single-ended equivalent circuit working principle can be divided into two complementary stages: during the sampling phase, the input signal charges the sampling capacitor C1, stores the charge, the compensation capacitor C2 is reset to the common-mode voltage VCM, and the integrating capacitor C3 keeps the output level stable; while during the integration phase, capacitor C1 is reset to the common-mode voltage VCM, the charge stored on it is transferred to the integrating capacitor C3, the compensation capacitor network provides accurate charge compensation, and a new voltage level is established at the output.

[0134] In this embodiment, the relationship between the capacitance values ​​is as follows:

[0135] , (3)

[0136] The transfer function of the SC-LPF in this invention can be expressed as:

[0137] (4)

[0138] in, This is the two-phase non-overlapping clock control signal for the SC-LPF. In this design, the passband gain of the SC-LPF is 12dB.

[0139] The signal output from the SC-LPF is transmitted to the ADC, converting the analog signal into a digital signal. The ADC provided by this invention is a fully differential SAR ADC. Gate voltage bootstrapping technology is used in the sample-and-hold circuit to fix the gate-source voltage during the conduction period of the switching transistor, effectively suppressing changes in its on-resistance and thus improving linearity. The DAC employs a CDAC structure and Vcm-based capacitor switching timing, eliminating static current loss while also offering the advantages of high-speed response and high accuracy, and reducing dynamic power consumption. The comparator uses a two-stage dynamic comparator structure, effectively reducing the overall circuit power consumption by introducing a clock control signal. The SAR Logic designed in this invention uses a structure combining shift registers and storage registers, which can be roughly divided into two working stages: the first stage is the signal acquisition stage, resetting the outputs of all D flip-flops to low level; the second stage is the data conversion stage, latching the comparison result of the comparator into the storage register.

[0140] Example 4:

[0141] Based on the above circuit, this embodiment provides a method for detecting weak signals from a sensor, including:

[0142] Step S1: Input the weak differential signal output by the sensor to the capacitively coupled chopper instrumentation amplifier. The passive component mismatch is suppressed by the quadrature timing mismatch averaging technique. At the same time, the offset voltage and flicker noise of the operational amplifier are modulated to the high-frequency region by chopper modulation to amplify the signal.

[0143] Step S2: The amplified differential signal is input to a fully differential switched capacitor low-pass filter, and high-frequency noise components are filtered out through a charge transfer process controlled by two-phase non-overlapping clocks.

[0144] Step S3: Input the filtered analog signal into a successive approximation analog-to-digital converter, and convert it into a digital signal through gate voltage bootstrap sampling, Vcm-based capacitor switching timing and dynamic comparison;

[0145] Step S4: Output the digital signal as the final detection result.

[0146] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-power, low-noise analog front-end circuit for use in sensors, characterized in that, include: Capacitively coupled chopper instrumentation amplifier, fully differential switched capacitor low-pass filter, successive approximation analog-to-digital converter; The capacitively coupled chopper instrumentation amplifier employs orthogonal timing mismatch averaging technology to suppress passive component mismatch between the input and feedback networks, and is used to amplify the weak differential signal output by the sensor. The differential input terminal of the fully differential switched capacitor low-pass filter is connected to the differential output terminal of the capacitively coupled chopper instrumentation amplifier, and is used to filter out high-frequency noise in the amplified signal. The input terminal of the successive approximation analog-to-digital converter is connected to the differential output terminal of the fully differential switched-capacitor low-pass filter, and is used to convert the filtered analog signal into a digital signal output.

2. The low-power, low-noise analog front-end circuit for sensors according to claim 1, characterized in that, The capacitively coupled chopper instrumentation amplifier includes a completely symmetrical differential upper half circuit and a differential lower half circuit. The upper half circuit includes: The first chopper CH1 is connected between the differential negative input terminal VIN and the first node A; The second chopper CH2 is connected between the first node A and the second node B; The first capacitor C1 is connected between the second node B and the third node C; The third chopper CH3 is connected between the third node C and the fourth node D; The first bias resistor Rb is connected between the fourth node D and the common-mode level VCM; The operational amplifier OPA has its non-inverting input connected to the fourth node D. The fourth chopper CH4 is connected between the inverting output terminal E and the differential positive output terminal VOP of the operational amplifier; The fifth chopper CH5 is connected between the first node A and the fifth node F; The second capacitor C2 is connected between the fifth node F and the sixth node G; The sixth chopper CH6 is connected between the sixth node G and the inverting output terminal E of the operational amplifier; The seventh chopper CH7 is connected between the fourth node D and the seventh node H; The third capacitor C3 is connected between the seventh node H and the eighth node I; The eighth chopper CH8 is connected between the eighth node I and the inverting output terminal E of the operational amplifier. The operational amplifier OPA also has an inverting input terminal and a non-inverting output terminal. The inverting input terminal is connected to the corresponding node of the differential lower half circuit, and the non-inverting output terminal is connected to the differential negative output terminal VON.

3. The low-power, low-noise analog front-end circuit for sensors according to claim 2, characterized in that, The orthogonal timing mismatch averaging technique operates sequentially in four orthogonal phases using the second chopper CH2, the third chopper CH3, the fifth chopper CH5, the sixth chopper CH6, the seventh chopper CH7, and the eighth chopper CH8: In the first phase, the connections of the input network capacitor and the feedback network capacitor remain unchanged; The second phase is the path for the switching feedback network capacitor; The third phase switches the path of the input network capacitor. The fourth phase simultaneously swaps the paths of the input network capacitor and the feedback network capacitor.

4. The low-power, low-noise analog front-end circuit for sensors according to claim 2, characterized in that, The first bias resistor Rb adopts a segmented duty cycle resistor structure, and achieves equivalent ultra-high impedance through segmented cascading.

5. The low-power, low-noise analog front-end circuit for sensors according to claim 1, characterized in that, The fully differential switched-capacitor low-pass filter includes a completely symmetrical differential upper half circuit and a differential lower half circuit. The upper half circuit includes: The first switch S1 is connected between the differential negative input terminal VIN and the first node A; The second switch S2 is connected between the first node A and the common-mode level VCM; The first sampling capacitor C1 is connected between the first node A and the second node B; The third switch S3 is connected between the second node B and the common-mode level VCM; The fourth switch S4 is connected between the second node B and the third node C; The second compensation capacitor C2 is connected between the second node B and the fourth node D; The third integrating capacitor C3 is connected between the third node C and the fifth node E; The fifth switch S5 is connected between the fourth node D and the common-mode level VCM; The sixth switch S6 is connected between the fourth node D and the fifth node E; An operational amplifier (OPA) has its non-inverting input connected to the third node C and its inverting output connected to the fifth node E. The inverting input of the operational amplifier OPA is connected to the corresponding node of the differential lower half circuit, and its non-inverting output is connected to the differential negative output VON.

6. The low-power, low-noise analog front-end circuit for sensors according to claim 1, characterized in that, The successive approximation analog-to-digital converter (ADC) includes a gate-voltage bootstrap sampling switch, a differential capacitor analog-to-digital converter (ADC), a comparator, and a successive approximation logic circuit. The gate-voltage bootstrap sampling switch is used for linear sampling of the differential input signal. The differential capacitor ADC is connected to the output terminal of the gate-voltage bootstrap sampling switch. The differential input terminal of the comparator is connected to the differential output terminal of the differential capacitor ADC. The input terminal of the successive approximation logic circuit is connected to the output terminal of the comparator, and its output terminal is the digital output terminal of the successive approximation ADC. The control terminal of the successive approximation logic circuit is connected to the control terminal of the differential capacitor ADC.

7. The low-power, low-noise analog front-end circuit for sensors according to claim 6, characterized in that, The differential capacitor-type digital-to-analog converter adopts Vcm-based capacitor switching timing; the comparator adopts a clock-controlled fully differential two-stage dynamic comparator structure.

8. A method for processing weak sensor signals based on the analog front-end circuit according to any one of claims 1 to 7, characterized in that, Includes the following steps: The weak differential signal output by the sensor is input to a capacitively coupled chopper instrumentation amplifier. The passive component mismatch is suppressed by the orthogonal timing mismatch averaging technique, and the signal is amplified. The amplified differential signal is input to a fully differential switched-capacitor low-pass filter to filter out high-frequency noise components. The filtered analog signal is input to a successive approximation analog-to-digital converter and converted into a digital signal. The digital signal is output as the final detection result.

9. The sensor weak signal processing method of the analog front-end circuit according to claim 8, characterized in that, The capacitor-coupled chopper instrumentation amplifier amplifies the signal by chopping modulation to modulate the offset voltage and flicker noise of the operational amplifier to the high-frequency region; through orthogonal timing mismatch averaging technology, the input network capacitor and feedback network capacitor are held, the feedback capacitor path is swapped, the input capacitor path is swapped, and the input and feedback capacitor paths are swapped in four orthogonal phases to dynamically average the capacitor mismatch.

10. The sensor weak signal processing method of the analog front-end circuit according to claim 8, characterized in that, The fully differential switched-capacitor low-pass filter filters out high-frequency noise components including: During the sampling phase, the input signal charges the first sampling capacitor C1, the compensation capacitor is reset to the common-mode voltage, and the integrating capacitor keeps the output level stable. During the integration phase, the first sampling capacitor C1 is reset to the common-mode voltage, and the charge stored on it is transferred to the integrating capacitor. The second compensation capacitor C2 provides charge compensation, and a new voltage level is established at the output.

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