A pulse insertion circuit and method for reducing clipping distortion of a power amplifier

Abstract

The present application relates to the technical fields of power amplifier, and discloses a pulse insertion circuit and method for reducing the clipping distortion of a power amplifier, the pulse insertion circuit comprising: a clock unit, a positive pulse insertion control module and a negative pulse insertion control module; the clock unit is used to provide a clock signal; the positive pulse insertion control module is used to insert a positive pulse when detecting that the P terminal or N terminal of the power amplifier is clipped from the bottom under the triggering of the clock signal, and to control the ending time of the positive pulse according to the output state feedback of the P terminal or N terminal, so that the width of the positive pulse is adaptively adjusted; the negative pulse insertion control module is used to insert a negative pulse when detecting that the P terminal or N terminal of the power amplifier is clipped from the top under the triggering of the clock signal, and to control the ending time of the negative pulse according to the output state feedback of the P terminal or N terminal, so that the width of the negative pulse is adaptively adjusted.The present application can improve the problem that the output duty cycle changes greatly with the power supply voltage and process angle, and improve the output effective power and dynamic range.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and in particular to a pulse insertion circuit and method for reducing power amplifier truncation distortion. Background Technology

[0002] In Class D power amplifiers, the output waveform may be truncated due to excessive input signal amplitude or insufficient power supply caused by battery discharge, resulting in hard clipping. This introduces a large number of harmonic components, causing a sharp increase in total harmonic distortion plus noise (THD+N), which seriously affects audio quality.

[0003] To address the aforementioned issues, a common industry practice is to employ a fixed-width pulse insertion scheme. By inserting pulses of a fixed width, the conduction time of the power transistor is forcibly shortened, reducing the peak value of the output inductor current. This limits the output signal to a safe range and avoids harsh distortion caused by hard clipping.

[0004] However, the above fixed-width pulse insertion scheme has the following drawbacks: the switching impedance of the delay chain implemented with inverters is strongly correlated with the power supply voltage. When the power supply voltage changes, the delay will change by a factor of several, which is particularly prominent in low-voltage applications; when the output stage power transistor is a high-voltage device, the duty cycle of the output terminal is related to the process corner of both the high-voltage and low-voltage transistors, resulting in poor consistency of the insertion pulse width under different process corners; in addition, the fixed-width pulse insertion scheme needs to take into account the extreme operating conditions of process corner and power supply voltage, and the insertion pulse width is usually more than 100 nanoseconds. Under most normal operating conditions, the insertion width is too long, resulting in a significant decrease in the maximum output power and dynamic range. Furthermore, corresponding adjustments are required for different electromagnetic interference (EMI) configurations, which increases the complexity of circuit design and chip area overhead.

[0005] Therefore, there is an urgent need to propose a pulse insertion circuit and method to reduce the truncated distortion of power amplifiers in order to solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to propose a pulse insertion circuit and method for reducing power amplifier cutoff distortion, which can improve the problem of large variations in output duty cycle with power supply voltage and process angle, and improve output effective power and dynamic range.

[0007] To solve the above-mentioned technical problems, the present invention provides a pulse insertion circuit for reducing power amplifier clipping distortion, comprising: a clock unit, a positive pulse insertion control module, and a negative pulse insertion control module; The clock unit is used to provide clock signals; The positive pulse insertion control module is used to insert a positive pulse when the P or N terminal of the power amplifier is detected to be cut off under the trigger of the clock signal, and to control the end time of the positive pulse according to the output status feedback of the P or N terminal, so that the width of the positive pulse is adaptively adjusted. The negative pulse insertion control module is used to insert a negative pulse when the clock signal triggers and the P or N terminal of the power amplifier is detected to be truncated, and to control the end time of the negative pulse according to the output status feedback of the P or N terminal, so that the width of the negative pulse is adaptively adjusted.

[0008] Furthermore, the forward pulse insertion control module includes a first NAND gate, a second NAND gate, a third NAND gate, a first MOS transistor delay network unit, and a first buffer; The first input terminal of the first NAND gate receives the first high-level indication signal output from the P terminal, and the second input terminal of the first NAND gate receives the second high-level indication signal output from the N terminal. One input of the second NAND gate is connected to the output of the first NAND gate, and the other input of the second NAND gate is connected to the output of the third NAND gate; one input of the third NAND gate is used to receive a clock signal, and the other input of the third NAND gate is connected to the output of the second NAND gate; the output of the second NAND gate outputs a positive pulse latch signal. One end of the first MOS transistor delay network unit is used to receive the positive pulse latch signal, and the other end of the first MOS transistor delay network unit is connected to the input terminal of the first buffer. The output terminal of the first buffer outputs a third high-level indication signal.

[0009] Furthermore, the first MOS transistor delay network unit includes a first PMOS transistor group, a first NMOS transistor group, a first MOS capacitor, and a second MOS capacitor; The first PMOS transistor group includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor connected in series, with the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor connected together. The first NMOS transistor group includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series. The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor, as well as the sources and drains of the first MOS capacitor and the second MOS capacitor, are all grounded. The gates of the first PMOS transistor and the first NMOS transistor are both connected to the output of the second NAND gate. The drains of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor are connected. The drains of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor, the gate of the third NMOS transistor, and the gate of the first MOS capacitor are connected. The drains of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor are connected. The drains of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the gate of the second MOS capacitor, and the input of the first buffer are connected.

[0010] Furthermore, the negative pulse insertion control module includes a first NOR gate, a second NOR gate, a third NOR gate, a second MOS transistor delay network unit, and a second buffer; The first input terminal of the third NOR gate receives the first low-level indication signal output from the P terminal, and the second input terminal of the third NOR gate receives the second low-level indication signal output from the N terminal; One input terminal of the second NOR gate is connected to the output terminal of the third NOR gate, and the other input terminal of the second NOR gate is connected to the output terminal of the first NOR gate; one input terminal of the first NOR gate is used to receive the clock signal after being inverted by the NOT gate, and the other input terminal of the first NOR gate is connected to the output terminal of the second NOR gate; the output terminal of the second NOR gate outputs a negative pulse latch signal. One end of the second MOS transistor delay network unit is used to receive the negative pulse latch signal, and the other end of the second MOS transistor delay network unit is connected to the input terminal of the second buffer. The output terminal of the second buffer outputs a third low-level indication signal.

[0011] Furthermore, the second MOS transistor delay network unit includes a second PMOS transistor group, a second NMOS transistor group, a third MOS capacitor, and a fourth MOS capacitor; The second PMOS transistor group includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor connected in series, with the sources of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor connected together. The second NMOS transistor group includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor connected in series. The sources of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor, as well as the sources and drains of the third MOS capacitor and the fourth MOS capacitor, are all grounded. The gates of the fifth PMOS transistor and the fifth NMOS transistor are both connected to the output of the second NOR gate. The drains of the fifth PMOS transistor, the fifth NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the sixth NMOS transistor are connected. The drains of the sixth PMOS transistor, the sixth NMOS transistor, the gate of the seventh PMOS transistor, the gate of the seventh NMOS transistor, and the gate of the third MOS capacitor are connected. The drains of the seventh PMOS transistor, the seventh NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are connected. The drains of the eighth PMOS transistor, the eighth NMOS transistor, the gate of the fourth MOS capacitor, and the input of the second buffer are connected.

[0012] Furthermore, it also includes a logic module; the logic module is used to perform logical operations on the positive pulse signal output by the positive pulse insertion control module and the negative pulse signal output by the negative pulse insertion control module with the original PWM signal, respectively, and output the power amplifier drive signal.

[0013] Furthermore, the logic module includes NOT gates, delays, fourth NOR gates, fourth NAND gates, first OR gates, second OR gates, first AND gates, and second AND gates; The input terminal of the NOT gate is used to receive a clock signal, and the output terminal of the NOT gate is connected to the negative pulse insertion control module to provide an inverted clock signal to the negative pulse insertion control module; the output terminal of the NOT gate is connected to the delay unit, the first input terminal of the fourth NOR gate, and the input terminal of the fourth NAND gate; The output of the delay unit is connected to the second input of the fourth NOR gate and the input of the fourth NAND gate; the delay unit is used to set the upper limit of the width of the inserted pulse. The third input of the fourth NOR gate is connected to the positive pulse insertion control module and is used to receive the third high-level indication signal output by the positive pulse insertion control module. The fourth input of the fourth NOR gate receives the mode enable signal. The output of the fourth NOR gate outputs a positive insertion pulse signal to one of the inputs of the first OR gate and one of the inputs of the second OR gate. The input terminal of the fourth NAND gate is connected to the negative pulse insertion control module, and is used to receive the third low-level indication signal output by the negative pulse insertion control module. The output terminal of the fourth NAND gate outputs a negative insertion pulse signal to one of the input terminals of the first AND gate and one of the input terminals of the second AND gate. The other input of the first OR gate receives the P-terminal PWM signal PWMP, and the output of the first OR gate is connected to the other input of the first AND gate. The other input of the second OR gate receives the N-terminal PWM signal PWMN, and the output of the second OR gate is connected to the other input of the second AND gate; The output terminals of the first AND gate and the second AND gate respectively output the P-terminal drive signal PWMOP and the N-terminal drive signal PWMON.

[0014] Furthermore, this invention also proposes a pulse insertion method for reducing power amplifier clipping distortion, using the pulse insertion circuit for reducing power amplifier clipping distortion as described above, comprising the following: Detect the level status at the power amplifier output terminal and generate an output status feedback signal; When the clock signal is triggered and a top or bottom cutoff distortion is detected at the power amplifier output, a pulse is inserted into the corresponding output. The end time of the inserted pulse is controlled according to the output status feedback signal, so that the pulse width is adaptively adjusted according to the actual output flip state.

[0015] Furthermore, the detection of the power amplifier output level specifically includes: The system acquires the first high-level indicator signal output from the P terminal and the second high-level indicator signal output from the N terminal. When the first high-level indicator signal is low and the second high-level indicator signal is high, or when the first high-level indicator signal is high and the second high-level indicator signal is low, it determines that the P terminal or the N terminal has truncation and generates the output status feedback signal of the P terminal or the N terminal. The system acquires the first low-level indicator signal output from the P terminal and the second low-level indicator signal output from the N terminal. When the first low-level indicator signal is low and the second low-level indicator signal is high, or when the first low-level indicator signal is high and the second low-level indicator signal is low, it determines that the P terminal or the N terminal has been truncated and generates the output status feedback signal of the P terminal or the N terminal.

[0016] Furthermore, when the clock signal triggers and a top-down or bottom-out distortion is detected in the power amplifier output, a pulse is inserted into the corresponding output terminal, and the end time of the inserted pulse is controlled according to the output status feedback signal, specifically including: A positive pulse is inserted into the PWM signal corresponding to the P terminal and the N terminal at the rising edge of the clock signal, and a negative pulse is inserted into the PWM signal corresponding to the P terminal and the N terminal at the falling edge of the clock signal. The positive pulse is terminated after a delay when the actual output level of the truncated end flips; the negative pulse is terminated after a delay when the actual output level of the truncated end flips. Within each clock cycle, the positive pulse insertion control and the negative pulse insertion control are reset by the corresponding level of the clock signal, so that the pulse insertion actions in each clock cycle are independent of each other. When the power amplifier is operating in 1SPW mode, positive pulse insertion is disabled, and only negative pulse insertion is allowed.

[0017] Through the above technical solution, the present invention has the following beneficial effects: By using output state feedback to control the pulse end time, the insertion pulse width can be adaptively adjusted according to the actual output flip state. This reduces the impact of power supply voltage fluctuations and process angle deviations on the pulse width and improves the consistency of pulse width under different operating conditions. At the same time, the pulse width does not need to be conservatively set according to extreme operating conditions, which can effectively narrow the insertion pulse width, thereby improving the output effective power and maximum dynamic range. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the pulse width limiting circuit for a traditional Class D power amplifier. Figure 2 The LPI output waveform diagram of a traditional Class D power amplifier's pulse width limiting circuit; Figure 3 This is a schematic diagram of a pulse insertion circuit for reducing power amplifier truncation distortion in one embodiment of the present invention; Figure 4 This is a flowchart of a pulse insertion method for reducing power amplifier truncation distortion in one embodiment of the present invention; Figure 5 This is an LPI output waveform diagram of a pulse insertion method for reducing power amplifier truncation distortion in one embodiment of the present invention; Figure 6 for Figure 5 Enlarged view of the waveform structure at point A; Figure 7 for Figure 5 Enlarged view of the waveform structure at point B. Detailed Implementation

[0019] Based on the teachings of this specification, those skilled in the art can form new technical solutions through cross-combination of different implementation methods without creating technical contradictions. Such variations should all be considered to fall within the protection scope of this invention.

[0020] The following description, in conjunction with the accompanying drawings, provides a more detailed account of a pulse insertion circuit and method for reducing power amplifier clipping distortion, wherein preferred embodiments of the invention are shown. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0021] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0022] First, combine Figure 1 The working principle of the traditional pulse insertion scheme is explained. For example... Figure 1 As shown, a traditional pulse insertion circuit includes a PWM (Pulse-Width Modulation) comparator, a CLK clock signal input, fixed-width pulse insertion units LPI_PP (Low Pulse Width Inject_Positive Pulse) and LPI_NP, as well as several logic gates. After logic operations, it outputs the P-terminal drive signal PWMOP and the N-terminal drive signal PWMON, respectively.

[0023] Combination Figure 2 In the traditional pulse insertion scheme, the rising edge of the clock signal CLK corresponds to the trough of the internal triangular wave Vtri of the power amplifier. When the power amplifier output does not truncate, the PWM comparator output will always be high. Inserting a fixed-width pulse LPI_PP at this time, after a logical OR operation, does not affect the output square wave. If the power amplifier's P-terminal experiences truncation, the P-terminal drive signal PWMOP will insert an upward pulse on the rising edge of the clock. Similarly, if the N-terminal experiences truncation, the N-terminal drive signal PWMON will insert a downward pulse on the falling edge of the clock. This results in a positive pulse being inserted at the P-terminal output on the rising edge and a negative pulse at the N-terminal output on the falling edge, achieving soft truncation. This action occurs once per clock cycle.

[0024] However, in the aforementioned traditional scheme, the delay of the fixed-width pulse insertion unit is determined by the delay chain implemented by the inverter. Its switching impedance is strongly correlated with the power supply voltage, and the delay changes exponentially when the power supply voltage changes, especially in low-voltage applications. When the power transistor is a high-voltage transistor, the duty cycle at the output terminal is related to the process angle of both the high-voltage and low-voltage transistors. The fixed-width pulse insertion scheme needs to consider extreme cases under different process angles and power supply voltages. The insertion pulse width is typically over 100 nanoseconds. In most process angles, an excessively long insertion width leads to a significant decrease in maximum output power, and adjustments are required for different EMI configurations, increasing the complexity of the circuit design.

[0025] To address the shortcomings of the aforementioned traditional solutions, such as Figure 3As shown, this embodiment of the invention proposes a pulse insertion circuit for reducing power amplifier clipping distortion, applied in a Class D power amplifier, to improve the distortion problem during output clipping. The pulse insertion circuit comprises a clock unit, a positive pulse insertion control module, and a negative pulse insertion control module.

[0026] Specifically, the clock unit provides a clock signal CLK as the timing reference for the entire pulse insertion circuit; the positive pulse insertion control module inserts a positive pulse when the P or N terminal of the power amplifier is detected to be at its bottom when triggered by the clock signal CLK, and controls the end time of the positive pulse based on the output status feedback of the P or N terminal, so that the width of the positive pulse is adaptively adjusted; the negative pulse insertion control module is configured in pairs with the positive pulse insertion control module, and inserts a negative pulse when the P or N terminal of the power amplifier is detected to be at its top when triggered by the clock signal CLK, and controls the end time of the negative pulse based on the output status feedback of the P or N terminal, so that the width of the negative pulse is adaptively adjusted.

[0027] In one embodiment, the positive pulse insertion control module includes a first NAND gate I0, a second NAND gate I1, a third NAND gate I2, a first MOS transistor delay network unit, and a first buffer I6.

[0028] Specifically, the first input terminal of the first NAND gate I0 receives the first high-level indication signal OUTP_HIGH output from the P terminal, and the second input terminal of the first NAND gate I0 receives the second high-level indication signal OUTN_HIGH output from the N terminal. Furthermore, the second NAND gate I1 and the third NAND gate I2 are cross-coupled to form a first RS latch. Specifically, one input terminal of the second NAND gate I1 is connected to the output terminal of the first NAND gate I0, and the other input terminal of the second NAND gate I1 is connected to the output terminal of the third NAND gate I2. One input terminal of the third NAND gate I2 is used to receive the clock signal CLK, and the other input terminal of the third NAND gate I2 is connected to the output terminal of the second NAND gate I1. The output terminal of the second NAND gate I1 outputs a positive pulse latch signal Q_PP. The first RS latch is reset when the clock signal CLK is low, and the output terminal of the first RS latch outputs a positive pulse latch signal Q_PP. One end of the first MOS transistor delay network unit is used to receive the positive pulse latch signal Q_PP, and the other end of the first MOS transistor delay network unit is connected to the input terminal of the first buffer I6. The output terminal of the first buffer I6 outputs a third high-level indicator signal OUT_HIGH.

[0029] Preferably, the first MOS delay network unit includes a first PMOS transistor group, a first NMOS transistor group, a first MOS capacitor MN8, and a second MOS capacitor MN9.

[0030] Specifically, the first PMOS transistor group includes a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, and a fourth PMOS transistor MP3 connected in series, with the sources of the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 connected together. The first NMOS transistor group includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, and a fourth NMOS transistor MN3 connected in series, with the sources of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3, as well as the sources and drains of the first MOS capacitor MN8 and the second MOS capacitor MN9, all grounded. The gates of the first PMOS transistor MP0 and the first NMOS transistor MN0 are both connected to the output of the second NAND gate I1. The drains of the first PMOS transistor MP0, the drain of the first NMOS transistor MN0, the gate of the second PMOS transistor MP1, and the gate of the second NMOS transistor MN1 are connected. The drains of the second PMOS transistor MP1, the drain of the second NMOS transistor MN1, the gate of the third PMOS transistor MP2, the gate of the third NMOS transistor MN2, and the gate of the first MOS capacitor MN8 are connected. The drains of the third PMOS transistor MP2, the drain of the third NMOS transistor MN2, the gate of the fourth PMOS transistor MP3, and the gate of the fourth NMOS transistor MN3 are connected. The drains of the fourth PMOS transistor MP3, the drain of the fourth NMOS transistor MN3, the gate of the second MOS capacitor MN9, and the input of the first buffer I6 are connected.

[0031] As those skilled in the art will know, the number of PMOS and NMOS transistors can be set according to actual needs, and the number and capacitance of MOS capacitors can also be adjusted according to the target delay. Other multi-stage series embodiments besides this one are also included. This embodiment uses a delay structure with multi-stage MOS transistors in series and MOS capacitors, which is compatible with the power transistor process of the power amplifier output stage, helping to reduce chip area overhead.

[0032] In this embodiment, when the P terminal experiences a bottoming out, OUTP_HIGH is low and OUTN_HIGH is high. The first NAND gate I0 outputs a high level, triggering the first RS latch to set, and Q_PP flips high. After Q_PP is delayed by the first MOS transistor delay network unit and the first buffer I6, the OUT_HIGH signal flips and is fed back to the subsequent logic module to end the positive pulse insertion, thus forming a feedback delay path controlled by the output state. This embodiment uses an RS latch combined with a MOS delay network structure, which can control the pulse end using the actual flipping time of the output terminal, helping to improve the consistency of the pulse width.

[0033] In one embodiment, the negative pulse insertion control module includes a first NOR gate I3, a second NOR gate I4, a third NOR gate I5, a second MOS transistor delay network unit, and a second buffer I9.

[0034] Specifically, the first input terminal of the third NOR gate I5 receives the first low-level indication signal OUTP_LOW_N output from the P terminal, and the second input terminal of the third NOR gate I5 receives the second low-level indication signal OUTN_LOW_N output from the N terminal. The first NOR gate I3 and the second NOR gate I4 are cross-coupled to form a second RS latch. Specifically, one input terminal of the second NOR gate I4 is connected to the output terminal of the third NOR gate I5, and the other input terminal of the second NOR gate I4 is connected to the output terminal of the first NOR gate I3. One input terminal of the first NOR gate I3 is used to receive the clock signal CLK after inversion by the NOT gate, and the other input terminal of the first NOR gate I3 is connected to the output terminal of the second NOR gate I4. The output terminal of the second NOR gate I4 outputs a negative pulse latch signal Q_NP. One end of the second MOS transistor delay network unit is used to receive the negative pulse latch signal Q_NP, and the other end of the second MOS transistor delay network unit is connected to the input of the second buffer I9. The output of the second buffer I9 outputs the third low-level indication signal OUT_LOW_N. The second RS latch is reset when the clock signal CLK is high, and the output of the second RS latch outputs the negative pulse latch signal Q_NP.

[0035] In this embodiment, when a truncation occurs at the N terminal, OUTP_LOW_N is low and OUTN_LOW_N is high. The third NOR gate I5 outputs a low level, triggering the second RS latch to set, and Q_NP flips low. After Q_NP is delayed by the second MOS transistor delay network unit and the second buffer I9, the OUT_LOW_N signal flips and is fed back to the subsequent logic module to end the negative pulse insertion. In this embodiment, the negative pulse insertion control module and the positive pulse insertion control module adopt a dual design, which can respectively correspond to the two distortion scenarios of truncation and truncation, which helps to improve the symmetry and reliability of the circuit.

[0036] Preferably, the second MOS transistor delay network unit includes a second PMOS transistor group, a second NMOS transistor group, and a third MOS capacitor MN. 10 and the fourth MOS capacitor MN 11 .

[0037] Specifically, the second PMOS transistor group includes a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, and an eighth PMOS transistor MP7 connected in series, with the sources of the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 connected together. The second NMOS transistor group includes a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, and an eighth NMOS transistor MN7 connected in series, with the sources of the fifth NMOS transistor MN4, the sixth NMOS transistor MN5, the seventh NMOS transistor MN6, and the eighth NMOS transistor MN7 connected together, and the third MOS capacitor MN... 10 and the fourth MOS capacitor MN 11 Both the source and drain of the device are grounded.

[0038] Furthermore, the gates of the fifth PMOS transistor MP4 and the fifth NMOS transistor MN4 are both connected to the output of the second NOR gate I4. The drains of the fifth PMOS transistor MP4, the drains of the fifth NMOS transistor MN4, the gates of the sixth PMOS transistor MP5 and the sixth NMOS transistor MN5 are connected. The drains of the sixth PMOS transistor MP5, the drains of the sixth NMOS transistor MN5, the gates of the seventh PMOS transistor MP6 and the seventh NMOS transistor MN6, and the third MOS capacitor MN are also connected. 10 The gates of the seventh PMOS transistor MP6, the drain of the seventh NMOS transistor MN6, the gate of the eighth PMOS transistor MP7, and the gate of the eighth NMOS transistor MN7 are connected; the drains of the eighth PMOS transistor MP7, the drain of the eighth NMOS transistor MN7, and the fourth MOS capacitor MN are connected. 11The gate of the first buffer is connected to the input of the second buffer I9.

[0039] In addition, this embodiment also includes a logic module. Specifically, the logic module is used to perform logical operations on the positive pulse signal output by the positive pulse insertion control module and the negative pulse signal output by the negative pulse insertion control module with the original PWM signal, and output a power amplifier drive signal based on the operation result.

[0040] This embodiment synthesizes the inserted pulse with the original PWM signal through a logic module. It can superimpose a compensation pulse only when there is truncation distortion without changing the normal PWM waveform, which helps to maintain the signal integrity under normal working conditions.

[0041] In one embodiment, the logic module includes NOT gate I7, delay unit I8, and fourth NOR gate I. 10 Fourth NAND gate I 11 First or gate I 12 Second OR gate I 13 First AND gate I 14 Second AND gate I 15 .

[0042] Specifically, the input of NOT gate I7 ​​is used to receive the clock signal CLK, and the output of NOT gate I7 ​​is connected to the negative pulse insertion control module to provide an inverted clock signal to the negative pulse insertion control module; the output of NOT gate I7 ​​is connected to the delay unit I8 and the fourth NOR gate I 10 The first input terminal and the fourth NAND gate I 11 The input terminal of the delay unit I8 is connected to the fourth NOR gate I. 10 The second input terminal and the fourth NAND gate I 11 The input terminal; the delay unit I8 is used to set the upper limit of the width of the inserted pulse; the fourth NOR gate I 10 The third input terminal is connected to the positive pulse insertion control module and is used to receive the third high-level indication signal OUT_HIGH output by the positive pulse insertion control module. The fourth NOR gate I 10 The fourth input receives the mode enable signal EN_1SPW, and the fourth NOR gate I... 10 The output terminal outputs a positive insertion pulse signal LPI_PP to the first OR gate I. 12 One of the input terminals and the second OR gate I 13 One of the input terminals.

[0043] Furthermore, the fourth NAND gate I 11The input terminal is connected to the negative pulse insertion control module, and is used to receive the third low-level indication signal OUT_LOW_N output by the negative pulse insertion control module. The fourth NAND gate I 11 The output terminal outputs a negative insertion pulse signal LPI_NP to the first AND gate I. 14 One of the input terminals and the second AND gate I 15 One of the input terminals; the first OR gate I 12 The other input terminal receives the P-terminal PWM signal PWMP, and the first OR gate I 12 The output terminal is connected to the first AND gate I. 14 The other input terminal; the second OR gate I 13 The other input terminal receives the N-terminal PWM signal PWMN, and the second OR gate I 13 The output terminal is connected to the second AND gate I. 15 The other input terminal; the first AND gate I 14 The output terminal and the second AND gate I 15 The output terminals output the P-terminal drive signal PWMOP and the N-terminal drive signal PWMON, respectively.

[0044] In this embodiment, the positive insertion pulse signal LPI_PP is superimposed on the original PWM signal through an OR gate operation to achieve positive pulse insertion; the negative insertion pulse signal LPI_NP is superimposed on the original PWM signal through an AND gate operation to achieve negative pulse insertion. The delay unit I8 and the feedback path work together for pulse termination control: under normal operating conditions, the feedback path is triggered first, and the pulse width is determined by the output state feedback; under extreme operating conditions, when the output edge is too slow, the delay unit I8 is triggered first, forcibly ending the pulse, thereby constituting upper limit protection for the pulse width.

[0045] As those skilled in the art will know, the delay parameters of the delay unit I8 can be set according to actual needs, and other delay value configurations besides those in this embodiment are also included. This embodiment adopts a combination of feedback path and fixed delay unit, which can achieve adaptive pulse width adjustment and limit the maximum pulse width under extreme operating conditions, thus helping to balance dynamic range and circuit reliability.

[0046] In addition, such as Figure 4 As shown, this embodiment also proposes a pulse insertion method for reducing power amplifier truncation distortion, using the pulse insertion circuit for reducing power amplifier truncation distortion as described above, including the following steps: S1. Detect the level status of the power amplifier output terminal (output terminal includes P terminal and N terminal) and generate an output status feedback signal; S2. When the clock signal is triggered and a top or bottom distortion is detected at the power amplifier output, a pulse is inserted into the corresponding output. The end time of the inserted pulse is controlled according to the output status feedback signal, so that the pulse width is adaptively adjusted according to the actual output flip state.

[0047] In one specific embodiment, in step S1, the first high-level indicator signal OUTP_HIGH output from the P terminal and the second high-level indicator signal OUTN_HIGH output from the N terminal are acquired. At the rising edge of the clock signal CLK, when the first high-level indicator signal OUTP_HIGH is low and the second high-level indicator signal OUTN_HIGH is high, it is determined that a truncation has occurred at the P terminal, and a P terminal output status feedback signal is generated. The first low-level indicator signal OUTP_LOW_N output from the P terminal and the second low-level indicator signal OUTN_LOW_N output from the N terminal are acquired. At the falling edge of the clock signal CLK, when the first low-level indicator signal OUTP_LOW_N is low and the second low-level indicator signal OUTN_LOW_N is high, it is determined that a truncation has occurred at the N terminal, and an N terminal output status feedback signal is generated.

[0048] In step S2, if the P-end is truncated to the bottom and the N-end is truncated to the top as described in step S1, a positive pulse is inserted into the PWM signal corresponding to the P-end at the rising edge of the clock signal CLK, and a negative pulse is inserted into the PWM signal corresponding to the N-end at the falling edge of the clock signal CLK. The positive pulse is terminated after a delay when the actual output level of the P-end flips, and the negative pulse is terminated after a delay when the actual output level of the N-end flips.

[0049] In another specific embodiment, for the cases where the P-end is truncated (when the first high-level indicator signal OUTP_HIGH is high and the second high-level indicator signal OUTN_HIGH is low) and the N-end is truncated (when the first low-level indicator signal OUTP_LOW_N is high and the second low-level indicator signal OUTN_LOW_N is low), a negative pulse is inserted into the PWM signal corresponding to the P-end at the falling edge of the clock signal CLK, and a positive pulse is inserted into the PWM signal corresponding to the N-end at the rising edge of the clock signal CLK. The negative pulse is terminated after a delay when the actual output level of the P-end flips, and the positive pulse is terminated after a delay when the actual output level of the N-end flips.

[0050] Furthermore, in this embodiment, the positive pulse only applies to the bottom of the truncated area, and the negative pulse only applies to the top of the truncated area.

[0051] In this embodiment, (1) the circuit structure and device function description: Figure 3 The area within the dashed box is compared to Figure 1 The added part Figure 3 The enable control signal is omitted. The delay I8 can be set to set the upper limit of the inserted pulse according to the fixed pulse type setting to be compatible with the original structure, or the time can be lengthened (for example, less than 0.5CLK period) to make it completely controlled by the feedback type LPI.

[0052] A high CLK level resets the RS latches of I3 and I4, while a low CLK level resets the RS latches of I1 and I2.

[0053] MP0~MP3, MN0~MN3, and MN8, together with the driver stage of the power transistors, determine the insertion pulse width. MOS devices are used as capacitors in the delay circuit because full-bridge circuits often use NMOSFETs for output power transistors HS and LS due to process support and on-resistance limitations. Here, the delay (I8) of the fixed pulse insertion method is set considering extreme cases under corner (process corner) and supply voltage conditions, inevitably resulting in a pulse width exceeding hundreds of nanoseconds, which may appear excessively long under most corner conditions. Therefore, it will not be effective in most cases, only ensuring a lower limit to prevent excessive power loss due to slow edges at output OUTP or OUTN under extreme conditions, while also maintaining some compatibility with traditional solutions. The delay of this method directly determines the actual insertion width (the width of the OUT terminal pulled high or low), and the end of LPI is controlled by feedback. Therefore, the pulse width variation across all corners is not significant, resulting in better consistency and eliminating the need for adjustments to different EMI configurations, thus reducing circuit area. The pulse width can be significantly shortened compared to a fixed LPI (e.g., fixed LPI 120ns -> 20ns), which greatly alleviates the impact of power supply voltage fluctuations on the absolute value change of delay I8, thereby greatly improving the effective output power.

[0054] (2) Overall circuit function description: LPI_PP truncates the output OUTP or OUTN, while LPI_NP truncates the output. The control parts of LPI_PP and LPI_NP (Low Pulse Width Inject_Negative Pulse) are dual; we will use LPI_PP as an example for explanation. Consider the truncation characteristics under BD (Bridge-Differential) and 1SPW (1-Side Pulse Width); we will use BD as an example for explanation. Figure 3 EN_1SPW=0.

[0055] Working principle: OUTP_HIGH and OUTN_HIGH are indicator signals for the P and N half-bridge outputs of the power amplifier. When the power amplifier output OUTP is high, OUTP_HIGH is 1, and vice versa. Under normal circumstances, when the rising edge of the clock arrives, it corresponds to the trough of the third-level waveform Vtri. If the peak is not truncated, the output of the PWM comparator will inevitably be high, corresponding to a high output OUT, a 0 output I0, and OUT_HIGH 1, thus blocking pulse insertion. When both ends of the output are truncated, one end of the output will be high and the other end will be low, and the corresponding output of the first NAND gate I0 will inevitably be 1.

[0056] When the rising edge of the clock arrives, due to the existing structure, a high pulse is inevitably inserted into the lower end of the output, causing the HS (High Side) to conduct for a period of time and the LS (Low Side) to turn off for a period of time. However, due to the EMI requirements of the power transistor HS, the turn-on time is limited. Furthermore, due to the addition of additional delay units (MP0~MP3, MN0~MN3), the RS latch output Q_PP composed of I1 and I2 will have a positive pulse, with its rising edge aligned with the rising edge of OUTP and its falling edge aligned with the falling edge of OUTP. When the bottom of the output OUTP is truncated and the top of OUTN is truncated, the waveform is as follows: Figures 5-7 As shown.

[0057] As mentioned above, the LPI module generates output pulses such as LPI_PP and LPI_NP, which are inserted into the preamplifier signal PWMP of OUTP. However, because OUTP is truncated, only LPI_PP is effective; and because OUTP is truncated, only LPI_NP is effective. This causes OUTP to change from a constant low to a low signal. Figures 5-7 The waveform shown is similar to OUTN.

[0058] The widths of OUTP and OUTN are determined by MP0~MP3, MN0~MN3, the corresponding MOS capacitors, and the fixed delay (I8). The latter only takes effect in extreme cases where the output edge is large (such as low voltage and low temperature).

[0059] When a pulse is inserted into the output, OUTP_HIGH will go high, so Q_PP will go high. After a certain delay, OUT_HIGH will go high, PWMOP will go low, OUTP will go low, and the output will return to normal.

[0060] Similarly, when OUTN is always high, it will be inserted with a low level. After OUTN turns low, OUTN_LOW_N will be 0, so Q_NP will turn low. After a certain delay, OUT_LOW_N will turn low, LPI_NP will be high, and after ANDing with PWMN, PWMON will turn low, OUTN will turn high, and it will return to its original state.

[0061] The principle is the same for OUTP (top-down) and OUTN (bottom-down).

[0062] For 1SPW mode: Compared to BD mode, where the common-mode point is 50% of the dynamic range and both sides of the output are simultaneously cropped, the common-mode point in 1SPW mode is often lower, with one side of the output cropping earlier (e.g., a 15% common-mode duty cycle). After cropping on both sides, the common-mode voltage in 1SPW has already shifted towards the center value. Therefore, for BD, inserting small pulses on both sides can be considered without affecting the output common-mode voltage; for 1SPW, inserting only LPI_NP (negative pulse) can be considered. This further improves the maximum dynamic range of 1SPW while avoiding premature impact on THD. Figure 3 EN_1SPW=1 indicates that the analysis process corresponds to the truncation under BD.

[0063] Additionally, if the impact of pulse insertion per cycle on the maximum output power or DR (Dynamic Range) is still significant, N-cycle insertion can be performed (replacing CLK with the corresponding frequency signal). For example, N=2 (generally ensuring >20kHz), but the corresponding duty cycle may require further adjustment (e.g., for applications requiring greater sound continuity, the corresponding circuit...). Figure 3 Delete the dashed box in the image, and change the I8 delay to the desired duty cycle signal (e.g., simply set the duty cycle to 25%, or any other duty cycle, but ensure alignment with CLK so that the inserted LPI direction remains consistent with the truncated waveform). A trade-off between sound quality and DR needs to be made.

[0064] Therefore, compared to traditional fixed LPI, this embodiment maintains a high degree of consistency in pulse width across different corners, effectively extending the maximum dynamic range in low-voltage applications and eliminating the need for repeated adjustments for different EMI configurations. Using the 1SPW mode further enhances the dynamic range while reducing the impact on signal continuity. The N-cycle insertion method allows for a more flexible trade-off between audible quality and maximum dynamic range, tailored to specific needs.

[0065] In summary, the pulse insertion circuit and method for reducing power amplifier clipping distortion proposed in this invention have the following advantages: By using output state feedback to control the pulse end time, the insertion pulse width can be adaptively adjusted according to the actual output flip state. This reduces the impact of power supply voltage fluctuations and process angle deviations on the pulse width and improves the consistency of pulse width under different operating conditions. At the same time, the pulse width does not need to be conservatively set according to extreme operating conditions, which can effectively narrow the insertion pulse width, thereby improving the output effective power and maximum dynamic range.

[0066] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A pulse insertion circuit for reducing power amplifier cutoff distortion, characterized in that, include: Clock unit, positive pulse insertion control module, and negative pulse insertion control module; The clock unit is used to provide clock signals; The positive pulse insertion control module is used to insert a positive pulse when the P or N terminal of the power amplifier is detected to be cut off under the trigger of the clock signal, and to control the end time of the positive pulse according to the output status feedback of the P or N terminal, so that the width of the positive pulse is adaptively adjusted. The negative pulse insertion control module is used to insert a negative pulse when the clock signal triggers and the P or N terminal of the power amplifier is detected to be truncated, and to control the end time of the negative pulse according to the output status feedback of the P or N terminal, so that the width of the negative pulse is adaptively adjusted.

2. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 1, characterized in that, The forward pulse insertion control module includes a first NAND gate, a second NAND gate, a third NAND gate, a first MOS transistor delay network unit, and a first buffer; The first input terminal of the first NAND gate receives the first high-level indication signal output from the P terminal, and the second input terminal of the first NAND gate receives the second high-level indication signal output from the N terminal. One input of the second NAND gate is connected to the output of the first NAND gate, and the other input of the second NAND gate is connected to the output of the third NAND gate; one input of the third NAND gate is used to receive a clock signal, and the other input of the third NAND gate is connected to the output of the second NAND gate; the output of the second NAND gate outputs a positive pulse latch signal. One end of the first MOS transistor delay network unit is used to receive the positive pulse latch signal, and the other end of the first MOS transistor delay network unit is connected to the input terminal of the first buffer. The output terminal of the first buffer outputs a third high-level indication signal.

3. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 2, characterized in that, The first MOS transistor delay network unit includes a first PMOS transistor group, a first NMOS transistor group, a first MOS capacitor, and a second MOS capacitor; The first PMOS transistor group includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor connected in series, with the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor connected together. The first NMOS transistor group includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series. The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor, as well as the sources and drains of the first MOS capacitor and the second MOS capacitor, are all grounded. The gates of the first PMOS transistor and the first NMOS transistor are both connected to the output of the second NAND gate. The drains of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor are connected. The drains of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor, the gate of the third NMOS transistor, and the gate of the first MOS capacitor are connected. The drains of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor are connected. The drains of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the gate of the second MOS capacitor, and the input of the first buffer are connected.

4. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 1, characterized in that, The negative pulse insertion control module includes a first NOR gate, a second NOR gate, a third NOR gate, a second MOS transistor delay network unit, and a second buffer. The first input terminal of the third NOR gate receives the first low-level indication signal output from the P terminal, and the second input terminal of the third NOR gate receives the second low-level indication signal output from the N terminal; One input terminal of the second NOR gate is connected to the output terminal of the third NOR gate, and the other input terminal of the second NOR gate is connected to the output terminal of the first NOR gate; one input terminal of the first NOR gate is used to receive the clock signal after being inverted by the NOT gate, and the other input terminal of the first NOR gate is connected to the output terminal of the second NOR gate; the output terminal of the second NOR gate outputs a negative pulse latch signal. One end of the second MOS transistor delay network unit is used to receive the negative pulse latch signal, and the other end of the second MOS transistor delay network unit is connected to the input terminal of the second buffer. The output terminal of the second buffer outputs a third low-level indication signal.

5. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 4, characterized in that, The second MOS delay network unit includes a second PMOS transistor group, a second NMOS transistor group, a third MOS capacitor, and a fourth MOS capacitor; The second PMOS transistor group includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor connected in series, with the sources of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor connected together. The second NMOS transistor group includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor connected in series. The sources of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor, as well as the sources and drains of the third MOS capacitor and the fourth MOS capacitor, are all grounded. The gates of the fifth PMOS transistor and the fifth NMOS transistor are both connected to the output of the second NOR gate. The drains of the fifth PMOS transistor, the fifth NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the sixth NMOS transistor are connected. The drains of the sixth PMOS transistor, the sixth NMOS transistor, the gate of the seventh PMOS transistor, the gate of the seventh NMOS transistor, and the gate of the third MOS capacitor are connected. The drains of the seventh PMOS transistor, the seventh NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are connected. The drains of the eighth PMOS transistor, the eighth NMOS transistor, the gate of the fourth MOS capacitor, and the input of the second buffer are connected.

6. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 1, characterized in that, It also includes a logic module; the logic module is used to perform logical operations on the positive pulse signal output by the positive pulse insertion control module and the negative pulse signal output by the negative pulse insertion control module with the original PWM signal, respectively, and output the power amplifier drive signal.

7. The pulse insertion circuit for reducing power amplifier truncation distortion as described in claim 6, characterized in that, The logic module includes NOT gates, delays, fourth NOR gates, fourth NAND gates, first OR gates, second OR gates, first AND gates, and second AND gates; The input terminal of the NOT gate is used to receive a clock signal, and the output terminal of the NOT gate is connected to the negative pulse insertion control module to provide an inverted clock signal to the negative pulse insertion control module; the output terminal of the NOT gate is connected to the delay unit, the first input terminal of the fourth NOR gate, and the input terminal of the fourth NAND gate; The output of the delay unit is connected to the second input of the fourth NOR gate and the input of the fourth NAND gate; the delay unit is used to set the upper limit of the width of the inserted pulse. The third input of the fourth NOR gate is connected to the positive pulse insertion control module and is used to receive the third high-level indication signal output by the positive pulse insertion control module. The fourth input of the fourth NOR gate receives the mode enable signal. The output of the fourth NOR gate outputs a positive insertion pulse signal to one of the inputs of the first OR gate and one of the inputs of the second OR gate. The input terminal of the fourth NAND gate is connected to the negative pulse insertion control module, and is used to receive the third low-level indication signal output by the negative pulse insertion control module. The output terminal of the fourth NAND gate outputs a negative insertion pulse signal to one of the input terminals of the first AND gate and one of the input terminals of the second AND gate. The other input of the first OR gate receives the P-terminal PWM signal PWMP, and the output of the first OR gate is connected to the other input of the first AND gate. The other input of the second OR gate receives the N-terminal PWM signal PWMN, and the output of the second OR gate is connected to the other input of the second AND gate; The output terminals of the first AND gate and the second AND gate respectively output the P-terminal drive signal PWMOP and the N-terminal drive signal PWMON.

8. A pulse insertion method for reducing power amplifier truncation distortion, using a pulse insertion circuit for reducing power amplifier truncation distortion as described in any one of claims 1-7, characterized in that, Including the following: Detect the level status at the power amplifier output terminal and generate an output status feedback signal; When the clock signal is triggered and a top or bottom cutoff distortion is detected at the power amplifier output, a pulse is inserted into the corresponding output. The end time of the inserted pulse is controlled according to the output status feedback signal, so that the pulse width is adaptively adjusted according to the actual output flip state.

9. The pulse insertion method for reducing power amplifier truncation distortion as described in claim 8, characterized in that, The detection of the power amplifier output level specifically includes: The system acquires the first high-level indicator signal output from the P terminal and the second high-level indicator signal output from the N terminal. When the first high-level indicator signal is low and the second high-level indicator signal is high, or when the first high-level indicator signal is high and the second high-level indicator signal is low, it determines that a bottoming out has occurred at the P terminal or the N terminal, and generates a status feedback signal for the P terminal or the N terminal. The system acquires the first low-level indicator signal output from the P terminal and the second low-level indicator signal output from the N terminal. When the first low-level indicator signal is low and the second low-level indicator signal is high, or when the first low-level indicator signal is high and the second low-level indicator signal is low, it determines that the P terminal or the N terminal has been truncated and generates a status feedback signal for the P terminal or the N terminal.

10. The pulse insertion method for reducing power amplifier truncation distortion as described in claim 8, characterized in that, When the clock signal is triggered and a top-down or bottom-out distortion is detected in the power amplifier output, a pulse is inserted into the corresponding output terminal, and the end time of the inserted pulse is controlled according to the output status feedback signal, specifically including: A positive pulse is inserted into the PWM signal corresponding to the P terminal and the N terminal at the rising edge of the clock signal, and a negative pulse is inserted into the PWM signal corresponding to the P terminal and the N terminal at the falling edge of the clock signal. The positive pulse is terminated after a delay when the actual output level of the truncated end flips; the negative pulse is terminated after a delay when the actual output level of the truncated end flips. Within each clock cycle, the positive pulse insertion control and the negative pulse insertion control are reset by the corresponding level of the clock signal, so that the pulse insertion actions in each clock cycle are independent of each other. When the power amplifier is operating in 1SPW mode, positive pulse insertion is disabled, and only negative pulse insertion is allowed.

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