latch, logic circuit, chip, and electronic device

Abstract

The application relates to the technical field of circuits, in particular to a latch, a logic circuit, a chip and an electronic device. The latch comprises a first voltage division module, a second voltage division module and a cross-coupling module. The first voltage division unit is used for voltage reduction of a first control signal. The second voltage division unit is used for voltage reduction of a second control signal. The cross-coupling module is used for being in a first stable state or a second stable state under the action of the first control signal and the second control signal. In the first stable state, a third output end outputs a first voltage, and the first voltage is obtained based on the first control signal. In the second stable state, the third output end outputs a second voltage, and the second voltage is obtained based on the second control signal. The latch improves the voltage range of the first control signal and the second control signal.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a latch, logic circuit, chip, and electronic device. Background Technology

[0002] In the field of switching chips, support for wide power supply voltages and high reliability are among the core performance indicators. As a key module for implementing dual-power-supply interface logic control, the performance of latches directly determines the stability and operating voltage range of the switches. Existing latch designs are limited by semiconductor processes, and their operating voltage range is typically narrow. For example, the power supply voltage must be maintained between 0.65 and 1.3 times the rated operating voltage of the switching transistor. When the power supply voltage exceeds this upper limit, the critical switching transistor inside the latch faces the risk of overvoltage breakdown, leading to permanent circuit damage. This limitation severely restricts the use of switching chips in wide-voltage industrial applications with higher power supply voltages. Summary of the Invention

[0003] To address the aforementioned issues, this application provides a latch, chip, and electronic device that can improve the range of power input voltage.

[0004] In a first aspect, this application provides a latch, comprising: a first voltage divider module, a second voltage divider module, and a cross-coupling module. The first voltage divider module includes a first input terminal and a first output terminal, the first input terminal being electrically connected to a first power supply module. The first power supply module outputs a first control signal, and the first voltage divider module steps down the voltage of the first control signal. The second voltage divider module includes a second input terminal and a second output terminal, the second input terminal being electrically connected to a second power supply module. The second power supply module outputs a second control signal, and the second voltage divider module steps down the voltage of the second control signal. The cross-coupling module includes a third input terminal, a fourth input terminal, and a third output terminal, the first output terminal being electrically connected to the third input terminal, and the second output terminal being electrically connected to the fourth input terminal. The cross-coupling module is configured to be in a first stable state or a second stable state under the action of the first control signal and the second control signal. In the first stable state, the third output terminal outputs a first voltage, which is obtained based on the first control signal. In the second stable state, the third output terminal outputs a second voltage, which is obtained based on the second control signal.

[0005] The latch described above can share the first control signal and the second control signal through the first voltage divider module and the second voltage divider module, thereby increasing the voltage range of the first power supply module and the second power supply module.

[0006] In one possible implementation of the first aspect described above, the cross-coupling module includes a first switch and a second switch. The first terminal of the first switch is configured as a third input terminal, and the first terminal of the second switch is configured as a fourth input terminal. The first terminal of the first switch is electrically connected to the third terminal of the second switch, and the first terminal of the second switch is electrically connected to the third terminal of the first switch. The second terminals of both the first and second switches are electrically connected to a third output terminal.

[0007] In one possible implementation of the first aspect described above, the cross-coupling module further includes a first resistor and a second resistor. The first terminal of the first switch is electrically connected to the third terminal of the second switch via the first resistor. The first terminal of the second switch is electrically connected to the third terminal of the first switch via the second resistor.

[0008] In one possible implementation of the first aspect described above, the first voltage divider module includes a third switching transistor, and the second voltage divider module includes a fourth switching transistor. The first terminal of the third switching transistor is configured as a first input terminal, and the second terminal of the third switching transistor is configured as a first output terminal; the second terminal of the third switching transistor is electrically connected to the first terminal of the first switching transistor. The first terminal of the fourth switching transistor is configured as a second input terminal, and the second terminal of the fourth switching transistor is configured as a second output terminal. The second terminal of the fourth switching transistor is electrically connected to the first terminal of the second switching transistor. The third terminal of the third switching transistor is electrically connected to the third terminal of the fourth switching transistor.

[0009] In one possible implementation of the first aspect described above, the latch further includes a filtering module, with the third output terminal electrically connected to the filtering module, which is used to filter the voltage output from the third output terminal.

[0010] In one possible implementation of the first aspect described above, the filtering module includes a first capacitor, a second capacitor, a first diode unit, and a second diode unit. A first terminal of the first capacitor is electrically connected to a third output terminal, a second terminal of the first capacitor is electrically connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is grounded. The first diode unit is connected in parallel with the first capacitor, the second diode unit is connected in parallel with the second capacitor, and the first diode unit and the second diode unit are connected in series. The first diode unit includes at least two diodes connected in series, and the second diode unit includes at least two diodes connected in series.

[0011] In one possible implementation of the first aspect described above, the first diode unit includes a first diode, a second diode, and a third diode; the second diode unit includes a fourth diode, a fifth diode, and a sixth diode. A first terminal of the first capacitor is also electrically connected to a first terminal of the first diode; a second terminal of the first diode is electrically connected to a first terminal of the second diode; a second terminal of the second diode is electrically connected to a first terminal of the third diode; and a second terminal of the first capacitor is electrically connected to a second terminal of the third diode. A first terminal of the second capacitor is electrically connected to a first terminal of the fourth diode; a second terminal of the fourth diode is electrically connected to a first terminal of the fifth diode; and a second terminal of the fifth diode is electrically connected to a first terminal of the sixth diode.

[0012] In one possible implementation of the first aspect described above, the cross-coupled module is in a first stable state when the first control signal is high and the second control signal is low.

[0013] In one possible implementation of the first aspect described above, the cross-coupled module is in a second stable state when the first control signal is low and the second control signal is high.

[0014] Secondly, this application provides a logic circuit including a latch of any one of the first aspects and various possible implementations thereof.

[0015] Thirdly, this application provides a chip including a latch comprising any one of the first aspects and various possible implementations thereof.

[0016] Fourthly, this application provides an electronic device including the chip described in the third aspect above. Attached Figure Description

[0017] Figure 1 A circuit diagram of a first type of latch is shown according to some embodiments.

[0018] Figure 2 According to some embodiments, a circuit diagram of a second type of latch is shown.

[0019] Figure 3 According to some embodiments, a circuit diagram of a third type of latch is shown.

[0020] Figure 4 According to some embodiments, a circuit diagram of a fourth latch is shown.

[0021] Figure 5 According to some embodiments, a circuit diagram of a fifth latch is shown.

[0022] Figure 6 According to some embodiments, a circuit diagram of a capacitor module is shown.

[0023] Figure 7 According to some embodiments, a circuit diagram of a sixth latch is shown. Detailed Implementation

[0024] The illustrative embodiments of this application include, but are not limited to, a latch, logic circuit, chip, and electronic device.

[0025] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are illustrative of this application but are not intended to limit the scope of this application.

[0026] Figure 1 The circuit diagram of the first type of latch is shown in the figure. Figure 1 As shown, the latch may include a first cross-coupling module. The first cross-coupling module includes a first transistor M11 and a second transistor M12. Both the first and second transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), and both have the same channel type, which is P-type.

[0027] like Figure 1 As shown, the first cross-coupling module can be connected to the third power supply module and the fourth power supply module respectively. The third power supply module is electrically connected to the first input terminal VO11 of the first cross-coupling module, and the fourth power supply module is electrically connected to the first input terminal VO12 of the first cross-coupling module. The first cross-coupling module can be a positive feedback cross-coupling module. The third power supply module can include a third power supply V11 and an eleventh resistor R11. The fourth power supply module can include a fourth power supply V12 and a twelfth resistor R12. Both the third power supply V11 and the fourth power supply V12 can be voltage sources.

[0028] refer to Figure 1 As shown, the first terminal of the third power supply V11 is connected to the first terminal of the eleventh resistor R11, and the first terminal of the fourth power supply V12 is connected to the second terminal of the twelfth resistor R12. The second terminals of the third power supply V11 and the fourth power supply V12 are grounded. The second terminal of the eleventh resistor R11 is connected to the drain of the first transistor M11 and the gate of the second transistor M12, respectively. The gate of the first transistor M11 (i.e., node V1X) is connected to the first terminal of the twelfth resistor R12 and the drain of the second transistor M12, respectively. The source of the first transistor M11 (i.e., node V1A) is connected to the source of the second transistor M12 (i.e., node V1A).

[0029] In some embodiments, the eleventh resistor R11 and the twelfth resistor R12 are in the hundreds of ohms range. For example, the resistance values ​​of the eleventh resistor R11 and the twelfth resistor R12 can be from 100Ω to 999Ω.

[0030] The third power supply module is used to input the first control signal to the first input terminal VO11, and the fourth power supply module is used to input the second control signal to the first input terminal VO12. The first control signal and the second control signal can be complementary logic levels, that is, when one is high and the other is low, the latch enters a stable state, at which time the latch completes the state storage function.

[0031] It is understandable that, depending on the difference between the first control signal and the second control signal, the latch can operate in the first stable state and the second stable state.

[0032] For example, the first input terminal VO11 of the first cross-coupling module receives the first control signal from the third power supply module and the first control signal is at a high level, and the first input terminal VO12 of the first cross-coupling module receives the second control signal from the fourth power supply module and the second control signal is at a low level. The first cross-coupling module stabilizes the latch in the first stable state based on a positive feedback mechanism.

[0033] Since the first control signal is high, both the first and second transistors are P-channel MOSFETs, and the voltage at node V1Y is raised to a high level. At this time, node V1A is close to 0V, and the gate voltage of the second transistor M12 is higher than its source voltage, so the second transistor M12 is turned off. The gate of the first transistor M11 is pulled low, and the drain of the first transistor M11 charges the source through parasitic capacitance, slightly raising the voltage at node V1A, so that the gate voltage of the first transistor M11 is lower than its source voltage, and the first transistor M11 is turned on. Because the first transistor M11 is turned on, the drain of the first transistor M11 charges the parasitic capacitance, causing the third output terminal of the cross-coupled module (i.e., node V1A) to be raised to a high level. Since node V1A is high, the first latch is in the first stable state, i.e., the first transistor M11 is turned on and the second transistor M12 is turned off, and it will not spontaneously flip. Node V1A remains high based on the turned-on first transistor M11.

[0034] The first input terminal VO11 of the third power supply, fourth power supply, and first cross-coupling module receives the first control signal from the third power supply module, and the first control signal is at a low level. The first input terminal VO12 of the first cross-coupling module receives the second control signal from the fourth power supply module, and the second control signal is at a high level. The first cross-coupling module stabilizes the latch in the second stable state based on a positive feedback mechanism.

[0035] Since the first control signal is low, both the first and second transistors are P-channel MOSFETs. The gate of the first transistor M11 is raised to a high level, and at this time, node V1A is close to 0V. The gate voltage of the first transistor M11 is higher than the source voltage, so the first transistor M11 is cut off. The gate of the second transistor M12 is pulled low, and the drain of the second transistor M12 charges the source through parasitic capacitance, slightly raising the voltage of node V1A. This causes the gate voltage of the second transistor M12 to be lower than the source voltage, and the second transistor M12 turns on. Because the second transistor M12 is on, its drain charges the parasitic capacitance, raising the voltage of node V1A to a high level. Since node V1A is high, the first latch is in a second stable state, i.e., the first transistor M11 is off and the second transistor M12 is on. It will not spontaneously flip, and node V1A remains high based on the on-state of the second transistor M12.

[0036] In some embodiments, when the first control signal and the second control signal of the latch are at the same level, i.e., two high levels or two low levels, the latch is not in an stable state and loses its latching function.

[0037] Understandable. Figure 1 The latch in the circuit consists of two P-type MOSFETs, M11 and M12. According to current semiconductor technology, the rated operating voltage of a P-type MOSFET is typically 2.5V. In operation, the drain-source breakdown voltage BVDS (the highest safe voltage across the source and drain terminals) is typically about 130% of the rated operating voltage, or 3.3V. To avoid drain-source breakdown, the voltage VDS between the source and drain of the P-type MOSFET needs to be less than or equal to 3.3V. Therefore, the voltages of the third power supply V11 and the fourth power supply V12 must ensure that, when the latch is operating, the drain-source voltage VDS of both transistors M11 and M12 is less than or equal to the drain-source breakdown voltage BVDS (3.3V). In the stable state of the latch, if the gate voltage of transistor M11 is close to a low level, such as 0V, and the source voltage is close to the output voltage of the third power supply V11 or the fourth power supply V12 (i.e., VDD), then the voltage between the gate and source VGS = 0 - VDD = -VDD. To avoid reverse gate-source breakdown, the voltage VGS between the gate and source of the first transistor M11 and the second transistor M12 must be greater than or equal to -3.3V. Therefore, -VDD must be greater than or equal to -3.3V, i.e., VDD≤3.3V, which is consistent with the drain-source constraint condition of VDS.

[0038] Therefore, the upper limit of the voltage output (i.e., VDD) of the third power supply V11 or the fourth power supply V12 is constrained by the drain-source breakdown voltage (BVDS) and gate-source reverse breakdown voltage of the P-type MOSFET, and must simultaneously satisfy VDD ≤ 3.3V (i.e., 130% of the rated operating voltage of the P-type MOSFET). If a higher VDD is selected, the first transistor M11 and the second transistor M12 will be damaged due to overvoltage. This limitation severely restricts the use of latches in wide voltage requirement scenarios.

[0039] In view of this, embodiments of this application disclose a latch. For example... Figure 2 As shown, the latch provided in this embodiment includes: a first voltage divider module, a second voltage divider module, and a cross-coupling module. The first voltage divider module includes a first input terminal and a first output terminal, with the first input terminal electrically connected to a first power supply module. The first power supply module outputs a first control signal, and the first voltage divider module steps down the first control signal. The second voltage divider module includes a second input terminal and a second output terminal, with the second input terminal electrically connected to a second power supply module. The second power supply module outputs a second control signal, and the second voltage divider module steps down the second control signal. The cross-coupling module includes a third input terminal, a fourth input terminal, and a third output terminal, with the first output terminal electrically connected to the third input terminal and the second output terminal electrically connected to the fourth input terminal. The cross-coupling module is used to be in a first stable state or a second stable state under the action of the first and second control signals. In the first stable state, the third output terminal outputs a first voltage, which is obtained based on the first control signal. In the second stable state, the third output terminal outputs a second voltage, which is obtained based on the second control signal.

[0040] After receiving the first control signal output by the first power module and the second control signal output by the second power module, the latch described above can divide the voltage of the cross-coupled module through the first voltage divider module and the second voltage divider module, thereby increasing the voltage range of the output voltage of the first power module and the second power module.

[0041] It is understood that the latches disclosed in this application can be used in single-pole double-throw (SPDT) switches and various electronic circuits or electronic devices that require latches. For example, the latches disclosed in this application can be applied to the fields of radio frequency and analog switches, digital systems and computers, data acquisition and signal processing, power management, display drivers, and programmable logic devices, etc. In the embodiments of this application, the application of the latches is not specifically limited.

[0042] For example, Figure 3 A circuit structure for a latch is shown, with reference to... Figure 3In this latch, the cross-coupling module may include a first switch M1 and a second switch M2.

[0043] In the embodiments of this application, unless otherwise stated, all switching transistors can be MOSFETs, and the channel type of each switching transistor can be the same, for example, all can be P-type channels. In addition, the first terminal of each switching transistor refers to the drain, the second terminal of each switching transistor refers to the source, and the third terminal of each switching transistor refers to the gate.

[0044] refer to Figure 3 As shown, the first terminal of the first switching transistor M1 is configured as the third input terminal, and the first terminal of the second switching transistor M2 is configured as the fourth input terminal. The first terminal of the first switching transistor M1 is electrically connected to the third terminal of the second switching transistor M2, and the first terminal of the second switching transistor M2 is electrically connected to the third terminal of the first switching transistor M1. The second terminals of both the first switching transistor M1 and the second terminal of the second switching transistor M2 are electrically connected to the third output terminal.

[0045] The connection between the substrate (bulk) of the first switching transistor M1 and the second terminal of the first switching transistor M1, and the connection between the substrate (bulk) of the second switching transistor M2 and the second terminal of the second switching transistor M2, can avoid threshold voltage drift caused by body effect and ensure the stability of latching state.

[0046] refer to Figure 3 As shown, the cross-coupling module may further include a first resistor RG1 and a second resistor RG2. The first terminal of the first switch M1 is electrically connected to the third terminal of the second switch M2 through the first resistor RG1. The first terminal of the second switch M2 is electrically connected to the third terminal of the first switch M1 through the second resistor RG2.

[0047] The first resistor RG1 and the second resistor RG2 are in the hundreds of ohms range. For example, the resistance values ​​of the first resistor RG1 and the second resistor RG2 can be from 100Ω to 999Ω.

[0048] When the latch switches between the first stable state and the second stable state, the voltage between the third and second terminals of the first switch M1 or the second switch M2 increases due to the charging and discharging of the third terminal. Therefore, the voltage of the transient third terminal and the transient VGS can be divided by the first resistor RG1 and the second resistor RG2, thereby protecting the first switch M1 and the second switch M2.

[0049] refer to Figure 3As shown, in this latch, the first voltage divider module may include a third switch M3, and the second voltage divider module includes a fourth switch M4. The first terminal of the third switch M3 is configured as a first input terminal VO1, and the second terminal of the third switch M3 is configured as a first output terminal VM. The second terminal of the third switch M3 is electrically connected to the first terminal of the first switch M1. The first terminal of the fourth switch M4 is configured as a second input terminal VO2, and the second terminal of the fourth switch M4 is configured as a second output terminal VN. The second terminal of the fourth switch M4 is electrically connected to the first terminal of the second switch M2. The third terminal of the third switch M3 is electrically connected to the third terminal of the fourth switch M4.

[0050] refer to Figure 3 As shown, the substrate (bulk) of the third switch M3 is connected to the second electrode of the third switch M3, and the substrate (bulk) of the fourth switch M4 is shorted to the second electrode of the fourth switch M4. This ensures stable conduction / cutoff characteristics under trigger signal control and avoids the influence of bulk effect on trigger sensitivity.

[0051] In some embodiments, the substrate (bulk) of the first switching transistor M1, the second electrode of the first switching transistor M1, the substrate (bulk) of the third switching transistor M3, and the second electrode of the third switching transistor M3 are connected, and the substrate (bulk) of the fourth switching transistor M4, the second electrode of the fourth switching transistor M4, the substrate (bulk) of the second switching transistor M2, and the second electrode of the second switching transistor M2 are connected, which can increase the output voltage of the third output terminal VA of the latch.

[0052] refer to Figure 3 As shown, the first voltage divider module may also include a fifth resistor RX1, a sixth resistor RX2 and a seventh resistor RY1, and the second voltage divider module may also include an eighth resistor RX3, a ninth resistor RX4 and a tenth resistor RY2.

[0053] refer to Figure 3 As shown, in the first power module (detailed below), the second terminal of the third resistor RZ1 is connected to the first terminal of the fifth resistor RX1, the first terminal of the third switch M3, and the first terminal of the seventh resistor RY1. The second terminal of the seventh resistor RY1 is connected to the first terminal of the tenth resistor RY2. The second terminal of the tenth resistor RY2 is connected to the first terminal of the eighth resistor RX3 and the first terminal of the fourth resistor RZ2 in the second power module (detailed below). The second terminal of the fifth resistor RX1 is connected to the first terminal of the first switch M1, the second terminal of the third switch M3, the first terminal of the sixth resistor RX2, and the first terminal of the first resistor RG1. The third terminal of the third switch M3 is connected to the third terminal of the fourth switch M4. Furthermore, the second terminal of the eighth resistor RX3 is connected to the first terminal of the second switch M2, the second terminal of the fourth switch M4, the first terminal of the ninth resistor RX4, and the second terminal of the second resistor RG2.

[0054] The resistance values ​​of the fifth resistor RX1, sixth resistor RX2, eighth resistor RX3, ninth resistor RX4, seventh resistor RY1, and tenth resistor RY2 are in the kiloohm range; for example, the resistance values ​​of the fifth resistor RX1, sixth resistor RX2, eighth resistor RX3, ninth resistor RX4, seventh resistor RY1, and tenth resistor RY2 can be from 1000Ω to 9999Ω. The resistance values ​​of the third resistor RZ1 and fourth resistor RZ2 are in the hundred ohm range; for example, the resistance values ​​of the third resistor RZ1 and fourth resistor RZ2 can be from 100Ω to 999Ω.

[0055] The first resistor RG1, the second resistor RG2, the third resistor RZ1, the fourth resistor RZ2, the fifth resistor RX1, the sixth resistor RX2, the seventh resistor RY1, the eighth resistor RX3, the ninth resistor RX4, and the tenth resistor RY2 can form a DC bias network.

[0056] refer to Figure 3 As shown, in this latch, the first power supply module may include a first power supply V1 and a third resistor RZ1, and the second power supply module includes a second power supply V2 and a fourth resistor RZ2.

[0057] refer to Figure 3 As shown, the first terminal of the first power supply V1 is connected to the first terminal of the third resistor RZ1, the first terminal of the second power supply V2 is connected to the second terminal of the fourth resistor RZ2, and the second terminals of the first power supply V1 and the second terminals of the second power supply V2 are grounded.

[0058] Both the first power supply V1 and the second power supply V2 can be voltage sources.

[0059] Combination Figure 3 As shown, when the first control signal and the second control signal of the latch are at different levels, that is, one is high and the other is low, the latch enters a stable state, such as the first stable state and the second stable state, and has the latching function.

[0060] For example, the first input terminal VO1 of the first voltage divider module receives a first control signal from the first power supply module, and the first control signal is at a high level. The second input terminal VO2 of the second voltage divider module receives a second control signal from the second power supply module, and the second control signal is at a low level. The cross-coupling module stabilizes the latch in a first stable state based on a positive feedback mechanism. At this time, the first output terminal VM of the first voltage divider module obtains a positive voltage spike through the parasitic capacitance of M3. The voltage of the first output terminal VM is approximately half of the first control signal plus the positive voltage spike. The voltage of node VZ is approximately half of the first control signal, making the voltage of the third terminal (i.e., node VZ) of the third switch M3 less than the voltage of the second terminal (i.e., the first output terminal VM) of the third switch M3, and the third switch M3 is turned on. The first input terminal VO1 of the first voltage divider module clamps the voltage of the second terminal (i.e., the first output terminal VM) of the third switch M3. The voltage of the first output terminal VM is approximately the voltage of the first input terminal VO1, which is approximately the first control signal. At this time, the voltage difference between the third terminal and the second terminal of the third switch M3 is approximately half of the first control signal, and the third switch M3 is stably turned on.

[0061] Furthermore, the voltage at the third terminal of the fourth switch M4, i.e., the voltage at node VZ, is approximately half of the first control signal, and the voltage at the second terminal of the fourth switch M4 is approximately 0V. Since the voltage at the third terminal of the fourth switch M4 is greater than the voltage at the second terminal of the fourth switch M4, the fourth switch M4 is turned off.

[0062] Since the initial voltage of the third output terminal VA is 0, the fourth switch M4 is cut off, causing the second output terminal VN to remain at a low level. The conduction of the third switch M3 makes the voltage at the first terminal (i.e., the first output terminal VM) of the first switch M1 approximately equal to the first control signal. The voltage at the third terminal of the first switch M1 is low. Because the third switch M3 is turned on, it charges the third output terminal VA through the parasitic capacitance of the first switch M1, slightly increasing the voltage at the third output terminal VA. This makes the voltage at the third terminal of the first switch M1 less than the voltage at the second terminal, causing the first switch M1 to turn on.

[0063] Furthermore, the third terminal of the second switch M2 (i.e., node VY) is at a high level, greater than the initial voltage of the third output terminal VA, and the second switch M2 is turned off. After the first switch M1 is turned on, the voltage of the third output terminal VA eventually rises to approximately the first control signal. Since the first output terminal VM and node VY are at a high level, the latch is in the first stable state, i.e., the first switch M1 is turned on, the second switch M2 is turned off, and the voltage of the third terminal of the fourth switch M4 is always greater than the voltage of the second terminal of the fourth switch M4, so the fourth switch M4 remains off. The voltage of the third terminal of the third switch M3 is always less than the voltage of the second terminal of the third switch M3, so the third switch M3 remains on. The second type of latch will not spontaneously flip, and node V1A remains at a high level based on the turned-on first switch M1.

[0064] For example, the first input terminal VO1 of the first voltage divider module receives a first control signal from the first power supply module, and the first control signal is at a low level. The second input terminal VO2 of the second voltage divider module receives a second control signal from the second power supply module, and the second control signal is at a high level. The cross-coupling module stabilizes the latch in a second stable state based on a positive feedback mechanism. At this time, the second output terminal VN of the second voltage divider module obtains a positive voltage spike through the parasitic capacitance of the fourth switch M4. The voltage of the second output terminal VN is approximately half of the second control signal plus the positive voltage spike. The voltage of node VZ is approximately half of the second control signal, making the voltage of the third terminal (i.e., node VZ) of the fourth switch M4 less than the voltage of the second terminal (i.e., the second output terminal VN) of the fourth switch M4, and the fourth switch M4 is turned on. The second input terminal VO2 clamps the voltage of the second terminal (i.e., the second output terminal VN) of the fourth switch M4. The voltage of the second output terminal VN is approximately the voltage of the second input terminal VO2, which is approximately the second control signal. At this time, the voltage difference between the third terminal and the second terminal of the fourth switch M4 is approximately (half of the second control signal), and the fourth switch M4 is stably turned on.

[0065] Furthermore, the voltage at the third terminal of the third switch M3, i.e., the voltage at node VZ, is approximately half of the second control signal, and the voltage at the second terminal of the third switch M3 is approximately 0V. Since the voltage at the third terminal of the third switch M3 is greater than the voltage at the second terminal of the third switch M3, the third switch M3 is turned off.

[0066] Since the initial voltage of the third output terminal VA is 0, the third switch M3 is cut off, causing the first output terminal VM to remain at a low level. The conduction of the fourth switch M4 makes the voltage at the first terminal (i.e., the second output terminal VN) of the second switch M2 approximately equal to the second control signal. The voltage at the third terminal of the second switch M2 is low. After the fourth switch M4 is turned on, it charges the third output terminal VA through the parasitic capacitance of the second switch M2, slightly increasing the voltage at the third output terminal VA. This makes the voltage at the third terminal of the second switch M2 less than the voltage at the second terminal, causing the second switch M2 to turn on.

[0067] Furthermore, the third terminal of the first switch M1 (i.e., the second output terminal VN) is at a high level, which is greater than the initial voltage of the third output terminal VA, so the first switch M1 is cut off. After the second switch M2 is turned on, the voltage of the third output terminal VA eventually rises to approximately the second control signal. Since the second output terminal VN and node VX are at a high level, the latch is in the second stable state, i.e., the second switch M2 is turned on, the first switch M1 is turned off, and the voltage of the third terminal of the third switch M3 is always greater than the voltage of the second terminal of the third switch M3, so the third switch M3 remains off. The voltage of the third terminal of the fourth switch M4 is always less than the voltage of the second terminal of the fourth switch M4, so the fourth switch M4 remains on. The latch will not spontaneously flip, and the third output terminal VA remains high based on the turned-on second switch M2.

[0068] In some embodiments, the node voltages and states of the specific first switch M1, second switch M2, third switch M3 and fourth switch M4 can be referred to Tables 1, 2, 3 and 4.

[0069] In Table 1, the rated operating voltage (BV) of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 is 2.5V, V1 is 0.65 times the rated operating voltage, and V2 is 0. VA = VM = VY = Vo1 = V1 = 0.65 * BV. Vo2 = V2 = 0. VN = VX = VZ = 0.325 * BV. The resistance values ​​of the fifth resistor RX1, the sixth resistor RX2, the eighth resistor RX3, and the ninth resistor RX4 are equal. The resistance values ​​of the seventh resistor RY1 and the tenth resistor RY2 are equal. The resistance values ​​of the third resistor RZ1 and the fourth resistor RZ2 are equal.

[0070] Table 1:

[0071]

[0072] Among them, the gate-source voltage VGS of the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 is not greater than the rated operating voltage (BV), and the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 can operate safely.

[0073] In Table 2, the rated operating voltage (BV) of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 is 2.5V, V1 is 0, and V2 is 0.65 times the rated operating voltage. VA = VM = VY = Vo1 = V1 = 0.65 * BV. Vo2 = V2 = 0. VN = VX = VZ = 0.325 * BV. The resistance values ​​of the fifth resistor RX1, the sixth resistor RX2, the eighth resistor RX3, and the ninth resistor RX4 are equal. The resistance values ​​of the seventh resistor RY1 and the tenth resistor RY2 are equal. The resistance values ​​of the third resistor RZ1 and the fourth resistor RZ2 are equal.

[0074] Table 2:

[0075]

[0076] Among them, the gate-source voltage VGS of the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 is not greater than the rated operating voltage (BV), and the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 can operate safely.

[0077] In Table 3, the rated operating voltage (BV) of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 is 2.5V, V1 is twice the rated operating voltage, and V2 is 0. VA = VM = VY = Vo1 = V1 = 2 * BV. Vo2 = V2 = 0. VN = VX = VZ = BV. The resistance values ​​of the fifth resistor RX1, the sixth resistor RX2, the eighth resistor RX3, and the ninth resistor RX4 are equal. The resistance values ​​of the seventh resistor RY1 and the tenth resistor RY2 are equal. The resistance values ​​of the third resistor RZ1 and the fourth resistor RZ2 are equal.

[0078] Table 3:

[0079]

[0080] Among them, the gate-source voltage VGS of the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 is not greater than the rated operating voltage (BV), and the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 can operate safely.

[0081] In Table 4, the rated operating voltage (BV) of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 is 2.5V, V1 is 0, and V2 is twice the rated operating voltage. VA = VM = VY = Vo1 = V1 = 2 * BV. Vo2 = V2 = 0. VN = VX = VZ = BV. The resistance values ​​of the fifth resistor RX1, the sixth resistor RX2, the eighth resistor RX3, and the ninth resistor RX4 are equal. The resistance values ​​of the seventh resistor RY1 and the tenth resistor RY2 are equal. The resistance values ​​of the third resistor RZ1 and the fourth resistor RZ2 are equal.

[0082] Table 4:

[0083]

[0084] Among them, the gate-source voltage VGS of the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 is not greater than the rated operating voltage (BV), and the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 can operate safely.

[0085] Based on Tables 1 to 4, under the conditions of a first power supply V1 / second power supply V2 at 0.65 to 2 times the rated operating voltage BV, Figure 3 The dual-power latch works normally.

[0086] In some embodiments, certain complementary metal-oxide-semiconductor (CMOS) devices can operate at a voltage slightly higher than the rated operating voltage BV, i.e., at approximately 1.3 times the rated operating voltage BV. This 0.3*BV margin above the rated operating voltage BV can improve the safety of the VGS of the first switch M1 and the second switch M2 during the transition between two stable states. Therefore, in CMOS processes, Figure 3 The third protection resistors of the first switching transistor M1 and the second switching transistor M2 in the latch, namely the first resistor RG1 and the second resistor RG2, can also be omitted.

[0087] For example, Figure 4 A latch structure that omits the first resistor RG1 and the second resistor RG2 is shown. (Reference) Figure 4 ,and Figure 3 The latch structure shown is different, Figure 4 In the latch shown, the cross-coupling module does not include a first resistor RG1 and a second resistor RG2. That is, the cross-coupling module includes a first switch M1 and a second switch M2, and the third terminal of the first switch M1 is connected to the first terminal of the second switch M2, and the third terminal of the second switch M2 is connected to the first terminal of the first switch M1.

[0088] The aforementioned latch, with its first switch M1, second switch M2, third switch M3, and fourth switch M4, can operate safely under signals from the first power supply V1 and the second power supply V2 without the risk of breakdown, thus increasing the power supply voltage and output voltage of existing latches. Furthermore, while increasing the upper limit of the power supply voltage range, it does not increase input / output voltage path losses and ensures that the lower limit of the power supply voltage range remains unchanged. The circuit structure is simple and does not introduce bias circuits for external voltage or current sources.

[0089] In some embodiments, the latch may further include a filtering module, which can filter the voltage output from the third output terminal, thereby improving the stability of the output voltage.

[0090] For example, Figure 5 A latch structure with a filtering module is shown. (Reference) Figure 5 ,and Figure 3 The latch structure shown is different, Figure 5 In the latch shown, the third output terminal VA is electrically connected to the filter module, so that the filter module can filter the voltage output from the third output terminal.

[0091] The filtering module may include capacitor and diode units.

[0092] For example, Figure 6 The circuit structure of a filtering module is shown, such as... Figure 6 As shown, the filtering module may include a first capacitor C1, a second capacitor C2, a first diode unit, and a second diode unit. The first terminal of the first capacitor C1 is electrically connected to the third output terminal, the second terminal of the first capacitor C1 is electrically connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is grounded. The first diode unit is connected in parallel with the first capacitor C1, the second diode unit is connected in parallel with the second capacitor C2, and the first diode unit and the second diode unit are connected in series.

[0093] refer to Figure 6The first diode unit may include a first diode D1, a second diode D2, and a third diode D3. The second diode unit includes a fourth diode D4, a fifth diode D5, and a sixth diode D6. The first terminal of the first capacitor C1 is electrically connected to the first terminal of the first diode D1. The second terminal of the first diode D1 is electrically connected to the first terminal of the second diode D2. The second terminal of the second diode D2 is electrically connected to the first terminal of the third diode D3. The second terminal of the first capacitor C1 is electrically connected to the second terminal of the third diode D3. The first terminal of the second capacitor C2 is electrically connected to the first terminal of the fourth diode D4. The second terminal of the fourth diode D4 is electrically connected to the first terminal of the fifth diode D5. The second terminal of the fifth diode D5 is electrically connected to the first terminal of the sixth diode D6.

[0094] refer to Figure 5 As shown, this latch can filter the voltage output from the third output terminal through a filtering module, providing it for subsequent electronic components. The capacitors can be 2.5V metal-oxide-semiconductor capacitors (MOSCAPs) using advanced technology, instead of passive metal-insulator-metal capacitors (MIMCAPs). A stacked diode configuration can be used to increase the voltage withstand capability; a single-stage MOSCAP has a withstand voltage of approximately 3V, while a two-stage MOSCAP can operate at voltages above 5V. Multiple diodes can provide a defined bias voltage across the MOSCAP, with more than two diode stages, the specific number determined by the acceptable level of power supply leakage.

[0095] It is understood that the first diode unit may include a greater or lesser number of diodes, and similarly, the second diode unit may include a greater or lesser number of diodes. That is, the first diode unit may include at least two diodes connected in series, and the second diode unit may include at least two diodes connected in series.

[0096] Furthermore, the number of capacitors is the same as the number of diode units. In this embodiment, the number of capacitors and diode units in the filter module are not specifically limited.

[0097] It's understandable that in practical applications, such as during rapid power switching, the voltage at the third output terminal VA might fail to return to zero during initialization. For example, when the first power supply V1 is 0V, a periodic square wave pulse signal with a period of 5-30ns and a large voltage amplitude might appear at the first power supply V1 terminal. Due to the latch's response time limitations, the pulse signal may not necessarily turn on the P-type MOSFET. During rapid switching of the first power supply V1, the voltage at the third output terminal VA is charged through resistors RX1, RX2, RX3, and RX4. Furthermore, when a capacitor module is connected in parallel at the third output terminal VA for power filtering, the capacitor module can store charge. Therefore, when the latch switches to a stable state, the abnormal initial state of the third output terminal VA may cause the latch to malfunction. To avoid this problem, diodes can be placed in the first and second voltage divider modules to ensure that the initial voltage at the third output terminal VA returns to zero at any given time.

[0098] For example, Figure 7 A latch circuit structure incorporating diodes in a voltage divider module is shown. (Reference) Figure 7 ,and Figure 3 The latch structure shown is different, Figure 7 In the latch shown, the fifth resistor RX1 and the seventh diode D7 are connected in series, the sixth resistor RX2 and the eighth diode D8 are connected in series, the eighth resistor RX3 and the ninth diode D9 are connected in series, and the ninth resistor RX4 and the tenth diode D10 are connected in series. This effectively blocks the charging of the third output terminal VA by rapidly switching power supply voltages, ensuring that the third output terminal VA mostly only performs discharging operations, thus maximizing the guarantee that the initial voltage of the third output terminal VA is zero at any given time. It is understood that the number of diodes can be set as needed, for example, it can be any number from 1 to 4. In this embodiment, no specific limitation is made.

[0099] It is understood that the latches and logic circuits disclosed in this application have broad application prospects in fields such as wireless communication technology, electromagnetic compatibility testing, and RF switch design.

[0100] In some embodiments of this application, a logic circuit is also provided, which includes the latch proposed in the above embodiments.

[0101] In some embodiments of this application, a chip is also provided that includes the latch proposed in the above embodiments.

[0102] In some embodiments of this application, an electronic device is also provided, including the chip described above.

[0103] Various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or combinations of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0104] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0105] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0106] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0107] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0108] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0109] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

[0110] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A latch, characterized in that, The latch includes: a first voltage divider module, a second voltage divider module, and a cross-coupling module; The first voltage divider module includes a first input terminal and a first output terminal. The first input terminal is used to be electrically connected to the first power module. The first power module is used to output a first control signal, and the first voltage divider module is used to step down the voltage of the first control signal. The second voltage divider module includes a second input terminal and a second output terminal. The second input terminal is used to be electrically connected to the second power module. The second power module is used to output a second control signal, and the second voltage divider module is used to step down the voltage of the second control signal. The cross-coupling module includes a third input terminal, a fourth input terminal, and a third output terminal. The first output terminal is electrically connected to the third input terminal, and the second output terminal is electrically connected to the fourth input terminal. The cross-coupling module is used to be in a first stable state or a second stable state under the action of the first control signal and the second control signal. In the first stable state, the third output terminal outputs a first voltage, which is obtained based on the first control signal. In the second stable state, the third output terminal outputs a second voltage, which is obtained based on the second control signal.

2. The latch according to claim 1, characterized in that, The cross-coupling module includes a first switch and a second switch, wherein the first terminal of the first switch is configured as the third input terminal, and the first terminal of the second switch is configured as the fourth input terminal; The first terminal of the first switching transistor is electrically connected to the third terminal of the second switching transistor, the first terminal of the second switching transistor is electrically connected to the third terminal of the first switching transistor, and the second terminals of both the first and second switching transistors are electrically connected to the third output terminal.

3. The latch according to claim 2, characterized in that, The cross-coupling module further includes a first resistor and a second resistor; The first terminal of the first switching transistor is electrically connected to the third terminal of the second switching transistor through the first resistor; The first terminal of the second switching transistor is electrically connected to the third terminal of the first switching transistor through the second resistor.

4. The latch according to claim 2 or 3, characterized in that, The first voltage divider module includes a third switching transistor, and the second voltage divider module includes a fourth switching transistor; The first terminal of the third switch is configured as the first input terminal, the second terminal of the third switch is configured as the first output terminal, and the second terminal of the third switch is electrically connected to the first terminal of the first switch. The first terminal of the fourth switch is configured as the second input terminal, and the second terminal of the fourth switch is configured as the second output terminal; The second terminal of the fourth switching transistor is electrically connected to the first terminal of the second switching transistor. The third terminal of the third switching transistor is electrically connected to the third terminal of the fourth switching transistor.

5. The latch according to claim 2 or 3, characterized in that, The latch also includes a filtering module, and the third output terminal is electrically connected to the filtering module. The filtering module is used to filter the voltage output from the third output terminal.

6. The latch according to claim 5, characterized in that, The filtering module includes a first capacitor, a second capacitor, a first diode unit, and a second diode unit; The first terminal of the first capacitor is electrically connected to the third output terminal, the second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded. The first diode unit is connected in parallel with the first capacitor, the second diode unit is connected in parallel with the second capacitor, and the first diode unit and the second diode unit are connected in series. The first diode unit includes at least two diodes connected in series, and the second diode unit includes at least two diodes connected in series.

7. The latch according to claim 6, characterized in that, The first diode unit includes a first diode, a second diode, and a third diode, and the second diode unit includes a fourth diode, a fifth diode, and a sixth diode; The first terminal of the first capacitor is also electrically connected to the first terminal of the first diode, the second terminal of the first diode is electrically connected to the first terminal of the second diode, the second terminal of the second diode is electrically connected to the first terminal of the third diode, and the second terminal of the first capacitor is electrically connected to the second terminal of the third diode. The first terminal of the second capacitor is electrically connected to the first terminal of the fourth diode, the second terminal of the fourth diode is electrically connected to the first terminal of the fifth diode, and the second terminal of the fifth diode is electrically connected to the first terminal of the sixth diode.

8. The latch according to claim 1, characterized in that, When the first control signal is high and the second control signal is low, the cross-coupling module is in the first stable state.

9. The latch according to claim 1, characterized in that, When the first control signal is low and the second control signal is high, the cross-coupling module is in the second stable state.

10. A logic circuit, characterized in that, Includes the latch as described in any one of claims 1-9.

11. A chip, characterized in that, Includes the latch as described in any one of claims 1-9.

12. An electronic device, characterized in that, The electronic device includes the chip as described in claim 11.

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