A method for preventing error and avoiding layer stacking of multi-layer interconnection HDI-FPC

Abstract

The application discloses a kind of interlayer error-proof avoidance lamination methods of multilayer interconnection HDI-FPC, and it is related to printed circuit board technical field.The application includes: before the multilayer flexible circuit board is laminated, the asymmetric layer in it is preprocessed, and the through perspective avoidance structure is preformed on the asymmetric layer, the position of perspective avoidance structure corresponds with the inner layer detection mark of multilayer flexible circuit board;During the multilayer lamination process, the visual detection system reads the inner layer detection mark through the perspective avoidance structure, to identify and layer rectification the pose of each layer circuit independently.The application eliminates the shielding and visual blind area of the upper layer non-transparent substrate to the inner layer target, breaks the traditional global single reference control mode, establishes the layer independent correction and rectification mechanism, prevents the intermediate layer deviation from subsequent lamination conduction accumulation, greatly reduces the micro-hole hole deviation and open-short circuit defect, significantly improves the product yield of high-order multilayer HDI-FPC.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board technology, and in particular to a method for interlayer error prevention and avoidance stacking of multilayer interconnect HDI-FPC. Background Technology

[0002] High-end multilayer interconnect HDI-FPCs have been widely used in high-end consumer electronics and automotive electronics due to their advantages of being thin, flexible, and having high-density wiring. The manufacturing process of HDI-FPCs typically involves multiple lamination and pressing processes of multi-core boards and multiple layers of pure adhesive (or cover film). However, traditional HDI-FPC multilayer lamination processing suffers from the following key technical challenges: 1. In multilayer stacking, the non-transparent PI / copper foil substrate of the upper layer is very likely to block the optical detection marks and fixture alignment holes that have been made in the inner layer, which makes it impossible for the visual recognition system to directly read the core target of the inner layer and to achieve independent recognition and individual correction of each layer.

[0003] 2. Traditional equipment mostly uses a single global reference hole, lacking a layer error tracing and layer correction mechanism. Once the intermediate layer experiences a slight displacement during transfer, adsorption, or resin flow, all subsequent layers will experience continuous displacement, causing the alignment tolerance to exceed the IPC standard, which in turn leads to blind hole alignment errors and open / short circuit defects.

[0004] Therefore, how to overcome visual occlusion between layers and achieve independent layer recognition and correction is a core technical problem that urgently needs to be solved to improve the yield of high-end HDI-FPC products. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides an interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPCs, the specific technical solution of which is as follows: A method for interlayer error prevention and avoidance stacking in a multilayer interconnected HDI-FPC includes the following steps: S100: Before the multilayer flexible circuit board is stacked, the asymmetric layer is pre-processed, and a through-hole perspective avoidance structure is pre-opened on the asymmetric layer; wherein, the position of the perspective avoidance structure corresponds to the position of the inner layer detection mark of the multilayer flexible circuit board. S200: The asymmetric layer and the inner circuit board are stacked in multiple layers. During the stacking process, the inner layer detection mark is read through the perspective avoidance structure by the vision inspection system to independently identify and correct the pose of each layer of circuits.

[0006] Preferably: The perspective avoidance structure is an avoidance through hole; The clearance through-hole includes a fixture clearance through-hole corresponding to the alignment hole of the bottom fixture, and a detection clearance through-hole corresponding to the inner detection target; A colored identification ring is coated circumferentially around the edge of the detection avoidance through hole. The colored identification ring is formed by mixing and curing a low-modulus elastic material with pigment.

[0007] Preferably: The perspective avoidance structure is an avoidance seam; From the outermost asymmetric layer to the innermost layer, the length of the avoidance joint in each layer decreases progressively in a step-like manner; Wherein, the extension length of the nth layer avoidance seam is greater than the extension length of the (n+1)th layer avoidance seam, and the perspective coverage of the nth layer avoidance seam simultaneously covers the (n+1)th layer avoidance seam and the colored identification mark set at the end of the (n+1)th layer avoidance seam, so as to form a visibility chain that can be read sequentially from top to bottom after overlapping, where n≥1.

[0008] Preferably: The width of the clearance joint is 0.30 mm to 0.40 mm; Both ends of the avoidance joint are rounded transition ends; The colored identification mark is formed by curing a colored stress-relieving material coated on the arc transition end; the colored stress-relieving material covers the inside of the arc transition end and extends outward from the seam.

[0009] Preferably: One end of the avoidance joint is provided with the colored identification mark, and the other end is coated with a colorless or substrate-colored stress relief material with the same mechanical modulus as the colored stress relief material.

[0010] Preferably: The elastic modulus of the colored stress relief material and the stress relief material after curing is less than or equal to 1.5 GPa, and its elastic modulus is lower than that of the polyimide substrate of the flexible circuit board. The colored stress-relieving material is made from the following components: matrix resin, curing agent, toughening agent, inorganic pigment, thixotropic agent, and coupling agent.

[0011] Preferably, the colored stress-relieving material comprises the following components by weight: 100 parts of matrix resin, 10-20 parts of toughening agent composed of core-shell rubber or carboxyl-terminated nitrile rubber, 5-15 parts of inorganic oxide pigment, 1-3 parts of fumed silica thixotropic agent, 0.5-1 parts of silane coupling agent, and an anhydride or imidazole curing agent added in equivalent amounts, wherein the matrix resin is a mixture of bisphenol A type epoxy resin and carbitol-modified flexible long-chain epoxy resin.

[0012] Preferably: In the same step, at least three of the aforementioned avoidance seams are pre-opened on the same asymmetric layer; There is an angle of 45° to 90° between the extension directions of at least two of the avoidance seams.

[0013] Preferably: There are four avoidance joints on the same layer, which are distributed sequentially at the four corners of the board edge. The four avoidance joints extend in alternating vertical directions.

[0014] Preferably, the end application process of the avoidance joint includes: S10: The clearance seam and the rounded transition ends at both ends are precisely machined by mechanical drilling or laser windowing. S20: Plasma cleaning is used to remove adhesive residue and residual copper powder; S30: Stress-relieving material is applied from the inside of the clearance joint end to the outside through dispensing or stencil printing to form a smooth transition end. S40: Pre-curing and positioning are performed, followed by final curing during the multi-layer lamination and pressing process.

[0015] The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC provided by this invention has the following beneficial effects: 1. The problem of the upper non-transparent substrate obscuring the inner target was solved, eliminating the visual blind spot between layers, enabling the visual inspection system to directly read the inner core target through the structure, and realizing the independent identification of the target in each layer; 2. Breaking away from the traditional global single-reference control mode, a layered independent correction and closed-loop deviation correction mechanism was established to prevent the intermediate layer deviation from being transmitted and accumulated to subsequent layers. This stabilized the stacking alignment tolerance of high-order multilayer HDI-FPC within a very small range, significantly reducing micro-via deviation and open / short circuit defects, and improving the yield and consistency of high-end HDI flexible boards. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art are briefly introduced below.

[0017] Figure 1 A schematic diagram of the structure of a multilayer interconnect HDI-FPC provided for an embodiment of the present invention; Figure 2 for Figure 1 A magnified view of part A in the middle; Figure 3 A schematic diagram of the detection avoidance through hole provided in an embodiment of the present invention; Figure 4A schematic diagram of the structure of a multilayer interconnect HDI-FPC provided for another embodiment of the present invention; Figure 5 for Figure 4 Enlarged view of the layout of section B; Figure 6 A schematic diagram of the clearance joint provided for an embodiment of the present invention.

[0018] Figure Labels 10-Perspective avoidance structure; 11-Detection avoidance through hole; 12-Avoidance seam; 20-Asymmetric layer. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0020] It should be noted that similar labels in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] Please see Figures 1-6 This embodiment provides an interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC, including the following steps: S100: Before the multilayer flexible circuit board is stacked, the asymmetric layer 20 is pre-processed, and a through-hole perspective avoidance structure 10 is pre-opened on the asymmetric layer 20; wherein, the position of the perspective avoidance structure 10 corresponds to the position of the inner layer detection mark of the multilayer flexible circuit board.

[0022] S200: The asymmetric layer 20 is stacked with the inner circuit board in multiple layers. During the stacking process, the vision inspection system reads the inner layer inspection mark without obstruction through the perspective avoidance structure 10, so as to realize the independent identification of the pose of each layer of circuit and the layered closed-loop correction.

[0023] Specifically, referring to step S100, before the formal lamination of the multilayer flexible printed circuit board (HDI-FPC), the asymmetric layer 20 (e.g., the L2 layer composed of a single-sided adhesive-free substrate) is pre-processed. This pre-processing includes pre-forming a through-hole transparent clearance structure 10 on the asymmetric layer 20 using precision mechanical drilling or laser windowing. The position of this transparent clearance structure in physical space corresponds vertically to the position of the inner layer detection marks (such as inner layer optical mark points, detection targets, PTH via monitoring holes, LDI optical identification points) etched on the inner layer circuit board (such as the L3 / L4 core board layer) and the bottom fixture alignment holes (such as D holes).

[0024] Referring to step S200, during the subsequent layer-by-layer lamination of the asymmetric layer 20 with each inner circuit board and the pure adhesive layer, the perspective avoidance structure 10 pre-processed on the asymmetric layer 20 allows the imaging optical path of the visual inspection system (such as a CCD camera) positioned above to penetrate the asymmetric layer 20 without obstruction, directly capturing and reading the core detection mark or target on the innermost core board. Based on the extracted inner target coordinates, the visual inspection system can independently calculate the real-time pose deviation of the inner circuit board (including X-axis translation, Y-axis translation, and in-plane rotation angle). It drives the alignment platform to perform closed-loop dynamic correction, corrects the pose, and then performs lamination.

[0025] Furthermore, the geometry of the perspective avoidance structure 10 is not limited to a regular circular hole, but also includes slits extending along a specific direction, elliptical windows, rectangular frames, or polygonal avoidance slots, as long as the opening space allows the light path of the vision inspection system to penetrate and expose the marking area of ​​the lower layer. In the multilayer interconnected HDI-FPC structure, the asymmetric layer 20 can be the second layer (L2), the penultimate layer (such as the L6 layer in a 7-layer board), or any asymmetric single-sided / double-sided substrate layer in an intermediate shielding / transition state.

[0026] Advantageously, by pre-establishing a perspective avoidance structure 10 corresponding to the inner layer detection mark in the asymmetric layer 20: 1. The problem of the upper non-transparent substrate obscuring the inner target was solved, eliminating the visual blind spot between layers, enabling the visual inspection system to directly read the inner core target through the structure, and realizing the independent identification of the target in each layer; 2. Breaking away from the traditional global single-reference control mode, a layered independent correction and closed-loop deviation correction mechanism was established to prevent the intermediate layer deviation from being transmitted and accumulated to subsequent layers. This stabilized the stacking alignment tolerance of high-order multilayer HDI-FPC within a very small range, significantly reducing micro-via deviation and open / short circuit defects, and improving the yield and consistency of high-end HDI flexible boards.

[0027] Further, please see Figure 2 and Figure 3 : The perspective avoidance structure 10 is an avoidance through hole.

[0028] The clearance through-hole includes a fixture clearance through-hole corresponding to the alignment hole of the bottom fixture, and a detection clearance through-hole 11 corresponding to the inner layer detection target.

[0029] A colored identification ring is coated around the edge of the detection avoidance through hole 11. The colored identification ring is formed by mixing and curing a low-modulus elastic material with pigment to enhance the visual detection contrast and buffer the stress concentration at the edge of the avoidance through hole.

[0030] Specifically, when the perspective avoidance structure 10 is an avoidance through hole, the avoidance through hole includes two types of through holes with different sizes opened on the asymmetric layer 20: the first type is a fixture avoidance through hole corresponding to the positioning pin of the bottom fixture (such as a Φ2.0mm~Φ3.5mm round hole), and the second type is a detection avoidance through hole for perspective exposure of the inner layer detection target and the etched inspection ring (such as a Φ1.5mm~Φ3.5mm round hole).

[0031] To address the issue of microcracks easily forming at the edges of conventionally drilled holes under lamination stress, a ring-shaped colored identification ring can be coated circumferentially around the edge of the through-hole (including the annular area on the inner wall and the upper surface of the hole opening). This colored identification ring is formed by dotting / screen printing and curing a mixture of a low-modulus elastic material and inorganic oxide pigment.

[0032] Furthermore, the cross-sectional shape of the avoidance through hole is not limited to a circle; it can also be a square hole, an oblong hole, or a polygonal through hole. The coating width of the color identification ring is recommended to be 0.15 mm to 0.35 mm, and the protrusion height is controlled to be ≤15 μm to avoid the formation of local steps on the board surface during lamination.

[0033] Beneficially, the color recognition circle forms an elastic protective band around the hole edge at the physical level, significantly reducing stress concentration on the flexible substrate at the hole edge and preventing crack initiation. On the other hand, the color recognition circle forms a strong color gradient contrast with the inner copper foil or PI background, enabling the edge extraction algorithm of the vision system (such as the Hough circle transform algorithm) to quickly lock the hole center reference, reducing noise interference and misjudgment rate in image detection.

[0034] Furthermore: The perspective avoidance structure 10 is an avoidance seam 12 extending in a specific direction.

[0035] From the outermost asymmetric layer 20 to the innermost layer, the length of the avoidance joint 12 in each layer gradually decreases in a stepped manner.

[0036] Wherein, the extension length of the nth layer avoidance seam 12 is greater than the extension length of the (n+1)th layer avoidance seam 12, and the perspective coverage of the nth layer avoidance seam 12 simultaneously covers the (n+1)th layer avoidance seam 12 and the color identification mark set at the end of the (n+1)th layer avoidance seam 12, so as to form a visibility chain that can be read sequentially from top to bottom after overlapping, where n≥1.

[0037] Specifically, when the perspective avoidance structure 10 is an avoidance seam 12 extending along a specific direction (such as the X-axis or Y-axis direction), the avoidance seams 12 on each layer gradually decrease in size in a step-like manner.

[0038] In the top-down superimposed field of view, the length of the avoidance gap 12 of the upper layer (nth layer) is longer than that of the avoidance gap 12 of the lower layer (n+1th layer). In the spatial projection, the avoidance gap 12 of the nth layer not only completely includes the opening of the avoidance gap 12 of the n+1th layer, but also extends to cover the colored identification mark set at the end of the avoidance gap 12 of the n+1th layer.

[0039] Furthermore, the formula for calculating the length of the avoidance seam 12 is divided into the following two types based on the layout of the colored dots at the ends: 1. Single-end small dot (the avoidance seam 12 has a colored identification mark on only one end):

[0040] Where D is the effective diameter or longitudinal length of the color identification mark (usually 0.6 mm to 1.0 mm), and S is the tolerance safety margin (usually 0.10 mm to 0.25 mm).

[0041] 2. Double-ended small dots (identification marks of different or the same color are provided at both ends of the avoidance seam 12):

[0042] The visual inspection system scans layer by layer from the outermost to the innermost layer according to the color wavelength threshold: the color mark of the second layer (such as red) is seen through the first layer gap, the color mark of the third layer (such as blue) is seen through the second layer gap, and so on, forming a "visibility chain" on a one-dimensional line.

[0043] Beneficially, the traditional two-dimensional large-area opening is reduced to a one-dimensional slit window, which greatly saves the physical space of the waste edge area of ​​the board and improves the layout utilization rate of the flexible board; at the same time, the "visibility chain" enables one-time rapid verification of the alignment status of multiple layers.

[0044] Furthermore, the width of the clearance joint 12 is controlled between 0.30 mm and 0.40 mm. Both ends of the clearance joint 12 are smooth arc transition ends with an arc radius R ≥ 0.3 mm, which eliminates stress concentration at right-angled sharp corners from a geometrical perspective.

[0045] The color identification mark is formed by curing a color stress-relieving material coated on the arc transition end; the color stress-relieving material covers the inside of the arc transition end and extends outward to reduce stress concentration at the seam end and prevent the substrate from tearing.

[0046] Furthermore: When the colored identification mark is only set at one end of the clearance joint 12, one end of the clearance joint 12 is coated with a colored stress-relieving material containing pigment (forming a colored mark), while the other end is coated with a colorless stress-relieving material or a stress-relieving material of the same color as the PI substrate. The mechanical elastic modulus and rheological properties of the two materials after curing are consistent, so that the two ends of the clearance joint 12 achieve symmetrical stress balance and buffer crack prevention protection.

[0047] Furthermore, the geometry of the colored identification mark and the end stress buffer point is not limited to a circle; it can also be elliptical, teardrop-shaped, rectangular with an expanded hole, or an extended teardrop shape. As long as the adhesive covers the edge of the seam head from the inside out and extends outward (extension ≥ 0.3 mm), it is acceptable.

[0048] Furthermore: The elastic modulus of the colored stress relief material and the cured stress relief material is less than or equal to 1.5 GPa, and its elastic modulus is lower than that of the polyimide substrate of the flexible circuit board.

[0049] Specifically, the elastic modulus of the cured colored stress-relieving material is preferably 0.8 GPa~1.5 GPa (far lower than the 2.5 GPa~3.0 GPa of PI substrate), and the glass transition temperature is... It has a temperature of ≥150℃ and can withstand a pressing temperature of 260℃ and vacuum plasma cleaning.

[0050] Furthermore, the components of the colored stress-relieving material, by mass parts, include: Matrix resin (100 parts): Bisphenol A type epoxy resin (such as E-51) and flexible carbitol modified epoxy resin are mixed at a mass ratio of 7:3; Curing agent (at an equivalent ratio of 1:1): latent imidazole or acid anhydride curing agent; Toughening agent (10-20 parts): Core-shell rubber (CSR) nanoparticles or carboxyl-terminated nitrile butadiene rubber (CTBN); Inorganic pigments (5-15 parts): Iron oxide red, titanium blue, titanium dioxide, chrome green, and other high-temperature resistant inorganic pigments (color difference at 260℃ for 30 minutes). ); Thixotropic agent (1-3 parts): Fumed silica (to control colloidal thixotropy and prevent flow); Coupling agent (0.5~1 part): Silane coupling agent KH-550.

[0051] Preparation steps: The matrix resin and toughening agent are vacuum stirred and degassed at 100℃ for 2 hours; after cooling to room temperature, inorganic pigments and thixotropic agents are added, and the mixture is ground 3 times with a three-roll mill until the particle size is < 5 μm; finally, curing agent and coupling agent are added, and after high-speed stirring and degasing, the mixture is loaded into syringes for later use.

[0052] Beneficially, this material system has extremely low elastic modulus and high toughness, excellent compatibility with pure rubber (Dongyi P15 series), is resistant to acid and alkali cleaning and does not contaminate the circuit area, effectively solving the contradiction between "optical path marking" and "mechanical buffering".

[0053] Furthermore: In the same step, at least three clearance joints 12 are pre-opened on the same asymmetric layer 20.

[0054] Among them, at least two avoidance seams 12 have an included angle of 45° to 90° between their extension directions, which is used to simultaneously capture the displacement caused by X-axis translation, Y-axis translation, in-plane rotation and anisotropic expansion and contraction of the substrate through multi-angle vector redundancy.

[0055] Furthermore: There are 4 avoidance joints 12 on the same layer, which are distributed sequentially in the four corner areas of the board edge.

[0056] The extension directions of the four avoidance joints 12 are arranged alternately at 0°, 90°, 0°, and 90°; and the relative positional tolerance between each avoidance joint 12 in the same layer is controlled within ≤30 μm.

[0057] Specifically, three or four avoidance joints 12 are pre-drilled on the same asymmetrical layer 20 and arranged sequentially in the non-circuit areas at the four corners of the board edge. The avoidance joints are arranged alternately at 0°, 90°, 0°, 90° (or at a 45° angle to the coordinate axis).

[0058] The algorithm flow for the visual inspection system to solve multi-slit arrays is as follows: 1. Image acquisition and color segmentation: The camera captures images from the four corner areas and extracts the target color channels (such as red / blue markers) based on the HSV color space. 2. Centroid Coordinate Fitting: The centroid coordinates of each colored endpoint are fitted using the least squares method. ; 3. Deviation vector matrix calculation: Constructing a matrix including X-axis translation Y-axis translation In-plane rotation angle and the coefficient of expansion and contraction of flexible boards Kinematic equations for solving the problem:

[0059] 4. Closed-loop compensation: The calculated offset vector is fed back to the alignment platform in real time for correction.

[0060] Beneficially, the orthogonal / oblique vector array layout covers the anisotropic expansion and contraction and rotational offset unique to FPC; multi-slot redundancy avoids the verification failure caused by offset in a single direction, ensuring that the "visibility chain" has a very high fault tolerance.

[0061] Furthermore, the process of applying the clearance seam 12 to its ends includes: S10: The clearance joint 12 and the rounded transition ends at both ends are precisely machined by mechanical drilling or laser windowing.

[0062] S20: Plasma cleaning is used to remove adhesive residue and residual copper powder.

[0063] S30: By applying adhesive or printing on a steel mesh, stress-relieving material is applied from the inside of the end of the clearance joint 12 outwards to form a smooth transition end point with an extension length ≥0.3 mm (the protrusion height is controlled within ≤15 μm).

[0064] S40: Pre-curing and shaping by baking at 120℃~150℃ for 10~20 minutes, followed by final curing during multi-layer lamination and pressing.

[0065] Specific embodiments are provided below. These embodiments are intended to enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way.

[0066] Preparation Example 1 In a reactor equipped with nitrogen protection and a stirrer, 134.2 g of diethylene glycol monoethyl ether (carbitol) and 277.5 g of epichlorohydrin were added, and the mixture was heated to 65°C. 1.5 g of tetrafluoroborate diethyl ether solution was slowly added dropwise, and the reaction was maintained at 70°C for 4 h after the addition was complete. The system was then cooled to 45°C, and 48.0 g of solid sodium hydroxide powder was added in portions for further reaction, with vigorous stirring continued for 3 h. After the reaction was complete, the precipitate was removed by filtration. The filtrate was distilled at 90°C and -0.098 MPa to remove unreacted excess epichlorohydrin and solvent. After washing with water, separation, and concentration under reduced pressure, carbitol glycidyl ether modified flexible epoxy resin was finally obtained, with an epoxy equivalent of 198 g / eq.

[0067] Preparation Example 2 70.0 g of bisphenol A type epoxy resin (E-51), 30.0 g of carbitol glycidyl ether modified flexible epoxy resin from Preparation Example 1, and 15.0 g of carboxyl-terminated butadiene-acrylonitrile rubber liquid resin (CTBN 1300x13) were added to a stirred tank. The mixture was heated to 100°C and stirred and degassed under a vacuum of -0.095 MPa for 120 min to obtain a transparent and homogeneous premix. The premix was cooled to 45°C, and 10.0 g of iron oxide red powder, 2.0 g of fumed silica (AEROSIL R972), and 0.8 g of silane coupling agent (KH-550) were added sequentially. After high-speed shear dispersion for 30 min, the mixture was milled three times using a three-roll mill. Subsequently, the mixture was cooled to 25°C, and 4.5 g of 2-ethyl-4-methylimidazolium (2E4MI) latent curing agent was added. After vacuum centrifugation and degassed for 15 min, a low-modulus red stress-relieving colloid was obtained. A portion of the adhesive was pre-cured at 140℃ for 15 min, then transferred to 160℃ for 60 min of curing. The tensile modulus of the cured specimen was measured to be 1.15 GPa, and the glass transition temperature was [not specified]. The color difference was measured at 156.4℃ after pressing at 260℃ for 30 minutes. .

[0068] Preparation Example 3 Using the same component amounts and process conditions as in Preparation Example 2, 70.0 g of E-51 epoxy resin, 30.0 g of the flexible epoxy resin from Preparation Example 1, and 15.0 g of CTBN 1300x13 liquid rubber were stirred and degassed for 120 min at 100°C and -0.095 MPa. After cooling to 45°C, 2.0 g of fumed silica R972 and 0.8 g of KH-550 coupling agent (without adding iron oxide red powder) were added. After high-speed shearing and grinding, 4.5 g of 2E4MI curing agent was added at 25°C, followed by centrifugation and degassed to obtain a highly transparent, colorless stress-relieving colloid. The tensile modulus of its cured specimen was tested to be 1.12 GPa, and the glass transition temperature was [not specified]. At 158.1℃, the peel strength to the PI substrate is 1.48 N / mm.

[0069] Example 1

[0070] In the production of HDI-FPC products, a single-sided adhesive-free rolled copper foil substrate (copper thickness 12.00 μm, PI thickness 12.5 μm) was used as the substrate for the second layer (L2) circuit layer. Before the L2 layer circuit film was exposed, pre-processing holes were performed using a precision CNC drilling machine according to the drilling program. This included four inspection clearance vias with a diameter of 3.50 mm (located corresponding to the LDI optical mark points and etched inspection rings of the inner L3 / L4 layers), and four fixture clearance vias with a diameter of 2.00 mm (corresponding to the PIN positioning D holes of the bottom layer stacked fixture). After drilling, the holes were roughened and deburred by a plasma vacuum cleaning chamber. Using a pneumatic precision dispensing machine, the red stress-relieving adhesive of Preparation Example 2 was applied to the inner wall and circumferential annular area of ​​each clearance via. The coating ring width was 0.25 mm, and the protrusion height was controlled to be less than 10 μm. Subsequently, the holes were pre-cured in a 140°C oven for 15 min to form a smooth red protective ring. In the lamination process, the pre-processed L2 layer, AD2-3 pure adhesive (15 μm thick), and the L3 / L4 core board layers with completed circuit etching are laminated with pins. During the lamination process, the core target on the innermost L3 / L4 layer is read through a 3.50 mm red protective ring by a top-mounted CCD vision system. Finally, the laminate is pressed and cured at 160℃ and 2.5 MPa for 120 min to obtain the laminated board.

[0071] Example 2

[0072] Produce HDI-FPC products of the same specifications as in Example 1. Four extending slits (avoidance slits) are precisely machined on the L2 layer single-sided adhesive-free substrate using a CNC UV laser cutting machine. The width of the avoidance slits is uniformly controlled at 0.35 mm, with smooth rounded ends at both ends. The four avoidance slits are arranged sequentially at the four corners of the board edge, with their extension directions alternating orthogonally at 0°, 90°, 0°, and 90°. Avoidance slit length for each layer: innermost layer (L3 / L4 layer) avoidance slit length... L2 layer avoidance joint length (Where the endpoint diameter D = 0.80 mm, and the safety margin S = 0.15 mm). After laser cutting, the edge adhesive residue was removed by vacuum plasma cleaning. Using a double-headed precision dispensing machine, the red adhesive of Preparation Example 2 was applied to one end of the arc-shaped seam of the L2 layer avoidance seam, covering the inside of the seam head and extending 0.35 mm outward to form a red circular endpoint with a diameter of 0.80 mm. At the same time, the colorless adhesive of Preparation Example 3 was applied to the other end of the arc-shaped seam of the same avoidance seam, with the same outward extension of 0.35 mm. Then, the adhesive was pre-cured at 130°C for 12 min to fix the shape of the adhesive. During lamination, the window of the upper avoidance seam completely exposed the red endpoint of the lower avoidance seam and the lower seam head. Finally, the multilayer lamination was completed by pressing at 160°C for 120 min.

[0073] Example 3

[0074] Produce HDI-FPC products of the same specifications as in Example 1. The processing steps and testing methods in this example are the same as in Example 2, the only difference being that the avoidance seams use a design with colored markings at both ends. Avoidance seam lengths for each layer: Inner layer (L3 / L4 layer) seam length L2 layer avoidance joint length After laser cutting and plasma cleaning, the red adhesive from Preparation Example 2 was applied to both ends of the L2 layer's avoidance seam using a dual-head dispensing machine, covering the seam ends and extending 0.35 mm outwards to form red circular endpoints with a diameter of 0.80 mm. It was then pre-cured at 130°C for 12 minutes to fix the shape. During lamination, the avoidance seam window of the upper layer simultaneously revealed the avoidance seam of the lower layer and its two red endpoints. Finally, the laminated board was pressed and cured at 160°C for 120 minutes to complete the fabrication.

[0075] Example 4

[0076] Produce HDI-FPC products of the same specifications as in Example 1. The processing steps and testing methods in this example are the same as in Example 2, except that the extension directions of the four pre-processed clearance seams on the L2 layer are arranged at 45°, 135°, 45°, and 135° obliquely to the board coordinate axis, and the included angle between adjacent clearance seams is 90°. The other clearance seam dimensions, dispensing extension parameters, and pre-curing / lamination bonding conditions are the same as in Example 2.

[0077] Comparative Example 1 The HDI-FPC product with the same specifications as in Example 1 was produced. The processing steps and testing methods for this comparative example were the same as in Example 2, except that the coating material at the ends of the clearance joint was not the low-modulus adhesive used in Example 2, but a conventional epoxy underfill adhesive (with a tensile modulus of 3.20 GPa after curing) was directly selected. The dispensing extension dimensions and subsequent lamination and pressing conditions were consistent with those in Example 2.

[0078] Comparative Example 2 Produce HDI-FPC products of the same specifications as in Example 1. The processing steps and testing methods for this comparative example are the same as in Example 2, except that the red colloid of Example 2 is applied only to one end of the L2 layer's avoidance seam (extending 0.35 mm), while the other end remains exposed. The remaining seam dimensions and lamination conditions are consistent with those of Example 2.

[0079] Comparative Example 3 Produce HDI-FPC products of the same specifications as in Example 1. The processing steps and testing methods for this comparative example are the same as in Example 2, the only difference being that the clearance joints on each layer are of the same length. The ends of the clearance seams were coated with the colorless colloid of Preparation Example 3. The remaining lamination and pressing conditions were the same as in Example 2.

[0080] Performance tests were conducted on the laminated boards and finished HDI-FPCs fabricated in each embodiment and comparative example. The test items included: 1. Alignment tolerance (μm): The misalignment between the blind hole and the target between each layer is measured using an X-ray inspection instrument; 2. Tear rate of seam end after thermal shock (%): After 500 cycles of thermal shock from -55℃ to 125℃, the proportion of tearing and cracking of the substrate at the seam end was observed by cross-section. 3. Vision system recognition error rate (%): The CCD camera continuously captured 1000 sets of samples, and the error rate of edge extraction and color recognition was calculated.

[0081] The test data is shown in Table 1:

[0082] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be within the scope of protection of the present invention.

Claims

1. A method for interlayer error prevention and avoidance stacking of multilayer interconnected HDI-FPC, characterized in that, Includes the following steps: S100: Before the multilayer flexible circuit board is stacked, the asymmetric layer (20) is pre-processed, and a through-hole perspective avoidance structure (10) is pre-opened on the asymmetric layer (20); wherein the position of the perspective avoidance structure (10) corresponds to the position of the inner layer detection mark of the multilayer flexible circuit board; S200: The asymmetric layer (20) is stacked with the inner circuit board in multiple layers. During the stacking process, the inner layer detection mark is read through the perspective avoidance structure (10) by the vision detection system to independently identify and correct the pose of each layer of the circuit.

2. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 1, characterized in that: The perspective avoidance structure (10) is an avoidance through hole; The clearance through hole includes a fixture clearance through hole corresponding to the alignment hole of the bottom fixture, and a detection clearance through hole (11) corresponding to the inner detection target. A colored identification ring is circumferentially coated on the edge of the detection avoidance through hole (11), the colored identification ring being formed by mixing and curing a low modulus elastic material with pigment.

3. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 1, characterized in that: The perspective avoidance structure (10) is an avoidance seam (12); From the outermost asymmetric layer (20) to the innermost layer, the length of the avoidance joint (12) in each layer decreases in a stepwise manner; The extension length of the nth layer avoidance seam (12) is greater than the extension length of the (n+1)th layer avoidance seam (12), and the perspective coverage of the nth layer avoidance seam (12) simultaneously covers the (n+1)th layer avoidance seam (12) and the color identification mark set at the end of the (n+1)th layer avoidance seam (12), so as to form a visibility chain that can be read sequentially from top to bottom after overlapping, where n≥1.

4. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 3, characterized in that: The width of the clearance joint (12) is 0.30 mm to 0.40 mm; Both ends of the avoidance joint (12) are rounded transition ends; The colored identification mark is formed by curing a colored stress-relieving material coated on the arc transition end; the colored stress-relieving material covers the inside of the arc transition end and extends outward from the seam.

5. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 4, characterized in that: One end of the avoidance seam (12) is provided with the colored identification mark, and the other end is coated with a colorless or substrate-colored stress relief material with the same mechanical modulus as the colored stress relief material.

6. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 4 or 5, characterized in that: The elastic modulus of the colored stress relief material and the stress relief material after curing is less than or equal to 1.5 GPa, and its elastic modulus is lower than that of the polyimide substrate of the flexible circuit board. The colored stress-relieving material is made from the following components: matrix resin, curing agent, toughening agent, inorganic pigment, thixotropic agent, and coupling agent.

7. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 6, characterized in that, The colored stress-relieving material comprises the following components by weight: 100 parts of matrix resin, 10-20 parts of toughening agent composed of core-shell rubber or carboxyl-terminated nitrile rubber, 5-15 parts of inorganic oxide pigment, 1-3 parts of fumed silica thixotropic agent, 0.5-1 parts of silane coupling agent, and an anhydride or imidazole curing agent added in equivalent amounts, wherein the matrix resin is a mixture of bisphenol A type epoxy resin and carbitol-modified flexible long-chain epoxy resin.

8. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 3, characterized in that: In the same step, at least three of the aforementioned clearance seams (12) are pre-opened on the same asymmetric layer (20). There is an angle of 45° to 90° between the extension directions of at least two of the avoidance seams (12).

9. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to claim 8, characterized in that: The number of avoidance joints (12) on the same layer is 4, which are distributed sequentially in the four corner areas of the board edge; The four avoidance joints (12) are arranged in alternating vertical directions.

10. The interlayer error prevention and avoidance stacking method for multilayer interconnected HDI-FPC according to any one of claims 3 to 9, characterized in that, The end application process of the avoidance joint (12) includes: S10: The clearance joint (12) and the rounded transition ends at both ends are precisely machined by mechanical drilling or laser windowing; S20: Plasma cleaning is used to remove adhesive residue and residual copper powder; S30: By applying glue or printing on a steel mesh, stress-relieving material is applied from the inside of the avoidance joint (12) end to the outside and extends outward to form a smooth transition end point; S40: Pre-curing and positioning are performed, followed by final curing during the multi-layer lamination and pressing process.

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