Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a lower structure including a lower word line, a lower local bit line, and a lower storage unit connected to the lower word line and the lower local bit line; an upper structure including an upper word line, an upper local bit line, and an upper storage unit connected to the upper word line and the upper local bit line; and an intermediate structure disposed between the lower structure and the upper structure. The intermediate structure includes a word line selection circuit electrically connected to the lower word line and the upper word line, and a sub-word line driver electrically connected to the word line selection circuit.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure relate to a semiconductor device including a memory cell and a selection circuit, and a method of manufacturing the semiconductor device. Background Technology

[0002] Research has been ongoing to reduce the size of components included in semiconductor devices and improve their performance. For example, in DRAM, research has been conducted to reliably and stably form components with reduced sizes; however, as component sizes decrease, the dispersion properties of semiconductor devices may deteriorate. Summary of the Invention

[0003] The example embodiment provides a semiconductor device with improved integration density.

[0004] An example embodiment provides a method for manufacturing a semiconductor device.

[0005] According to an example embodiment, a semiconductor device includes: a lower structure including a lower bonding layer; an intermediate structure disposed on the lower structure and including a first intermediate bonding layer bonded to the lower bonding layer and a second intermediate bonding layer opposite to the first intermediate bonding layer; and an upper structure disposed on the intermediate structure and including an upper bonding layer bonded to the second intermediate bonding layer, wherein the lower structure further includes lower memory cells arranged in a first direction, a second direction, and a perpendicular direction intersecting each other, wherein the intermediate structure further includes a first peripheral circuit, and wherein the upper structure further includes lower memory cells arranged in the first direction, a second direction, and a perpendicular direction intersecting each other. The upper storage cell is arranged in the second direction and the vertical direction, wherein each of the lower bonding layer and the first intermediate bonding layer includes a dielectric material and does not include a bonding metal material, wherein each of the second intermediate bonding layer and the upper bonding layer includes a bonding dielectric layer and a bonding metal pattern, the bonding dielectric layer including a dielectric material and the bonding metal pattern including a bonding metal material, wherein the bonding dielectric layer of the second intermediate bonding layer is bonded to the bonding dielectric layer of the upper bonding layer, and wherein the bonding metal pattern of the second intermediate bonding layer is bonded to the bonding metal pattern of the upper bonding layer.

[0006] According to an example embodiment, a semiconductor device includes: a lower structure including a lower word line, a lower local bit line, and a lower memory cell connected to the lower word line and the lower local bit line; an upper structure including an upper word line, an upper local bit line, and an upper memory cell connected to the upper word line and the upper local bit line; and an intermediate structure disposed between the lower structure and the upper structure, wherein the intermediate structure includes: a word line selection circuit electrically connected to the lower word line and the upper word line; and a sub-word line driver electrically connected to the word line selection circuit.

[0007] According to an example embodiment, a semiconductor device includes: a lower structure including a lower bonding layer; an intermediate structure disposed on the lower structure and including a first intermediate bonding layer bonded to the lower bonding layer and a second intermediate bonding layer opposite to the first intermediate bonding layer; and an upper structure disposed on the intermediate structure and including an upper bonding layer bonded to the second intermediate bonding layer, wherein the lower structure further includes: lower memory cells arranged in a first direction, a second direction, and a vertical direction intersecting each other; a lower word line connected to the lower memory cells; and a lower local bit line connected to the lower memory cells. The storage unit, wherein the intermediate structure further includes a first peripheral circuit, wherein the upper structure further includes: an upper storage unit arranged in the first direction, the second direction, and the vertical direction; an upper word line connected to the upper storage unit; an upper local bit line connected to the upper storage unit; and a second peripheral circuit disposed at a height higher than the height of the upper storage unit, wherein the first peripheral circuit includes: a sub-word line selection circuit electrically connected to the lower word line and the upper word line; and a sub-word line driver connected to the sub-word line selection circuit.

[0008] According to an example embodiment, a method of manufacturing a semiconductor device includes: forming a lower structure including a lower memory cell and a lower bonding layer; forming a preliminary intermediate structure including a first peripheral circuit and a first intermediate bonding layer; forming a first bonding structure by performing a first wafer bonding process for bonding the lower bonding layer to the first intermediate bonding layer; forming a second intermediate bonding layer on the preliminary intermediate structure of the first bonding structure; forming an upper structure including an upper memory cell, a second peripheral circuit, and an upper bonding layer; and forming a second bonding structure by performing a second wafer bonding process for bonding the second intermediate bonding layer and the upper bonding layer.

[0009] Each of the lower bonding layer and the first intermediate bonding layer may include a dielectric material and may not include a bonding metal material.

[0010] The second intermediate bonding layer may include a first bonding dielectric layer and a first bonding metal pattern. The upper bonding layer may include a second bonding dielectric layer and a second bonding metal pattern. The first bonding dielectric layer and the second bonding dielectric layer may be bonded to each other by the second wafer bonding process, and the first bonding metal pattern and the second bonding metal pattern may be bonded to each other by the second wafer bonding process.

[0011] The lower structure may further include: a lower word line connected to the lower memory cell; and a lower local bit line connected to the lower memory cell. The upper structure may further include: an upper word line connected to the upper memory cell; and an upper local bit line connected to the upper memory cell.

[0012] The first peripheral circuit may include a sub-word line selection circuit and a sub-word line driver connected to the sub-word line selection circuit.

[0013] The first peripheral circuit may further include a bit line selection circuit and a bit line sense amplifier connected to the bit line selection circuit.

[0014] The initial upper structure may further include upper global bit lines connected to the upper local bit lines. The upper global bit lines may be formed after the upper memory cell and the second peripheral circuitry are formed.

[0015] Forming the upper structure may include: forming an upper memory cell on a preliminary upper semiconductor body; forming an upper semiconductor body by reducing the thickness of the preliminary upper semiconductor body; forming a second peripheral circuit on the upper semiconductor body; and forming the upper bonding layer.

[0016] The upper semiconductor body can be disposed between the upper storage unit and the second peripheral circuit.

[0017] The second intermediate bonding layer may include a first bonding dielectric layer and a first bonding metal pattern.

[0018] Forming the upper bonding layer may include: forming an insulating structure covering the upper memory cell on the upper semiconductor body; forming a second bonding dielectric layer on the insulating structure; and forming a second bonding metal pattern coplanar with the upper surface of the second bonding dielectric layer. The first bonding dielectric layer and the second bonding dielectric layer may be bonded to each other by the second wafer bonding process, and the first bonding metal pattern and the second bonding metal pattern may be bonded to each other by the second wafer bonding process.

[0019] The method may further include forming an upper interconnect. After forming the second bonding structure, the upper interconnect may be formed on the upper semiconductor body. Attached Figure Description

[0020] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 5 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 6 This is a cross-sectional view showing a semiconductor device according to an example embodiment; Figure 7 , Figure 8A and Figure 8B This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 9 , Figure 10 and Figure 11 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 12 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 13 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 14 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 15 This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C and Figure 21 This is a diagram illustrating a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0021] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0022] In the following text, terms such as “upper,” “middle,” and “lower” may be replaced with other terms such as “first,” “second,” and “third” to describe the elements in the example embodiments. Terms such as “first,” “second,” and “third” can be used to describe various elements, but the elements are not limited by the terms, and “first element” may be referred to as “second element.” In the example embodiments, terms such as “lower,” “upper,” “upper end,” and “lower end” may be described based on the accompanying drawings. The terms “lower,” “upper,” “upper end,” and “lower end” are described based on the accompanying drawings.

[0023] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B A semiconductor device according to an example embodiment is described. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B middle, Figure 1 This is a perspective view illustrating a semiconductor device according to an example embodiment. Figure 2A This is a diagram illustrating the vertical arrangement of semiconductor devices according to an example embodiment. Figure 2B It is a diagram of an example circuit including a semiconductor device according to an example embodiment. Figure 3A This is a diagram illustrating the vertical arrangement of semiconductor devices according to an example embodiment, and Figure 3B It is a diagram of an example circuit including a semiconductor device according to an example embodiment. Figure 2A and Figure 2B This is a diagram showing the sub-word line driver SWD and the word line selection circuit WSC, and Figure 3A and Figure 3B This diagram shows the bit line sense amplifier BLSA and the bit line selection circuit BLSC.

[0024] refer to Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The semiconductor device 1 according to the example embodiment may include a lower structure STC1, an intermediate structure STC2 located on the lower structure STC1, and an upper structure STC3 located on the intermediate structure STC2. The lower structure STC1, the intermediate structure STC2, and the upper structure STC3 may be arranged sequentially in the vertical direction Z.

[0025] The lower structure STC1 and the middle structure STC2 can be joined together to form a first joining region JNC1, and the middle structure STC2 and the upper structure STC3 can be joined together to form a second joining region JNC2.

[0026] Semiconductor device 1 may include a plurality of memory cells BA. Each of the plurality of memory cells BA may include a first memory cell region BA1 located in the lower structure STC1, a second memory cell region BA2 located in the intermediate structure STC2, and a third memory cell region BA3 located in the upper structure STC3.

[0027] The first memory region BA1 of the lower structure STC1 may include a lower memory cell MC1 arranged in three dimensions, and the third memory region BA3 of the upper structure STC3 may include an upper memory cell MC2 arranged in three dimensions. The second memory region BA2 of the intermediate structure STC2 may include a first peripheral circuit PC1 for operating the lower memory cell MC1 and the upper memory cell MC2.

[0028] The lower structure STC1 may also include a lower word line WL_L connected to the lower memory cell MC1 and a lower local bit line LBL_L connected to the lower memory cell MC1.

[0029] The lower structure STC1 may also include a lower global bit line GBL_L electrically connected to the lower local bit line LBL_L at a height higher than the height of the lower memory cell MC1 and the height of the lower local bit line LBL_L.

[0030] The upper structure STC3 may also include an upper word line WL_U connected to the upper memory cell MC2 and an upper local bit line LBL_U connected to the upper memory cell MC2.

[0031] The upper structure STC3 may also include an upper global bit line GBL_U that is electrically connected to the upper local bit line LBL_U at a height lower than the height of the upper memory cell MC2 and the height of the upper local bit line LBL_U.

[0032] Each lower local bit line LBL_L can be connected to the lower memory cell MC1 arranged in the vertical direction Z.

[0033] Each lower global bit line GBL_L can be connected to N lower local bit lines LBL_L. N can be a natural number of 2 or greater.

[0034] Each upper local bit line LBL_U can be connected to the upper memory cell MC2 arranged in the vertical direction Z.

[0035] Each upper global bit line GBL_U can be connected to N upper local bit lines LBL_U.

[0036] The lower character line WL_L may include a first lower character line WL_L1, a second lower character line WL_L2, a third lower character line WL_L3, and a fourth lower character line WL_L4 arranged sequentially in a direction away from the intermediate structure STC2.

[0037] The upper character line WL_U may include a first upper character line WL_U1, a second upper character line WL_U2, a third upper character line WL_U3, and a fourth upper character line WL_U4 arranged sequentially in the direction away from the intermediate structure STC2.

[0038] The first peripheral circuit PC1 of the intermediate structure STC2 may include a word line select circuit WSC and a sub-word line driver SWD connected to the word line select circuit WSC.

[0039] The lower word line WL_L can be electrically connected to the word line selection circuit WSC via the lower word line interconnect structure RI_L_WL. The upper word line WL_U can be electrically connected to the word line selection circuit WSC via the upper word line interconnect structure RI_U_WL.

[0040] Each word line select circuit (WSC) may include a first word line select transistor (STw1) electrically connected to the corresponding lower word line WL_L and a second word line select transistor (STw2) electrically connected to the corresponding upper word line WL_U. The first word line select transistor (STw1) and the second word line select transistor (STw2) may be configured to operate in a complementary manner.

[0041] In the example embodiment, when the first word line select transistor STw1 is in the on state and the second word line select transistor STw2 is in the off state, the lower word line WL_L can be connected to the sub-word line driver SWD, and the upper word line WL_U can be disconnected from the sub-word line driver SWD.

[0042] In the example embodiment, when the first word line select transistor STw1 is in the off state and the second word line select transistor STw2 is in the on state, the lower word line WL_L can be disconnected from the sub-word line driver SWD, and the upper word line WL_U can be connected to the sub-word line driver SWD.

[0043] In an example embodiment, a sub-word line driver SWD can be connected to a selected word line among the lower word line WL_L and the upper word line WL_U via a word line selection circuit WSC connected to the sub-word line driver SWD.

[0044] The word line selection circuit WSC may include a first word line selection circuit WSC1, a second word line selection circuit WSC2, a third word line selection circuit WSC3, and a fourth word line selection circuit WSC4.

[0045] The first word line selection circuit WSC1 can be electrically connected to the first lower word line WL_L1 and the first upper word line WL_U1. The second word line selection circuit WSC2 can be electrically connected to the second lower word line WL_L2 and the second upper word line WL_U2. The third word line selection circuit WSC3 can be electrically connected to the third lower word line WL_L3 and the third upper word line WL_U3. The fourth word line selection circuit WSC4 can be electrically connected to the fourth lower word line WL_L4 and the fourth upper word line WL_U4.

[0046] The sub-word line driver SWD may include a first sub-word line driver SWD1 connected to a first word line selection circuit WSC1, a second sub-word line driver SWD2 connected to a second word line selection circuit WSC2, a third sub-word line driver SWD3 connected to a third word line selection circuit WSC3, and a fourth sub-word line driver SWD4 connected to a fourth word line selection circuit WSC4.

[0047] Each sub-word line driver SWD may include a PMOS transistor PT, a first NMOS transistor NT1, and a second NMOS transistor NT2. A drive signal PXID may be connected to the source terminal of the PMOS transistor PT, a selected word line among the lower word line WL_L and the upper word line WL_U may be electrically connected to the drain terminal of the PMOS transistor PT, and a word line enable signal NWEIB may be connected to the gate terminal of the PMOS transistor PT. The PMOS transistor PT may be a pull-up transistor. A pre-charge voltage corresponding to the reverse path voltage VBB2 may be connected to the source terminal of the first NMOS transistor NT1, a selected word line among the lower word line WL_L and the upper word line WL_U may be electrically connected to the drain terminal of the first NMOS transistor NT1, and a word line enable signal NWEIB may be connected to the gate terminal of the first NMOS transistor NT1. The first NMOS transistor NT1 may be a pull-down transistor. The complementary drive signal PXIB can be connected to the gate terminal of the second NMOS transistor NT2, the precharge voltage corresponding to the reverse path voltage VBB2 can be connected to the source terminal of the second NMOS transistor NT2, and the selected word line among the lower word line WL_L and the upper word line WL_U can be electrically connected to the drain terminal of the second NMOS transistor NT2.

[0048] The second NMOS transistor NT2 can be a holding transistor used to maintain the selected word line at a ground voltage level when the selected word line among the lower word line WL_L and the upper word line WL_U is not selected. The second NMOS transistor NT2 can be connected in parallel to the first NMOS transistor NT1. Each sub-word line driver SWD can drive the selected word line among the lower word line WL_L and the upper word line WL_U in response to the word line enable signal NWEIB and the drive signal PXID. The PMOS transistor PT can pull the selected word line among the lower word line WL_L and the upper word line WL_U to the level of the drive signal PXID in response to the word line enable signal NWEIB. The first NMOS transistor NT1 can pull the selected word line among the lower word line WL_L and the upper word line WL_U to the level of the negative voltage VBB2 in response to the word line enable signal NWEIB. The second NMOS transistor NT2, which can act as a holding transistor, can maintain the selected word line of the lower word line WL_L and the upper word line WL_U at a negative voltage VBB2 level when the selected word line becomes inactive. For this purpose, the second NMOS transistor NT2 can switch between its source, which provides the negative voltage VBB2, and its drain, which is electrically connected to the selected word line of the lower word line WL_L and the upper word line WL_U, in response to a drive signal PXIB complementary to the drive signal PXID.

[0049] The circuitry of the sub-word line driver SWD described above may be an example embodiment, and the circuitry of the sub-word line driver SWD may be implemented using various circuit elements.

[0050] The first peripheral circuit PC1 of the intermediate structure STC2 may also include a bit line select circuit BLSC and a bit line sense amplifier BLSA connected to the bit line select circuit BLSC.

[0051] The bit line select circuit BLSC can be electrically connected to the lower global bit line GBL_L and the upper global bit line GBL_U. The lower global bit line GBL_L can be connected to the bit line select circuit BLSC via the lower bit line interconnect structure RI_L_BL. The upper global bit line GBL_U can be connected to the bit line select circuit BLSC via the upper bit line interconnect structure RI_U_BL.

[0052] Each bit line sense amplifier (BLSA) can be electrically connected to a pair of global bit lines selected by the bit line selection circuit (BLSC) from the lower global bit line (GBL_L) and the upper global bit line (GBL_U) connected to the bit line sense amplifier (BLSA), depending on the operation of the corresponding bit line selection circuit (BLSC) in the bit line selection circuit (BLSC), and can also be not electrically connected to a pair of global bit lines not selected by the bit line selection circuit (BLSC).

[0053] Each bit-line sense amplifier (BLSA) can be connected to M global bit lines, including the lower global bit line GBL_L and the upper global bit line GBL_U. In the example, "M" can be a natural number of 4 or greater.

[0054] Each bit-line sense amplifier (BLSA) may include multiple sense amplifier transistors P1_a, P1_b, N1_a, and N1_b. The sense amplifier transistors P1_a, P1_b, N1_a, and N1_b may include a first PMOS transistor P1_a and a second PMOS transistor P1_b, a first NMOS transistor N1_a, and a second NMOS transistor N1_b.

[0055] Each bit line selection circuit BLSC may include a selection transistor STb.

[0056] Each bit line select circuit (BLSC) may include a first select circuit (SC1) and a second select circuit (SC2). In each BLSC, the first select circuit (SC1) may include a first lower select transistor (STb1) connected to the first lower global bit line GBL_L1 in the lower global bit line GBL_L and a second lower select transistor (STb2) connected to the second lower global bit line GBL_L2 in the lower global bit line GBL_L.

[0057] In each bit line selection circuit BLSC, the second selection circuit SC2 may include a first up selection transistor STb3 connected to the first upper global bit line GBL_U1 in the upper global bit line GBL_U and a second up selection transistor STb4 connected to the second upper global bit line GBL_U2 in the upper global bit line GBL_U.

[0058] The following will describe the interconnected first bit line sense amplifier BLSA1 and first bit line select circuit BLSC1 in the bit line sense amplifier BLSA and bit line select circuit BLSC.

[0059] The first PMOS transistor P1_a and the second PMOS transistor P1_b can be referred to as a PMOS transistor pair, and the first NMOS transistor N1_a and the second NMOS transistor N1_b can be referred to as an NMOS transistor pair.

[0060] The source of the first PMOS transistor P1_a and the source of the second PMOS transistor P1_b can be connected to the first control line LA through the first node ND1_a. The source of the first NMOS transistor N1_a and the source of the second NMOS transistor N1_b can be connected to the second control line LAB through the second node ND1_b. The first node ND1_a and the second node ND1_b can be referred to as the first source node and the second source node, respectively.

[0061] According to the operation of the first bit selection circuit BLSC1, the drain of the first PMOS transistor P1_a and the drain of the first NMOS transistor N1_a can be connected to one of the first lower global bit line GBL_L1, the second lower global bit line GBL_L2, the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 through the first drain node ND1_c.

[0062] According to the operation of the first bit selection circuit BLSC1, the drain of the second PMOS transistor P1_b and the drain of the second NMOS transistor N1_b can be connected to one of the first lower global bit line GBL_L1, the second lower global bit line GBL_L2, the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 through the second drain node ND1_d. It can be a complementary bit line among the first lower global bit line GBL_L1, the second lower global bit line GBL_L2, the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2.

[0063] In the example embodiment, depending on the operation of the first line selection circuit BLSC1, the first line sense amplifier BLSA1 can be connected to one of the selected global bit lines among the first lower global bit line GBL_L1, the second lower global bit line GBL_L2, the first upper global bit line GBL_U1, and the second upper global bit line GBL_U2, and may not be connected to one of the unselected global bit lines.

[0064] In the example embodiment, depending on the operation of the first line selection circuit BLSC1, the first line sense amplifier BLSA1 can be connected to a pair of global bit lines, namely the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2, and can be disconnected from the pair of global bit lines, namely the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2.

[0065] In the example embodiment, depending on the operation of the first line selection circuit BLSC1, the first line sense amplifier BLSA1 may not be connected to a pair of global bit lines, namely the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2, but may be connected to a pair of global bit lines, namely the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2.

[0066] In the example embodiment, depending on the operation of the first line selection circuit BLSC1, the first line sense amplifier BLSA1 can be connected to a pair of global bit lines, namely the first lower global bit line GBL_L1 and the first upper global bit line GBL_U1, and can be disconnected from the pair of global bit lines, namely the second lower global bit line GBL_L2 and the second upper global bit line GBL_U2.

[0067] In the example embodiment, depending on the operation of the first line selection circuit BLSC1, the first line sense amplifier BLSA1 may not be connected to a pair of global bit lines, namely the first lower global bit line GBL_L1 and the first upper global bit line GBL_U1, but may be connected to a pair of global bit lines, namely the second lower global bit line GBL_L2 and the second upper global bit line GBL_U2.

[0068] In the example embodiment, the upper selection transistors STb3 and STb4 and the lower selection transistors STb1 and STb2 can be configured to operate in a complementary manner. For example, when the first upper selection transistor STb3 and the second upper selection transistor STb4 of the second selection circuit SC2 are in the off state and the first lower selection transistor STb1 and the second lower selection transistor STb2 of the first selection circuit SC1 are in the on state, the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2 can be a pair of global bit lines selected by the first first line selection circuit BLSC1 and electrically connected to the first first line sense amplifier BLSA1, and the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 can be a pair of global bit lines not selected by the first first line selection circuit BLSC1 and electrically isolated from the first first line sense amplifier BLSA1. For example, when the first upper selection transistor STb3 and the second upper selection transistor STb4 of the second selection circuit SC2 are in the off state and the first lower selection transistor STb1 and the second lower selection transistor STb2 of the first selection circuit SC1 are in the on state, the drain of the first PMOS transistor P1_a and the drain of the first NMOS transistor N1_a can be connected to the first lower global bit line GBL_L1 through the first drain node ND1_c, and the drain of the second PMOS transistor P1_b and the drain of the second NMOS transistor N1_b can be connected to the second lower global bit line GBL_L2, which can be a complementary bit line, through the second drain node ND1_d.

[0069] When the first upper selection transistor STb3 and the second upper selection transistor STb4 of the second selection circuit SC2 are in the on state and the first lower selection transistor STb1 and the second lower selection transistor STb2 of the first selection circuit SC1 are in the off state, the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2 can be a pair of global bit lines that are not selected by the first bit line selection circuit BLSC1 and are electrically isolated from the first bit line sense amplifier BLSA1, and the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 can be a pair of global bit lines that are selected by the first bit line selection circuit BLSC1 and electrically connected to the first bit line sense amplifier BLSA1.

[0070] When the first line sense amplifier BLSA1 is electrically connected to the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2 through the first line selection circuit BLSC1, but is not electrically connected to the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 through the first line selection circuit BLSC1, the first line sense amplifier BLSA1 can sense the voltage change of the first lower global bit line GBL_1 and amplify the sensed voltage.

[0071] When the first line sense amplifier BLSA1 is not electrically connected to the first lower global bit line GBL_L1 and the second lower global bit line GBL_L2 through the first line selection circuit BLSC1, but is electrically connected to the first upper global bit line GBL_U1 and the second upper global bit line GBL_U2 through the first line selection circuit BLSC1, the first line sense amplifier BLSA1 can sense the voltage change of the first upper global bit line GBL_U1 and amplify the sensed voltage.

[0072] When the first line sense amplifier BLSA1 performs sensing and amplification operations, the internal power supply voltage can be applied to the first node ND1_a via the first control line LA, and the second node ND1_b can be connected to the ground terminal via the second control line LAB. The first line sense amplifier BLSA1 may include pairs of PMOS transistors and pairs of NMOS transistors, and can be implemented as circuit elements in which the transistors are cross-coupled to each other, but its exemplary embodiments are not limited thereto. For example, the circuitry of the first line sense amplifier BLSA1 can be implemented using various circuit elements.

[0073] The upper structure STC3 may also include a second peripheral circuit PC2. The second peripheral circuit PC2 may include circuitry for data or command input / output or power / ground input. The second peripheral circuit PC2 may be positioned at a height higher than that of the upper storage unit MC2.

[0074] Reference Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 5 The above description is for reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B An example embodiment of the semiconductor device 1 is described. Regarding... Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 5 , Figure 4AThis is a cross-sectional view showing an example embodiment of the semiconductor device 1 described above. Figure 4B It is shown Figure 4A A magnified view of region "A" in the image. Figure 4C It is shown Figure 4A Enlarged views of regions "A1" and "A2" in the image. Figure 4D It is shown Figure 4A A magnified view of region "B" in the image. Figure 4E It is shown Figure 4A An enlarged view of region "C" in the image, and Figure 5 This is a perspective view showing a portion of the components of the intermediate structure STC2. Figure 4A In the diagram, the cross-sectional structure taken along line I-I' represents the region cut along the second direction Y, and the cross-sectional structure taken along line II-II' represents the region cut in the first direction X, which is perpendicular to the second direction Y.

[0075] refer to Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B And also refer to Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 5 The semiconductor device 1 may include at least one memory cell array region MCA and a connection region IA adjacent to the at least one memory cell array region MCA.

[0076] At least one memory cell array region MCA can be a region in which lower memory cell MC1 and upper memory cell MC2 are configured. The lower word line WL_L can be connected to the lower memory cell MC1 in at least one memory cell array region MCA and can extend into the connection region IA.

[0077] The lower structure STC1 may also include a lower substrate 3 and a protective insulating layer 57 located below the lower substrate 3. The lower substrate 3 may be a semiconductor substrate that may include semiconductor materials such as monocrystalline silicon, but its exemplary embodiments are not limited thereto. For example, the lower substrate 3 may be an insulating substrate.

[0078] The intermediate structure STC2 may also include an intermediate semiconductor body 103. The intermediate semiconductor body 103 may include monocrystalline silicon.

[0079] The upper structure STC3 may also include an upper semiconductor body 203. The upper semiconductor body 203 may include monocrystalline silicon.

[0080] The lower storage cell MC1 can be disposed on the lower substrate 3. The lower storage cell MC1 can be arranged in three dimensions in the first direction X, the second direction Y, and the vertical direction Z.

[0081] The first direction X and the second direction Y can be parallel to the upper surface of the lower base 3, and the vertical direction Z can be perpendicular to the upper surface of the lower base 3.

[0082] The first direction X can intersect the second direction Y. For example, the first direction X can be perpendicular to the second direction Y.

[0083] The upper memory cell MC2 can be disposed below the upper semiconductor body 203. The upper memory cell MC2 can be arranged in three dimensions in the first direction X, the second direction Y, and the vertical direction Z.

[0084] Each lower memory cell MC1 may include a lower cell transistor cTRa and a lower data storage structure DSa. Each upper memory cell MC2 may include an upper cell transistor cTRb and an upper data storage structure DSb. The lower data storage structure DSa and the upper data storage structure DSb may be cell capacitors that can store data in a memory such as DRAM.

[0085] Each lower-level transistor cTRa may include a lower channel region cCHa, a first lower source / drain region cSD1a and a second lower source / drain region cSD2a, a lower gate dielectric layer 12, and a lower gate electrode WL_L. Here, the lower gate electrode WL_L may be the lower word line WL_L described above. Each upper-level transistor cTRb may include an upper channel region cCHb, a first upper source / drain region cSD1b and a second upper source / drain region cSD2b, an upper gate dielectric layer 212, and an upper gate electrode WL_U. The upper gate electrode WL_U may be the upper word line WL_U described above.

[0086] In each lower cell transistor cTRa, the first lower source / drain region cSD1a and the second lower source / drain region cSD2a can be spaced apart from each other in the second direction Y. The lower channel region cCHa can be disposed between the first lower source / drain region cSD1a and the second lower source / drain region cSD2a. The lower gate electrode (i.e., the lower word line WL_L) can overlap perpendicularly with the lower channel region cCHa, and the lower gate dielectric layer 12 can be disposed between the lower channel region cCHa and the lower word line WL_L. Each lower word line WL_L can surround the corresponding lower channel region cCHa and can extend in the first direction X. Each lower word line WL_L can have a horizontal via OPa. The lower channel region cCHa and the lower gate dielectric layer 12 can be disposed in the horizontal via OPa.

[0087] In each upper-level transistor cTRb, the first upper source / drain region cSD1b and the second upper source / drain region cSD2b can be spaced apart from each other in the second direction Y. The upper channel region cCHb can be disposed between the first upper source / drain region cSD1b and the second upper source / drain region cSD2b. The upper gate electrode (i.e., the upper word line WL_U) can overlap perpendicularly with the upper channel region cCHb, and the upper gate dielectric layer 212 can be disposed between the upper channel region cCHb and the upper word line WL_U. Each upper word line WL_U can surround a corresponding upper channel region cCHb and can extend in the first direction X. Each upper word line WL_U can have a horizontal via OPb. The upper channel region cCHb and the upper gate dielectric layer 212 can be disposed in the horizontal via OPb.

[0088] Each lower data storage structure DSa may include a first lower electrode 30 connected to the corresponding second lower source / drain region cSD2a, a second lower electrode 36 covering the first lower electrode 30, and a lower dielectric layer 33 located between the first lower electrode 30 and the second lower electrode 36. The second lower electrode 36 may be a lower plate electrode.

[0089] Each upper data storage structure DSb may include a first upper electrode 230 connected to the corresponding second upper source / drain region cSD2b, a second upper electrode 236 covering the first upper electrode 230, and an upper dielectric layer 233 located between the first upper electrode 230 and the second upper electrode 236. The second upper electrode 236 may be an upper plate electrode.

[0090] In each lower data storage structure DSa, the first lower electrode 30 may have a columnar shape extending in the second direction Y, and the second lower electrode 36 may include a first electrode material layer 34 in contact with the lower dielectric layer 33 and a second electrode material layer 35 in contact with the first electrode material layer 34. In an example embodiment, the first lower electrode 30 is not limited to a columnar shape. For example, the first lower electrode 30 may have a cylindrical shape. In each upper data storage structure DSb, the first upper electrode 230 may have a columnar shape extending in the second direction Y, and the second upper electrode 236 may include a first electrode material layer 234 in contact with the upper dielectric layer 233 and a second electrode material layer 235 in contact with the first electrode material layer 234. In an example embodiment, the first upper electrode 230 is not limited to a columnar shape. For example, the first upper electrode 230 may have a cylindrical shape.

[0091] In the lower data storage structure DSa, the lower surface of each second lower electrode 36 can be set at a height lower than the height of the lowest unit transistor in the lower unit transistor cTRa, and the upper surface of each second lower electrode 36 can be set at a height higher than the height of the highest unit transistor in the lower unit transistor cTRa. Each second lower electrode 36 can extend in the first direction X. In the upper data storage structure DSb, the upper surface of each second upper electrode 236 can be set at a height lower than the height of the lowest unit transistor in the upper unit transistor cTRb, and the upper surface of each second upper electrode 236 can be set at a height higher than the height of the highest unit transistor in the upper unit transistor cTRb. Each second upper electrode 236 can extend in the first direction X.

[0092] The lower structure STC1 may also include a lower active pattern 9. The upper structure STC3 may also include an upper active pattern 209.

[0093] The lower active pattern 9 and the upper active pattern 209 can be formed of a semiconductor material that can be used as a channel region of a transistor. For example, each of the lower active pattern 9 and the upper active pattern 209 may include a single-crystal silicon semiconductor, an oxide semiconductor, or a two-dimensional material having semiconductor properties. Each of the lower active pattern 9 and the upper active pattern 209 may have a strip shape extending in the second direction Y.

[0094] The first lower source / drain region cSD1a, the second lower source / drain region cSD2a, and the lower channel region cCHa can be disposed in the lower active pattern 9. For example, each lower active pattern 9 may include a first lower source / drain region cSD1a and a second lower source / drain region cSD2a spaced apart from each other in the second direction Y, and a lower channel region cCHa located between the first lower source / drain region cSD1a and the second lower source / drain region cSD2a.

[0095] The first upper source / drain region cSD1b, the second upper source / drain region cSD2b, and the upper channel region cCHb can be disposed in the active pattern 209. For example, each active pattern 209 may include a first upper source / drain region cSD1b and a second upper source / drain region cSD2b spaced apart from each other in the second direction Y, and an upper channel region cCHb located between the first upper source / drain region cSD1b and the second upper source / drain region cSD2b.

[0096] Each lower local bit line LBL_L can have a cylindrical shape extending in the vertical direction Z. The lower local bit lines LBL_L can be arranged in the first direction X and the second direction Y. Each upper local bit line LBL_U can have a cylindrical shape extending in the vertical direction Z. The upper local bit lines LBL_U can be arranged in the first direction X and the second direction Y.

[0097] The lower local bit line LBL_L can overlap perpendicularly with the upper local bit line LBL_U.

[0098] Each lower local bit line LBL_L can be connected to a lower memory cell MC1 arranged in the vertical direction Z. For example, each lower local bit line LBL_L can be connected to the first lower source / drain region cSD1a of the lower cell transistor cTRa. The lower local bit line LBL_L can have a recessed side surface that contacts the lower memory cell MC1.

[0099] Each upper local bit line LBL_U can be connected to an upper memory cell MC2 arranged in the vertical direction Z. For example, each upper local bit line LBL_U can be connected to the first upper source / drain region cSD1b of the upper cell transistor cTRb. The upper local bit line LBL_U can have a recessed side surface that contacts the upper memory cell MC2.

[0100] Each lower local bit line LBL_L may include a lower pillar pattern 24b and a lower conductive pad 24a covering the side surface and lower surface of the lower pillar pattern 24b. Each upper local bit line LBL_U may include an upper pillar pattern 224b and an upper conductive pad 224a covering the side surface and upper surface of the upper pillar pattern 224b.

[0101] Each of the lower conductive pad 24a and the upper conductive pad 224a may include at least one of doped polysilicon, a metal semiconductor compound, or a metal nitride. For example, each of the lower conductive pad 24a and the upper conductive pad 224a may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, or CoSi, and each of the lower pillar pattern 24b and the upper pillar pattern 224b may include a material different from the material of the lower conductive pad 24a and the upper conductive pad 224a, and may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, or CoSi.

[0102] The lower structure STC1 may also include a lower cover insulating layer 18 disposed on the lower unit transistor cTRa. The second lower electrode 36 may extend upward and penetrate the lower cover insulating layer 18. The lower local bit line LBL_L may extend upward and penetrate the lower cover insulating layer 18.

[0103] The upper structure STC3 may also include an upper cover insulating layer 224 disposed below the upper unit transistor cTRb. The second upper electrode 236 may extend downward and penetrate the upper cover insulating layer 218. The upper local bit line LBL_U may extend downward and penetrate the upper cover insulating layer 218.

[0104] The lower global bit line GBL_L can be set on the lower cover insulating layer 18. The upper global bit line GBL_U can be set below the upper cover insulating layer 218.

[0105] The lower structure STC1 may further include a lower bit line contact plug 39 disposed between the lower global bit line GBL_L and the lower local bit line LBL_L, and connecting the lower global bit line GBL_L to the lower local bit line LBL_L. Therefore, each lower global bit line GBL_L can be electrically connected to N lower local bit lines LBL_L through the lower bit line contact plug 39.

[0106] The upper structure STC3 may further include an upper line contact plug 239 disposed between the upper global bit line GBL_U and the upper local bit line LBL_U, and connecting the upper global bit line GBL_U to the upper local bit line LBL_U. Therefore, each upper global bit line GBL_U can be electrically connected to N upper local bit lines LBL_U through the upper line contact plug 239.

[0107] The lower structure STC1 may also include a lower insulating structure 51 covering the lower memory cell MC1, the lower local bit line LBL_L, the lower word line WL_L, the lower overlay insulating layer 18, and the lower global bit line GBL_L.

[0108] The upper structure STC3 may also include an upper insulating structure 251 covering the upper memory cell MC2, the upper local bit line LBL_U, the upper word line WL_U, the upper overlay insulating layer 218, and the upper global bit line GBL_U.

[0109] The intermediate semiconductor body 103 may include an intermediate active region 106a that may be defined by the device isolation region 106s.

[0110] The intermediate structure STC2 may include an intermediate transistor pTRa, which may be included in the first peripheral circuit PC1. Each intermediate transistor pTRa may include an intermediate peripheral source / drain region pSDa disposed in the corresponding intermediate active region 106a, an intermediate peripheral channel region pCHa located between the intermediate peripheral source / drain regions pSDa, and an intermediate peripheral gate pGa located on the intermediate peripheral channel region pCHa. Here, the intermediate peripheral gate pGa may include an intermediate peripheral gate electrode pGEa located on the intermediate peripheral channel region pCHa and an intermediate peripheral gate dielectric layer pGOa located between the intermediate peripheral gate electrode pGEa and the intermediate peripheral channel region pCHa.

[0111] The intermediate structure STC2 may also include an intermediate insulating structure 127 disposed on the intermediate semiconductor body 103 and covering the first peripheral circuit PC1, and a back insulating layer 112 disposed below the intermediate semiconductor body 103.

[0112] The lower structure STC1 may further include a lower bonding layer 54 disposed on the lower insulating structure 51. The intermediate structure STC2 may further include a first intermediate bonding layer 115 disposed below the back insulating layer 112 and a second intermediate bonding layer 142 disposed on the intermediate insulating structure 127. The upper structure STC3 may further include an upper bonding layer 257 disposed below the upper insulating structure 251.

[0113] The lower bonding layer 54 can be bonded to the first intermediate bonding layer 115 via a dielectric-dielectric bonding process. Therefore, a first bonding region JNC1 can be formed between the lower structure STC1 and the intermediate structure STC2.

[0114] The lower bonding layer 54 and the first intermediate bonding layer 115 may be dielectric layers that can be used as bonding layers in a dielectric-dielectric bonding process. Each of the lower bonding layer 54 and the first intermediate bonding layer 115 may include a dielectric material and may not include a bonding metal material. For example, each of the lower bonding layer 54 and the first intermediate bonding layer 115 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0115] The second intermediate bonding layer 142 may include an intermediate bonding metal pattern 139 and an intermediate bonding dielectric layer 136 that can be used as bonding layers in a hybrid bonding process including metal-to-metal bonding and dielectric-to-dielectric bonding. The upper bonding layer 257 may include an upper bonding metal pattern 245 and an upper bonding dielectric layer 254 that can be used as bonding layers in a hybrid bonding process.

[0116] Through a hybrid bonding process, the intermediate bonding metal pattern 139 can be bonded to the upper bonding metal pattern 245, and the intermediate bonding dielectric layer 136 can be bonded to the upper bonding dielectric layer 254. Therefore, a second bonding region JNC2 can be formed between the upper structure STC3 and the intermediate structure STC2.

[0117] Each of the intermediate bonding metal pattern 139 and the upper bonding metal pattern 245 may include a bonding metal (e.g., copper (Cu)) that can be used for metal-to-metal bonding in a hybrid bonding process, and the intermediate bonding dielectric layer 136 and the upper bonding dielectric layer 254 may include a bonding dielectric that can be used for dielectric-to-dielectric bonding in a hybrid bonding process. The bonding dielectric may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0118] The lower structure STC1 and the intermediate structure STC2 may include the lower routing interconnect structures RI_L_WL and RI_L_BL. The lower routing interconnect structures RI_L_WL and RI_L_BL may include the lower word routing interconnect structure RI_L_WL and the lower bit routing interconnect structure RI_L_BL described above.

[0119] Each lower-level line interconnect structure RI_L_WL may include a first lower-level line interconnect structure 48w and a second lower-level line interconnect structure 124w connected to the first lower-level line interconnect structure 48w. Each lower-level line interconnect structure RI_L_BL may include a first lower-level line interconnect structure 48b and a second lower-level line interconnect structure 124b connected to the first lower-level line interconnect structure 48b.

[0120] Each first lower word line can be connected to a corresponding lower word line WL_L via interconnect structure 48w, and each second lower word line can be connected to a corresponding first word line select transistor STw1 via interconnect structure 124w. For example, in the lower word line interconnect structure RI_L_WL, the lower word line interconnect structure RI_L_WL that electrically connects the first lower word line WL_L1 to the first word line select transistor STw1 may include a first lower word line interconnect structure 48w connected to the first lower word line WL_L1 and a second lower word line interconnect structure 124w connected to the first word line select transistor STw1.

[0121] Each first lower bit line can be connected to the corresponding lower global bit line GBL_L in the lower global bit line GBL_L by interconnect structure 48b, and each second lower bit line can be connected to the corresponding bit line select transistor in the first bit line select transistor STb1 and the second bit line select transistor STb2 by interconnect structure 124b.

[0122] The lower structure STC1 may include a first lower word line interconnect structure 48w and a first lower bit line interconnect structure 48b, and the intermediate structure STC2 may include a second lower word line interconnect structure 124w and a second lower bit line interconnect structure 124b.

[0123] Each first lower word line may include a lower gate contact plug 42w that contacts the corresponding lower word line WL_L in the lower word line WL_L, and a first lower interconnect 45w located on the lower gate contact plug 42w. Each second lower word line may include a first intermediate routing interconnect 121w connected to the first intermediate through path 118w and the first intermediate through path 118w.

[0124] Each first intermediate through-path 118w can penetrate the intermediate semiconductor body 103, can extend downward, can penetrate the first intermediate bonding layer 115 and the lower bonding layer 54, and can be connected to the corresponding first lower interconnect in the first lower interconnect 45w.

[0125] Each first intermediate route interconnect structure 121w can be connected to the corresponding first word line select transistor STw1 in the first word line select transistor STw1. For example, as Figure 5 As shown, a first intermediate routing interconnect structure 121w may include a contact plug 119a connected to a first word line select transistor STw1 and an interconnect 120a connecting the contact plug 119a to a first intermediate through-path 118w. Figure 5 In the above, the portion represented as STw1_PGa can be the peripheral gate pGa of the first word line select transistor STw1, and the portion represented as STw2_PGa can be the peripheral gate pGa of the second word line select transistor STw2.

[0126] Each first lower bit line interconnect structure 48b may include a lower bit line contact plug 42b and a second lower interconnect 45b located on the lower bit line contact plug 42b, which contact the corresponding lower global bit line GBL_L in the lower global bit line GBL_L. Each second lower bit line interconnect structure 124b may include a second intermediate route interconnect structure 121b connected to the second intermediate through-path 118b and the second intermediate through-path 118b. Each second intermediate through-path 118b may penetrate the intermediate semiconductor body 103, may extend downward, may penetrate the first intermediate bonding layer 115 and the lower bonding layer 54, and may connect to the corresponding second lower interconnect in the second lower interconnect 45b. Each second intermediate route interconnect structure 121b may connect to the corresponding bit line select transistor in the first bit line select transistor STb1 and the second bit line select transistor STb2.

[0127] The intermediate structure STC2 and the upper structure STC3 may include the upper routing interconnect structures RI_U_WL and RI_U_BL. The upper routing interconnect structures RI_U_WL and RI_U_BL may include the upper sub-routing interconnect structure RI_U_WL and the upper sub-routing interconnect structure RI_U_BL described above.

[0128] Each upper-level line interconnect structure RI_U_WL may include a first upper-level line interconnect structure 248w and a second upper-level line interconnect structure 130w connected to the first upper-level line interconnect structure 248w. Each upper-level line interconnect structure RI_U_BL may include a first upper-level line interconnect structure 248b and a second upper-level line interconnect structure 130b connected to the first upper-level line interconnect structure 248b.

[0129] Each first word line can be connected to a corresponding word line WL_U in the word line WL_U network via interconnect structure 248w, and each second word line can be connected to a corresponding second word line select transistor STw2 in the second word line select transistor STw2 network. For example, in the word line interconnect structure RI_U_WL, the word line interconnect structure RI_U_WL that electrically connects the first word line WL_U1 to the first word line select transistor STw1 may include a first word line interconnect structure 248w connected to the first word line WL_U1 and a second word line interconnect structure 130w connected to the second word line select transistor STw2.

[0130] Each first upper-level line can be connected to the corresponding upper global bit line GBL_U in the upper global bit line GBL_U by interconnect structure 248b, and each second upper-level line can be connected to the corresponding bit line selection transistor in the third bit line selection transistor STb3 and the fourth bit line selection transistor STb4 by interconnect structure 130b.

[0131] The upper structure STC3 may include a first upper word line interconnect structure 248w and a first upper host line interconnect structure 248b, and the middle structure STC2 may include a second upper word line interconnect structure 130w and a second upper host line interconnect structure 130b.

[0132] Each first upper character line may include a first upper character line interconnection structure 242w and a first upper bonding metal pattern 245w located below the first upper character line interconnection structure 242w, which are connected to the corresponding upper character line WL_U in the upper character line WL_U.

[0133] Each of the first-1 upper word line interconnect structures 242w may include an upper gate contact plug 240w that contacts the corresponding upper word line WL_U in the upper word line WL_U and a first connection structure 241w that electrically connects the upper gate contact plug 240w to the first upper bonding metal pattern 245w.

[0134] The upper gate contact plug 240w can overlap perpendicularly with the lower gate contact plug 42w.

[0135] Each second word line may include, via interconnect structure 130w, a first intermediate bonding metal pattern 139w bonded to a corresponding first upper bonding metal pattern 245w, and a second connection structure 133w electrically connecting the first intermediate bonding metal pattern 139w to the second word line select transistor STw2. For example, as Figure 5 As shown, a second connection structure 133w may include a first contact plug 119b connected to a second word line select transistor STw2, a first interconnect (also referred to as a "second intermediate routing interconnect structure") 121b located on the first contact plug 119b, a second contact plug 132a located on the first interconnect 121b, and a second interconnect 132b connecting a first intermediate bonding metal pattern 139w to the second contact plug 132a.

[0136] In an example embodiment, to improve integration density, the first intermediate through-path 118w and the first intermediate bonding metal pattern 139w may overlap perpendicularly to each other. Each first upper-level line interconnect structure 248b may include a first-1 upper-level line interconnect structure 242b connected to the corresponding upper global bit line GBL_U in the upper global bit line GBL_U, and a second upper bonding metal pattern 245b located below the first-1 upper-level line interconnect structure 242b.

[0137] Each second upper-level line may include a second intermediate bonding metal pattern 139b bonded to a corresponding second upper bonding metal pattern 245b in the second upper bonding metal pattern 245b, and a third connection structure 133b electrically connecting the second intermediate bonding metal pattern 139b to a corresponding bit line selection transistor in the third bit line selection transistor STb3 and the fourth bit line selection transistor STb4.

[0138] The upper semiconductor body 203 may include an upper active region 206a that may be defined by the device isolation region 206s.

[0139] The upper structure STC3 may include an upper transistor pTRb, which may be included in the second peripheral circuit PC2. Each upper transistor pTRb may include an upper peripheral source / drain region pSDb disposed in the upper active region 206a, an upper peripheral channel region pCHb located between the upper peripheral source / drain regions pSDb, and an upper peripheral gate pGb located on the upper peripheral channel region pCHb. Here, the upper peripheral gate pGb may include an upper peripheral gate electrode pGEb located on the upper peripheral channel region pCHb and an upper peripheral gate dielectric layer pGOb located between the upper peripheral gate electrode pGEb and the upper peripheral channel region pCHb.

[0140] The upper structure STC3 may also include an upper insulating structure 285 disposed on the upper semiconductor body 203 and covering the second peripheral circuit PC2, a routing interconnect structure 275 embedded in the upper insulating structure 285, and an upper interconnect 280 located on the routing interconnect structure 275.

[0141] The intermediate structure STC2 and the upper structure STC3 may further include a connection routing structure RI_U_c for electrically connecting the first peripheral circuit PC1 to the second peripheral circuit PC2. The connection routing structure RI_U_c may include a first connection routing structure RI_U_Ca and a second connection routing structure RI_U_Cb. The first connection routing structure RI_U_Ca and the upper word line are set at the same height by the interconnect structure RI_U_WL. The second connection routing structure RI_U_Cb is connected to the first connection routing structure RI_U_Ca, extends upward, passes through the upper semiconductor body 203, and is configured to be electrically connected to the second peripheral circuit PC2 on the upper semiconductor body 203.

[0142] The upper structure STC3 may also include pad patterns 290 for input / output.

[0143] At least one pad pattern 290 may be connected to at least one upper interconnect 280.

[0144] The pad pattern 290 may have a shape that protrudes from the upper insulating structure 285, but its exemplary embodiments are not limited thereto. For example, the pad pattern 290 may not be provided, and the area of ​​the upper interconnect 280 exposed by the opening 285a of the upper insulating structure 285 may be defined as a pad area 280P for input / output.

[0145] In the example embodiment, the intermediate transistor pTRa of the first peripheral circuit PC1 can be formed as a planar transistor, but the example embodiment is not limited thereto. For example, the intermediate transistor pTRa of the first peripheral circuit PC1 can be formed as a fin field-effect transistor (FinFET) or a gate-all-around transistor. A gate-all-around transistor can be a transistor in which the channel can be formed as nanowires or nanosheets stacked in the vertical direction.

[0146] In the example embodiment, the upper transistor pTRb of the second peripheral circuit PC2 can be formed as a planar transistor, but the example embodiment is not limited to this. For example, the upper transistor pTRb of the second peripheral circuit PC2 can be formed as a fin field-effect transistor (FinFET) or a gate-all-around transistor.

[0147] In the following, example embodiments of semiconductor device 1 will be described. The various example embodiments described below and those described above can be combined to form example embodiments. In the following, elements described above may be directly referenced without detailed description, or may be omitted entirely. Furthermore, the following figures can be used to describe elements that can be modified or replaced, but elements that can be modified, replaced, or added can be combined with each other or with the elements described above to form a semiconductor device according to the example embodiments. Additionally, where the previously described elements include multiple elements, an example in which the number of elements described above is one will be described.

[0148] Reference Figure 6 An example embodiment of the semiconductor device described above is given. Figure 6 This is a cross-sectional view illustrating an example embodiment of the semiconductor device described above.

[0149] refer to Figure 6 In the example embodiment, the semiconductor device 1a may include a first memory cell array region MCA1a, a second memory cell array region MCA2a, and a connection region IAa located between the first memory cell array region MCA1a and the second memory cell array region MCA2a. The first memory cell array region MCA1a and the second memory cell array region MCA2a may have a mirror-symmetric structure.

[0150] Semiconductor device 1a may include the lower structure STC1, the intermediate structure STC2, and the upper structure STC3 described above. For example, each of the first memory cell array region MCA1a and the second memory cell array region MCA2a may include the memory cell array regions described above ( Figure 4AThe MCA in the above-described component is essentially the same. In the connection region IAa, the area adjacent to the first memory cell array region MCA1a may include elements similar to the connection region described above. Figure 4A The IA in the second memory cell array region (MCA2a) is essentially the same element, and the region adjacent to the second memory cell array region (MCA2a) may include the connection region described above. Figure 4A The IA in the text is essentially the same element.

[0151] The lower word line WL_L, which is located in the first memory cell array region MCA1a and extends into the connection region IAa, may be spaced apart from the lower word line WL_L, which is located in the second memory cell array region MCA2a and extends into the connection region IAa. Similarly, the upper word line WL_U, which is located in the first memory cell array region MCA1a and extends into the connection region IAa, may be spaced apart from the upper word line WL_U, which is located in the second memory cell array region MCA2a and extends into the connection region IAa.

[0152] The lower word line WL_L in the first memory cell array region MCA1a and the lower word line WL_L in the second memory cell array region MCA2a may be spaced apart from each other in a first direction, and the upper word line WL_U in the first memory cell array region MCA1a and the upper word line WL_U in the second memory cell array region MCA2a may also be spaced apart from each other in the first direction, but the example embodiment is not limited thereto. For example, the lower word line WL_L in the first memory cell array region MCA1a and the lower word line WL_L in the second memory cell array region MCA2a may be modified to be connected to each other in the connection region IAa, and the upper word line WL_U in the first memory cell array region MCA1a and the upper word line WL_U in the second memory cell array region MCA2a may be modified to be connected to each other in the connection region IAa. (Refer to...) Figure 7 , Figure 8A , Figure 8B , Figure 9 , Figure 10 and Figure 11 An example embodiment is described, which can be modified as above, for the lower letter line WL_L and the upper letter line WL_U.

[0153] First, refer to Figure 7 An example embodiment of the semiconductor device described above is given. Figure 7 This is a cross-sectional view illustrating an example embodiment of the semiconductor device described above.

[0154] refer to Figure 7In the example embodiment, the semiconductor device 1b may include a first memory cell array region MCA1b, a second memory cell array region MCA2b, and a connection region IAb located between the first memory cell array region MCA1b and the second memory cell array region MCA2b. The first memory cell array region MCA1b and the second memory cell array region MCA2b may have a mirror-symmetric structure.

[0155] Semiconductor device 1b may include the lower structure STC1, the intermediate structure STC2, and the upper structure STC3 described above. For example, each of the first memory cell array region MCA1b and the second memory cell array region MCA2b may include the memory cell array regions described above ( Figure 4A The MCA in the text is essentially the same component.

[0156] The above reference Figure 6 The described lower word line WL_L can be replaced by a lower word line WL_La set in the first memory cell array region MCA1b, the connection region IAb, and the second memory cell array region MCA2b. Each lower word line WL_La can intersect with the first memory cell array region MCA1b, the connection region IAb, and the second memory cell array region MCA2b.

[0157] The above reference Figure 6 The described top word line WL_U can be replaced by the top word line WL_Ua set in the first memory cell array region MCA1b, the connection region IAb, and the second memory cell array region MCA2b. Each top word line WL_Lb can intersect with the first memory cell array region MCA1b, the connection region IAb, and the second memory cell array region MCA2b.

[0158] In the connection region IAb, the lower gate contact plug described above ( Figure 4D The 42w in the above description can be replaced with the lower gate contact plug 42wa connected to the lower word line WL_La. In the connection area IAb, the upper gate contact plug described above ( Figure 4D The 240w in the middle can be replaced with the upper gate contact plug 240wa connected to the upper word line WL_Ua.

[0159] The lower structure STC1 may further include a lower insulating spacer 41a disposed on the side surface of the lower gate contact plug 42wa. The upper structure STC3 may further include an upper insulating spacer 239a disposed on the side surface of the upper gate contact plug 240a.

[0160] In the lower gate contact plug 42wa, the contact plug 42wa connected to the lowest word line in the lower word line WL_La can penetrate other lower word lines, and the lower insulating spacer 41a can electrically insulate the contact plug 42wa from other lower word lines. In the upper gate contact plug 240wa, the contact plug 240wa connected to the highest word line in the upper word line WL_Ua can penetrate other upper word lines, and the upper insulating spacer 239a can electrically insulate the contact plug 240wa from other upper word lines.

[0161] The structure including the lower word line WL_La and the lower gate contact plug 42wa, and the structure including the upper word line WL_Ua and the upper gate contact plug 240wa, can be a mirror-symmetric structure. The lower word line WL_La can overlap perpendicularly with the upper word line WL_Ua, and the lower gate contact plug 42wa can overlap perpendicularly with the upper gate contact plug 240wa.

[0162] Reference Figure 8A and Figure 8B Description Reference Figure 7 Example embodiments of the gate contact plugs 42wa and 240wa and the word lines WL_La and WL_Ua are described. Figure 8A It is a reference. Figure 7 A perspective view of an example embodiment of the lower word line WL_La and gate contact plug 42wa, and... Figure 8B This is a perspective view showing one of the lower word lines and one of the gate contact plugs.

[0163] refer to Figure 8A and Figure 8B as well as Figure 7 Stack groups G1a and G2a can be configured, comprising a first stack group G1a and a second stack group G2a spaced apart from each other in the second direction Y. Each stack group G1a and G2a may include a lower word line WL_La stacked in the vertical direction.

[0164] In each of the stack groups G1a and G2a, the bottom word line WL_La may include a first bottom word line WL_L1, a second bottom word line WL_L2 located below the first bottom word line WL_L1, a third bottom word line WL_L3 located below the second bottom word line WL_L2, and a fourth bottom word line WL_L4 located below the third bottom word line WL_L2.

[0165] The first stack group G1a may include a first stack region ST1a located in the first memory cell array region MCA1b, a second stack region ST1b located in the second memory cell array region MCA2b, and a third stack region ST1c located in the connection region IAb.

[0166] The second stack group G2a may include a fourth stack region ST2a located in the first memory cell array region MCA1b, a fifth stack region ST2b located in the second memory cell array region MCA2b, and a sixth stack region ST2c located in the connection region IAb.

[0167] Each lower word line WL_La may have a first width in the first memory cell array region MCA1b and the second memory cell array region MCA2b in the second direction Y, and a second width greater than the first width in the connection region IAb in the second direction Y.

[0168] In the first memory cell array region MCA1b and the second memory cell array region MCA2b, each lower word line WL_La can be as follows: Figure 4D It also has a horizontal through-hole OPa. The horizontal through-hole OPa can penetrate the lower letter line WL_La in the second direction Y.

[0169] In the lower word lines WL_La, each word line that is at a height higher than the lowest word line WL_L4 in WL_La can have at least one vertical through-hole 40a. For example, the first lower word line WL_L1 can have a vertical through-hole 40a through which the lower gate contact plug 42wa connected to the second lower word line WL_L2, the third lower word line WL_L3, and the fourth lower word line WL_L4 penetrates, and the second lower word line WL_L2 can have a vertical through-hole 40a through which the lower gate contact plug 42wa connected to the third lower word line WL_L3 and the fourth lower word line WL_L4 penetrates. In the lower gate contact plug 42wa, the lower gate contact plug passing through the vertical through-hole 40a can be penetrated by a lower gate insulating spacer ( Figure 7 41a) is electrically insulated from the lower letter line WL_L with a vertical through hole 40a.

[0170] Multiple lower gate contact plugs 42wa can be arranged in the first direction X.

[0171] Reference Figure 9 , Figure 10 and Figure 11 An example embodiment of the semiconductor device described above is given. Figure 9 This is a cross-sectional view illustrating an example embodiment of the semiconductor device described above. Figure 10 It is shown Figure 9 A perspective view of an example embodiment of the lower word line WL_Lb and the lower gate contact plug 42wb, and Figure 11 This is a perspective view showing one of the lower word lines and one of the gate contact plugs among the lower gate contact plugs.

[0172] refer to Figure 9 , Figure 10 and Figure 11 In the example embodiment, the semiconductor device 1c may include a first memory cell array region MCA1c, a second memory cell array region MCA2c, and a connection region IAc located between the first memory cell array region MCA1c and the second memory cell array region MCA2c. The first memory cell array region MCA1c and the second memory cell array region MCA2c may have a mirror-symmetric structure. The semiconductor device 1c may include the lower structure STC1, the intermediate structure STC2, and the upper structure STC3 described above. For example, each of the first memory cell array region MCA1c and the second memory cell array region MCA2c may include a memory cell array region (…) described above. Figure 4A The MCA in the text is essentially the same component.

[0173] The above reference Figure 7 , Figure 8A and Figure 8B The described lower word line WL_La can be replaced by a lower word line WL_Lb disposed in the first memory cell array region MCA1c, the connection region IAc, and the second memory cell array region MCA2c. Each lower word line WL_Lb can span the first memory cell array region MCA1c, the connection region IAc, and the second memory cell array region MCA2c, and can include first portions ST1aa, ST1ab, ST1ac, and ST1ad in the first memory cell array region MCA1b that are spaced apart from each other in the second direction Y, and can include second portions ST1ba, ST1bb, ST1bc, and ST1bd in the second memory cell array region MCA2b that are spaced apart from each other in the second direction Y, and can include a connection portion ST1ca in the connection region IAc that connects the first portions ST1aa, ST1ab, ST1ac, and ST1ad to the second portions ST1ba, ST1bb, ST1bc, and ST1bd.

[0174] above Figure 6 The upper word line WL_U described in the text can be replaced by an upper word line WL_Ub that has a mirror-symmetric structure with the lower word line WL_Lb.

[0175] In the connection region IAc, the lower gate contact plug described above ( Figure 4D In the context of 42w), the upper gate contact plug (42wb) can be replaced with the lower gate contact plug 42wb connected to the lower word line WL_Lb. In the connection region IAc, the upper gate contact plug described above (…) Figure 4D The 240w in the middle can be replaced by the upper gate contact plug 240wb connected to the upper word line WL_Ub.

[0176] The lower structure STC1 may further include a lower insulating spacer 41b disposed on the side surface of the lower gate contact plug 42wb. The upper structure STC3 may further include an upper insulating spacer 239b disposed on the side surface of the upper gate contact plug 240b.

[0177] In the lower gate contact plug 42wb, the contact plug 42wb connected to the lowest word line in the lower word line WL_Lb can penetrate other lower word lines, and the lower insulating spacer 41b can electrically insulate the contact plug 42wb from other lower word lines. In the upper gate contact plug 240wb, the contact plug 240wb connected to the highest word line in the upper word line WL_Ub can penetrate other upper word lines, and the upper insulating spacer 239b can electrically insulate the contact plug 240wb from other upper word lines.

[0178] The structure including the lower word line WL_Lb and the lower gate contact plug 42wb, and the structure including the upper word line WL_Ub and the upper gate contact plug 240wb, can be a mirror-symmetric structure. The lower word line WL_Lb can overlap perpendicularly with the upper word line WL_Ub, and the lower gate contact plug 42wb can overlap perpendicularly with the upper gate contact plug 240wb.

[0179] The lower character line WL_Lb may include a first lower character line WL_L1, a second lower character line WL_L2 located below the first lower character line WL_L1, a third lower character line WL_L3 located below the second lower character line WL_L2, and a fourth lower character line WL_L4 located below the third lower character line WL_L2.

[0180] In the first memory cell array region MCA1b and the second memory cell array region MCA2b, each lower word line WL_Lb can be as follows: Figure 4D It also has a horizontal through-hole OPa. The horizontal through-hole OPa can penetrate the lower letter line WL_Lb in the second direction Y.

[0181] In the lower word lines WL_Lb, each word line that is at a height higher than the lowest word line WL_L4 in the lower word lines WL_Lb can have at least one vertical through-hole 40b. For example, the first lower word line WL_L1 can have a vertical through-hole 40b through which the lower gate contact plug 42wb connected to the second lower word line WL_L2, the third lower word line WL_L3, and the fourth lower word line WL_L4 penetrates, and the second lower word line WL_L2 can have a vertical through-hole 40b through which the lower gate contact plug 42wb connected to the third lower word line WL_L3 and the fourth lower word line WL_L4 penetrates. In the lower gate contact plug 42wb, the lower gate contact plug passing through the vertical through-hole 40b can be penetrated by a lower gate insulating spacer ( Figure 941b) is electrically insulated from the lower letter line WL_L with a vertical through hole 40b.

[0182] Multiple lower gate contact plugs 42wb can be arranged in the second direction Y.

[0183] refer to Figure 12 The following will describe example embodiments of the semiconductor devices described above. Figure 12 This is a cross-sectional view illustrating an example embodiment of the semiconductor device described above.

[0184] refer to Figure 12 The semiconductor device 1d in the example embodiment may further include an input / output routing structure 305. The input / output routing structure 305 may have a shape that penetrates the first structure STC1, the second structure STC2, and the third structure STC3. For example, the input / output routing structure 305 may include a first input / output pad pattern 350, an upper through electrode 315 passing through the upper semiconductor body 203, an upper connection portion 310 located between the first input / output pad pattern 350 and the upper through electrode 315, a lower connection portion 320 disposed below the upper through electrode 315 and at the same height as the upper word line interconnect structure RI_U_WL and the first lower word line interconnect structure 48w, a lower through electrode 330 disposed below the lower connection portion 320 and passing through the lower substrate 3, and a second input / output pad pattern 340 located below the lower through electrode 330.

[0185] The first input / output pad pattern 350 and the second input / output pad pattern 340 can overlap each other perpendicularly.

[0186] The input / output routing structure 305 can be electrically connected to the circuitry in the second peripheral circuit PC2 for data or command input / output or power / ground input.

[0187] In the following description, reference will be made to Figure 13 An example embodiment of the semiconductor device described above is given. Figure 13 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0188] refer to Figure 13 The semiconductor device according to the example embodiment may include a package substrate 505 and a semiconductor chip 1 located on the package substrate 505.

[0189] In the example embodiment, semiconductor chip 1 may be one of the semiconductor chips in the example embodiments described above. For example, according to the above reference... Figures 1 to 12 The semiconductor devices of the described example embodiments can be mounted on package substrate 505. For example, refer to... Figures 4A to 4EThe semiconductor device 1, which includes a first structure STC1, a second structure STC2, and a third structure STC3, can be mounted on a packaging substrate 505 in the form of a semiconductor chip.

[0190] The packaging substrate 505 can be implemented as a printed circuit board or a redistribution substrate. The packaging substrate 505 may include a first pad 515 disposed on the upper surface of the packaging substrate 505, a second pad 520 disposed on the lower surface of the packaging substrate 505, and an internal interconnection 525 electrically connecting the first pad 515 and the second pad 520 to each other.

[0191] The conductive bumps 85 can be provided to connect the pad pattern 290 of the third structure STC3 of the semiconductor chip 1 to the first pad 515 of the packaging substrate 505. A bottom filler material 550 can be provided to fill the space between the semiconductor chip 1 and the packaging substrate 505, and a molding layer 560 can be provided to cover the semiconductor chip 1 located on the packaging substrate 505.

[0192] Therefore, the semiconductor chip 1 can be mounted on the packaging substrate 505 in a flip-chip structure.

[0193] In the following description, reference will be made to Figure 14 An example embodiment of the semiconductor device described above is given. Figure 14 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0194] refer to Figure 14 The semiconductor device according to the example embodiment may include a packaging substrate 605 and a semiconductor chip 1 located on the packaging substrate 605.

[0195] In the example embodiment, semiconductor chip 1 may be one of the semiconductor chips in the example embodiments described above. For example, according to the above reference... Figures 1 to 12 The semiconductor device of one of the described example embodiments can be mounted on a package substrate 605. For example, refer to Figures 4A to 4E The semiconductor device 1, which includes a first structure STC1, a second structure STC2, and a third structure STC3, can be mounted on a packaging substrate 605 in the form of a semiconductor chip.

[0196] The packaging substrate 605 may include a first pad 615 disposed on the surface facing the semiconductor chip 1, a second pad 620 disposed on the lower surface of the packaging substrate 605, and an internal interconnect 625 electrically connecting the first pad 615 to the second pad 620. An adhesive layer 126 may be disposed between the semiconductor chip 1 and the packaging substrate 605.

[0197] The semiconductor chip 1 may include a pad region 280P for input / output as described above. Wiring 630 may be provided to electrically connect the pad region 280P of the semiconductor chip 1 to a first pad 615 of the package substrate 605. A molding layer 635 covering the semiconductor chip 1 and the wiring 630 may be provided on the package substrate 605. The semiconductor chip 1 may be mounted on the package substrate 605 via wiring bonding.

[0198] In the example embodiment, a semiconductor chip 1 can be mounted on the packaging substrate 605, but the example embodiment is not limited to this. For example, multiple semiconductor chips 1 can be mounted on the packaging substrate 605.

[0199] In the following description, reference will be made to Figure 15 An example embodiment of the semiconductor device described above is given. Figure 15 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0200] refer to Figure 15 The semiconductor device 900 in the example embodiment may include a packaging substrate 703, an interposer INT located on the packaging substrate 703, and a first chip structure CHa and a second chip structure CHb mounted on the interposer INT.

[0201] In the example, the package substrate 703 may include a substrate body 706, a lower pad 712 located in the lower part of the substrate body 706, a connection pattern 715 disposed below the lower pad 712 and electrically connected to the lower pad 712, an upper pad 709 disposed on the substrate body 706, and an internal interconnection 718 in the substrate body 706 electrically connecting the lower pad 712 to the upper pad 709. The connection pattern 715 may be a solder ball comprising a solder material such as SnAg or SnAgCu. The package substrate 703 may be implemented as a printed circuit board.

[0202] The interposer INT may include an interposer substrate 723a, a first lower insulating layer 725a located below the interposer substrate 723a, a first upper insulating layer 727a located on the interposer substrate 723a, a first insulating structure 748a located on the first upper insulating layer 727a, and an interconnect structure 736 located in the first insulating structure 748a. The interconnect structure 736 may include a power / ground path and a signal path.

[0203] The second chip structure CHb may include a lower chip 871 and a plurality of semiconductor chips 872 stacked vertically on the lower chip 871 and spaced apart from each other.

[0204] Each of the plurality of semiconductor chips 872 may include a reference Figure 12The semiconductor device 1d is described. Therefore, each of the plurality of semiconductor chips 872 may include a reference. Figure 12 The semiconductor device 1d is described with a first structure STC1, a second structure STC2, and a third structure STC3. In each of the plurality of semiconductor chips 872, the third structure STC3 may be disposed below the first structure STC1.

[0205] The second chip structure CHb may further include a bump structure 879 for interconnecting the lower chip 871 to a plurality of semiconductor chips 872. The lower chip 871 may further include a through electrode 873 for electrically connecting the plurality of semiconductor chips 872 to a plurality of interposer layers INT.

[0206] The plurality of semiconductor chips 872 may include through electrodes 873 for interconnecting the plurality of semiconductor chips 872.

[0207] In the example embodiment, the through-electrode 773 of the plurality of semiconductor chips 872 may be a reference. Figure 12 The input / output routing structure described is 305.

[0208] The second chip structure CHb may further include a molding layer 874 covering the lower portion of each of the plurality of semiconductor chips 872 located on the lower chip 871 and covering the plurality of semiconductor chips 872. The second chip structure CHb may be mounted on the interposer layer INT in a flip-chip manner. The lower chip 871 may be configured as a buffer chip or a logic chip.

[0209] Conductive bumps 65 can be configured to connect the interposer layer INT to the pads 759 of the first chip structure CHa. The first chip structure CHa can be configured as a processor unit. For example, the first chip structure CHa may include a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor (DSP). The first chip structure CHa may include an application processor (AP). The application processor (AP) can be configured for wireless communication applications or application-specific integrated circuits (ASICs).

[0210] In the following description, reference will be made to Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C and Figure 21 A method for manufacturing a semiconductor device according to an example embodiment is described. As for... Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C and Figure 21 , Figure 16 This is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an example embodiment, and Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C and Figure 21 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. In the following description, descriptions of elements that can be understood from the example embodiments of the semiconductor device described above may not be provided.

[0211] refer to Figure 16 and Figure 17 A lower structure STC1 can be formed. For example, a lower structure STC1 (S10) can be formed including a lower memory cell MC1, a lower local bit line LBL_L, a lower global bit line GBL_L, and a lower bonding layer 54. As described above, each lower memory cell MC1 may include a lower cell transistor ( Figure 4B cTRa) and its underlying data storage structure ( Figure 4B (DSa in the text). As described above, the lower structure STC1 may include a lower word line WL_L connected to the lower memory cell MC1. The lower bonding layer 54 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0212] Forming the lower structure STC1 may include: forming a lower memory cell MC1, a lower word line WL_L, and a lower local bit line LBL_L on the lower substrate 3; forming a lower global bit line GBL_L connected to the lower local bit line LBL_L; forming a first lower word line interconnect structure 48w connected to the lower word line WL_L and a first lower bit line interconnect structure 48b connected to the lower global bit line GBL_L; forming a lower insulating structure 51 covering the first lower word line interconnect structure 48w and the first lower bit line interconnect structure 48b; forming a lower bonding layer 54 on the lower insulating structure 51; and forming a protective insulating layer 57 below the lower substrate 3.

[0213] refer to Figure 16 and Figure 18 This can form a preliminary intermediate structure STC2a (S20) including a first peripheral circuit PC1 and a first intermediate bonding layer 115. The first intermediate bonding layer 115 may include at least one of SiO, SiN, SiCN, SiOC, SiON or SiOCN.

[0214] Forming the preliminary intermediate structure STC2a may include: forming a first peripheral circuit PC1 on the intermediate semiconductor body 103; forming an insulating structure 127a covering the first peripheral circuit PC1 on the intermediate semiconductor body 103; forming a back-side insulating layer 112 covering the lower surface of the intermediate semiconductor body 103; and forming a first intermediate bonding layer 115 covering the back-side insulating layer 112.

[0215] refer to Figure 16 and Figure 19A A first wafer bonding process can be performed to bond the lower bonding layer 54 to the first intermediate bonding layer 115 to form a first bonding structure STC_a (S30). The first wafer bonding process can be a dielectric-dielectric bonding process.

[0216] refer to Figure 16 and Figure 19B A second intermediate bonding layer 142 (S40) can be formed on the first bonding structure STC_a.

[0217] The second intermediate bonding layer 142 may include an intermediate bonding dielectric layer 136 and an intermediate bonding metal pattern 139. The intermediate bonding dielectric layer 136 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. The intermediate bonding metal pattern 139 may include copper.

[0218] Forming the intermediate bonding dielectric layer 136 may include: forming a second lower-level line interconnect structure 124w, a second lower-level line interconnect structure 124b, a second connection structure 133w, and a third connection structure 133b; forming the intermediate bonding dielectric layer 136 on the intermediate insulating structure 127; and forming an intermediate bonding metal pattern 139 having an upper surface coplanar with the upper surface of the intermediate bonding dielectric layer 136. Therefore, a bonding structure STC_b comprising a first structure STC1 and a second structure STC2 bonded to each other can be formed.

[0219] refer to Figure 16 and Figure 20A The upper word line WL_U can be formed (S50). For example, an upper cell active pattern 209 can be formed on the initial upper semiconductor body 203a, and an upper word line WL_U extending around the cell active pattern 209 and in a second direction can be formed.

[0220] In the example embodiment, an upper local bit line LBL_U may be formed. For example, an upper cover insulating layer 218 may be formed at a height higher than the height of the cell active pattern 209, and an upper local bit line LBL_U may be formed that penetrates the upper cover insulating layer 218 and is connected to the cell active pattern 209.

[0221] An insulating structure 251a can be formed that covers the upper letter line WL_U and has an upper surface that is coplanar with the upper surface of the upper covering insulating layer 218.

[0222] refer to Figure 16 and Figure 20B The upper semiconductor body 203 can be formed by reducing the thickness of the initial upper semiconductor body 203a. A second peripheral circuit PC2 can be formed (S55). The second peripheral circuit PC2 can be formed on the upper semiconductor body 203. An insulating structure 285 covering the second peripheral circuit PC2 can be formed on the upper semiconductor body 203.

[0223] refer to Figure 16 and Figure 20C This can form an upper data storage structure ( Figure 4C DSb in (S60). It can form a connection to the data storage structure above ( Figure 4C The upper unit transistor of DSb in ( Figure 4C cTRb in the middle). Data storage structure ( Figure 4C DSb in the middle and upper unit transistor ( Figure 4C The cTRb in the memory can be included in the upper storage unit MC2.

[0224] The upper global bit line GBL_U (S65) can be formed. The upper global bit line GBL_U can be electrically connected to the upper local bit line LBL_U.

[0225] A preliminary upper structure STC3c can be formed. For example, by forming an upper bonding layer 257, a preliminary upper structure STC3c (S70) including an upper memory cell MC2, a second peripheral circuit PC2, an upper global bit line GBL_U, and an upper bonding layer 257 can be formed.

[0226] The upper bonding layer 257 may include an upper bonding metal pattern 245 and an upper bonding dielectric layer 254. The upper bonding dielectric layer 254 may be formed on the upper insulating structure 251 covering the upper global bit line GBL_U. The upper bonding metal pattern 245 may have an upper surface coplanar with the upper surface of the upper bonding dielectric layer 254. The upper bonding dielectric layer 254 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. The upper bonding metal pattern 245 may include a metal such as copper.

[0227] refer to Figure 16 and Figure 21A second wafer bonding process can be performed to bond the second intermediate bonding layer 142 to the upper bonding layer 257 to form a second bonding structure (S80). The upper bonding metal pattern 245 and the intermediate bonding metal pattern 139 can be bonded to each other through the second wafer bonding process, and the upper bonding dielectric layer 254 and the intermediate bonding dielectric layer 136 can be bonded to each other through the second wafer bonding process.

[0228] refer to Figures 4A to 4E as well as Figure 16 An interconnect process (S90) can be performed. The interconnect process can be a process for forming a routing interconnect structure 275, an upper interconnect 280, a second connection routing structure RI_U_Cb, and a pad pattern 290 for electrically connecting the second peripheral circuit PC2.

[0229] According to the foregoing example embodiments, a semiconductor device can be provided, the semiconductor device comprising: a lower structure including a lower memory cell; an intermediate structure bonded to the lower structure and including a first peripheral circuit; and an upper structure bonded to the intermediate structure and including an upper memory cell.

[0230] Additionally, the first peripheral circuitry of the intermediate structure may include: a word line selection circuit connected to the lower word line of the lower structure and the upper word line of the upper structure; and a sub-word line driver connected to the word line selection circuit.

[0231] Additionally, the second peripheral circuitry of the intermediate structure may include: a bit line selection circuit connected to the lower bit line of the lower structure and the upper bit line of the upper structure; and a bit line sense amplifier connected to the bit line selection circuit.

[0232] Furthermore, the word line select circuit can reduce the total number of sub-word line drivers, and the bit line select circuit can reduce the total number of bit line sense amplifiers. Therefore, even if the number of current memory cells and the number of previous memory cells increase, space can still be guaranteed for setting up sub-word line drivers and bit line sense amplifiers.

[0233] Furthermore, the upper and lower memory cells, which are opposite to each other and have an intermediate structure between them, can be arranged in a symmetrical structure. Therefore, since the upper and lower memory cells can be formed in a symmetrical structure, the uniformity of the semiconductor device can be improved, the performance of the semiconductor device can be optimized, and the integration density of the semiconductor device can be increased.

[0234] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The lower structure includes a lower bonding layer; An intermediate structure is disposed on the lower structure and includes a first intermediate bonding layer bonded to the lower bonding layer and a second intermediate bonding layer opposite to the first intermediate bonding layer. as well as The upper structure is disposed on the intermediate structure and includes an upper bonding layer bonded to the second intermediate bonding layer. The lower structure further includes a lower storage unit. The intermediate structure also includes a first peripheral circuit. The upper structure also includes an upper storage unit. Each of the lower bonding layer and the first intermediate bonding layer comprises a dielectric material and does not include a bonding metal material. Each of the second intermediate bonding layer and the upper bonding layer includes a bonding dielectric layer and a bonding metal pattern, wherein the bonding dielectric layer includes a dielectric material and the bonding metal pattern includes a bonding metal material. Wherein, the bonding dielectric layer of the second intermediate bonding layer is bonded to the bonding dielectric layer of the upper bonding layer, and The bonding metal pattern of the second intermediate bonding layer is bonded to the bonding metal pattern of the upper bonding layer.

2. The semiconductor device of claim 1, wherein, The lower storage cells are arranged in a first direction, a second direction, and a perpendicular direction that intersect each other. The upper storage unit is arranged in the first direction, the second direction, and the vertical direction. The lower structure further includes: Lower word line, the lower word line being connected to the lower memory cell; and A lower local bit line, the lower local bit line being connected to the lower memory cell, and The upper structure further includes: Upper word line, the upper word line being connected to the upper storage unit; and Upper local bit line, which is connected to the upper memory cell.

3. The semiconductor device of claim 2, wherein, The upper character line and the lower character line overlap perpendicularly, and The upper local bit line and the lower local bit line overlap perpendicularly.

4. The semiconductor device of claim 2, wherein, The lower structure also includes a lower gate contact plug connected to the lower word line. The upper structure further includes an upper gate contact plug connected to the upper word line, and The upper gate contact plug and the lower gate contact plug overlap vertically.

5. The semiconductor device of claim 2, wherein, The first peripheral circuit includes: Word line selection circuit, the word line selection circuit being connected to the lower word line and the upper word line; and A sub-word line driver, which is connected to the word line selection circuit.

6. The semiconductor device of claim 5, wherein, Each of the aforementioned word line selection circuits includes: A lower word line select transistor, the lower word line select transistor being electrically connected to a corresponding lower word line among the lower word lines; and A word line select transistor is electrically connected to the corresponding word line among the word lines.

7. The semiconductor device of claim 6, wherein, The upper word line select transistor and the lower word line select transistor are configured to operate in a complementary manner, such that when the lower word line select transistor is in the on state, the upper word line select transistor is in the off state, and when the lower word line select transistor is in the off state, the upper word line select transistor is in the on state.

8. The semiconductor device of claim 5, wherein, The lower structure and the intermediate structure further include a first lower routing interconnect structure that electrically connects the lower word line to the sub-word line driver, and The intermediate structure and the upper structure further include a first upper routing interconnect structure that electrically connects the upper word line to the sub-word line driver.

9. The semiconductor device of claim 8, wherein, The intermediate structure also includes an intermediate semiconductor body, and The first lower routing interconnection structure includes: A lower gate contact plug, the lower gate contact plug being connected to the lower word line; A first lower routing interconnect is disposed on and connected to the lower gate contact plug; A through-conductive pattern, the through-conductive pattern penetrating the intermediate semiconductor body and connected to the first lower routing interconnect; and A first intermediate routing interconnect is disposed on the intermediate semiconductor body and connected to the through conductive pattern.

10. The semiconductor device of claim 2, wherein, The lower structure also includes a lower global bit line electrically connected to the lower local bit line. The upper structure further includes an upper global bit line electrically connected to the upper local bit line. Each of the lower global bit lines is electrically connected to N lower local bit lines among the lower local bit lines. Each of the aforementioned upper global bit lines is electrically connected to N upper local bit lines among the aforementioned upper local bit lines, and Where N is a natural number of 2 or greater.

11. The semiconductor device of claim 10, wherein, The lower global bit line overlaps perpendicularly with the upper global bit line.

12. The semiconductor device of claim 10, wherein, The first peripheral circuit also includes: Bit line selection circuit, the bit line selection circuit being electrically connected to the lower global bit line and the upper global bit line; and Bit line sense amplifier, which is connected to the bit line selection circuit.

13. The semiconductor device of claim 1, wherein, The upper structure also includes a second peripheral circuit disposed at a height higher than that of the upper storage unit.

14. A semiconductor device, the semiconductor device comprising: The lower structure includes a lower word line, a lower local bit line, and a lower memory cell connected to the lower word line and the lower local bit line; The upper structure includes an upper word line, an upper local bit line, and an upper memory cell connected to the upper word line and the upper local bit line; as well as An intermediate structure is disposed between the lower structure and the upper structure, and The intermediate structure includes: Word line selection circuit, the word line selection circuit being electrically connected to the lower word line and the upper word line; and A sub-word line driver, which is electrically connected to the word line selection circuit.

15. The semiconductor device of claim 14, wherein, Each of the aforementioned word line selection circuits includes: A lower word line select transistor, the lower word line select transistor being electrically connected to a corresponding lower word line among the lower word lines; and A word line select transistor is electrically connected to the corresponding word line among the word lines.

16. The semiconductor device of claim 14, wherein, The intermediate structure also includes: Bit line selection circuit, the bit line selection circuit being electrically connected to the lower local bit line and the upper local bit line; and Bit line sense amplifier, which is electrically connected to the bit line selection circuit.

17. The semiconductor device according to claim 16, wherein, The lower structure also includes a lower global bit line electrically connected to the lower local bit line. The upper structure further includes an upper global bit line electrically connected to the upper local bit line. Each of the lower global bit lines is electrically connected to N lower local bit lines among the lower local bit lines. Each of the aforementioned upper global bit lines is electrically connected to N upper local bit lines among the aforementioned upper local bit lines, and Where N is a natural number of 2 or greater.

18. The semiconductor device according to claim 17, wherein, The first bit selection circuit in the bit line selection circuit is connected to the first bit sense amplifier in the bit line sense amplifier. The first bit line selection circuit includes: The first lower-level line selects the transistor; The second lower-level line selects the transistor; The first upper-level line selects the transistor; and The second upper-level line selects the transistor. Wherein, the first lower bit line select transistor and the second lower bit line select transistor are electrically connected to the first lower global bit line and the second lower global bit line, respectively, and The first upper-level line selection transistor and the second upper-level line selection transistor are electrically connected to the first upper-global bit line and the second upper-global bit line, respectively.

19. A semiconductor device, the semiconductor device comprising: The lower structure includes a lower bonding layer; An intermediate structure is disposed on the lower structure and includes a first intermediate bonding layer bonded to the lower bonding layer and a second intermediate bonding layer opposite to the first intermediate bonding layer. as well as The upper structure is disposed on the intermediate structure and includes an upper bonding layer bonded to the second intermediate bonding layer. The lower structure further includes: Lower storage units are arranged in a first direction, a second direction, and a perpendicular direction that intersect each other; Lower word line, the lower word line being connected to the lower memory cell; and A lower local bit line, which is connected to the lower memory cell. The intermediate structure also includes a first peripheral circuit. The upper structure further includes: Upper storage unit, the upper storage unit being arranged in the first direction, the second direction and the vertical direction; Upper word line, the upper word line being connected to the upper storage unit; Upper local bit line, the upper local bit line being connected to the upper memory cell; and The second peripheral circuit is disposed at a height higher than the height of the upper storage cell. The first peripheral circuit includes: Sub-word line selection circuit, the sub-word line selection circuit being electrically connected to the lower word line and the upper word line; and Sub-word line driver, the sub-word line driver being connected to the sub-word line selection circuit.

20. The semiconductor device according to claim 19, in, The lower structure also includes a lower global bit line electrically connected to the lower local bit line. The upper structure further includes an upper global bit line electrically connected to the upper local bit line. Each of the lower global bit lines is electrically connected to N lower local bit lines among the lower local bit lines. Each of the aforementioned upper global bit lines is electrically connected to N upper local bit lines among the aforementioned upper local bit lines, and Where N is a natural number of 2 or greater, The intermediate structure further includes: Bit line selection circuit, the bit line selection circuit being electrically connected to the lower local bit line and the upper local bit line; and Bit line sense amplifier, the bit line sense amplifier being electrically connected to the bit line selection circuit. Each of the lower bonding layer and the first intermediate bonding layer comprises a dielectric material and does not include a bonding metal material. Each of the second intermediate bonding layer and the upper bonding layer includes a bonding dielectric layer and a bonding metal pattern, wherein the bonding dielectric layer includes a dielectric material and the bonding metal pattern includes a bonding metal material. Wherein, the bonding dielectric layer of the second intermediate bonding layer is bonded to the bonding dielectric layer of the upper bonding layer, and The bonding metal pattern of the second intermediate bonding layer is bonded to the bonding metal pattern of the upper bonding layer.

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