Single-hole light-emitting red LED and preparation method thereof

Abstract

The application relates to the technical field of LED, in particular to a single-hole light-emitting red LED and a preparation method thereof. The red LED comprises, from bottom to top, a back electrode, a Si substrate, a bonding layer, an AgTiW mirror surface, a dielectric film, an IZO contact layer, GaP, a limiting layer, a P-type semiconductor, a light-emitting layer, an N-type semiconductor, a front contact electrode, a passivation layer and a front pad electrode. The red LED has a single-hole light-emitting area. A plurality of dielectric holes are arranged in the single-hole light-emitting area. The size of the AgTiW mirror surface matches that of the single-hole light-emitting area. The GaP is in the dielectric holes and is connected with the AgTiW mirror surface through the IZO contact layer. The red LED obtained by reasonably designing the light-emitting area has a significantly compressed light-emitting angle, a reduced contact resistance and improved long-term operation reliability.

Description

Technical Field

[0001] This invention relates to the field of LED technology, specifically to a single-aperture red LED and its fabrication method. Background Technology

[0002] Red LEDs, as the earliest industrialized III-V compound semiconductor light source, have been widely used in fields such as indicator lighting, photoelectric sensing, automotive taillights, biomedicine, and plant supplemental lighting due to their advantages such as small size, long lifespan, fast response, and no mercury pollution. However, in special application scenarios such as long-distance security monitoring, covert signal detection, laser aiming assistance, and free-space optical communication, the system places more stringent requirements on the light source. For example, the emission angle needs to be extremely narrow to achieve highly directional lighting or detection; at the same time, it needs to maintain stable light emission over a wide current range to meet the requirements of low power consumption and long battery life.

[0003] Traditional red LED chips generally employ a planar, all-encompassing light-emitting structure, with light emitted isotropically from the entire light-emitting surface. This results in a large emission angle and severe beam divergence, making it difficult to form a highly concentrated "dot-like" light spot. Even with secondary light distribution using external lenses, the near-field divergence problem cannot be fundamentally solved, and it also increases system size and cost. More importantly, under low current injection conditions, traditional red LEDs face severe current congestion and surface recombination losses. These shortcomings prevent traditional red LEDs from meeting the specific application requirements of high directivity, low power consumption, and narrow beams.

[0004] To address the aforementioned bottlenecks, researchers have recently begun exploring single-aperture light-emitting structures. By limiting the effective aperture of the active region, the emission angle is physically compressed, while simultaneously improving the uniformity of current distribution. However, simply reducing the size of the emission window cannot solve the problem of interfacial contact stability under microcurrents, and it is also prone to increased leakage current due to defects at the window edge. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a single-aperture red LED and its fabrication method. This red LED effectively solves the problems of light leakage, unconcentrated light source, and uneven current spread, achieving significant angle compression, reduced contact resistance, and high reliability for long-term operation.

[0006] The first objective of this invention is to provide a single-aperture red LED, which, from bottom to top, comprises a back electrode, a Si substrate, a bonding layer, an AgTiW mirror, a dielectric film, an IZO (indium zinc oxide) contact layer, a GaP, a confinement layer, a P-type semiconductor, a light-emitting layer, an N-type semiconductor, a front contact electrode, a passivation layer, and a front pad electrode. The red LED has a single-hole light-emitting area; The single-hole light-emitting region has multiple dielectric holes arrayed within it. The size of the AgTiW mirror is matched to the single-aperture light-emitting area; The GaP is located within the dielectric pore and connected to the AgTiW mirror surface through the IZO contact layer.

[0007] This invention designs the light-emitting area as a single-hole light-emitting area, and then expands the single-hole light-emitting area into a multi-hole array, which gives it a stronger light confinement capability. At the same time, the multi-hole array can also disperse current, avoid overheating of the single hole, and improve stability. Using IZO as a transparent conductive contact layer can reduce contact resistance and improve current spreading capability. At the same time, by connecting GaP and AgTiW mirrors through IZO, the chip achieves low resistance and high reflection. High GaP doping achieves lateral current confinement, so that the light source is concentrated from the single hole, which significantly compresses the emission angle of the red light point source and reduces contact resistance.

[0008] Furthermore, in the AgTiW mirror, the thickness of Ag is 1500±100Å, and the thickness of TiW is 1000±50Å.

[0009] Furthermore, the dielectric film is made of silicon oxide and has a thickness of 3000Å-6000Å.

[0010] Furthermore, the bonding layer is made of TiPtAu.

[0011] Furthermore, the thickness of the GaP is 1μm-1.5μm.

[0012] Furthermore, the front pad electrode covers the entire surface except for the single-hole light-emitting area and also covers the sidewalls of the passivation layer. In this technical solution, a front pad electrode is applied to the surface of the passivation layer, providing double-layer protection, reducing the risk of sidewall leakage, and aiding current spread. This allows the current to spread as evenly as possible throughout the device, reducing LED voltage and improving light extraction efficiency.

[0013] The second objective of this invention is to provide a method for fabricating a single-aperture red LED, comprising the following steps: (1) After cleaning the surface of the epitaxial wafer, an amorphous thin film IZO is deposited on its surface. Using positive resist as a mask pattern, and combined with ICP etching technology, the IZO and the underlying GaP are imaged to create the IZO contact layer. (2) A dielectric film is deposited on the surface of the wafer source by PECVD (plasma-enhanced chemical vapor deposition), and an array of dielectric holes is fabricated by using positive photoresist as a mask pattern and dry etching. (3) Using negative adhesive as a mask pattern, magnetron sputtering and peeling process are used to make a local reflective mirror, and an AgTiW mirror layer is sputtered. (4) Using electron beam evaporation, a bonding layer is deposited on the surface of the epitaxial wafer and bonded to a silicon wafer with TiPtAu deposited on its surface; (5) Using negative adhesive as a mask pattern, combined with electron beam evaporation and negative adhesive stripping technology, the front contact electrode is fabricated; (6) Use positive adhesive to make a mask pattern and wet etching to make a passivation layer; (7) Use negative adhesive as a mask pattern, and combine it with metal vapor deposition technology and negative adhesive stripping technology to fabricate the front pad electrode; (8) The back electrode is fabricated by mechanically thinning the Si substrate, alloying, cutting with blades, and testing to complete the fabrication of the red LED chip.

[0014] Further, in step (1), the ICP etching process is as follows: power of 590W / 240W, BCl3 flow rate of 10sccm-12sccm, Cl2 flow rate of 8sccm-12sccm, and HBr flow rate of 50sccm-60sccm; in step (2), the ICP etching process is as follows: power of 590W / 240W, BCl3 flow rate of 10sccm-15sccm, Cl2 flow rate of 6sccm-8sccm, and CF4 flow rate of 90sccm-110sccm. Specifically, the power of 590W / 240W refers to the power of the ICP RF source and the RF source being 590W and 240W respectively.

[0015] Furthermore, in step (4), the bonding layer is bonded using In-Au bonding. First, TiPtAu is deposited by evaporation with thicknesses of 500nm / 800nm / 10000nm, and then In is deposited by evaporation. The total thickness of the bonding layer is 2.2μm. The bonding process is as follows: temperature is 210℃-230℃, and pressure is 2000kg-2200kg.

[0016] Further, in step (5), the materials of the front contact electrodes are Au / AuGeNi / Au / Ti / Au, with thicknesses of 400Å-600Å / 800Å-1200Å / 3000Å-4000Å / 400Å-600Å / 800Å-1200Å respectively; in step (7), the materials of the front pad electrodes are TiW / Au / Au / AuGeNi / Au / Pt / Au, with electrode thicknesses of 150Å-250Å / 1200Å-1700Å / 300Å-500Å / 700Å-900Å / 3000Å-4000Å / 700Å-900Å / 25000Å-35000Å respectively.

[0017] Compared with the prior art, the present invention has the following advantages: This invention optimizes the device structure, particularly by setting the single-aperture light-emitting area as a multi-aperture array, to achieve beam confinement and current dispersion. Simultaneously, the spacing between apertures and the contact layer pattern can be adjusted to improve total power and directivity. By sputtering an amorphous thin-film contact layer IZO on the epitaxial layer and patterning the IZO and the underlying GaP, the highly doped GaP remains within the dielectric aperture, creating an impedance difference within the chip source. Current preferentially enters from the low-impedance vertical channel, achieving lateral current confinement and concentrating the light source emission from a single aperture. Through patterning and a stripping process, a silver mirror is sputtered below the single-aperture light-emitting area, introducing low-resistivity Ag as a reflector to achieve low chip resistance and high reflectivity, reducing chip voltage and increasing chip brightness. By covering the passivation layer surface with a front-side pad electrode, the risk of sidewall leakage is reduced and current spread is facilitated, lowering LED voltage and improving light extraction efficiency. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the red LED chip structure with single-hole light emission according to the present invention; Figure 2 This is a top view of the red LED chip with single-hole light emission according to the present invention.

[0019] Explanation of the labels in the diagram: 1. Back electrode; 2. Si substrate; 3. Bonding layer; 4. AgTiW mirror; 5. Dielectric film; 6. IZO contact layer; 7. GaP; 8. Confinement layer; 9. P-type semiconductor; 10. Light-emitting layer; 11. N-type semiconductor; 12. Front contact electrode; 13. Passivation layer; 14. Front pad electrode. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0022] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0023] Please see Figures 1 to 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] One embodiment of the present invention provides a single-aperture red LED, the structural schematic of which is shown below. Figure 1 As shown, the red LED, from bottom to top, includes a back electrode 1, a Si substrate 2, a bonding layer 3, an AgTiW mirror 4, a dielectric film 5, an IZO contact layer 6, a GaP 7, a confinement layer 8, a P-type semiconductor 9, a light-emitting layer 10, an N-type semiconductor 11, a front contact electrode 12, a passivation layer 13, and a front pad electrode 14. The red LED has a single-hole light-emitting area; The single-aperture emitting region contains an array of multiple dielectric apertures. The small-diameter array of dielectric apertures provides better light confinement, and high power and high directivity can be achieved by adjusting the spacing between the apertures and the contact layer pattern. Specifically, the aperture diameter d of the dielectric apertures is controlled between 5μm and 50μm. The array-type dielectric aperture design of this invention further optimizes the current density distribution and far-field emission angle. The lower limit of 5μm prevents excessive proximity between dielectric apertures, which can lead to current congestion and heat accumulation. When d < 5μm, the active region between apertures is excessively depleted, resulting in excessively high local current density and accelerated device aging. The upper limit of 50μm ensures that the lateral current spread capability of ITO matches the aperture spacing. The typical sheet resistance of ITO is 50Ω / sq-100Ω / sq, and its effective lateral diffusion length is approximately 30μm-40μm. If d > 50μm, insufficient current overlap between adjacent apertures will create dark areas and reduce light output uniformity. In this embodiment, the preferred aperture spacing d=20μm, at which point the current injected into adjacent apertures overlaps at the midpoint between the apertures, resulting in a uniform light intensity distribution.

[0025] The size of the AgTiW mirror is matched to the single-aperture light-emitting area; The GaP is located within the dielectric aperture and connected to the AgTiW mirror via the IZO contact layer. By placing the GaP and IZO contact layer within the porous array dielectric aperture, the high doping and relatively low resistivity of GaP can be utilized to create an impedance difference within the wafer source. This causes current to preferentially enter from the low-impedance vertical channel, achieving lateral current confinement. Consequently, the light source is more concentrated, emitting light from the single-aperture emitting region, forming a highly concentrated point-like light spot.

[0026] In some embodiments, the AgTiW mirror has a thickness of 1500±100 Å and a TiW thickness of 1000±50 Å. As a low-resistivity reflector, the AgTiW mirror can further achieve low resistance and high reflectivity in the chip, thereby improving chip brightness.

[0027] In some embodiments, the dielectric film is made of silicon oxide with a thickness of 3000 Å-6000 Å; the bonding layer is made of TiPtAu; and the GaP layer has a thickness of 1 μm-1.5 μm.

[0028] In some embodiments, the front pad electrode covers the entire surface except for the single-hole light-emitting area and also covers the sidewalls of the passivation layer. By covering the passivation layer surface with a front pad electrode, double protection is achieved, reducing the risk of sidewall leakage while helping current spread, allowing the current to spread as evenly as possible throughout the device, reducing LED voltage and improving light extraction efficiency.

[0029] Another embodiment of the present invention provides a method for preparing a single-aperture red LED, comprising the following steps: (1) After cleaning the surface of the epitaxial wafer, an amorphous thin film IZO is deposited on its surface. Using positive resist as a mask pattern and combined with ICP etching technology, the IZO and the underlying GaP are imaged to create the IZO contact layer; specifically, First, a GaAs substrate is provided as the epitaxial structure growth substrate, and the epitaxial layer is grown from bottom to top until the outermost surface contains a 1μm-1.5μm GaP layer; Then, the epitaxial wafer is organically cleaned and sputtered using magnetron sputtering with a sputtering power of 500W and an oxygen flow rate of 0.2 sccm. An amorphous thin film IZO is sputtered on the surface of the epitaxial wafer to create an ohmic contact on the P-side. Positive photoresist is used as a mask pattern, and ICP etching technology is used to pattern the IZO and the underlying GaP. The ICP etching power is 590W / 240W, the BCl3 flow rate is 10-12 sccm, the Cl2 flow rate is 8-12 sccm, and the HBr flow rate is 50-60 sccm. The IZO pattern is adapted to the size of the point light source core (i.e., the single-hole light-emitting area).

[0030] (2) A dielectric film is deposited on the surface of the wafer source using PECVD, and a mask pattern is created using positive photoresist. Dry etching is then employed to fabricate an array of dielectric vias. Specifically, A 3000Å-6000Å silicon oxide dielectric film was deposited by PECVD, and a positive photoresist was used as a mask pattern. The silicon oxide was then etched by dry ICP to create the dielectric via pattern. The ICP etching power was 590W / 240W, the BCl3 flow rate was 10sccm-15sccm, the Cl2 flow rate was 6sccm-8sccm, and the CF4 flow rate was 90sccm-110sccm. The dielectric via pattern was adapted to the size of the point light source chip.

[0031] (3) A negative adhesive is used as a mask pattern. A local reflector is made by using magnetron sputtering and a stripping process, and an AgTiW mirror is sputtered. Specifically, in the AgTiW reflector, the thickness of Ag is 1500±100Å and the thickness of TiW is 1000±50Å.

[0032] (4) Using electron beam evaporation, a bonding layer is deposited on the surface of the epitaxial wafer and bonded to the silicon wafer with TiPtAu deposited on the surface. Specifically, using electron beam evaporation, TiPtAu with a thickness of 500nm / 800nm / 10000nm is first deposited, and then In is deposited until the total thickness of the bonding layer is 2.2μm. Then the epitaxial layer is bonded to the silicon wafer with TiPtAu deposited on the surface. The bonding temperature is 210℃-230℃ and the pressure is 2000kg-2200kg.

[0033] (5) A negative adhesive is used as a mask pattern, and electron beam evaporation and negative adhesive stripping are used to fabricate the front contact electrode. Specifically, the material layers of the front contact electrode are Au / AuGeNi / Au / Ti / Au, and the thickness of the electrode material is 400Å-600Å / 800Å-1200Å / 3000Å-4000Å / 400Å-600Å / 800Å-1200Å, preferably 500Å / 1000Å / 3600Å / 500Å / 1000Å.

[0034] (6) Use positive photoresist as a mask pattern and wet etching to form a passivation layer; specifically, use positive photoresist as a mask pattern and dry ICP etching to form a mesa, wherein the ICP etching power is 800W, the BCl3 flow rate is 35sccm-45sccm, the Cl2 flow rate is 12sccm-16sccm, the HBr flow rate is 8sccm-12sccm, and the N2 flow rate is 50sccm-70sccm; then, through organic cleaning, use PECVD to deposit a passivation layer SiN, and further use positive photoresist photolithography and wet etching technology to form a SiN pattern, wherein the thickness of the SiN layer is 5400Å, and use a fluorine-containing solution to etch the SiN that is not protected by the photoresist.

[0035] (7) A negative adhesive is used as a mask pattern, and metal vapor deposition and negative adhesive stripping are used to fabricate the front pad electrode. Specifically, the material layers of the front pad electrode are TiW / Au / Au / AuGeNi / Au / Pt / Au, and the electrode thicknesses are 150Å-250Å / 1200Å-1700Å / 300Å-500Å / 700Å-900Å / 3000Å-4000Å / 700Å-900Å / 25000Å-35000Å, preferably 200Å / 1500Å / 400Å / 800Å / 3600Å / 800Å / 27200Å.

[0036] (8) The back electrode was fabricated by mechanically thinning the Si substrate, followed by alloying, blade cutting, and testing to complete the fabrication of the red LED chip. Its top view is shown below. Figure 2 As shown.

[0037] The present invention will be further described below through specific embodiments: Example 1 A method for fabricating a single-aperture red LED includes the following steps: (1) First, a GaAs substrate is provided as the epitaxial growth substrate, and an epitaxial layer is grown from bottom to top until the outermost surface contains a 1μm GaP layer; then, the epitaxial wafer is organically cleaned and magnetron sputtering is used, with a sputtering power of 500W and an oxygen flow rate of 0.2sccm. An amorphous thin film IZO is sputtered on the surface of the epitaxial wafer to make a P-side ohmic contact. Positive photoresist is used as a mask pattern, and ICP etching technology is used to pattern the IZO; the ICP etching power is 590W / 240W, the BCl3 flow rate is 12sccm, the Cl2 flow rate is 10sccm, and the HBr flow rate is 55sccm. The IZO pattern is adapted to the core size of the point light source (i.e., the single-hole light-emitting area).

[0038] (2) A 5000Å silicon oxide dielectric film was deposited by PECVD. The mask pattern was made by using positive photoresist. The silicon oxide was etched by dry ICP to create the dielectric hole pattern. The ICP etching power was 590W / 240W, the BCl3 flow rate was 15sccm, the Cl2 flow rate was 7sccm, and the CF4 flow rate was 100sccm. The d size of the dielectric hole pattern was 20μm.

[0039] (3) A negative adhesive is used as a mask pattern. A local reflector is made by using magnetron sputtering and a stripping process. An AgTiW mirror is sputtered, with the Ag layer having a thickness of 1500 Å and the TiW layer having a thickness of 1000 Å.

[0040] (4) Using electron beam evaporation, first deposit TiPtAu with a thickness of 500nm / 800nm / 10000nm, then deposit In until the total thickness of the bonding layer is 2.2μm; then bond the epitaxial layer to the silicon wafer with TiPtAu deposited on the surface at a bonding temperature of 220℃ and a bonding pressure of 2200kg.

[0041] (5) A negative adhesive is used as a mask pattern, and electron beam evaporation and negative adhesive stripping are used to fabricate the front contact electrode. The material layers of the front contact electrode are Au / AuGeNi / Au / Ti / Au, and the thicknesses of the electrode materials are 500Å / 1000Å / 3600Å / 500Å / 1000Å, respectively.

[0042] (6) Use positive photoresist as a mask pattern, dry ICP etching to create a mesa, wherein the ICP etching power is 800W, the BCl3 flow rate is 40sccm, the Cl2 flow rate is 15sccm, the HBr flow rate is 10sccm, and the N2 flow rate is 60sccm; then, through organic cleaning, a passivation layer SiN is deposited using PECVD, and further SiN pattern is created using positive photoresist photolithography and wet etching technology, wherein the thickness of the SiN layer is 5400Å, and the SiN not protected by photoresist is etched using a fluorine-containing solution.

[0043] (7) Using negative adhesive as a mask pattern, and combining metal vapor deposition technology and negative adhesive stripping technology, the front pad electrode is fabricated. The material layers of the front pad electrode are TiW / Au / Au / AuGeNi / Au / Pt / Au, and the electrode thicknesses are 200Å / 1500Å / 400Å / 800Å / 3600Å / 800Å / 27200Å, respectively.

[0044] (8) The back electrode is fabricated by mechanically thinning the Si substrate, alloying, cutting with blades, and testing to complete the fabrication of the red LED chip.

[0045] Comparative Example 1 A traditional red LED chip, fabricated using conventional methods.

[0046] The divergence angles of the red LED obtained in Example 1 and the conventional red LED in Comparative Example 1 were compared. The divergence angle of the red LED in Example 1 was 60°, while that of the red LED in Comparative Example 1 was 135°. It can be seen that the red LED optimized by this invention has a significantly compressed emission angle, good directivity, and high brightness.

[0047] In summary, by rationally optimizing the device structure, especially by setting the single-hole light-emitting area into a multi-hole array, and combining the design of the reflector and the front pad electrode, the present invention achieves a significant reduction in the emission angle of the red LED, a decrease in contact resistance, and an improvement in long-term operational reliability.

[0048] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A single-aperture red LED, characterized in that, The red LED, from bottom to top, includes a back electrode, a Si substrate, a bonding layer, an AgTiW mirror, a dielectric film, an IZO contact layer, a GaP layer, a confinement layer, a P-type semiconductor, a light-emitting layer, an N-type semiconductor, a front contact electrode, a passivation layer, and a front pad electrode. The red LED has a single-hole light-emitting area; The single-hole light-emitting region has multiple dielectric holes arrayed within it. The size of the AgTiW mirror is matched to the single-aperture light-emitting area; The GaP is located within the dielectric pore and connected to the AgTiW mirror surface through the IZO contact layer.

2. A single-aperture red LED according to claim 1, characterized in that, In the AgTiW mirror, the thickness of Ag is 1500±100Å and the thickness of TiW is 1000±50Å.

3. A single-aperture red LED according to claim 1, characterized in that, The dielectric film is made of silicon oxide and has a thickness of 3000Å-6000Å.

4. A single-aperture red LED according to claim 1, characterized in that, The bonding layer is made of TiPtAu.

5. A single-aperture red LED according to claim 1, characterized in that, The thickness of the GaP is 1μm-1.5μm.

6. A single-aperture red LED according to claim 1, characterized in that, The front pad electrode covers the entire surface except for the single-hole light-emitting area and covers the sidewalls of the passivation layer.

7. A method for preparing a single-aperture red LED according to any one of claims 1-6, characterized in that, Includes the following steps: (1) After cleaning the surface of the epitaxial wafer, an amorphous thin film IZO is deposited on its surface. Using positive resist as a mask pattern, and combined with ICP etching technology, the IZO and the underlying GaP are imaged to create the IZO contact layer. (2) A dielectric film is deposited on the surface of the wafer source by PECVD, and a mask pattern is made by using positive photoresist and dry etching to create an array of dielectric aperture patterns. (3) Using negative adhesive as a mask pattern, magnetron sputtering and peeling process are used to make a local reflective mirror, and an AgTiW mirror layer is sputtered. (4) Using electron beam evaporation, a bonding layer is deposited on the surface of the epitaxial wafer and bonded to a silicon wafer with TiPtAu deposited on its surface; (5) Using negative adhesive as a mask pattern, combined with electron beam evaporation and negative adhesive stripping technology, the front contact electrode is fabricated; (6) Use positive adhesive to make a mask pattern and wet etching to make a passivation layer; (7) Use negative adhesive as a mask pattern, and combine it with metal vapor deposition technology and negative adhesive stripping technology to fabricate the front pad electrode; (8) The back electrode is fabricated by mechanically thinning the Si substrate, alloying, cutting with blades, and testing to complete the fabrication of the red LED chip.

8. The method for preparing a single-aperture red LED according to claim 7, characterized in that, In step (1), the ICP etching process is as follows: power is 590W / 240W, BCl3 flow rate is 10sccm-12sccm, Cl2 flow rate is 8sccm-12sccm, and HBr flow rate is 50sccm-60sccm; in step (2), the ICP etching process is as follows: power is 590W / 240W, BCl3 flow rate is 10sccm-15sccm, Cl2 flow rate is 6sccm-8sccm, and CF4 flow rate is 90sccm-110sccm.

9. A method for preparing a single-aperture red LED according to claim 7, characterized in that, In step (4), the bonding layer is bonded using In-Au bonding. First, TiPtAu is deposited by evaporation with thicknesses of 500nm / 800nm / 10000nm, and then In is deposited by evaporation. The total thickness of the bonding layer is 2.2μm. The bonding process is as follows: temperature is 210℃-230℃, and pressure is 2000kg-2200kg.

10. A method for preparing a single-aperture red LED according to claim 7, characterized in that, In step (5), the materials of the front contact electrodes are Au / AuGeNi / Au / Ti / Au, with thicknesses of 400Å-600Å / 800Å-1200Å / 3000Å-4000Å / 400Å-600Å / 800Å-1200Å respectively; in step (7), the materials of the front pad electrodes are TiW / Au / Au / AuGeNi / Au / Pt / Au, with electrode thicknesses of 150Å-250Å / 1200Å-1700Å / 300Å-500Å / 700Å-900Å / 3000Å-4000Å / 700Å-900Å / 25000Å-35000Å respectively.

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