Current reuse low noise amplifier (LNA)

Abstract

Current reuse low noise amplifiers (LNAs) are disclosed. In one aspect, a low noise amplifier places at least two common source transistors (224, 244) in parallel from a radio frequency perspective while reusing current from a direct current perspective. The combined output from at least one common gate transistor (402) provides a desired amplified signal. Variations of these aspects allow for improved noise performance, reduced current requirements, space savings, and other flexibility in meeting design requirements.

Description

Priority application

[0001] This application relates to U.S. Provisional Patent Application No. 63 / 569,295, filed March 25, 2024, entitled “Current Reuse Low Noise Amplifier (LNA)”, the contents of which are incorporated herein by reference in their entirety. background Technical Field

[0002] The technology disclosed herein relates generally to low-noise amplifiers (LNAs), and more particularly to providing designers with greater flexibility in meeting design criteria related to noise factor, size, voltage margin, current consumption and cost. Background Technology

[0003] Communication devices are ubiquitous in modern society, and more specifically, mobile communication devices have become increasingly prevalent. This widespread use is partly driven by the numerous features now enabled on such devices. The increased processing power in these devices means they have evolved from mere communication tools into sophisticated mobile entertainment hubs, thus enhancing the user experience. With the proliferation of functions available for these devices, the pressure to find greater bandwidth—through which data can be sent to and from them—has increased. This bandwidth pressure has led to the continuous evolution of wireless protocols using increasingly higher frequencies and more complex coding techniques. Adapting to these new protocols presents challenges to the hardware used to send and receive signals compliant with these new protocols. Simultaneously, mobile communication devices face pressure to reduce power consumption to extend battery life. Therefore, giving designers flexibility in meeting these demands provides room for innovation. Summary of the Invention

[0004] The aspects disclosed in the specific implementation include a current-reuse low-noise amplifier (LNA). Specifically, the LNA arranges at least two common-source transistors in parallel from an RF perspective, while reusing current from a DC perspective. The combined output from at least one common-gate transistor provides the desired amplified signal. These changes allow for improved noise performance, reduced current requirements, space savings, and additional flexibility in meeting design requirements.

[0005] In this regard, in one aspect, an LNA structure is disclosed. The LNA structure includes an input node and an output node configured to receive radio frequency (RF) signals, and a first LNA including a first common-source n-type field-effect transistor (NFET) coupled between the input node and the output node. The LNA structure also includes a second LNA including a second common-source NFET coupled between the input node and the output node, the second LNA being electrically parallel to the first LNA in the RF domain and sharing a direct current (DC) current.

[0006] In another aspect, an LNA structure is disclosed. The LNA structure includes an input node configured to receive an RF signal and an output node. The LNA structure also includes a first LNA and a second LNA, the first LNA including a first common-source p-type field-effect transistor (PFET) coupled between the input node and the output node, and the second LNA including a second common-source PFET coupled between the input node and the output node. The second LNA is electrically parallel to the first LNA in the RF domain and shares a DC current.

[0007] In another aspect, a receiver is disclosed. The receiver includes an antenna and an LNA structure coupled to the antenna. The LNA structure includes an input node configured to receive RF signals and an output node. The LNA structure also includes a first LNA and a second LNA, the first LNA including a first common-source NFET coupled between the input node and the output node, and the second LNA including a second common-source NFET coupled between the input node and the output node, the second LNA being electrically parallel to the first LNA in the RF domain and sharing a DC current.

[0008] In another aspect, an LNA structure is disclosed. The LNA structure includes an input node configured to receive an RF signal, an output node, and a common-gate field-effect transistor (FET) coupled to the output node. The LNA structure also includes a first LNA and a second LNA. The first LNA includes a first common-source n-type FET (NFET) coupled between the input node and the common-gate FET. The second LNA includes a common-source PFET coupled between the input node and the common-gate FET. The second LNA is electrically parallel to the first LNA in the RF domain, wherein the common-gate FET, the first common-source NFET, and the common-source PFET share a DC current.

[0009] In another aspect, a method for operating a low-noise amplifier structure is disclosed. The method includes: receiving a signal to be amplified at an input node; splitting the signal to be amplified into a first signal and a second signal, the first signal being routed to a first LNA stage and the second signal being routed to a second LNA stage connected in parallel with the first LNA stage; and sharing a DC current between the first LNA stage and the second LNA stage. The method further includes: amplifying the first signal using a first common-source NFET in the first LNA stage; amplifying the second signal using a second common-source NFET in the second LNA stage; and combining the first signal and the second signal. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of a conventional low-noise amplifier (LNA);

[0011] Figure 2 This is a circuit diagram of a low-noise amplifier, in which two half-size LNAs are stacked in parallel from a radio frequency (RF) perspective, but share current from a direct current (DC) perspective, and have options for improving noise factor, current limit, size, etc.

[0012] Figure 3A It is a circuit diagram that can be used in some designs of stacked LNAs without common gate transistors;

[0013] Figure 3B Is using Figure 3A The circuit diagram shows a circuit with mutual coupling between some inductors;

[0014] Figure 4A This is a circuit diagram of a stacked LNA with a shared common gate transistor;

[0015] Figure 4B Is using Figure 4A The circuit diagram shows a circuit with mutual coupling between some inductors;

[0016] Figure 5 This is a circuit diagram of a stacked LNA with coupled inductors to help provide additional design options;

[0017] Figure 6 This is a circuit diagram of three stacked LNAs that can be used with higher power supply voltages;

[0018] Figure 7 This is a circuit diagram of three stacked LNAs with parallel common-source stages and shared common-gate stages from an RF perspective, where all four stages share a similar configuration. Figure 6 DC current;

[0019] Figure 8This is a circuit diagram of a stacked complementary LNA that may be suitable for some design standards;

[0020] Figure 9 It is similar to Figure 8 However, it has a circuit diagram that may be suitable for some design standards for a common-gate P-type field-effect transistor;

[0021] Figure 10 This is a flowchart illustrating an exemplary process for using a parallel LNA according to various aspects of this disclosure;

[0022] Figure 11 According to this disclosure, it may include Figure 2-9 Block diagram of a mobile communication device with an LNA;

[0023] Figure 12 It is similar to Figure 8 The circuit, but relative to Figure 8 The circuit has a circuit diagram with inverted common-source and common-gate stages; and

[0024] Figure 13 It is similar to Figure 9 The circuit, but relative to Figure 9 The circuit diagram has inverted common-source and common-gate stages. Detailed Implementation

[0025] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0026] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or intermediate elements may be present. In contrast, when an element is referred to as "directly on" or "directly" extending "to" another element, no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0028] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms and those discussed above are intended to include different orientations of the device other than those depicted in the figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0031] Consistent with the statements regarding definitions above, this disclosure uses the term "transceiver" in a broad manner. Current industry literature uses "transceiver" in two ways. A first way broadly refers to a transceiver as a circuit that transmits and receives multiple signals. Exemplary circuitry may include a baseband processor coupled to one or more antennas, up / down conversion circuitry, filters, amplifiers, couplers, etc. A second way, used by some authors of industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuitry as a transceiver. This intermediate circuitry may include up / down conversion circuitry, mixers, oscillators, filters, etc., but typically does not include a power amplifier. As used herein, the term transceiver is used in the first sense. Where necessary to distinguish between the two definitions, the terms "transceiver chain" and "transceiver circuitry" are used respectively.

[0032] In addition, the extent to which the term “approximately” is used in the claims is defined herein as within twenty-five percent (25%).

[0033] The aspects disclosed in the specific implementation include a current-reuse low-noise amplifier (LNA). Specifically, the LNA arranges at least two common-source transistors in parallel from an RF perspective, while reusing current from a DC perspective. The combined output from at least one common-gate transistor provides the desired amplified signal. These changes allow for improved noise performance, reduced current requirements, space savings, and additional flexibility in meeting design requirements.

[0034] Before discussing the various aspects of this disclosure, refer to Figure 1 This provides a brief overview of a typical LNA, along with a discussion of the challenges such a structure faces in today's business environment. See below for references. Figure 2 This discussion begins with the various aspects of this disclosure and the flexibility they offer in addressing those challenges.

[0035] In this regard, Figure 1A typical LNA 100 is shown. As explained below, this LNA 100 is a common-source, common-gate LNA (sometimes referred to as a CS-CG LNA or a cascaded common-source LNA). LNA 100 has an input node 102 (RFin) and an output node 104 (RFout). A voltage source Vdd is provided at the power supply node 106 via a capacitor 108, a battery (not shown), both, or similar means. An RLC circuit 110 is formed by a resistor 112, an inductor 114, and a capacitor 116. The power supply node 106 is coupled to the output node 104 via the RLC circuit 110 and an output matching capacitor 118. The output matching capacitor 118 provides some DC blocking but may also contribute to impedance transformation. Therefore, the RLC circuit 110 and the output matching capacitor together form an output matching network. A common-source transistor 120 has a gate 120G, which is coupled to the input node 102 via a matching inductor 122 and a DC blocking capacitor 124. A bias voltage can also be applied to the gate 120G via bias resistor 126. The source 120S of the common-source transistor 120 is coupled to ground 128 via source degradation inductor 130. The common-gate transistor 132 couples the common-source transistor 120 to capacitor 118. A second bias biases the gate 132G via a second bias resistor 134. In most typical LNAs of this type, the transistors are field-effect transistors (FETs), and more specifically, n-type FETs (NFETs).

[0036] In many cases, Vdd is set by the mobile device's battery, power management circuitry (e.g., with a DC-DC converter), or otherwise available within the system. However, the LNA 100 can operate at a lower voltage. One past effort to utilize this difference between the available and desired supply voltage involved series reuse of current, where current flows through LNA stages arranged in series. Another past effort relied on complementary processes, where the first LNA stage relied on an NFET, and the second parallel LNA stage relied on a p-type FET (PFET). While each has its merits, each effort offers only limited design flexibility.

[0037] The aspects of this disclosure envision using only NFETs to place the LNA stage in a parallel radio frequency (RF) signal path, said NFETs being able to operate at half of a specified supply while sharing direct current (DC). Designers can then choose between improved noise factor (NF), reduced current consumption, or some other possible space-saving options as described below. This additional design flexibility provides designers with better options.

[0038] In this regard, Figure 2This is a circuit diagram of a first aspect of a parallel LNA that allows current reuse via stacked NFETs. Specifically, LNA structure 200 includes an input node 202 (RFin) and an output node 204 (RFout). Between input node 202 and output node 204, a first LNA stage 206 and a second LNA stage 208 are positioned in parallel with each other after sharing an input matching inductor 210. Note that if LNA stages 206 and 208 are comparable in size to LNA 100 and have similar DC currents, the input matching inductor 210 may tend to be smaller, and in one tested aspect, the inductance of the input matching inductor 210 may be approximately half that of the matching inductor 122 (e.g., 4 nanohenries (nH)) (e.g., 2.2 nH). This reduction in inductance means that physically smaller inductors can be used. This reduction in inductor size also means that the noise factor (NF) is less sensitive to the inductor Q. The combination of a lower Q and a smaller inductor means that in some cases, the smaller inductor can be a printed inductor, printed on a laminate along with other circuitry, rather than a high-Q surface mount device (SMD) inductor.

[0039] Alternatively, if the dimensions of LNA stages 206 and 208 are changed relative to LNA 100 (e.g., halved), the DC current can also be changed (e.g., halved could be half the DC current). However, despite the halved current, it appears to be a conventional LNA 100 operating at twice the current.

[0040] Continue to refer to Figure 2 The first LNA stage 206 can be coupled to a voltage source node 212, which has a supply voltage Vdd supplied by a capacitor 214, a DC-DC converter, a battery, or a similar device. Voltage source node 212 is coupled to a common-gate transistor 216 via an RLC circuit 218 at node 220. Node 220 is coupled to the output node 204 via a matching capacitor 222. Similarly, the combination of the RLC circuit 218 and the matching capacitor 222 can act as an impedance matching circuit. The common-gate transistor 216 is connected to the common-source transistor 224 in a common-source, common-gate configuration. The common-source transistor 224 is coupled to node 226 via a degenerate inductor 228. The gate 224G of the common-source transistor 224 is coupled to the input node 202 via a DC blocking capacitor 230 and biased via a bias resistor 232. Note that the DC blocking capacitor 230 can also form part of the RF matching. The gate 216G of the common-gate transistor 216 is biased via a bias resistor 234 and a capacitor 236.

[0041] Similarly, the second LNA stage 208 can be biased by Vmid, which is approximately Vdd / 2. Vmid is a function of the bias voltage through resistor 232 and the gate-source voltage drop of common-source transistor 224. In other respects, the second LNA stage 208 is almost identical to the first LNA stage 206. Vmid is supplied to the second common-gate transistor 238 through the second RLC circuit 240. The second common-gate transistor 238 is coupled to the output node 204 through the second matching capacitor 242, and the RLC circuit 240 and the matching capacitor 242 together form an impedance matching circuit. The second common-gate transistor 238 is connected to the second common-source transistor 244 in a common-source, common-gate configuration. The source 244S of the common-source transistor 244 is coupled to the degenerate inductor 246. The gate 244G of the common-source transistor 244 is coupled to the input node 202 through capacitor 248 and input matching inductor 210. The bias resistor 250 helps to bias the gate 244G. Similarly, bias resistor 252 and capacitor 254 bias the gate 238G of common gate transistor 238.

[0042] The two parallel paths are effectively combined at output node 204 to provide an amplified signal.

[0043] It should be understood that the LNA structure 200 can be used with different currents, different sizes and / or different Q requirements for one or more inductors, thus providing greater flexibility.

[0044] The LNA structure 200 has many arrangements, thus providing more design options. (Reference) Figure 3A-9 12 and 13 provide some exemplary permutations.

[0045] In this regard, Figure 3A The LNA structure 300 omits the common-gate transistors connected in a cascode configuration. This approach provides more headroom for a given Vdd, but at the cost of... Figure 2 The reverse isolation provided by the cascode structure. Otherwise, many components are identical, and repeated discussion is omitted. Figure 3B Similarly, but with the addition of mutual coupling 310 between degenerate inductors 228 and 246 to the LNA structure 300B. By using coupled inductors in this way, some area reduction is possible. The dimensions of the coupled source degenerate inductors (e.g., 228, 246) are only slightly larger than each constant uncoupled version, resulting in a relatively large area saving relative to the overall area of ​​the LNA structure 300.

[0046] Figure 4AAn LNA structure 400 combines common-gate transistors 216 and 238, connected in a cascode configuration, into a single common-gate transistor 402. A choke inductor 404 and a choke capacitor 406 are added instead of the RLC circuit 240 to force current through capacitor 408, thus combining the outputs of common-source transistors 224 and 244 for the common-gate transistor 402. This approach provides more output headroom by improving output compression characteristics while maintaining or improving reverse isolation. Note that Vmid may be lower than... Figure 2 and 3A Vmid in the equation. For example, if Vdd is 1.2V, then... Figure 4A The Vmid may be between approximately 0.15V and 0.4V. Note that adding mutual coupling may also provide space-saving benefits, such as... Figure 4B The LNA structure 400B is shown in the figure, in which source degradation inductors 228 and 246 are coupled (as shown by line 420).

[0047] Figure 5 Almost identical to LNA structure 200, but in LNA structure 500, inductor 502 is inductively coupled to inductor 504, and inductor 506 is inductively coupled to inductor 508. This inductive coupling can be used to replace or supplement the output capacitance coupling between capacitors 222 and 242. The coupling value K can be selected as needed. Load1Load2 and K Ls1Ls2 The Vmid of the LNA structure 500 is likely closer to Vdd / 2 (compared to...). Figure 4A Compared to Vdd).

[0048] Note that more than two LNA stages can be connected in parallel. Therefore, Figure 6 An LNA structure 600 is shown, which has three complete LNA stages 602, 604, and 606 arranged in parallel between input node 202 and output node 204. Each LNA stage 602, 604, and 606 includes both a common-gate transistor and a common-source transistor, similar to LNA structure 200. Note that Vmid1 will be approximately Vdd / 3, and Vmid2 will be approximately 2Vdd / 3.

[0049] In comparison, Figure 7The LNA structure 700 shown has three LNA stages 702, 704, and 706 sharing a common-gate transistor 708, similar to LNA structure 400. Both LNA structures 600 and 700 have a current reuse factor of three (instead of two), but may require a higher Vdd (e.g., 1.8V), while Vmid1 may be approximately 0.1–0.4V, and Vmid2 may be approximately Vmid1 + (0.1–0.4V). This approach can reduce current by a factor of three, or provide a greater improvement in NF at the same current through size settings. In either case, it provides designers with additional options.

[0050] While the above discussion assumes that each transistor uses an NFET homogeneously, the concepts behind the disclosed structure can be extended to complementary structures, such as... Figure 8 , 9 It is better shown in 12 and 13. In Figure 8 In this configuration, LNA structure 800 is similar to LNA structure 400 because it contains two common-source transistors 802 and 804 and a shared common-gate transistor 806. The first common-source transistor 802 and common-gate transistor 806 are NFETs, while the second common-source transistor 804 is a PFET. From an RF perspective, the two common-source transistors 802 and 804 undergo inductance degradation through inductors 808 and 810 respectively, but share the same load and DC current. A choke circuit 812 is provided to direct the current from the two common-source transistors 802 and 804 to the common-gate transistor 806. Similarly, Figure 12 LNA structure 1200 uses a complementary structure, but changes the order of transistors 802, 804, and 806, and adds a choke circuit formed by inductors 1202 and 1204 and capacitor 1206, similar to LNA structure 400. The total number of inductors is the same in LNA structure 800 and LNA structure 1200, and therefore, the space-saving options are comparable. Note that for LNA structure 800, Vmid can be approximately Vdd-0.15V to Vdd-0.4V. The Vmid of LNA structure 1200 is comparable to that of LNA structure 400.

[0051] Figure 9 An LNA structure 900 is shown, which inverts the common-gate transistor 902 as a PFET instead of the NFET of the LNA structure 800. This also inverts the position of the choke circuit 812 from between the second common-source transistor 804 and the common-gate transistor 806 to between the first common-source transistor 804 and the common-gate transistor 902. Similarly, Figure 13LNA structure 1300 uses a similar complementary structure, but like LNA structure 1200, it changes the transistor order. Similarly, the total number of inductors is the same between LNA structure 900 and LNA structure 1300. The Vmid of LNA structure 1300 is comparable to that of LNA structure 800.

[0052] It should also be noted that the LNA structures 2-7 can be implemented entirely using PFETs instead of the NFETs shown. While this option gives designers more flexibility, this approach may be less appealing because, with current technology, NFET technology achieves superior performance for LNAs.

[0053] Figure 10 A process 1000 for using an LNA structure according to aspects of this disclosure is illustrated. Process 1000 begins by receiving a signal to be amplified at input node 202 (box 1002). The LNA structure splits the signal into RF parallel LNA stages (box 1004). Each LNA stage amplifies the corresponding split signal using an RF parallel common-source transistor sharing a DC current (box 1006). The amplified signals are then combined (box 1008).

[0054] Current reuse LNAs disclosed herein can be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular mobile phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radio equipment, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor helicopters.

[0055] Figure 11 This is a schematic diagram of an exemplary communication device 1100, wherein the current reuse LNA of this disclosure may be provided, for example, in a receiver within a transceiver. In this document, communication device 1100 may be any type of communication device, such as those listed above, as well as access points, base stations (e.g., eNBs or gNBs), and any other type of wireless communication device that supports wireless communication, such as cellular, wireless local area networks (WLANs), Bluetooth, ultra-wideband (UWB), and near-field communication.

[0056] More specifically, the communication device 1100 will typically include a control system 1102, a baseband processor 1104, a transmitting circuit system 1106, a receiving circuit system 1108 (which may include the LNA of this disclosure), an antenna switching circuit system 1110, multiple antennas 1112, and a user interface circuit system 1114. In a non-limiting example, as an example, the control system 1102 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 1102 may include at least multiple microprocessors, multiple embedded memory circuits, and multiple communication bus interfaces. The receiving circuit system 1108 receives radio frequency signals from one or more base stations via antennas 1112 and through the antenna switching circuit system 1110. Low-noise amplifiers (e.g., those described above) and filters in the receiving circuit system 1108 cooperate to amplify the received signals and remove broadband interference from them for processing. Then, a downconversion and digitization circuitry system (not shown) downconverts the filtered received signal to an intermediate frequency (IF) or baseband frequency signal, and then uses (multiple) analog-to-digital converters (ADCs) to digitize the IF or baseband frequency signal into one or more digital streams.

[0057] The baseband processor 1104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 1104 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0058] For transmission, baseband processor 1104 receives digitized data representing voice, data, or control information from control system 1102 and encodes it for transmission. The encoded data is output to transmit circuitry system 1106, where digital-to-analog converters (DACs) convert the digitally encoded data into analog signals, and modulators modulate the analog signals onto carrier signals at one or more desired transmission frequencies. Power amplifiers amplify the modulated carrier signals to a level suitable for transmission, and antenna switching circuitry system 1110 delivers the modulated carrier signals to antenna 1112. Multiple antennas 1112 and replicated transmit circuitry system 1106 and receive circuitry system 1108 provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0059] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in many different orders other than those shown. Furthermore, the operations described in a single operational step may actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flowcharts may undergo many different modifications, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0060] The prior description of this disclosure is provided to enable any person skilled in the art to make or use it. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein. Claims (as amended under Article 19 of the Treaty) 1. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source n-type field-effect transistor (NFET) coupled between the input node and the output node. A second LNA, comprising a second common-source NFET coupled between the input node and the output node, the second LNA being electrically parallel to the first LNA in the RF domain and sharing a direct current (DC) current; and A first common-gate NFET is positioned between a first common-source NFET and the output node and shares the DC current. The first common-gate NFET is also positioned between a second common-source NFET and the output node so as to share the DC current with both the first and second common-source NFETs. 2. The LNA structure according to claim 1 further includes a choke coil between the first common-source NFET and the second common-source NFET. 3. The LNA structure according to claim 2, wherein the choke coil includes a choke capacitor and a choke inductor. 4. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source p-type field-effect transistor (PFET) coupled between the input node and the output node. A second LNA, comprising a second common-source PFET coupled between the input node and the output node, the second LNA being electrically parallel to the first LNA in the RF domain and sharing a direct current (DC) current; and A first common-gate PFET is positioned between a first common-source PFET and the output node, wherein the first common-gate PFET is also positioned between a second common-source PFET and the output node so as to share the DC current with the first common-source PFET and the second common-source PFET. 5. A receiver, comprising: antenna; A low-noise amplifier (LNA) structure coupled to the antenna, the LNA structure comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source n-type field-effect transistor (NFET) coupled between the input node and the output node. A second LNA, comprising a second common-source NFET coupled between the input node and the output node, the second LNA being electrically parallel to the first LNA in the RF domain and sharing a direct current (DC) current; and A first common-gate NFET is positioned between a first common-source NFET and the output node and shares the DC current, wherein the first common-gate NFET is also positioned between a second common-source NFET and the output node. 6. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A common-gate field-effect transistor (FET) coupled to the output node; The first LNA includes a first common-source n-type FET (NFET) coupled between the input node and the common-gate FET. The second LNA includes a common-source p-type FET (PFET) coupled between the input node and the common-gate FET, and the second LNA is electrically connected in parallel with the first LNA in the RF domain; The common-gate FET, the first common-source NFET, and the common-source PFET share a direct current (DC) current. 7. The LNA structure according to claim 6, wherein the common gate FET comprises an NFET. 8. The LNA structure according to claim 6, wherein the common gate FET comprises a common gate PFET. 9. The LNA structure according to claim 8 further includes a choke coil positioned between the first common-source NFET and the common-gate PFET. 10. A method of operating a low-noise amplifier structure, the method comprising: Receive the signal to be amplified at the input node; The signal to be amplified is split into a first signal and a second signal. The first signal is routed to a first low-noise amplifier (LNA) stage, and the second signal is routed to a second LNA stage connected in parallel with the first LNA stage. A direct current (DC) is shared between the first LNA stage and the second LNA stage; The first signal is amplified by the first common-source n-type field-effect transistor (NFET) in the first LNA stage and the first common-gate NFET cascaded with the first common-source NFET; The second signal is amplified using the second common-source NFET and the first common-gate NFET in the second LNA stage; and Combine the first signal and the second signal.

Claims

1. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source n-type field-effect transistor (NFET) coupled between the input node and the output node. as well as The second LNA includes a second common-source NFET coupled between the input node and the output node, and the second LNA is electrically parallel to the first LNA in the RF domain and shares a direct current (DC) current.

2. The LNA structure according to claim 1 further includes a first common-gate NFET, the first common-gate NFET being positioned between the first common-source NFET and the output node and sharing the DC current.

3. The LNA structure according to claim 2 further includes a second common-gate NFET, wherein the second common-gate NFET is cascaded with the second common-source NFET and positioned between the second common-source NFET and the output node.

4. The LNA structure of claim 2, wherein the first common-gate NFET is further positioned between the second common-source NFET and the output node so as to share the DC current with the first common-source NFET and the second common-source NFET.

5. The LNA structure according to claim 4 further includes a choke coil between the first common-source NFET and the second common-source NFET.

6. The LNA structure according to claim 5, wherein the choke coil comprises a choke capacitor and a choke inductor.

7. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source p-type field-effect transistor (PFET) coupled between the input node and the output node. as well as The second LNA includes a second common-source PFET coupled between the input node and the output node, and the second LNA is electrically parallel to the first LNA in the RF domain and shares a direct current (DC) current.

8. The LNA structure according to claim 7 further includes a first common-gate PFET, wherein the first common-gate PFET is positioned between the first common-source PFET and the output node.

9. A receiver, comprising: antenna; A low-noise amplifier (LNA) structure coupled to the antenna, the LNA structure comprising: An input node configured to receive radio frequency (RF) signals; Output node; A first LNA, the first LNA including a first common-source n-type field-effect transistor (NFET) coupled between the input node and the output node; and The second LNA includes a second common-source NFET coupled between the input node and the output node, and the second LNA is electrically parallel to the first LNA in the RF domain and shares a direct current (DC) current.

10. The receiver of claim 9, wherein the LNA structure further comprises a first common-gate NFET, the first common-gate NFET being positioned between the first common-source NFET and the output node and sharing the DC current.

11. The receiver of claim 10, wherein the LNA structure further comprises a second common-gate NFET, the second common-gate NFET being cascaded with the second common-source NFET and positioned between the second common-source NFET and the output node.

12. The LNA structure of claim 10, wherein the first common-gate NFET is further positioned between the second common-source NFET and the output node.

13. A low-noise amplifier (LNA) structure, comprising: An input node configured to receive radio frequency (RF) signals; Output node; A common-gate field-effect transistor (FET) coupled to the output node; The first LNA includes a first common-source n-type FET (NFET) coupled between the input node and the common-gate FET. The second LNA includes a common-source p-type FET (PFET) coupled between the input node and the common-gate FET, and the second LNA is electrically connected in parallel with the first LNA in the RF domain; The common-gate FET, the first common-source NFET, and the common-source PFET share a direct current (DC) current.

14. The LNA structure of claim 13, wherein the common-gate FET comprises an NFET.

15. The LNA structure of claim 13, wherein the common gate FET comprises a common gate PFET.

16. The LNA structure of claim 15 further includes a choke coil positioned between the first common-source NFET and the common-gate PFET.

17. A method of operating a low-noise amplifier structure, the method comprising: Receive the signal to be amplified at the input node; The signal to be amplified is split into a first signal and a second signal. The first signal is routed to a first low-noise amplifier (LNA) stage, and the second signal is routed to a second LNA stage connected in parallel with the first LNA stage. A direct current (DC) is shared between the first LNA stage and the second LNA stage; The first signal is amplified using the first common-source n-type field-effect transistor (NFET) in the first LNA stage; The second signal is amplified by the second common-source NFET in the second LNA stage; as well as Combine the first signal and the second signal.

18. The method of claim 17, wherein amplifying the first signal further comprises amplifying the first signal using a first common-gate NFET connected to the first common-source NFET in a common-source, common-gate configuration.

19. The method of claim 18, wherein amplifying the second signal further comprises amplifying the second signal using a second cascode NFET connected to the second cascode NFET in a cascode configuration.

20. The method of claim 18, wherein amplifying the second signal further comprises using the first common-gate NFET to further amplify the second signal.

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