D / A converter

Abstract

The resistor (R+) converts the total current of the plurality of current source units (3) into an analog output voltage. Each current source unit (3) inputs: first to fourth overlapping clocks (Φ1 to Φ4) whose phases are sequentially shifted by 90°; and a portion of each of the digital inputs corresponding to the current source unit (3) that is synchronized with the first to fourth overlapping clocks (Φ1 to Φ4), i.e., first to fourth digital inputs (D i1 ~D i4 ). Each current source unit (3) has first to fourth switch sections (SW1 to SW4) connected in parallel to each other and a current source (I0) connected in series to the first to fourth switch sections (SW1 to SW4). The first switch section (SW1) outputs the current of the current source (I0) in accordance with the first digital input (D i1 ) during a period in which the first and second overlapping clocks (Φ1, Φ2) overlap. The same applies to the switch sections (SW2 to SW4).

Description

Technical Field

[0001] This disclosure relates to D / A converters. Background Technology

[0002] Current-output type D / A converters (DACs) are practically used as the fastest conversion method among DACs, converting the current from a current source module flowing through a resistor into an analog voltage for output. Current source modules (cells) are broadly classified into two types: unary structures with multiple current source units having the same current value, and binary structures with multiple current source units weighted by a power of 2 ratio of current values. In a unary structure, the number of current source units controlling the output current is determined by the digital input. In a binary structure, the current source unit for the output current is selected based on the digital input. Thus, by controlling the current value of the current source module according to the digital input, an analog voltage corresponding to the magnitude of the digital input is output.

[0003] Each bit of the digital input has a binary weight (a power of 2). The D / A converter outputs an analog voltage corresponding to this weight. In the 8-bit case, the weight ratio from the least significant bit to the most significant bit is 1, 2, 4, ... 64, 128. When directly setting it as a binary structure of the current quantities of multiple current source units, the current quantities of the current source modules from the least significant bit to the most significant bit are I0=1I, I1=2I, I2=4I, ... I7=128I, starting from the least significant bit. However, bit switching, such as switching from 127 (01111111) to 128 (10000000), causes a problem. Current flows through 127 with I0+I1+I2+I3+I4+I5+I6, and current flows through 128 with I7. The current source unit that flows between 127 and 128 is replaced as a whole. Therefore, when the current quantity of each current source unit has an error and they are biased towards the positive or negative side and overlap, a large error (differential nonlinear error) is generated.

[0004] On the other hand, in the case of a unary structure, a current of 127I flows through 127, and a current of 127I+1I flows through 128. Therefore, the errors do not overlap and only become the error of the additional 1I, which can suppress the error. Therefore, the unary structure is more advantageous in terms of accuracy. However, the logic circuit needs to perform decoding processing to convert the binary code input to the current source module of the unary structure into thermometer code (also known as binary / unary conversion or binary / thermometer conversion). The more bits in the binary number, the more stages of logic processing this binary / unary conversion becomes, and the longer the processing time of the logic circuit. Due to this delay, the switching of the switches in the current source module is also delayed, thus slowing down the conversion speed. Therefore, considering the trade-off between accuracy and speed, segmented structures, in which the high-order side is a unary structure and the low-order side is a binary structure, are mostly used.

[0005] The current source unit has a current source through which a certain current value flows and a switch that controls whether to output that current (see, for example, Non-Patent Document 1). The operation of the current source unit is broadly divided into two types: single-ended operation and differential operation. In single-ended operation, two switches are used to switch whether to output the current from the current source module or discard it as a dummy current. In differential operation, two switches are used to switch whether to output the current from the current source module as a positive output or as a negative output.

[0006] A current source module for a quad switching system, in which two pairs of switches are connected to a single current source (see, for example, Non-Patent Document 2), is also proposed. While one pair is operating, the other decodes the next input data, thereby alternately extracting the output. Thus, since the delay of the logic circuit is no longer observed, a high-speed switching operation can be achieved.

[0007] From the moment a digital signal is input to the sub-DAC until the output voltage gradually transitions and stabilizes to its final value, a certain transition time is required. Therefore, a sub-DAC with two sets of current source modules featuring four-way switching is proposed. These sub-DACs operate alternately (time-interleaved operation), and the output is selectively extracted via a multiplexer (e.g., see Non-Patent Document 3). A total of four sets of switches switch with a 90° phase difference. The voltage during the transition period of the first half of each group's operation is not output; instead, the voltage stabilized to its final value during the second half of the operation is extracted as the output. Thus, because the transition time of the sub-DAC's output voltage can be shortened significantly, a speed increase of up to twice that of a single sub-DAC can be achieved.

[0008] Existing technical documents

[0009] Non-patent literature

[0010] Non-patent literature 1: A. van den Bosch, et al., "A 10-bit 1-GSample / s Nyquistcurrent-steering CMOS D / A converter," IEEE JSSC, Mar. 2001.

[0011] Non-patent literature 2: B. Schafferer, et al., "A 3V CMOS 400mW 14b 1.4GS / s DAC for Multi-Carrier Applications," IEEE ISSCC2004.

[0012] Non-patent literature 3: E. Olieman, et al., "An Interleaved Full Nyquist High-Speed ​​DAC Technique," IEEE JSSC, Mar. 2015. Summary of the Invention

[0013] The problem that the invention aims to solve

[0014] In the quad-switching DAC of Non-Patent Document 2, doubling the conversion speed is the limit. To further achieve higher speeds, Non-Patent Document 3 uses a multiplexer to time-interleave the two sub-DACs. However, since the two sub-DACs use independent current sources, errors in the current values ​​of these sources cause a bias, resulting in the analog output voltage deviating from the ideal value relative to the digital input. Furthermore, a gain error occurs, causing the output voltage range to deviate from the ideal value.

[0015] Furthermore, in Non-Patent Document 3, the multiplexer that selectively extracts the output of the sub-DAC is located outside the sub-DAC. Therefore, the magnitude of the current flowing through the multiplexer varies depending on the digital input. Since the drain voltage / current characteristics of the transistor are not linear, the voltage drop in the multiplexer caused by the transistor relative to the digital input is a non-linear error. Therefore, the analog output voltage deviates from the ideal value relative to the digital input.

[0016] Furthermore, the DAC in Non-Patent Document 3 performs an RZ (Return-to-Zero) operation that causes the output current of one of the two sub-DACs to flow to a dummy state. Therefore, half of the current from the current source module is discarded, which is disadvantageous in terms of power efficiency.

[0017] This disclosure was made to solve the aforementioned problems, and its purpose is to provide a D / A converter that can prevent offset, gain error and nonlinear error and improve power efficiency.

[0018] Methods for solving problems

[0019] The D / A converter disclosed herein is characterized by comprising: a current source module having multiple current source units connected in parallel and outputting current according to a digital input; and a resistor that converts the total current of the multiple current source units into an analog output voltage, wherein each current source unit inputs: a first to a fourth overlapping clock with phases staggered by 90°; and a portion of the digital input corresponding to each current source unit that is synchronized with the first to the fourth overlapping clock, namely, the first to fourth digital inputs; each current source unit having a first to a fourth switching section connected in parallel, and an electrical resistor connected in series with the first to the fourth switching section. The current source is configured such that the first switch outputs the current of the current source according to the first digital input during the overlap of the first and second overlapping clocks; the second switch outputs the current of the current source according to the second digital input during the overlap of the second and third overlapping clocks; the third switch outputs the current of the current source according to the third digital input during the overlap of the third and fourth overlapping clocks; and the fourth switch outputs the current of the current source according to the fourth digital input during the overlap of the fourth and first overlapping clocks.

[0020] Invention Effects

[0021] In this disclosure, the first to fourth switching sections use a common current source, thus preventing offset and gain errors. Furthermore, since the first to fourth switching sections have switching operations within the current source unit, the magnitude of the current flowing through them is independent of the digital input, thus preventing nonlinear errors. Additionally, due to NRZ operation, power efficiency is improved. Attached Figure Description

[0022] Figure 1 This is a circuit diagram showing the D / A converter according to Embodiment 1.

[0023] Figure 2 This is a circuit diagram showing the current source unit involved in Embodiment 1.

[0024] Figure 3 This is a timing diagram showing the operation of the current source unit according to Embodiment 1.

[0025] Figure 4 This is a circuit diagram showing the current source unit involved in Embodiment 2.

[0026] Figure 5 This is a timing diagram showing the operation of the current source unit according to Embodiment 2. Detailed Implementation

[0027] The D / A converter according to the embodiments will be described with reference to the accompanying drawings. Sometimes the same or corresponding components are labeled with the same reference numerals, and repeated descriptions are omitted.

[0028] Implementation Method 1

[0029] Figure 1 This is a circuit diagram showing the D / A converter according to Embodiment 1. Logic circuit 1 accepts digital inputs D0 to D10. n The processed data is input to current source module 2. Four overlapping clocks Φ1 to Φ4, with phases staggered by 90°, are also input to current source module 2. Adjacent overlapping clocks, such as overlapping clocks Φ1 and Φ2, have phases staggered by 90° and overlap by 1 / 4 cycle. Furthermore, overlapping clocks Φ1 to Φ4 are generated, for example, by a four-phase clock generator disclosed in Japanese Patent No. 4152969.

[0030] The current source module 2 has multiple current source units 3 connected in parallel. Each current source unit 3 outputs current according to its corresponding digital input. Resistors R+ and R- are connected between the current source module 2 and the power supply. Resistor R+ converts the total current from the multiple current source units 3 into an analog output voltage V. out +. Current source unit 3 performs differential operation, and resistor R- converts the total current from the inverted outputs of multiple current source units 3 into an analog output voltage V. out -

[0031] Current source unit 3 has switches SW1 to SW4 connected in parallel and a current source I0 connected in series with the switches SW1 to SW4. Current source module 2 connects to digital inputs D0 to D... n High side D k+1 ~D n The corresponding current source unit 3 is set as a single-element structure, and will be connected to the digital inputs D0~D n The lower side D0~D kThe corresponding current source unit 3 is set as a segmented binary structure. For example, in an 8-bit DAC, the high-order 5-bit unary structure consists of 31 current source units 3 flowing with the same current, and the low-order 3-bit binary structure consists of current source units 3 containing current source I0 with current ratios of 1, 2, and 4. The current values ​​of current source I0 in the multiple current source units 3 of the unary structure are the same. The current values ​​of current source I0 in the multiple current source units 3 of the binary structure are weighted by a power of 2 ratio of current values. Logic circuit 1 processes the binary code D input to the current source unit 3 of the unary structure. k+1 ~D n Decoding the thermometer code.

[0032] Figure 2 This is a circuit diagram showing the current source unit according to Embodiment 1. The current source I0 is composed of two transistors controlled by voltages Vb and Vbcas respectively, through which a current of a certain value flows. Switches SW1 to SW4 are connected to the drain of the current source I0.

[0033] Number input D i1 ~D i4 It is the digital input D corresponding to the i-th current source unit 3. i The parts synchronized with the overlapping clocks Φ1 to Φ4 respectively. Digital input D i1 ~D i4 The current is sequentially input to current source unit 3 with a 90-degree phase difference. Logic circuit 1 then inputs the digital input D corresponding to current source unit 3. i And generate digital input D i1 ~D i4 .

[0034] The switching section SW1 has transistors Q connected in series. 11 ~Q 13 and the transistors Q connected in series 11 ′~Q 13 ′. Transistor Q 11 ~Q 13 With transistor Q 11 ′~Q 13 They are connected in parallel. Similarly, the switching section SW2 has transistors Q connected in series. 21 ~Q 23 and the transistors Q connected in series 21 ′~Q 23 The switching section SW3 has transistors Q connected in series. 31 ~Q 33 and the transistors Q connected in series 31 ′~Q 33 The switching section SW4 has transistors Q connected in series.41 ~Q 43 and the transistors Q connected in series 41 ′~Q 43 ′.

[0035] transistor Q 11 ~Q 13 The overlapping clocks Φ1, Φ2, and digital input D are respectively used. i1 Control. Transistor Q 21 ~Q 23 The overlapping clocks Φ2 and Φ3, and the digital input D are respectively used. i2 Control. Transistor Q 31 ~Q 33 The overlapping clocks Φ3 and Φ4, and the digital input D are respectively used. i3 Control. Transistor Q 41 ~Q 43 The overlapping clocks Φ4, Φ1, and digital input D are respectively used. i4 control.

[0036] Figure 3 This is a timing diagram illustrating the operation of the current source unit according to Embodiment 1. At digital input D... i1 After becoming "1", transistor Q is synchronized with the overlapping clock Φ1 becoming "1". 11 Turn on. Then, synchronously with the overlapping clock Φ2 becoming "1", transistor Q... 12 It also conducts. During the period when both overlapping clocks Φ1 and Φ2 are "1", it conducts according to the digital input D. i1 transistor Q 13 When the circuit is turned on / off, the switching section SW1 outputs current from current source I0. The current from current source I0 flows through the digital input D. i1 When I is "1", it flows through I out +, flows through I when it is "0". out - That is, inputting D via numbers. i1 Decide to allow the current from current source I0 to flow through I out + and I out Which one in - controls the timing of current flow through overlapping clocks Φ1 and Φ2.

[0037] Then, when the overlapping clock Φ1 becomes "0", transistor Q... 11 At the cutoff, the current output from the switching unit SW1 stops. Afterwards, D... i2 To become "1", the same action is performed in the switch section SW2, D i3 To become "1", the same action is performed in the switch section SW3, D i4 It becomes "1" and performs the same action in the switch section SW4.

[0038] During the overlap of overlapping clocks Φ1 and Φ2, the switching unit SW1 adjusts the digital input D. i1 The output current source I0 outputs current. Switch SW2 operates according to the digital input D during the overlapping period of clocks Φ2 and Φ3. i2 The output current source I0 outputs current. Switch SW3 adjusts the current according to the digital input D during the overlapping period of clocks Φ3 and Φ4. i3 The output current source I0 is the current. During the overlapping period of the overlapping clocks Φ4 and Φ1, the switching unit SW4 adjusts the current according to the digital input D. i4 The current from the output current source I0.

[0039] Thus, by using a four-phase clock with a 90° phase difference, the switching sections SW1 to SW4 in the current source unit 3 operate in a time-interleaved manner. As a result, any one of the switching sections SW1 to SW4 operates to output current from the current source I0, which is thus called NRZ (Non-Return-to-Zero) operation.

[0040] As explained above, in this embodiment, the switching sections SW1 to SW4 of the current source unit 3 use a common current source I0, thus preventing offset and gain errors. Furthermore, since the current source unit 3 has switching sections SW1 to SW4 that perform switching operations, the magnitude of the current flowing through the switching sections SW1 to SW4 is independent of the digital input, thus preventing nonlinear errors. Additionally, since the current source unit 3 performs NRZ operation, power efficiency is improved.

[0041] Furthermore, logic circuit 1 is implemented by processing circuits such as the CPU and system LSI that execute programs stored in memory. Additionally, multiple processing circuits can also cooperate to perform the aforementioned functions.

[0042] Implementation Method 2

[0043] Figure 4 This is a circuit diagram showing the current source unit according to Embodiment 2. The switching unit SW1 includes AND circuits A1 and A1', and a transistor Q connected in series. 14 Q 15 and the transistors Q connected in series. 14 ′、Q 15 The switching unit SW2 has AND circuits A2 and A2', and a transistor Q connected in series. 24 Q 25 and the transistors Q connected in series. 24 ′、Q 25 The switching unit SW3 has AND circuits A3 and A3', and transistor Q connected in series. 34 Q 35and the transistors Q connected in series. 34 ′、Q 35 The switching unit SW4 has AND circuits A4 and A4', and transistor Q connected in series. 44 Q 45 and the transistors Q connected in series. 44 ′、Q 45 ′.

[0044] Overlapping clock Φ1 and digital input D i1 The timing is essentially the same. Therefore, the AND circuit A1 is paired with the overlapping clock Φ1 and the digital input D. i1 Perform an AND operation. Transistor Q1 is controlled by the output D of the AND circuit A1. i1 Control. Transistor Q 15 Controlled by the overlapping clock Φ2. The AND circuit A1′ controls the overlapping clock Φ1 and the digital input D. i1 - Perform an AND operation. Transistor Q1' is controlled by the output of the AND circuit A1'. 15 It is controlled by the overlapping clock Φ2.

[0045] AND circuit A2 corresponds to the overlapping clock Φ2 and digital input D. i2 Perform an AND operation. Transistor Q. 24 The output D of AND circuit A2 i2 Control. Transistor Q 25 Controlled by the overlapping clock Φ3. The AND circuit A2′ controls the overlapping clock Φ2 and the digital input D. i2 - Perform an AND operation. Transistor Q 24 The output of the AND circuit A2 is controlled by transistor Q. 25 It is controlled by the overlapping clock Φ3.

[0046] AND circuit A3 supports the overlapping clock Φ3 and digital input D. i3 Perform an AND operation. Transistor Q. 34 The output D of AND circuit A3 i3 Control. Transistor Q 35 Controlled by the overlapping clock Φ4. The AND circuit A3' controls the overlapping clock Φ3 and the digital input D. i3 - Perform an AND operation. Transistor Q 34 The output of the AND circuit A3 is controlled by transistor Q. 35 It is controlled by the overlapping clock Φ4.

[0047] AND circuit A4 supports the overlapping clock Φ4 and digital input D. i4 Perform an AND operation. Transistor Q. 44 The output D of AND circuit A4i4 Control. Transistor Q 45 Controlled by the overlapping clock Φ1. The AND circuit A4' controls the overlapping clock Φ4 and the digital input D. i4 - Perform an AND operation. Transistor Q 44 The output of the AND circuit A4 is controlled by transistor Q. 45 It is controlled by the overlapping clock Φ1.

[0048] Figure 5 This is a timing diagram illustrating the operation of the current source unit according to Embodiment 2. Similar to Embodiment 1, the switching units SW1 to SW4 within the current source unit 3 operate in a time-interleaved manner using a four-phase clock with a 90° phase difference. That is, during the overlap of the overlapping clocks Φ1 and Φ2, the switching unit SW1 operates according to the digital input D... i1 The output current source I0 outputs current. Switch SW2 operates according to the digital input D during the overlapping period of clocks Φ2 and Φ3. i2 The output current source I0 outputs current. Switch SW3 adjusts the current according to the digital input D during the overlapping period of clocks Φ3 and Φ4. i3 The output current source I0 is the current. During the overlapping period of the overlapping clocks Φ4 and Φ1, the switching unit SW4 adjusts the current according to the digital input D. i4 The current from the output current source I0 is thus obtained, achieving the same effect as in embodiment 1.

[0049] Furthermore, in this embodiment, by using an AND circuit, the number of transistor stages in each switching section SW1 to SW4 is reduced by one stage compared to Embodiment 1. This allows the output voltage range to be extended by the amount of one transistor stage.

[0050] Alternatively, an AND operation can be performed on the overlapping clocks Φ1 and Φ2 to make the transistor Q in Implementation 1... 11 Q 12 It is level 1. In this case, the number of transistor stages is also reduced by one. However, as the operating speed increases, the pulse width during the "1" after the AND operation becomes narrower, thus the speed limit is lower compared to the case without AND operation.

[0051] Label Explanation

[0052] 1: Logic circuit; 2: Current source module; 3: Current source unit; A1~A4: AND circuit; D0~D n D i1 ~D i4 I0: Digital input; Q: Current source; 11 ~Q 45 : Transistor; R+, R-: Resistor; SW1~SW4: Switching section; Φ1~Φ4: Overlapping clock.

Claims

1. A D / A converter, characterized in that, The D / A converter has the following features: A current source module having multiple current source units connected in parallel and each outputting current according to a digital input; and A resistor that converts the combined current from the plurality of current source units into an analog output voltage. Each current source unit input includes: 1st to 4th overlapping clocks with phases staggered by 90°; and the portion of the digital input corresponding to each current source unit that is synchronized with the 1st to 4th overlapping clocks, i.e., the 1st to 4th digital inputs. Each current source unit has a first to a fourth switching section connected in parallel with each other, and a current source connected in series with the first to the fourth switching sections. The first switch outputs the current of the current source according to the first digital input during the overlap of the first overlapping clock and the second overlapping clock. The second switch outputs the current of the current source according to the second digital input during the overlap of the second and third overlapping clocks. The third switch outputs the current of the current source according to the third digital input during the overlap of the third and fourth overlapping clocks. The fourth switch outputs the current of the current source according to the fourth digital input during the period when the fourth overlapping clock and the first overlapping clock overlap.

2. The D / A converter according to claim 1, characterized in that, The D / A converter also includes logic circuitry that generates the first to fourth digital inputs based on the digital inputs corresponding to each current source unit.

3. The D / A converter according to claim 1 or 2, characterized in that, The first switching section has a first to a third transistor connected in series, and the first to the third transistors are controlled by the first overlapping clock, the second overlapping clock, and the first digital input, respectively. The second switching section has a fourth to a sixth transistor connected in series, and the fourth to sixth transistors are controlled by the second overlapping clock, the third overlapping clock, and the second digital input, respectively. The third switching section has a 7th to a 9th transistor connected in series, and the 7th to 9th transistors are controlled by the 3rd overlapping clock, the 4th overlapping clock, and the 3rd digital input, respectively. The fourth switching section has a 10th to a 12th transistor connected in series, and the 10th to the 12th transistors are controlled by the fourth overlapping clock, the first overlapping clock, and the fourth digital input, respectively.

4. The D / A converter according to claim 1 or 2, characterized in that, The first switching unit includes a first AND circuit and a first transistor and a second transistor connected in series. The first AND circuit performs an AND operation on the first overlapping clock and the first digital input. The first transistor and the second transistor are controlled by the output of the first AND circuit and the second overlapping clock, respectively. The second switching section includes a second AND circuit and a third transistor and a fourth transistor connected in series. The second AND circuit performs an AND operation on the second overlapping clock and the second digital input. The third transistor and the fourth transistor are controlled by the output of the second AND circuit and the third overlapping clock, respectively. The third switching section includes a third AND circuit and a fifth transistor and a sixth transistor connected in series. The third AND circuit performs an AND operation on the third overlapping clock and the third digital input. The fifth transistor and the sixth transistor are controlled by the output of the third AND circuit and the fourth overlapping clock, respectively. The fourth switch section has a fourth AND circuit and a seventh transistor and an eighth transistor connected in series. The fourth AND circuit performs an AND operation on the fourth overlapping clock and the fourth digital input. The seventh transistor and the eighth transistor are controlled by the output of the fourth AND circuit and the first overlapping clock, respectively.

5. The D / A converter according to claim 1 or 2, characterized in that, The current source module is a segmented structure in which the current source unit corresponding to the high-order side of the digital input is set as a unary structure, and the current source unit corresponding to the low-order side of the digital input is set as a binary structure. The current values ​​of the current sources in the plurality of current source units of the uni-element structure are the same. The current values ​​of the current sources of the plurality of current source units in the binary structure are weighted by a power of 2 ratio of current values.

6. The D / A converter according to claim 1 or 2, characterized in that, The current source unit performs differential operation.

Images