A current measurement based temperature calibration circuit and method

Abstract

This invention relates to the field of integrated circuit design technology, specifically disclosing a temperature calibration circuit and method based on current measurement. The calibration circuit includes: a load current-to-voltage circuit for converting external load current into a first voltage; a temperature detection circuit for converting temperature into a second voltage; an input selector for selecting the output of the first and second voltages; an ADC converter for converting the first and second voltages into current data and temperature data, respectively; and a temperature calibration unit for calculating a temperature calibration coefficient in the digital domain based on the current and temperature data to obtain calibrated current data. This invention integrates a temperature sensor that can reflect the chip's temperature in real time, fully considering the errors introduced by temperature changes in the actual application environment. Based on current and temperature data, it calculates the temperature calibration coefficient in the digital domain, performing dynamic temperature calibration on-chip to compensate for temperature drift errors, thereby improving the accuracy of current monitoring at different temperatures.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a temperature calibration circuit and method based on current measurement. Background Technology

[0002] An on-chip operational amplifier (AMP) drives external resistive loads (RL) such as resistors, LEDs, and sensors, generating a load current (iload). Figure 1 As shown, where V IN To simulate the input voltage, V OUT This is the output voltage.

[0003] Existing technical solutions utilize internal circuitry to accurately extract the load current using a current mirror, convert it into a voltage signal, and then use an ADC to sample and output a digital value (DATA) to an external MCU. The MCU's algorithm then calculates, monitors, and diagnoses faults related to load current, real-time power, and other information. Figure 2 As shown, where m is the mirror image ratio.

[0004] The technical pain points of existing technical solutions include: (1) The on-chip resistor for current-to-voltage conversion usually has a large error due to process angle and temperature changes, resulting in a large error in the current acquired by the ADC; (2) Errors introduced by the change in resistor process angle can usually be eliminated by on-chip calibration at room temperature during chip factory testing. However, errors caused by resistor temperature drift will change dynamically with the fluctuation of ambient temperature in the application, resulting in a large monitoring current error (the typical drift of on-chip Poly resistor is -300ppm / °C, and a temperature change from 25°C to 125°C can introduce an error of -3%). (3) Traditional solutions usually choose ultra-low temperature drift thin film resistors (< + / -20ppm / °C) to reduce temperature drift, but such resistors usually require additional masks, which increases chip manufacturing costs.

[0005] Based on this technical background, the present invention studies a temperature calibration circuit and method based on current measurement. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention proposes a temperature calibration circuit and method based on current measurement. This calibration circuit integrates a temperature sensor to reflect the chip's temperature in real time, fully considering the errors introduced by temperature changes in actual application environments. Based on current and temperature data, a temperature calibration coefficient is calculated in the digital domain, and dynamic temperature calibration is performed on-chip to compensate for temperature drift errors, thereby improving the accuracy of current monitoring at different temperatures and solving the temperature drift problem caused by on-chip resistors.

[0007] To achieve the above objectives, a first aspect of the present invention provides a temperature calibration circuit based on current measurement, comprising: A load current to voltage converter circuit is used to convert external load current into a first voltage. Temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage; An input selector has two input terminals and an output terminal. The two input terminals are electrically connected to the first voltage and the second voltage, respectively, and are used to select the output of the first voltage and the second voltage. An ADC converter, whose input is electrically connected to the output of the input selector, is used to convert the first voltage and the second voltage into current data and temperature data, respectively. The temperature calibration unit is electrically connected to the output of the ADC converter and is used to calculate the temperature calibration coefficient in the digital domain based on the current data and temperature data to obtain the calibrated current data.

[0008] A second aspect of the present invention provides a temperature calibration method performed in the above-described calibration circuit, comprising: The external load current is converted into a first voltage through a load current to voltage conversion circuit; A temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage. The first voltage and the second voltage are selected and output using an input selector; The first voltage and the second voltage are converted into current data and temperature data, respectively, using an ADC converter. Based on the current and temperature data, the temperature calibration coefficient is calculated in the digital domain using the temperature calibration unit to obtain the calibrated current data.

[0009] The beneficial effects of this invention include: (1) The present invention proposes a temperature calibration circuit based on current measurement. The integrated temperature sensor can reflect the temperature of the chip in real time. It fully considers the error introduced by temperature changes in the actual application environment. Based on current data and temperature data, the temperature calibration coefficient is calculated in the digital domain. Dynamic temperature calibration is performed on the chip to compensate for temperature drift error, improve the accuracy of current monitoring at different temperatures, and solve the temperature drift problem caused by on-chip resistors.

[0010] (2) This invention proposes a temperature calibration circuit based on current measurement. It uses a simple current mirror and an operational transconductance amplifier to make the current mirror Vds equal to achieve a precise current replication ratio, which greatly improves the accuracy of current monitoring at different temperatures. At the same time, all compensation algorithms are implemented in the digital domain, which has high accuracy, small area and low cost.

[0011] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0012] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0013] Figure 1 A schematic diagram of a structure for generating load current by driving an external load using an existing on-chip operational amplifier.

[0014] Figure 2 This is a schematic diagram of the structure where the existing load current is converted into voltage, acquired and converted by an ADC, and then sent to the MCU for processing.

[0015] Figure 3 This is a schematic diagram of a specific embodiment of the temperature calibration circuit based on current measurement proposed in this invention.

[0016] Figure 4 This is a schematic diagram of the digital domain temperature calibration process in a specific embodiment of the temperature calibration circuit based on current measurement proposed in this invention.

[0017] Figure 5 This is a schematic diagram of the customer application process in a specific embodiment of the temperature calibration circuit based on current measurement proposed in this invention.

[0018] Explanation of reference numerals in the attached figures: MN0 - First NMOS input transistor, MN1 - Second NMOS input transistor, MN2 - NMOS bias transistor, MN3 - Output NMOS transistor, MN4 - Mirror NMOS transistor, MN5 - Feedback NMOS transistor, MP1 - First PMOS load transistor, MP2 - Second PMOS load transistor, MP3 - Output PMOS transistor, MP4 - Mirror PMOS transistor, MP5 - Current bias PMOS transistor, NPN0 - Detection NPN transistor, OTA - Operational transconductance amplifier, RL - External load, rmon - On-chip resistor, input_mux - Input selector, ADC - ADC converter, TemperatureCalibration - Temperature calibration unit; - The current flowing through the output PMOS transistor, - The current flowing through the output NMOS transistor, -Load current, -The current flowing through the on-chip resistor, - The width-to-length ratio of the mirrored PMOS transistor and the output PMOS transistor -First voltage, temp - the second voltage. - Current data, -Temperature data, - Calibrated current data; AVDD - Power supply, AGND - Ground, VBN - First bias voltage, VBP - Second bias voltage, VIN - Analog input voltage, VOUT - Output pin. Detailed Implementation

[0019] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0020] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its normal operating state, while "inner" and "outer" refer to their position relative to the device's outline. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] This invention provides a temperature calibration circuit based on current measurement, such as... Figure 3 As shown, it includes: A load current to voltage converter circuit is used to convert the external load RL current into a first voltage vimon. Temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage vtemp; The input selector input_mux has two input terminals and one output terminal. The two input terminals are electrically connected to the first voltage vimon and the second voltage vtemp, respectively, and are used to select the output of the first voltage vimon and the second voltage vtemp. The ADC converter ADC is electrically connected to the output of the input selector input_mux, and is used to convert the first voltage vimon and the second voltage vtemp into current data data_imon and temperature data data_temp, respectively. The Temperature Calibration unit, whose input is electrically connected to the ADC output of the ADC converter, is used to calculate the temperature calibration coefficient in the digital domain based on the current data data_imon and the temperature data data_temp, and obtain the calibrated current data data_imon_cal.

[0022] In this invention, the integrated temperature sensor can reflect the temperature of the chip in real time, fully taking into account the error introduced by temperature changes in the actual application environment. Based on the current data data_imon and temperature data data_temp, the temperature calibration coefficient is calculated in the digital domain, and dynamic temperature calibration is performed on the chip to compensate for temperature drift error, thereby improving the accuracy of current monitoring at different temperatures and solving the temperature drift problem caused by on-chip resistors.

[0023] According to the present invention, the load current to voltage conversion circuit includes: The output amplifier includes an input stage and an output stage. The output of the input stage is electrically connected to the input of the output stage, and the output of the output stage is electrically connected to an external load RL. The output voltage of the output stage is a first voltage vimon. A current mirror unit, electrically connected to the output stage, is used to generate a mirror current proportional to the current of the output stage. The current mirror replication unit includes an operational transconductance amplifier OTA, a feedback NMOS transistor MN5, and an on-chip resistor rmon. The non-inverting input of the operational transconductance amplifier OTA is electrically connected to the output of the current mirror unit, the inverting input is electrically connected to the output of the output stage, the output is electrically connected to the gate of the feedback NMOS transistor MN5, the drain of the feedback NMOS transistor MN5 is electrically connected to the non-inverting input of the operational transconductance amplifier OTA, the source is electrically connected to one end of the on-chip resistor rmon, and the other end of the on-chip resistor rmon is electrically connected to ground AGND.

[0024] According to the present invention, the input stage includes a pair of NMOS input transistors, a pair of PMOS load transistors, and an NMOS bias transistor MN2. The pair of NMOS input transistors includes a first NMOS input transistor MN0 and a second NMOS input transistor MN1. The pair of PMOS load transistors includes a first PMOS load transistor MP1 and a second PMOS load transistor MP2. The source of the first NMOS input transistor MN0 is electrically connected to the drain of the NMOS bias transistor MN2, and its drain is electrically connected to the drain of the first PMOS load transistor MP1. The source of the NMOS bias transistor MN2 is connected to ground. The gate of the first PMOS bias transistor is connected to the first bias voltage VBN, the gate of the first PMOS bias transistor is connected to its own drain, and the source is connected to the power supply AVDD. The gate of the second NMOS input transistor MN1 is connected to the analog input voltage VIN, the source is connected to the drain of the NMOS bias transistor MN2, the drain is connected to the drain of the second PMOS load transistor MP2, and serves as the output of the input stage. The gate of the second PMOS load transistor MP2 is connected to the gate of the first PMOS load transistor MP1, and the source is connected to the power supply AVDD. The output stage includes an output NMOS transistor MN3 and an output PMOS transistor MP3. The gate of the output NMOS transistor MN3 is electrically connected to the first bias voltage VBN, the source is electrically connected to ground AGND, and the drain is electrically connected to the gate of the first NMOS input transistor MN0, the drain of the output PMOS transistor MP3, and one end of the external load RL. The other end of the external load RL is electrically connected to ground AGND. The gate of the output PMOS transistor MP3 is electrically connected to the drain of the second NMOS input transistor MN1, and the source is electrically connected to the power supply AVDD.

[0025] According to the present invention, the current mirror unit includes a mirror NMOS transistor MN4 and a mirror PMOS transistor MP4. The gate of the mirror NMOS transistor MN4 is electrically connected to the first voltage vimon, the source is electrically connected to ground AGND, and the drain is electrically connected to the drain of the mirror PMOS transistor MP4, and serves as the output of the current mirror unit. The gate of the mirror PMOS transistor MP4 is electrically connected to the gate of the output PMOS transistor MP3, and the source is electrically connected to the power supply AVDD. The width-to-length ratio of the mirrored NMOS transistor MN4 and the output NMOS transistor MN3 is the same as the width-to-length ratio of the mirrored PMOS transistor MP4 and the output PMOS transistor MP3. ; The temperature detection circuit includes a detection NPN transistor NPN0 and a current-biased PMOS transistor MP5. The base of the detection NPN transistor NPN0 is electrically connected to its own collector and the drain of the current-biased PMOS transistor MP5. The emitter is electrically connected to ground AGND. The gate of the current-biased PMOS transistor MP5 is electrically connected to the second bias voltage VBP, and the source is electrically connected to the power supply AVDD. The base-emitter voltage of the NPN transistor NPN0, i.e., VBE, is the second voltage vtemp.

[0026] In this invention, a simple current mirror and an operational transconductance amplifier (OTA) are used to make the current mirror Vds equal, thereby achieving a precise current replication ratio and improving the accuracy of current monitoring at different temperatures. At the same time, all compensation algorithms are implemented in the digital domain, resulting in high accuracy, small area, and low cost.

[0027] According to the present invention, the method of converting the external load RL current into a first voltage vimon includes: A load current with a ratio of 1 / m is generated by a current mirror unit. ; The mirrored load current flows through the on-chip resistor rmon, generating a voltage drop. Calculate the resistance value of the on-chip resistor rmon at temperature T; Calculate the voltage of the on-chip resistor to ground AGND at temperature T, i.e., the first voltage vimon, based on the current flowing through the on-chip resistor and the resistance value of the on-chip resistor at temperature T. The formula used to calculate the load current is: ; in, The current flowing through the output PMOS transistor, The current flowing through the output NMOS transistor, This is the load current; The formula used to calculate the current flowing through the on-chip resistor is: ; in, The current flowing through the on-chip resistor, The width-to-length ratio of the output PMOS transistor and the mirrored PMOS transistor; The formula used to calculate the resistance of the on-chip resistor at temperature T is: ; in, To be at temperature The resistance value of the on-chip resistor, The range is 296-302K, which is equivalent to 23-29℃. The temperature coefficient of the on-chip resistor. This represents the resistance value of the on-chip resistor at temperature T. The formula for calculating the first voltage is: ; in, The voltage is the first voltage at temperature T. Monitoring the temperature of the calibration circuit and converting the temperature into a second voltage vtemp includes; The temperature of the calibration circuit is monitored using the NPN transistor NPN0. The second voltage vtemp is calculated by detecting the base-emitter voltage of the NPN transistor NPN0; The formula for calculating the base-emitter voltage of an NPN transistor NPN0 is as follows: ; in, To be at temperature The base-emitter voltage of the NPN transistor is detected at any time. It is a constant with a value of -1 to 3 mV / ℃; The formula for calculating the second voltage is: temp ; in, temp is the second voltage. To detect the base-emitter voltage of an NPN transistor at temperature T; According to the present invention, based on current data data_imon and temperature data data_temp, a temperature calibration coefficient is calculated in the digital domain to obtain calibrated current data data_imon_cal, including: The temperature offset and temperature gain are calculated based on the first temperature data and the second temperature data, and the temperature offset and temperature gain are written into the first digital register for storage. The first temperature data is the temperature data at room temperature, and the second temperature data is the temperature data at the highest temperature. The temperature coefficient of the current, i.e. the temperature coefficient of the on-chip resistor rmon, is calculated based on the first current data and the second current data, and then written into the second digital register for storage. The first current data is the current data at room temperature, and the second current data is the current data at the highest temperature. Calculate the change in the current temperature data relative to the first temperature based on the temperature offset and temperature gain; The calibration coefficient at the current temperature is calculated based on the temperature coefficient of the current and the change in the current temperature data relative to the first temperature. The calibrated current data, data_imon_cal, is calculated based on the calibration coefficient at the current temperature.

[0028] According to the present invention, the temperature offset is the first temperature data, and its expression is: ; in, This is the temperature offset. This is the first temperature data; The formula for calculating temperature gain is: ; in, For temperature gain, This is the second temperature data. This is the highest temperature, with a value of 120-150℃; The formula used to calculate the temperature coefficient of current is: ; in, The temperature coefficient of current. This is the first current data. This is the second current data; The formula used to calculate the change in the current temperature data relative to the first temperature data is: ; in, The change in temperature data relative to the first temperature data is represented by T, where T is the current temperature. This refers to the temperature data at the current temperature. The formula used to calculate the calibration coefficient at the current temperature is: ; The formula used to obtain the calibrated current data is: ; in, For the calibrated current data, This is the current data at the current temperature.

[0029] The present invention also provides a method for performing temperature calibration in the above-described calibration circuit, comprising: The external load RL current is converted into the first voltage vimon through a load current to voltage conversion circuit; The temperature detection circuit monitors the operating temperature of the chip and converts the temperature into a second voltage, vtemp. The first voltage vimon and the second voltage vtemp are selected and output through the input selector input_mux; The first voltage vimon and the second voltage vtemp are converted into current data data_imon and temperature data data_temp, respectively, using an ADC converter. Based on the current data data_imon and the temperature data data_temp, the temperature calibration coefficient is calculated in the digital domain using the temperature calibration unit TemperatureCalibration to obtain the calibrated current data data_imon_cal.

[0030] According to the present invention, the circuit analysis process for converting the external load RL current into the first voltage vimon includes: A load current with a ratio of 1 / m is generated by a current mirror unit. ; The mirrored load current flows through the on-chip resistor rmon, generating a voltage drop. Calculate the resistance value of the on-chip resistor rmon at temperature T; Based on the current flowing through the on-chip resistor and the resistance value of the on-chip resistor rmon at temperature T, calculate the voltage of the on-chip resistor rmon to ground AGND at temperature T, i.e., the first voltage vimon; Monitoring the temperature of the calibration circuit and converting the temperature into a second voltage vtemp includes; The temperature of the calibration circuit is monitored using the NPN transistor NPN0. The second voltage vtemp is calculated by detecting the base-emitter voltage of the NPN transistor NPN0.

[0031] According to the present invention, the temperature calibration coefficient is calculated in the digital domain based on the current data data_imon and the temperature data data_temp to obtain the calibrated current data data_imon_cal, including: The temperature offset and temperature gain are calculated based on the first temperature data and the second temperature data, and the temperature offset and temperature gain are written into the first digital register for storage. The first temperature data is the temperature data at room temperature, and the second temperature data is the temperature data at the highest temperature. The temperature coefficient of the current, i.e. the temperature coefficient of the on-chip resistor rmon, is calculated based on the first current data and the second current data, and then written into the second digital register for storage. The first current data is the current data at room temperature, and the second current data is the current data at the highest temperature. Calculate the change in the current temperature data relative to the first temperature based on the temperature offset and temperature gain; The calibration coefficient at the current temperature is calculated based on the temperature coefficient of the current and the change in the current temperature data relative to the first temperature. The calibrated current data, data_imon_cal, is calculated based on the calibration coefficient at the current temperature.

[0032] The present invention will now be described in more detail through specific embodiments.

[0033] Example 1

[0034] like Figure 3 As shown, this embodiment provides a temperature calibration circuit based on current measurement, including: A load current to voltage converter circuit is used to convert the external load RL current into a first voltage vimon. Temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage vtemp; The input selector input_mux has two input terminals and one output terminal. The two input terminals are electrically connected to the first voltage vimon and the second voltage vtemp, respectively, and are used to select the output of the first voltage vimon and the second voltage vtemp. The ADC converter ADC is electrically connected to the output of the input selector input_mux, and is used to convert the first voltage vimon and the second voltage vtemp into current data data_imon and temperature data data_temp, respectively. The Temperature Calibration unit is electrically connected to the ADC output of the ADC converter. It is used to calculate the temperature calibration coefficient in the digital domain based on the current data data_imon and the temperature data data_temp, and obtain the calibrated current data data_imon_cal. The load current to voltage conversion circuit includes: The output amplifier includes an input stage and an output stage. The output of the input stage is electrically connected to the input of the output stage, and the output of the output stage is electrically connected to an external load RL. The output voltage of the output stage is a first voltage vimon. A current mirror unit, electrically connected to the output stage, is used to generate a mirror current proportional to the current of the output stage. The current mirror replication unit includes an operational transconductance amplifier OTA, a feedback NMOS transistor MN5, and an on-chip resistor rmon. The non-inverting input of the operational transconductance amplifier OTA is electrically connected to the output of the current mirror unit, the inverting input is electrically connected to the output of the output stage, the output is electrically connected to the gate of the feedback NMOS transistor MN5, the drain of the feedback NMOS transistor MN5 is electrically connected to the non-inverting input of the operational transconductance amplifier OTA, the source is electrically connected to one end of the on-chip resistor rmon, and the other end of the on-chip resistor rmon is electrically connected to ground AGND. The input stage includes a pair of NMOS input transistors, a pair of PMOS load transistors, and an NMOS bias transistor MN2. The pair of NMOS input transistors includes a first NMOS input transistor MN0 and a second NMOS input transistor MN1. The pair of PMOS load transistors includes a first PMOS load transistor MP1 and a second PMOS load transistor MP2. The source of the first NMOS input transistor MN0 is electrically connected to the drain of the NMOS bias transistor MN2, and its drain is electrically connected to the drain of the first PMOS load transistor MP1. The source of the NMOS bias transistor MN2 is electrically connected to ground AGND, and its gate is electrically connected to the first bias voltage VBN. The gate of the first PMOS bias transistor is electrically connected to its own drain, and its source is electrically connected to the power supply AVDD. The gate of the second NMOS input transistor MN1 is electrically connected to the analog input voltage VIN, its source is electrically connected to the drain of the NMOS bias transistor MN2, and its drain is electrically connected to the drain of the second PMOS load transistor MP2, serving as the output of the input stage. The gate of the second PMOS load transistor MP2 is electrically connected to the gate of the first PMOS load transistor MP1, and its source is electrically connected to the power supply AVDD. The output stage includes an output NMOS transistor MN3 and an output PMOS transistor MP3. The gate of the output NMOS transistor MN3 is electrically connected to the first bias voltage VBN, the source is electrically connected to ground AGND, and the drain is electrically connected to the gate of the first NMOS input transistor MN0, the drain of the output PMOS transistor MP3, and one end of the external load RL. The other end of the external load RL is electrically connected to ground AGND. The gate of the output PMOS transistor MP3 is electrically connected to the drain of the second NMOS input transistor MN1, and the source is electrically connected to the power supply AVDD. The current mirror unit includes a mirror NMOS transistor MN4 and a mirror PMOS transistor MP4. The gate of the mirror NMOS transistor MN4 is electrically connected to the first voltage vimon, the source is electrically connected to ground AGND, and the drain is electrically connected to the drain of the mirror PMOS transistor MP4, serving as the output of the current mirror unit. The gate of the mirror PMOS transistor MP4 is electrically connected to the gate of the output PMOS transistor MP3, and the source is electrically connected to the power supply AVDD. The width-to-length ratio of the mirrored NMOS transistor MN4 and the output NMOS transistor MN3 is the same as the width-to-length ratio of the mirrored PMOS transistor MP4 and the output PMOS transistor MP3. ; The temperature detection circuit includes a detection NPN transistor NPN0 and a current-biased PMOS transistor MP5. The base of the detection NPN transistor NPN0 is electrically connected to its own collector and the drain of the current-biased PMOS transistor MP5. The emitter is electrically connected to ground AGND. The gate of the current-biased PMOS transistor MP5 is electrically connected to the second bias voltage VBP, and the source is electrically connected to the power supply AVDD. The base-emitter voltage of the NPN transistor NPN0, i.e., VBE, is the second voltage vtemp.

[0035] This embodiment provides a temperature calibration method, including: (a) such as Figure 3 As shown, calculate the first voltage. Specifically, it includes: A two-stage output amplifier is constructed using MN0 / MN1 / MN2 / MP1 / MP2 / MN3 / MP3, with the output pin being VOUT. VOUT is connected to an external load RL to generate a load current iload. A current mirror circuit is constructed using MP3 / MP4 / MN3 / MN4, where the width-to-length ratio of MP3 and MP4 is m:1, and the width-to-length ratio of MN3 and MN4 is m:1. OTA is used to make the current mirror Vds equal, thereby achieving more accurate current replication. The current replication ratio is 1 / m. The mirror current imon is obtained by combining OTA with MN5; The current imon flows through the on-chip resistor Rmon, generating a voltage vimon; The relevant formulas include: The formula used to calculate the load current is: ; in, The current flowing through the output PMOS transistor, The current flowing through the output NMOS transistor, This is the load current; The formula used to calculate the current flowing through the on-chip resistor is: ; in, The current flowing through the on-chip resistor, The width-to-length ratio of the mirrored PMOS transistor and the output PMOS transistor; The formula used to calculate the resistance of the on-chip resistor at temperature T is: ; in, To be at temperature The resistance value of the on-chip resistor, It is 300K, which is 27℃. This represents the resistance value of the on-chip resistor at temperature T. This refers to the temperature coefficient of the on-chip resistor. For ordinary poly resistors, it is usually around -300ppm / ℃. A temperature change of 100℃ will introduce a -3% error. The formula for calculating the first voltage is: ; in, The voltage is the first voltage at temperature T. (ii) The calculation of the second voltage vtemp specifically includes: The temperature of the calibration circuit is monitored using the NPN transistor NPN0. The second voltage vtemp is calculated by detecting the base-emitter voltage of the NPN transistor NPN0; The expression is as follows: ; in, fixed, It can be simplified to a formula related to temperature T: ; in, ; The formula for calculating the second voltage is: temp ; in, temp is the second voltage. To detect the base-emitter voltage of an NPN transistor at temperature T; (III) Vimon / vtemp data acquisition and conversion + digital temperature calibration specifically includes: vimon / vtemp are sampled by the ADC through the input mux and transferred to obtain data_imon and data_temp containing current and temperature information, respectively. The relationship between vimon and vtemp and temperature is obtained by collecting and converting data at different temperatures. The relevant values ​​are filled into a digital register for storage, and the temperature calibration coefficient is calculated in the digital domain. The temperature drift current data data_imon_ca can be obtained by switching the vimon and vtemp channels at different temperatures; (iv) If Figure 4 As shown, the temperature calibration process in this embodiment specifically includes: 1. At 25 respectively and 125 Convert the vtemp channel and The temperature temp and the output expression of adc are calculated, and the result is... and Write to digital register for storage; ; in, ; ; 2. At 25 respectively and 125 Convert the vimon channel to get data_imon_25 and data_imon_125 The expression for the temperature coefficient TC (ratio / C) of imon is calculated and written into a digital register for storage. ; 3. Digital domain calculation temperature relative to room temperature 25°C The change in; ; 4. The expression for the output data_imon after imon conversion as a function of temperature is as follows; ); 5. The numeric field is based on TC and Calculate the calibration factor at this temperature. ; 6. Data_imon_cal after digital output temperature calibration; ; Steps 1 and 2 involve testing in the laboratory to obtain the calibration parameters, which are then stored in a register. All calculations are performed in the digital domain.

[0036] like Figure 5 As shown, this embodiment provides a customer application flow for a temperature calibration circuit based on current measurement.

[0037] The temperature calibration circuit based on current measurement proposed in the embodiments of the present invention uses a simple current mirror and OTA to make the current mirror Vds equal to achieve a precise current replication ratio; the integrated temperature sensor can reflect the temperature of the chip in real time; fully considering the error introduced by temperature changes in the actual application environment, on-chip dynamic temperature calibration is performed to compensate for temperature drift error and improve the accuracy of current monitoring at different temperatures; all compensation algorithms are implemented in the digital domain, with high accuracy, small area, and low cost.

[0038] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A temperature calibration circuit based on current measurement, characterized in that, include: A load current to voltage converter circuit is used to convert external load current into a first voltage. Temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage; An input selector has two input terminals and an output terminal. The two input terminals are electrically connected to the first voltage and the second voltage, respectively, and are used to select the output of the first voltage and the second voltage. An ADC converter, whose input is electrically connected to the output of the input selector, is used to convert the first voltage and the second voltage into current data and temperature data, respectively. The temperature calibration unit is electrically connected to the output of the ADC converter and is used to calculate the temperature calibration coefficient in the digital domain based on the current data and temperature data to obtain the calibrated current data. The load current to voltage conversion circuit includes: An output amplifier includes an input stage and an output stage, wherein the output of the input stage is electrically connected to the input of the output stage, the output of the output stage is electrically connected to an external load, and the output voltage of the output stage is the first voltage; A current mirror unit, electrically connected to the output stage, is used to generate a mirror current proportional to the current of the output stage. The current mirroring unit includes an operational transconductance amplifier, a feedback NMOS transistor, and an on-chip resistor. The non-inverting input of the operational transconductance amplifier is electrically connected to the output of the current mirroring unit, the inverting input is electrically connected to the output of the output stage, the output is electrically connected to the gate of the feedback NMOS transistor, the drain of the feedback NMOS transistor is electrically connected to the non-inverting input of the operational transconductance amplifier, the source is electrically connected to one end of the on-chip resistor, and the other end of the on-chip resistor is electrically connected to ground. The current mirror unit includes a mirror NMOS transistor and a mirror PMOS transistor. The gate of the mirror NMOS transistor is electrically connected to the first voltage, the source is electrically connected to ground, and the drain is electrically connected to the drain of the mirror PMOS transistor, serving as the output of the current mirror unit. The gate of the mirror PMOS transistor is electrically connected to the gate of the output PMOS transistor, and the source is electrically connected to the power supply. The aspect ratio of the mirrored NMOS transistor and the output NMOS transistor is the same as the aspect ratio of the mirrored PMOS transistor and the output PMOS transistor. ; The temperature detection circuit includes a detection NPN transistor and a current-biased PMOS transistor. The base of the detection NPN transistor is electrically connected to its own collector and the drain of the current-biased PMOS transistor, and the emitter is electrically connected to ground. The gate of the current-biased PMOS transistor is electrically connected to a second bias voltage, and the source is electrically connected to a power supply. The base-emitter voltage of the NPN transistor, i.e., VBE, is the second voltage. Based on the current and temperature data, a temperature calibration coefficient is calculated in the digital domain to obtain calibrated current data, including: The temperature offset and temperature gain are calculated based on the first temperature data and the second temperature data, and the temperature offset and temperature gain are written into the first digital register for storage, wherein the first temperature data is the temperature data at room temperature, and the second temperature data is the temperature data at the highest temperature. The temperature coefficient of the current, i.e. the temperature coefficient of the on-chip resistor, is calculated based on the first current data and the second current data, and then written into the second digital register for storage. The first current data is the current data at room temperature, and the second current data is the current data at the highest temperature. Calculate the change in the current temperature data relative to the first temperature based on the temperature offset and temperature gain; The calibration coefficient at the current temperature is calculated based on the current temperature coefficient and the change in the current temperature data relative to the first temperature. The calibrated current data is calculated based on the calibration coefficient at the current temperature.

2. The calibration circuit according to claim 1, characterized in that, The input stage includes a pair of NMOS input transistors, a pair of PMOS load transistors, and an NMOS bias transistor. The pair of NMOS input transistors includes a first NMOS input transistor and a second NMOS input transistor. The pair of PMOS load transistors includes a first PMOS load transistor and a second PMOS load transistor. The source of the first NMOS input transistor is electrically connected to the drain of the NMOS bias transistor, and its drain is electrically connected to the drain of the first PMOS load transistor. The source of the NMOS bias transistor is electrically connected to ground, and its gate is electrically connected to a first bias voltage. The gate of the first PMOS load transistor is electrically connected to its own drain, and its source is electrically connected to a power supply. The gate of the second NMOS input transistor is electrically connected to an analog input voltage, its source is electrically connected to the drain of the NMOS bias transistor, and its drain is electrically connected to the drain of the second PMOS load transistor, serving as the output of the input stage. The gate of the second PMOS load transistor is electrically connected to the gate of the first PMOS load transistor, and its source is electrically connected to a power supply. The output stage includes an output NMOS transistor and an output PMOS transistor. The gate of the output NMOS transistor is electrically connected to the first bias voltage, the source is electrically connected to ground, and the drain is electrically connected to the gate of the first NMOS input transistor, the drain of the output PMOS transistor, and one end of the external load. The other end of the external load is electrically connected to ground. The gate of the output PMOS transistor is electrically connected to the drain of the second NMOS input transistor, and the source is electrically connected to the power supply.

3. The calibration circuit according to claim 1, characterized in that, The process of converting external load current into a first voltage includes: The current mirror unit generates a load current with a ratio of 1 / m. The mirrored load current flows through the on-chip resistor, generating a voltage drop; Calculate the resistance value of the on-chip resistor at temperature T; Calculate the voltage to ground of the on-chip resistor at temperature T, i.e., the first voltage, based on the current flowing through the on-chip resistor and the resistance value of the on-chip resistor at temperature T. The formula used to calculate the load current is: ； in, The current flowing through the output PMOS transistor, The current flowing through the output NMOS transistor, This is the load current; The formula used to calculate the current flowing through the on-chip resistor is: ； in, The current flowing through the on-chip resistor, The width-to-length ratio of the output PMOS transistor and the mirrored PMOS transistor; The formula used to calculate the resistance of the on-chip resistor at temperature T is: ]； in, To be at temperature The resistance value of the on-chip resistor, The value is 296-302K, which is equivalent to 23-29℃. The temperature coefficient of the on-chip resistor. This represents the resistance value of the on-chip resistor at temperature T. The formula for calculating the first voltage is: ； in, The voltage is the first voltage at temperature T. Monitoring the temperature of the calibration circuit and converting the temperature into a second voltage includes; The operating temperature of the chip is monitored using an NPN transistor. The second voltage is calculated using the base-emitter voltage of the NPN transistor being detected; The formula for calculating the base-emitter voltage of the NPN transistor is as follows: ； in, To be at temperature The base-emitter voltage of the NPN transistor is detected at any time. It is a constant with a value of -1 to 3 mV / ℃; The formula for calculating the second voltage is: temp ; in, temp is the second voltage. To detect the base-emitter voltage of an NPN transistor at temperature T.

4. The calibration circuit according to claim 1, characterized in that, The temperature offset is the first temperature data, and its expression is: ； in, This is the temperature offset. This is the first temperature data; The formula for calculating the temperature gain is: ； in, For temperature gain, This is the second temperature data. This is the highest temperature, with a value of 120-150℃; The formula used to calculate the temperature coefficient of current is: ； in, The temperature coefficient of current. This is the first current data. This is the second current data; The formula used to calculate the change in the current temperature data relative to the first temperature data is: ； in, The change in temperature data relative to the first temperature data is represented by T, where T is the current temperature. This refers to the temperature data at the current temperature. The formula used to calculate the calibration coefficient at the current temperature is: ; The formula used to obtain the calibrated current data is: ； in, For the calibrated current data, This is the current data at the current temperature.

5. A method for temperature calibration in the calibration circuit according to any one of claims 1-4, characterized in that, include: The external load current is converted into a first voltage through a load current to voltage conversion circuit; A temperature detection circuit is used to monitor the operating temperature of the chip and convert the temperature into a second voltage. The first voltage and the second voltage are selected and output using an input selector; The first voltage and the second voltage are converted into current data and temperature data, respectively, using an ADC converter. Based on the current and temperature data, the temperature calibration coefficient is calculated in the digital domain using the temperature calibration unit to obtain the calibrated current data.

6. The method according to claim 5, characterized in that, The circuit analysis process for converting external load current into a first voltage includes: The current mirror unit generates a load current with a ratio of 1 / m. The mirrored load current flows through the on-chip resistor, generating a voltage drop. Calculate the resistance value of the on-chip resistor at temperature T; Calculate the voltage to ground of the on-chip resistor at temperature T, i.e., the first voltage, based on the current flowing through the on-chip resistor and the resistance value of the on-chip resistor at temperature T. Monitoring the temperature of the calibration circuit and converting the temperature into a second voltage includes; The temperature of the calibration circuit is monitored using a detection NPN transistor; The second voltage is calculated using the base-emitter voltage of the NPN transistor.

7. The method according to claim 5, characterized in that, Based on the current and temperature data, a temperature calibration coefficient is calculated in the digital domain to obtain calibrated current data, including: The temperature offset and temperature gain are calculated based on the first temperature data and the second temperature data, and the temperature offset and temperature gain are written into the first digital register for storage, wherein the first temperature data is the temperature data at room temperature, and the second temperature data is the temperature data at the highest temperature. The temperature coefficient of the current, i.e. the temperature coefficient of the on-chip resistor, is calculated based on the first current data and the second current data, and then written into the second digital register for storage. The first current data is the current data at room temperature, and the second current data is the current data at the highest temperature. Calculate the change in the current temperature data relative to the first temperature based on the temperature offset and temperature gain; The calibration coefficient at the current temperature is calculated based on the current temperature coefficient and the change in the current temperature data relative to the first temperature. The calibrated current data is calculated based on the calibration coefficient at the current temperature.

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